ff_reset_verilog.v

gistfile1.v

//----------------------------------------------------------------------------
//  A verilog module for a ff_reset (based on my vhdl module ff_reset.vhd)
//	Written by Gandhi Puvvada  Date: 2/15/2008
//	File name: ff_reset.v
//      Analyze and simulate for 550ns in modelsim. 
//      Answer all questions posted below.
//----------------------------------------------------------------------------
// When you compile this design in synopsys, use the following command so that,
// the mapped design can NOT use complex cells with builtin muxes. 
//    set_dont_use lcb500kv/FDS*
//----------------------------------------------------------------------------
/*
          -- Analyze the first 3 or 4 clocks (clock count Clk_CNT = 0 to 3).
             Initally why some FF outputs were undefined and some were defined?
             FFs which started with unknown output differed in the time when 
             they came out of that unknown state to a known value.
  
          -- Why Flip-flops differed at the beginning of clock count 7 and why 
             again at the beginning of clock count 8 the FF outputs became 
             the same?
  
          -- Differences during clock count 12
  
          -- Differences at the beginning of clock count 13
  
          -- Why didn't inactivating the data_enable between 
             clock count 14 and 15 did not produce any differences 
             between the FF outputs?
*/ //-----------------------------------------------------------------------------
module ff_reset (
    D, Clk, Reset_b, de, // de = Data Enable
    Q_bad_r, Q_async_r, Q_sync_r, Q_no_r,
    Q_async_r_de, Q_sync_r_de, Q_no_r_de	);

input  D, Clk, Reset_b, de;
output Q_bad_r, Q_async_r, Q_sync_r, Q_no_r ;
output Q_async_r_de, Q_sync_r_de, Q_no_r_de ;
reg Q_bad_r, Q_async_r, Q_sync_r, Q_no_r ;
reg Q_async_r_de, Q_sync_r_de, Q_no_r_de ;

	// Flip-flop with BAD reset
	// This Reset_b acts like high active data-enable control!
//------------
  always @(posedge Clk, posedge Reset_b) 
    begin	: FF_BAD_R					
        if (!Reset_b)
		    ; // nothing to do
        else
		Q_bad_r <= D;
    end
//------------

	// Flip-flop with asynchronous reset
//------------
  always @(posedge Clk, posedge Reset_b) 
    begin	: FF_ASYNC_R					
        if (!Reset_b)
		Q_async_r <= 1'b0;
        else
		Q_async_r <= D;
    end
//------------

	// Flip-flop with synchronous reset
//------------
  always @(posedge Clk) 
    begin	: FF_SYNC_R					
        if (!Reset_b)
		Q_sync_r <= /*TO DO*/;
        else
		Q_sync_r <= D;
    end
//------------

	// Flip-flop without reset
//------------
  always @(posedge Clk) 
    begin	: FF_NO_R				
 	Q_no_r <= D;
    end
//------------


	// Flip-flop with asynchronous reset and Data Enable (de)
//------------
  always @(posedge Clk, posedge Reset_b) 
    begin	: FF_ASYNC_R_DE					
        if (!Reset_b)
		Q_async_r_de  <= /*TO DO*/;
        else if (de)
		Q_async_r_de  <= D;
    end
//------------


	// Flip-flop with synchronous reset and Data Enable (de)
//------------
  always @(posedge Clk) 
    begin	: FF_SYNC_R_DE					
        if (!Reset_b)
		Q_sync_r_de  <= /*TO DO*/;
        else if (de)
		Q_sync_r_de  <= D;
    end
//------------


	// Flip-flop without reset but with Data Enable (de)
//------------
  always @(posedge Clk) 
    begin	: FF_NO_R_DE					
      if (de)
		Q_no_r_de <= D;
    end
//------------

endmodule