dma_input_gate_test.py

from artiq.experiment import *

class DMAInputGateTest(EnvExperiment):
    def build(self):
        self.setattr_device("core")
        self.setattr_device("core_dma")
        self.setattr_device("loop_out")
        self.setattr_device("loop_in")
        self.setattr_device("scheduler")

        self.setattr_argument("use_dma", BooleanValue(default=True))

    @kernel
    def execute(self):
        with parallel:
            with sequential:
                delay(1 * us)
                self.loop_out.pulse(1 * us)
            self.loop_in.gate_rising(3 * us)

    @kernel
    def run(self):
        with self.core_dma.record("test"):
            self.execute()
        handle = self.core_dma.get_handle("test")

        while not self.scheduler.check_pause():
            self.core.break_realtime()
            for i in range(100):
                # Gratuituously large delay to avoid any silly race conditions.
                delay(50*us)

                before = now_mu()
                if self.use_dma:
                    self.core_dma.playback_handle(handle)
                else:
                    self.execute()
                after = now_mu()

                count = self.loop_in.count()
                if count != 1:
                    print("Mismatch:", i, count)
                    print(before, after, after - before)
                    self.core.break_realtime()
                    return

gistfile1.txt

print:Mismatch: 0 0
print:10802032690608 10802032693608 3000