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February 20, 2018 18:20
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Diff of Netgear RN214 Linux 4.4.111-alpine tree against Linux 4.4.111 upstream
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| /dts-v1/; | |
| / { | |
| compatible = "annapurna-labs,alpine", "al,alpine", "netgear,readynas-20x", "netgear,readynas-204"; | |
| clock-ranges; | |
| version = "2.5"; | |
| #address-cells = <0x2>; | |
| #size-cells = <0x2>; | |
| soc { | |
| compatible = "simple-bus"; | |
| ranges; | |
| #address-cells = <0x2>; | |
| #size-cells = <0x2>; | |
| interrupt-parent = <0x2>; | |
| mc { | |
| reg = <0x0 0xfb080000 0x0 0x10000>; | |
| compatible = "annapurna-labs,al-mc"; | |
| }; | |
| ccu { | |
| reg = <0x0 0xfb090000 0x0 0x10000>; | |
| compatible = "annapurna-labs,al-ccu", "al,alpine-ccu"; | |
| io_coherency = <0x1>; | |
| }; | |
| pbs { | |
| reg = <0x0 0xfd8a8000 0x0 0x1000>; | |
| compatible = "annapurna-labs,al-pbs"; | |
| }; | |
| pmu { | |
| interrupts = <0x0 0x44 0x4 0x0 0x45 0x4 0x0 0x46 0x4 0x0 0x47 0x4>; | |
| compatible = "arm,cortex-a15-pmu"; | |
| }; | |
| spi { | |
| reg = <0x0 0xfd882000 0x0 0x1000>; | |
| interrupts = <0x0 0x17 0x4>; | |
| compatible = "snps,dw-apb-ssi"; | |
| clock-names = "sbclk"; | |
| clocks = <0x3>; | |
| num-cs = <0x4>; | |
| status = "disabled"; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| bus-num = <0x0>; | |
| }; | |
| msix { | |
| reg = <0x0 0xfbe00000 0x0 0x100000>; | |
| interrupts = <0x0 0x60 0x1 0x0 0x9f 0x1>; | |
| compatible = "annapurna-labs,al-msix", "annapurna-labs,alpine-msix"; | |
| msi-controller; | |
| phandle = <0x6>; | |
| interrupt-controller; | |
| linux,phandle = <0x6>; | |
| interrupt-parent = <0x2>; | |
| }; | |
| wdt0 { | |
| reg = <0x0 0xfd88c000 0x0 0x1000>; | |
| interrupts = <0x0 0xd 0x4>; | |
| compatible = "arm,sp805", "arm,primecell"; | |
| clock-names = "apb_pclk"; | |
| clocks = <0x3>; | |
| phandle = <0x5>; | |
| linux,phandle = <0x5>; | |
| }; | |
| wdt1 { | |
| reg = <0x0 0xfd88d000 0x0 0x1000>; | |
| interrupts = <0x0 0xe 0x4>; | |
| compatible = "arm,sp805", "arm,primecell"; | |
| clock-names = "apb_pclk"; | |
| clocks = <0x3>; | |
| status = "disabled"; | |
| }; | |
| wdt2 { | |
| reg = <0x0 0xfd88e000 0x0 0x1000>; | |
| interrupts = <0x0 0xf 0x4>; | |
| compatible = "arm,sp805", "arm,primecell"; | |
| clock-names = "apb_pclk"; | |
| clocks = <0x3>; | |
| status = "disabled"; | |
| }; | |
| wdt3 { | |
| reg = <0x0 0xfd88f000 0x0 0x1000>; | |
| interrupts = <0x0 0x10 0x4>; | |
| compatible = "arm,sp805", "arm,primecell"; | |
| clock-names = "apb_pclk"; | |
| clocks = <0x3>; | |
| status = "disabled"; | |
| }; | |
| i2c-gen { | |
| reg = <0x0 0xfd894000 0x0 0x1000>; | |
| interrupts = <0x0 0x8 0x4>; | |
| compatible = "snps,designware-i2c"; | |
| clock-frequency = <0x61a80>; | |
| clocks = <0x3>; | |
| status = "disabled"; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| }; | |
| i2c-pld { | |
| reg = <0x0 0xfd880000 0x0 0x1000>; | |
| interrupts = <0x0 0x15 0x4>; | |
| compatible = "snps,designware-i2c"; | |
| clock-frequency = <0x61a80>; | |
| clocks = <0x3>; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| i2c_mux@70 { | |
| reg = <0x70>; | |
| compatible = "pca9548"; | |
| }; | |
| rtc@68 { | |
| reg = <0x68>; | |
| compatible = "ds1337"; | |
| }; | |
| g762@3e { | |
| reg = <0x3e>; | |
| compatible = "gmt,g762"; | |
| fan_startv = <0x3>; | |
| clocks = <0x4>; | |
| fan_gear_mode = <0x0>; | |
| pwm_polarity = <0x0>; | |
| }; | |
| }; | |
| nand-flash { | |
| reg = <0x0 0xfa100000 0x0 0x202000>; | |
| interrupts = <0x0 0x1 0x4>; | |
| compatible = "annapurna-labs,al-nand"; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x1>; | |
| partition@0 { | |
| reg = <0x0 0x1c0000>; | |
| label = "u-boot"; | |
| }; | |
| partition@1 { | |
| reg = <0x1c0000 0x40000>; | |
| label = "u-boot-env"; | |
| }; | |
| partition@2 { | |
| reg = <0x200000 0x600000>; | |
| label = "uImage"; | |
| }; | |
| partition@3 { | |
| reg = <0x800000 0x400000>; | |
| label = "minirootfs"; | |
| }; | |
| partition@4 { | |
| reg = <0xc00000 0x6400000>; | |
| label = "ubifs"; | |
| }; | |
| partition@5 { | |
| reg = <0x80000 0x20000>; | |
| label = "dts"; | |
| }; | |
| partition@6 { | |
| reg = <0x7000000 0x1000000>; | |
| label = "factory-diag"; | |
| }; | |
| }; | |
| gpio0 { | |
| reg = <0x0 0xfd887000 0x0 0x1000>; | |
| interrupts = <0x0 0x2 0x4>; | |
| #gpio-cells = <0x2>; | |
| compatible = "arm,pl061", "arm,primecell"; | |
| clock-names = "apb_pclk"; | |
| clocks = <0x3>; | |
| baseidx = <0x0>; | |
| gpio-controller; | |
| }; | |
| gpio1 { | |
| reg = <0x0 0xfd888000 0x0 0x1000>; | |
| interrupts = <0x0 0x3 0x4>; | |
| #gpio-cells = <0x2>; | |
| compatible = "arm,pl061", "arm,primecell"; | |
| clock-names = "apb_pclk"; | |
| clocks = <0x3>; | |
| baseidx = <0x8>; | |
| gpio-controller; | |
| }; | |
| gpio2 { | |
| reg = <0x0 0xfd889000 0x0 0x1000>; | |
| interrupts = <0x0 0x4 0x4>; | |
| #gpio-cells = <0x2>; | |
| compatible = "arm,pl061", "arm,primecell"; | |
| clock-names = "apb_pclk"; | |
| clocks = <0x3>; | |
| baseidx = <0x10>; | |
| phandle = <0xd>; | |
| gpio-controller; | |
| linux,phandle = <0xd>; | |
| }; | |
| gpio3 { | |
| reg = <0x0 0xfd88a000 0x0 0x1000>; | |
| interrupts = <0x0 0x5 0x4>; | |
| #gpio-cells = <0x2>; | |
| compatible = "arm,pl061", "arm,primecell"; | |
| clock-names = "apb_pclk"; | |
| clocks = <0x3>; | |
| baseidx = <0x18>; | |
| phandle = <0xc>; | |
| gpio-controller; | |
| linux,phandle = <0xc>; | |
| }; | |
| gpio4 { | |
| reg = <0x0 0xfd88b000 0x0 0x1000>; | |
| interrupts = <0x0 0x6 0x4>; | |
| #gpio-cells = <0x2>; | |
| compatible = "arm,pl061", "arm,primecell"; | |
| clock-names = "apb_pclk"; | |
| clocks = <0x3>; | |
| baseidx = <0x20>; | |
| phandle = <0xe>; | |
| gpio-controller; | |
| linux,phandle = <0xe>; | |
| }; | |
| gpio5 { | |
| reg = <0x0 0xfd897000 0x0 0x1000>; | |
| interrupts = <0x0 0x7 0x4>; | |
| #gpio-cells = <0x2>; | |
| compatible = "arm,pl061", "arm,primecell"; | |
| clock-names = "apb_pclk"; | |
| clocks = <0x3>; | |
| baseidx = <0x28>; | |
| phandle = <0xf>; | |
| gpio-controller; | |
| linux,phandle = <0xf>; | |
| }; | |
| uart0 { | |
| reg = <0x0 0xfd883000 0x0 0x1000>; | |
| interrupts = <0x0 0x11 0x4>; | |
| reg-shift = <0x2>; | |
| compatible = "ns16550a"; | |
| clock-frequency = <0x165a0bc0>; | |
| reg-io-width = <0x4>; | |
| }; | |
| uart1 { | |
| reg = <0x0 0xfd884000 0x0 0x1000>; | |
| interrupts = <0x0 0x12 0x4>; | |
| reg-shift = <0x2>; | |
| compatible = "ns16550a"; | |
| clock-frequency = <0x165a0bc0>; | |
| reg-io-width = <0x4>; | |
| }; | |
| uart2 { | |
| reg = <0x0 0xfd885000 0x0 0x1000>; | |
| interrupts = <0x0 0x13 0x4>; | |
| reg-shift = <0x2>; | |
| compatible = "ns16550a"; | |
| clock-frequency = <0x165a0bc0>; | |
| status = "disabled"; | |
| reg-io-width = <0x4>; | |
| }; | |
| uart3 { | |
| reg = <0x0 0xfd886000 0x0 0x1000>; | |
| interrupts = <0x0 0x14 0x4>; | |
| reg-shift = <0x2>; | |
| compatible = "ns16550a"; | |
| clock-frequency = <0x165a0bc0>; | |
| status = "disabled"; | |
| reg-io-width = <0x4>; | |
| }; | |
| pcie-external0-3-10 { | |
| reg = <0x0 0xfd800000 0x0 0x20000>; | |
| compatible = "annapurna-labs,al-pci"; | |
| bus-range = <0x0 0xff>; | |
| device_type = "pci"; | |
| #interrupt-cells = <0x1>; | |
| ranges = <0x0 0x0 0xfb600000 0x0 0xfb600000 0x0 0x200000 0x1000000 0x0 0x10000 0x0 0xe0000000 0x0 0x10000 0x2000000 0x0 0xe0010000 0x0 0xe0010000 0x0 0x7ff0000>; | |
| #address-cells = <0x3>; | |
| interrupt-map = <0x0 0x0 0x0 0x1 0x2 0x0 0x28 0x4>; | |
| interrupt-map-mask = <0x0 0x0 0x0 0x7>; | |
| #size-cells = <0x2>; | |
| interrupt-parent = <0x2>; | |
| }; | |
| pcie-external1-3-10 { | |
| reg = <0x0 0xfd820000 0x0 0x20000>; | |
| compatible = "annapurna-labs,al-pci"; | |
| bus-range = <0x0 0xff>; | |
| device_type = "pci"; | |
| #interrupt-cells = <0x1>; | |
| ranges = <0x0 0x0 0xfb800000 0x0 0xfb800000 0x0 0x200000 0x1000000 0x0 0x20000 0x0 0xe8000000 0x0 0x10000 0x2000000 0x0 0xe8010000 0x0 0xe8010000 0x0 0x3ff0000>; | |
| #address-cells = <0x3>; | |
| interrupt-map = <0x0 0x0 0x0 0x1 0x2 0x0 0x29 0x4>; | |
| interrupt-map-mask = <0x0 0x0 0x0 0x7>; | |
| #size-cells = <0x2>; | |
| interrupt-parent = <0x2>; | |
| }; | |
| pcie-external2-3-10 { | |
| reg = <0x0 0xfd840000 0x0 0x20000>; | |
| compatible = "annapurna-labs,al-pci"; | |
| bus-range = <0x0 0xff>; | |
| device_type = "pci"; | |
| #interrupt-cells = <0x1>; | |
| ranges = <0x0 0x0 0xfba00000 0x0 0xfba00000 0x0 0x200000 0x1000000 0x0 0x30000 0x0 0xec000000 0x0 0x10000 0x2000000 0x0 0xec010000 0x0 0xec010000 0x0 0x3ff0000>; | |
| #address-cells = <0x3>; | |
| interrupt-map = <0x0 0x0 0x0 0x1 0x2 0x0 0x2a 0x4>; | |
| interrupt-map-mask = <0x0 0x0 0x0 0x7>; | |
| #size-cells = <0x2>; | |
| interrupt-parent = <0x2>; | |
| }; | |
| thermal { | |
| reg = <0x0 0xfd860a00 0x0 0x100>; | |
| compatible = "annapurna-labs,al-thermal"; | |
| }; | |
| clocks { | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| nbclk { | |
| #clock-cells = <0x0>; | |
| compatible = "fixed-clock"; | |
| clock-frequency = <0x2faf0800>; | |
| }; | |
| sbclk { | |
| #clock-cells = <0x0>; | |
| compatible = "fixed-clock"; | |
| clock-frequency = <0x165a0bc0>; | |
| phandle = <0x3>; | |
| linux,phandle = <0x3>; | |
| }; | |
| cpuclk { | |
| #clock-cells = <0x0>; | |
| compatible = "fixed-clock"; | |
| clock-frequency = "SrN"; | |
| phandle = <0x1>; | |
| linux,phandle = <0x1>; | |
| }; | |
| fixedclk { | |
| #clock-cells = <0x0>; | |
| compatible = "fixed-clock"; | |
| clock-frequency = <0x1964>; | |
| phandle = <0x4>; | |
| linux,phandle = <0x4>; | |
| }; | |
| refclk { | |
| #clock-cells = <0x0>; | |
| compatible = "fixed-clock"; | |
| clock-frequency = <0x5f5e100>; | |
| }; | |
| }; | |
| cpu_resume { | |
| reg = <0x0 0xfbff5ec0 0x0 0x30>; | |
| compatible = "annapurna-labs,al-cpu-resume", "al,alpine-cpu-resume"; | |
| }; | |
| nb_service { | |
| reg = <0x0 0xfb070000 0x0 0x10000>; | |
| interrupts = <0x0 0x40 0x4 0x0 0x41 0x4 0x0 0x42 0x4 0x0 0x43 0x4>; | |
| compatible = "annapurna-labs,al-nb-service", "al,alpine-sysfabric-service", "syscon"; | |
| dev_ord_relax = <0x0>; | |
| }; | |
| reboot { | |
| compatible = "annapurna-labs,alpine-reboot"; | |
| wdt-parent = <0x5>; | |
| }; | |
| spi-3-10-20 { | |
| reg = <0x0 0xfd882000 0x0 0x1000>; | |
| interrupts = <0x0 0x17 0x4>; | |
| compatible = "snps,dw-spi-mmio"; | |
| clock-names = "sbclk"; | |
| clocks = <0x3>; | |
| #address-cells = <0x1>; | |
| num-chipselect = <0x4>; | |
| #size-cells = <0x0>; | |
| bus-num = <0x0>; | |
| }; | |
| serdes { | |
| reg = <0x0 0xfd8c0000 0x0 0x1000>; | |
| compatible = "annapurna-labs,al-serdes"; | |
| }; | |
| arch-timer { | |
| interrupts = <0x1 0xd 0xf08 0x1 0xe 0xf08 0x1 0xb 0xf08 0x1 0xa 0xf08>; | |
| compatible = "arm,cortex-a15-timer", "arm,armv7-timer"; | |
| clock-frequency = <0x2faf080>; | |
| }; | |
| timer0 { | |
| reg = <0x0 0xfd890000 0x0 0x1000>; | |
| interrupts = <0x0 0x9 0x4>; | |
| compatible = "arm,sp804", "arm,primecell"; | |
| clock-names = "sbclk"; | |
| clocks = <0x3>; | |
| status = "disabled"; | |
| }; | |
| timer1 { | |
| reg = <0x0 0xfd891000 0x0 0x1000>; | |
| interrupts = <0x0 0xa 0x4>; | |
| compatible = "arm,sp804", "arm,primecell"; | |
| clock-names = "sbclk"; | |
| clocks = <0x3>; | |
| status = "disabled"; | |
| }; | |
| timer2 { | |
| reg = <0x0 0xfd892000 0x0 0x1000>; | |
| interrupts = <0x0 0xb 0x4>; | |
| compatible = "arm,sp804", "arm,primecell"; | |
| clock-names = "sbclk"; | |
| clocks = <0x3>; | |
| status = "disabled"; | |
| }; | |
| timer3 { | |
| reg = <0x0 0xfd893000 0x0 0x1000>; | |
| interrupts = <0x0 0xc 0x4>; | |
| compatible = "arm,sp804", "arm,primecell"; | |
| clock-names = "sbclk"; | |
| clocks = <0x3>; | |
| status = "disabled"; | |
| }; | |
| gic_main { | |
| reg = <0x0 0xfb001000 0x0 0x1000 0x0 0xfb002000 0x0 0x2000 0x0 0xfb004000 0x0 0x1000 0x0 0xfb006000 0x0 0x2000>; | |
| interrupts = <0x1 0x9 0xf04>; | |
| compatible = "arm,cortex-a15-gic"; | |
| #interrupt-cells = <0x3>; | |
| #address-cells = <0x0>; | |
| phandle = <0x2>; | |
| interrupt-controller; | |
| #size-cells = <0x0>; | |
| linux,phandle = <0x2>; | |
| }; | |
| pinctrl { | |
| reg = <0x0 0xfd8a8000 0x0 0x1000>; | |
| compatible = "annapurna-labs,al-pinctrl"; | |
| if_nand_cs_0 { | |
| id = "if_nand_cs_0"; | |
| arg = <0x0>; | |
| phandle = <0x8>; | |
| linux,phandle = <0x8>; | |
| }; | |
| if_nand_cs_1 { | |
| id = "if_nand_cs_1"; | |
| arg = <0x0>; | |
| }; | |
| if_nand_cs_2 { | |
| id = "if_nand_cs_2"; | |
| arg = <0x0>; | |
| }; | |
| if_nand_cs_3 { | |
| id = "if_nand_cs_3"; | |
| arg = <0x0>; | |
| }; | |
| if_gpio10 { | |
| id = "if_gpio"; | |
| arg = <0xa>; | |
| }; | |
| if_gpio11 { | |
| id = "if_gpio"; | |
| arg = <0xb>; | |
| }; | |
| if_gpio12 { | |
| id = "if_gpio"; | |
| arg = <0xc>; | |
| }; | |
| if_gpio13 { | |
| id = "if_gpio"; | |
| arg = <0xd>; | |
| }; | |
| if_gpio14 { | |
| id = "if_gpio"; | |
| arg = <0xe>; | |
| }; | |
| if_gpio15 { | |
| id = "if_gpio"; | |
| arg = <0xf>; | |
| }; | |
| if_gpio16 { | |
| id = "if_gpio"; | |
| arg = <0x10>; | |
| }; | |
| if_gpio17 { | |
| id = "if_gpio"; | |
| arg = <0x11>; | |
| }; | |
| if_gpio18 { | |
| id = "if_gpio"; | |
| arg = <0x12>; | |
| }; | |
| if_gpio19 { | |
| id = "if_gpio"; | |
| arg = <0x13>; | |
| }; | |
| if_gpio20 { | |
| id = "if_gpio"; | |
| arg = <0x14>; | |
| }; | |
| if_gpio21 { | |
| id = "if_gpio"; | |
| arg = <0x15>; | |
| }; | |
| if_gpio22 { | |
| id = "if_gpio"; | |
| arg = <0x16>; | |
| }; | |
| if_gpio23 { | |
| id = "if_gpio"; | |
| arg = <0x17>; | |
| }; | |
| if_gpio24 { | |
| id = "if_gpio"; | |
| arg = <0x18>; | |
| }; | |
| if_gpio25 { | |
| id = "if_gpio"; | |
| arg = <0x19>; | |
| }; | |
| if_gpio26 { | |
| id = "if_gpio"; | |
| arg = <0x1a>; | |
| }; | |
| if_gpio27 { | |
| id = "if_gpio"; | |
| arg = <0x1b>; | |
| }; | |
| if_gpio28 { | |
| id = "if_gpio"; | |
| arg = <0x1c>; | |
| }; | |
| if_gpio29 { | |
| id = "if_gpio"; | |
| arg = <0x1d>; | |
| }; | |
| if_gpio30 { | |
| id = "if_gpio"; | |
| arg = <0x1e>; | |
| }; | |
| if_gpio31 { | |
| id = "if_gpio"; | |
| arg = <0x1f>; | |
| }; | |
| if_gpio32 { | |
| id = "if_gpio"; | |
| arg = <0x20>; | |
| }; | |
| if_gpio33 { | |
| id = "if_gpio"; | |
| arg = <0x21>; | |
| }; | |
| if_gpio34 { | |
| id = "if_gpio"; | |
| arg = <0x22>; | |
| }; | |
| if_gpio35 { | |
| id = "if_gpio"; | |
| arg = <0x23>; | |
| }; | |
| if_gpio36 { | |
| id = "if_gpio"; | |
| arg = <0x24>; | |
| }; | |
| if_gpio37 { | |
| id = "if_gpio"; | |
| arg = <0x25>; | |
| }; | |
| if_gpio38 { | |
| id = "if_gpio"; | |
| arg = <0x26>; | |
| }; | |
| if_gpio39 { | |
| id = "if_gpio"; | |
| arg = <0x27>; | |
| }; | |
| if_gpio40 { | |
| id = "if_gpio"; | |
| arg = <0x28>; | |
| }; | |
| if_gpio41 { | |
| id = "if_gpio"; | |
| arg = <0x29>; | |
| }; | |
| if_gpio42 { | |
| id = "if_gpio"; | |
| arg = <0x2a>; | |
| }; | |
| if_gpio43 { | |
| id = "if_gpio"; | |
| arg = <0x2b>; | |
| }; | |
| if_pci_ep_reset_out { | |
| id = "if_pci_ep_reset_out"; | |
| arg = <0x0>; | |
| }; | |
| if_nand_8 { | |
| id = "if_nand_8"; | |
| arg = <0x0>; | |
| phandle = <0x7>; | |
| linux,phandle = <0x7>; | |
| }; | |
| if_nor_16 { | |
| id = "if_nor_16"; | |
| arg = <0x0>; | |
| }; | |
| if_nor_wp { | |
| id = "if_nor_wp"; | |
| arg = <0x0>; | |
| }; | |
| if_eth_gpio { | |
| id = "if_eth_gpio"; | |
| arg = <0x0>; | |
| }; | |
| if_eth_leds { | |
| id = "if_eth_leds"; | |
| arg = <0x0>; | |
| phandle = <0xa>; | |
| linux,phandle = <0xa>; | |
| }; | |
| if_sram_8 { | |
| id = "if_sram_8"; | |
| arg = <0x0>; | |
| }; | |
| if_uart_1_modem { | |
| id = "if_uart_1_modem"; | |
| arg = <0x0>; | |
| }; | |
| if_uart_1 { | |
| id = "if_uart_1"; | |
| arg = <0x0>; | |
| phandle = <0xb>; | |
| linux,phandle = <0xb>; | |
| }; | |
| if_uart_2 { | |
| id = "if_uart_2"; | |
| arg = <0x0>; | |
| }; | |
| if_uart_3 { | |
| id = "if_uart_3"; | |
| arg = <0x0>; | |
| }; | |
| if_ulpi_0_rst_n { | |
| id = "if_ulpi_0_rst_n"; | |
| arg = <0x0>; | |
| }; | |
| if_i2c_gen { | |
| id = "if_i2c_gen"; | |
| arg = <0x0>; | |
| }; | |
| if_sram_cs_0 { | |
| id = "if_sram_cs_0"; | |
| arg = <0x0>; | |
| }; | |
| if_sram_cs_1 { | |
| id = "if_sram_cs_1"; | |
| arg = <0x0>; | |
| }; | |
| if_sram_cs_2 { | |
| id = "if_sram_cs_2"; | |
| arg = <0x0>; | |
| }; | |
| if_sram_cs_3 { | |
| id = "if_sram_cs_3"; | |
| arg = <0x0>; | |
| }; | |
| if_ulpi_1_rst_n { | |
| id = "if_ulpi_1_rst_n"; | |
| arg = <0x0>; | |
| }; | |
| if_gpio0 { | |
| id = "if_gpio"; | |
| arg = <0x0>; | |
| }; | |
| if_gpio1 { | |
| id = "if_gpio"; | |
| arg = <0x1>; | |
| }; | |
| if_gpio2 { | |
| id = "if_gpio"; | |
| arg = <0x2>; | |
| }; | |
| if_gpio3 { | |
| id = "if_gpio"; | |
| arg = <0x3>; | |
| }; | |
| if_gpio4 { | |
| id = "if_gpio"; | |
| arg = <0x4>; | |
| }; | |
| if_gpio5 { | |
| id = "if_gpio"; | |
| arg = <0x5>; | |
| }; | |
| if_gpio6 { | |
| id = "if_gpio"; | |
| arg = <0x6>; | |
| }; | |
| if_gpio7 { | |
| id = "if_gpio"; | |
| arg = <0x7>; | |
| }; | |
| if_gpio8 { | |
| id = "if_gpio"; | |
| arg = <0x8>; | |
| }; | |
| if_gpio9 { | |
| id = "if_gpio"; | |
| arg = <0x9>; | |
| }; | |
| if_nor_8 { | |
| id = "if_nor_8"; | |
| arg = <0x0>; | |
| }; | |
| if_pci_ep_int_a { | |
| id = "if_pci_ep_int_a"; | |
| arg = <0x0>; | |
| }; | |
| if_sata_0_leds { | |
| id = "if_sata_0_leds"; | |
| arg = <0x0>; | |
| }; | |
| if_sata_1_leds { | |
| id = "if_sata_1_leds"; | |
| arg = <0x0>; | |
| phandle = <0x9>; | |
| linux,phandle = <0x9>; | |
| }; | |
| if_sram_16 { | |
| id = "if_sram_16"; | |
| arg = <0x0>; | |
| }; | |
| if_nand_16 { | |
| id = "if_nand_16"; | |
| arg = <0x0>; | |
| }; | |
| if_nand_wp { | |
| id = "if_nand_wp"; | |
| arg = <0x0>; | |
| }; | |
| if_ulpi_1_b { | |
| id = "if_ulpi_1_b"; | |
| arg = <0x0>; | |
| }; | |
| if_spim_a_ss_1 { | |
| id = "if_spim_a_ss_1"; | |
| arg = <0x0>; | |
| }; | |
| if_spim_a_ss_2 { | |
| id = "if_spim_a_ss_2"; | |
| arg = <0x0>; | |
| }; | |
| if_spim_a_ss_3 { | |
| id = "if_spim_a_ss_3"; | |
| arg = <0x0>; | |
| }; | |
| if_nor_cs_0 { | |
| id = "if_nor_cs_0"; | |
| arg = <0x0>; | |
| }; | |
| if_nor_cs_1 { | |
| id = "if_nor_cs_1"; | |
| arg = <0x0>; | |
| }; | |
| if_nor_cs_2 { | |
| id = "if_nor_cs_2"; | |
| arg = <0x0>; | |
| }; | |
| if_nor_cs_3 { | |
| id = "if_nor_cs_3"; | |
| arg = <0x0>; | |
| }; | |
| }; | |
| pcie-internal-3-19 { | |
| reg = <0x0 0xfbc00000 0x0 0x100000>; | |
| msi-parent = <0x6>; | |
| reg-names = "ecam"; | |
| compatible = "annapurna-labs,alpine-internal-pcie"; | |
| bus-range = <0x0 0x0>; | |
| device_type = "pci"; | |
| #interrupt-cells = <0x1>; | |
| ranges = <0x0 0x0 0xfbc00000 0x0 0xfbc00000 0x0 0x100000 0x2000000 0x0 0xfe000000 0x0 0xfe000000 0x0 0x1000000>; | |
| #address-cells = <0x3>; | |
| interrupt-map = <0x4000 0x0 0x0 0x1 0x2 0x0 0x2b 0x4 0x4800 0x0 0x0 0x1 0x2 0x0 0x2c 0x4>; | |
| interrupt-map-mask = <0xf800 0x0 0x0 0x7>; | |
| #size-cells = <0x2>; | |
| interrupt-parent = <0x2>; | |
| }; | |
| board-cfg { | |
| id = "Netgear NAS RN20x"; | |
| u-boot-offset = <0x20000>; | |
| pcie { | |
| ep-ports; | |
| port0 { | |
| gen = <0x2>; | |
| width = <0x2>; | |
| status = "enabled"; | |
| }; | |
| port1 { | |
| gen = <0x2>; | |
| width = <0x2>; | |
| status = "enabled"; | |
| }; | |
| port2 { | |
| gen = <0x3>; | |
| width = <0x4>; | |
| status = "disabled"; | |
| }; | |
| }; | |
| pinctrl_init { | |
| pinctrl-0 = <0x7 0x8 0x9 0xa 0xb>; | |
| }; | |
| ethernet { | |
| port0 { | |
| status = "disabled"; | |
| }; | |
| port1 { | |
| mode = "rgmii"; | |
| status = "enabled"; | |
| ext_phy { | |
| phy_mgmt_if = "mdc-mdio"; | |
| phy-addr = <0x4>; | |
| mdc-mdio-freq = "1.0Mhz"; | |
| auto-neg-mode = "out-of-band"; | |
| }; | |
| }; | |
| port2 { | |
| status = "disabled"; | |
| }; | |
| port3 { | |
| mode = "rgmii"; | |
| status = "enabled"; | |
| ext_phy { | |
| phy_mgmt_if = "mdc-mdio"; | |
| phy-addr = <0x5>; | |
| mdc-mdio-freq = "1.0Mhz"; | |
| auto-neg-mode = "out-of-band"; | |
| }; | |
| }; | |
| }; | |
| gpio_init { | |
| gpio-list = <0x4 0x0 0x0 0x5 0x0 0x0 0x14 0x1 0x0 0x15 0x1 0x0 0x16 0x1 0x0 0x17 0x1 0x0 0x1c 0x1 0x0 0x1d 0x1 0x1 0x1e 0x1 0x1 0x1f 0x1 0x1 0x20 0x0 0x0 0x21 0x1 0x0 0x22 0x1 0x0 0x23 0x1 0x0 0x24 0x1 0x0 0x25 0x1 0x0 0x26 0x1 0x0 0x27 0x1 0x0 0x28 0x1 0x0 0x29 0x1 0x0 0x2a 0x1 0x0 0x2b 0x0 0x0 0x2c 0x0 0x0 0x2d 0x1 0x0 0x2e 0x1 0x0 0x2f 0x1 0x1>; | |
| }; | |
| serdes { | |
| group0 { | |
| ssc = "disabled"; | |
| active-lanes = <0x0 0x1 0x2 0x3>; | |
| inv-rx-lanes; | |
| inv-tx-lanes; | |
| interface = "pcie_g3x4"; | |
| ref-clock = "100Mhz"; | |
| lane_1_params { | |
| rx { | |
| override = "disabled"; | |
| }; | |
| tx { | |
| override = "disabled"; | |
| }; | |
| }; | |
| lane_3_params { | |
| rx { | |
| override = "disabled"; | |
| }; | |
| tx { | |
| override = "disabled"; | |
| }; | |
| }; | |
| lane_0_params { | |
| rx { | |
| override = "disabled"; | |
| }; | |
| tx { | |
| override = "disabled"; | |
| }; | |
| }; | |
| lane_2_params { | |
| rx { | |
| override = "disabled"; | |
| }; | |
| tx { | |
| override = "disabled"; | |
| }; | |
| }; | |
| }; | |
| group1 { | |
| ssc = "disabled"; | |
| active-lanes = <0x0 0x1 0x2 0x3>; | |
| inv-rx-lanes; | |
| inv-tx-lanes; | |
| interface = "sata"; | |
| ref-clock = "100Mhz"; | |
| lane_1_params { | |
| rx { | |
| dfe_3rd_tap_ctrl = <0x0>; | |
| dfe_2nd_tap_ctrl = <0x8>; | |
| dfe_3db_freq = <0x7>; | |
| dcgain = <0x0>; | |
| low_freq_agc_gain = <0x7>; | |
| override = "enabled"; | |
| high_freq_agc_boost = <0x0>; | |
| precal_code_sel = <0x0>; | |
| dfe_gain = <0x0>; | |
| dfe_1st_tap_ctrl = <0x0>; | |
| dfe_4th_tap_ctrl = <0x8>; | |
| }; | |
| tx { | |
| amp = <0x1>; | |
| total_driver_units = <0x13>; | |
| slew_rate = <0x0>; | |
| override = "enabled"; | |
| post_emph = <0x2>; | |
| pre_emph = <0x0>; | |
| }; | |
| }; | |
| lane_3_params { | |
| rx { | |
| dfe_3rd_tap_ctrl = <0x0>; | |
| dfe_2nd_tap_ctrl = <0x8>; | |
| dfe_3db_freq = <0x7>; | |
| dcgain = <0x0>; | |
| low_freq_agc_gain = <0x7>; | |
| override = "enabled"; | |
| high_freq_agc_boost = <0x0>; | |
| precal_code_sel = <0x0>; | |
| dfe_gain = <0x0>; | |
| dfe_1st_tap_ctrl = <0x0>; | |
| dfe_4th_tap_ctrl = <0x8>; | |
| }; | |
| tx { | |
| amp = <0x1>; | |
| total_driver_units = <0x13>; | |
| slew_rate = <0x0>; | |
| override = "enabled"; | |
| post_emph = <0x2>; | |
| pre_emph = <0x0>; | |
| }; | |
| }; | |
| lane_0_params { | |
| rx { | |
| dfe_3rd_tap_ctrl = <0x0>; | |
| dfe_2nd_tap_ctrl = <0x8>; | |
| dfe_3db_freq = <0x7>; | |
| dcgain = <0x0>; | |
| low_freq_agc_gain = <0x7>; | |
| override = "enabled"; | |
| high_freq_agc_boost = <0x0>; | |
| precal_code_sel = <0x0>; | |
| dfe_gain = <0x0>; | |
| dfe_1st_tap_ctrl = <0x0>; | |
| dfe_4th_tap_ctrl = <0x8>; | |
| }; | |
| tx { | |
| amp = <0x1>; | |
| total_driver_units = <0x13>; | |
| slew_rate = <0x0>; | |
| override = "enabled"; | |
| post_emph = <0x2>; | |
| pre_emph = <0x0>; | |
| }; | |
| }; | |
| lane_2_params { | |
| rx { | |
| dfe_3rd_tap_ctrl = <0x0>; | |
| dfe_2nd_tap_ctrl = <0x8>; | |
| dfe_3db_freq = <0x7>; | |
| dcgain = <0x0>; | |
| low_freq_agc_gain = <0x7>; | |
| override = "enabled"; | |
| high_freq_agc_boost = <0x0>; | |
| precal_code_sel = <0x0>; | |
| dfe_gain = <0x0>; | |
| dfe_1st_tap_ctrl = <0x0>; | |
| dfe_4th_tap_ctrl = <0x8>; | |
| }; | |
| tx { | |
| amp = <0x1>; | |
| total_driver_units = <0x13>; | |
| slew_rate = <0x0>; | |
| override = "enabled"; | |
| post_emph = <0x2>; | |
| pre_emph = <0x0>; | |
| }; | |
| }; | |
| }; | |
| group2 { | |
| ssc = "disabled"; | |
| active-lanes = <0x0 0x1 0x2 0x3>; | |
| inv-rx-lanes; | |
| inv-tx-lanes; | |
| interface = "sata"; | |
| ref-clock = "100Mhz"; | |
| lane_1_params { | |
| rx { | |
| dfe_3rd_tap_ctrl = <0x0>; | |
| dfe_2nd_tap_ctrl = <0x8>; | |
| dfe_3db_freq = <0x7>; | |
| dcgain = <0x0>; | |
| low_freq_agc_gain = <0x7>; | |
| override = "enabled"; | |
| high_freq_agc_boost = <0x0>; | |
| precal_code_sel = <0x0>; | |
| dfe_gain = <0x0>; | |
| dfe_1st_tap_ctrl = <0x0>; | |
| dfe_4th_tap_ctrl = <0x8>; | |
| }; | |
| tx { | |
| amp = <0x1>; | |
| total_driver_units = <0x13>; | |
| slew_rate = <0x0>; | |
| override = "enabled"; | |
| post_emph = <0x2>; | |
| pre_emph = <0x0>; | |
| }; | |
| }; | |
| lane_3_params { | |
| rx { | |
| dfe_3rd_tap_ctrl = <0x0>; | |
| dfe_2nd_tap_ctrl = <0x8>; | |
| dfe_3db_freq = <0x7>; | |
| dcgain = <0x0>; | |
| low_freq_agc_gain = <0x7>; | |
| override = "enabled"; | |
| high_freq_agc_boost = <0x0>; | |
| precal_code_sel = <0x0>; | |
| dfe_gain = <0x0>; | |
| dfe_1st_tap_ctrl = <0x0>; | |
| dfe_4th_tap_ctrl = <0x8>; | |
| }; | |
| tx { | |
| amp = <0x1>; | |
| total_driver_units = <0x13>; | |
| slew_rate = <0x0>; | |
| override = "enabled"; | |
| post_emph = <0x2>; | |
| pre_emph = <0x0>; | |
| }; | |
| }; | |
| lane_0_params { | |
| rx { | |
| dfe_3rd_tap_ctrl = <0x0>; | |
| dfe_2nd_tap_ctrl = <0x8>; | |
| dfe_3db_freq = <0x7>; | |
| dcgain = <0x0>; | |
| low_freq_agc_gain = <0x7>; | |
| override = "enabled"; | |
| high_freq_agc_boost = <0x0>; | |
| precal_code_sel = <0x0>; | |
| dfe_gain = <0x0>; | |
| dfe_1st_tap_ctrl = <0x0>; | |
| dfe_4th_tap_ctrl = <0x8>; | |
| }; | |
| tx { | |
| amp = <0x1>; | |
| total_driver_units = <0x13>; | |
| slew_rate = <0x0>; | |
| override = "enabled"; | |
| post_emph = <0x2>; | |
| pre_emph = <0x0>; | |
| }; | |
| }; | |
| lane_2_params { | |
| rx { | |
| dfe_3rd_tap_ctrl = <0x0>; | |
| dfe_2nd_tap_ctrl = <0x8>; | |
| dfe_3db_freq = <0x7>; | |
| dcgain = <0x0>; | |
| low_freq_agc_gain = <0x7>; | |
| override = "enabled"; | |
| high_freq_agc_boost = <0x0>; | |
| precal_code_sel = <0x0>; | |
| dfe_gain = <0x0>; | |
| dfe_1st_tap_ctrl = <0x0>; | |
| dfe_4th_tap_ctrl = <0x8>; | |
| }; | |
| tx { | |
| amp = <0x1>; | |
| total_driver_units = <0x13>; | |
| slew_rate = <0x0>; | |
| override = "enabled"; | |
| post_emph = <0x2>; | |
| pre_emph = <0x0>; | |
| }; | |
| }; | |
| }; | |
| group3 { | |
| ssc = "disabled"; | |
| active-lanes = <0x1 0x3>; | |
| inv-rx-lanes; | |
| inv-tx-lanes; | |
| interface = "10gbe"; | |
| ref-clock = "156.25Mhz"; | |
| lane_1_params { | |
| rx { | |
| override = "disabled"; | |
| }; | |
| tx { | |
| override = "disabled"; | |
| }; | |
| }; | |
| lane_3_params { | |
| rx { | |
| override = "disabled"; | |
| }; | |
| tx { | |
| override = "disabled"; | |
| }; | |
| }; | |
| lane_0_params { | |
| rx { | |
| override = "disabled"; | |
| }; | |
| tx { | |
| override = "disabled"; | |
| }; | |
| }; | |
| lane_2_params { | |
| rx { | |
| override = "disabled"; | |
| }; | |
| tx { | |
| override = "disabled"; | |
| }; | |
| }; | |
| }; | |
| }; | |
| }; | |
| nor_flash { | |
| reg = <0x0 0xf4000000 0x0 0x4000000>; | |
| device-width = <0x1>; | |
| bank-width = <0x1>; | |
| compatible = "cfi-flash"; | |
| status = "disabled"; | |
| }; | |
| pcie-internal-3-10-20 { | |
| compatible = "annapurna-labs,al-internal-pcie"; | |
| bus-range = <0x0 0x0>; | |
| device_type = "pci"; | |
| #interrupt-cells = <0x1>; | |
| ranges = <0x0 0x0 0xfbc00000 0x0 0xfbc00000 0x0 0x100000 0x2000000 0x0 0xfe000000 0x0 0xfe000000 0x0 0x1000000>; | |
| #address-cells = <0x3>; | |
| interrupt-map = <0x4000 0x0 0x0 0x1 0x2 0x0 0x2b 0x4 0x4800 0x0 0x0 0x1 0x2 0x0 0x2c 0x4>; | |
| interrupt-map-mask = <0xf800 0x0 0x0 0x7>; | |
| #size-cells = <0x2>; | |
| interrupt-parent = <0x2>; | |
| }; | |
| pcie-external0 { | |
| reg = <0x0 0xfd800000 0x0 0x20000>; | |
| msi-parent = <0x6>; | |
| reg-names = "ecam"; | |
| compatible = "annapurna-labs,alpine-external-pcie"; | |
| cfg-space-offset = <0x2000>; | |
| bus-range = <0x0 0xff>; | |
| device_type = "pci"; | |
| #interrupt-cells = <0x1>; | |
| ranges = <0x0 0x0 0xfb600000 0x0 0xfb600000 0x0 0x200000 0x1000000 0x0 0x10000 0x0 0xe0000000 0x0 0x10000 0x2000000 0x0 0xe0010000 0x0 0xe0010000 0x0 0x7ff0000>; | |
| #address-cells = <0x3>; | |
| interrupt-map = <0x0 0x0 0x0 0x1 0x1 0x0 0x29 0x4>; | |
| interrupt-map-mask = <0x0 0x0 0x0 0x7>; | |
| #size-cells = <0x2>; | |
| interrupt-parent = <0x2>; | |
| }; | |
| pcie-external1 { | |
| reg = <0x0 0xfd820000 0x0 0x20000>; | |
| msi-parent = <0x6>; | |
| reg-names = "ecam"; | |
| compatible = "annapurna-labs,alpine-external-pcie"; | |
| cfg-space-offset = <0x2000>; | |
| bus-range = <0x0 0xff>; | |
| device_type = "pci"; | |
| #interrupt-cells = <0x1>; | |
| ranges = <0x0 0x0 0xfb800000 0x0 0xfb800000 0x0 0x200000 0x1000000 0x0 0x20000 0x0 0xe8000000 0x0 0x10000 0x2000000 0x0 0xe8010000 0x0 0xe8010000 0x0 0x3ff0000>; | |
| #address-cells = <0x3>; | |
| interrupt-map = <0x0 0x0 0x0 0x1 0x1 0x0 0x2a 0x4>; | |
| interrupt-map-mask = <0x0 0x0 0x0 0x7>; | |
| #size-cells = <0x2>; | |
| interrupt-parent = <0x2>; | |
| }; | |
| pcie-external2 { | |
| reg = <0x0 0xfd840000 0x0 0x20000>; | |
| msi-parent = <0x6>; | |
| reg-names = "ecam"; | |
| compatible = "annapurna-labs,alpine-external-pcie"; | |
| cfg-space-offset = <0x2000>; | |
| bus-range = <0x0 0xff>; | |
| device_type = "pci"; | |
| #interrupt-cells = <0x1>; | |
| ranges = <0x0 0x0 0xfba00000 0x0 0xfba00000 0x0 0x200000 0x1000000 0x0 0x30000 0x0 0xec000000 0x0 0x10000 0x2000000 0x0 0xec010000 0x0 0xec010000 0x0 0x3ff0000>; | |
| status = "disabled"; | |
| #address-cells = <0x3>; | |
| interrupt-map = <0x0 0x0 0x0 0x1 0x1 0x0 0x2b 0x4>; | |
| interrupt-map-mask = <0x0 0x0 0x0 0x7>; | |
| #size-cells = <0x2>; | |
| interrupt-parent = <0x2>; | |
| }; | |
| }; | |
| cpus { | |
| enable-method = "al,alpine-smp"; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| cpu@0 { | |
| reg = <0x0>; | |
| compatible = "arm,cortex-a15"; | |
| clock-names = "cpu"; | |
| clock-frequency = "SrN"; | |
| device_type = "cpu"; | |
| clocks = <0x1>; | |
| }; | |
| cpu@1 { | |
| reg = <0x1>; | |
| compatible = "arm,cortex-a15"; | |
| clock-names = "cpu"; | |
| clock-frequency = "SrN"; | |
| device_type = "cpu"; | |
| clocks = <0x1>; | |
| }; | |
| cpu@2 { | |
| reg = <0x2>; | |
| compatible = "arm,cortex-a15"; | |
| clock-names = "cpu"; | |
| clock-frequency = "SrN"; | |
| device_type = "cpu"; | |
| clocks = <0x1>; | |
| }; | |
| cpu@3 { | |
| reg = <0x3>; | |
| compatible = "arm,cortex-a15"; | |
| clock-names = "cpu"; | |
| clock-frequency = "SrN"; | |
| device_type = "cpu"; | |
| clocks = <0x1>; | |
| }; | |
| }; | |
| leds { | |
| compatible = "gpio-leds"; | |
| power-led { | |
| gpios = <0xe 0x1 0x0>; | |
| label = "pwr"; | |
| default-state = "keep"; | |
| }; | |
| backup-led { | |
| gpios = <0xc 0x4 0x0>; | |
| label = "backup"; | |
| default-state = "off"; | |
| }; | |
| act-led { | |
| gpios = <0xe 0x2 0x0>; | |
| label = "act"; | |
| default-state = "off"; | |
| }; | |
| sata1-led { | |
| gpios = <0xd 0x4 0x0>; | |
| label = "sata1"; | |
| default-state = "keep"; | |
| }; | |
| sata2-led { | |
| gpios = <0xd 0x5 0x0>; | |
| label = "sata2"; | |
| default-state = "keep"; | |
| }; | |
| sata3-led { | |
| gpios = <0xd 0x6 0x0>; | |
| label = "sata3"; | |
| default-state = "keep"; | |
| }; | |
| sata4-led { | |
| gpios = <0xd 0x7 0x0>; | |
| label = "sata4"; | |
| default-state = "keep"; | |
| }; | |
| }; | |
| readynas_lcd { | |
| compatible = "readynas-lcd"; | |
| lcd-device = <0x10>; | |
| }; | |
| chosen { | |
| linux,initrd-end = <0x1b38573>; | |
| bootargs = "rootdelay=4 console=ttyS0,115200 pci=pcie_bus_perf root=UUID=a0027444-4343-4d80-afd0-ae64504cf887"; | |
| linux,initrd-start = <0x1633000>; | |
| }; | |
| gpio_keys { | |
| compatible = "gpio-keys"; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| button@1 { | |
| gpios = <0xf 0x3 0x0>; | |
| label = "Power Button"; | |
| linux,code = <0x74>; | |
| }; | |
| button@2 { | |
| gpios = <0xf 0x4 0x1>; | |
| label = "Reset Button"; | |
| linux,code = <0x198>; | |
| }; | |
| button@3 { | |
| gpios = <0xe 0x0 0x1>; | |
| label = "Backup Button"; | |
| linux,code = <0x85>; | |
| }; | |
| }; | |
| memory { | |
| reg = <0x0 0x0 0x0 0x20000000 0x0 0x20000000 0x0 0x20000000 0x0 0x40000000 0x0 0x20000000 0x0 0x60000000 0x0 0x20000000>; | |
| device_type = "memory"; | |
| }; | |
| aliases { | |
| }; | |
| gpio_lcd { | |
| lcm-bits = <0xe 0x4 0x0 0xe 0x5 0x0 0xe 0x6 0x0 0xe 0x7 0x0>; | |
| compatible = "gpio-lcd"; | |
| lcm-data-4bit; | |
| lcm-lines = <0x2>; | |
| lcm-bl = <0xf 0x0 0x0>; | |
| lcm-en = <0xf 0x2 0x0>; | |
| lcm-rs = <0xe 0x3 0x0>; | |
| lcm-rw = <0xf 0x1 0x0>; | |
| phandle = <0x10>; | |
| linux,phandle = <0x10>; | |
| }; | |
| gpio_pwr { | |
| gpios = <0xc 0x7 0x0>; | |
| compatible = "gpio-power-off"; | |
| }; | |
| }; |
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| /dts-v1/; | |
| // magic: 0xd00dfeed | |
| // totalsize: 0x6080 (24704) | |
| // off_dt_struct: 0x68 | |
| // off_dt_strings: 0x58e8 | |
| // off_mem_rsvmap: 0x28 | |
| // version: 17 | |
| // last_comp_version: 16 | |
| // boot_cpuid_phys: 0x0 | |
| // size_dt_strings: 0x411 | |
| // size_dt_struct: 0x5880 | |
| /memreserve/ 0 0x100000; | |
| /memreserve/ 0x7000000 0x6000; | |
| /memreserve/ 0x1633000 0x505573; | |
| / { | |
| #address-cells = <0x00000002>; | |
| #size-cells = <0x00000002>; | |
| compatible = "annapurna-labs,alpine", "al,alpine", "netgear,readynas-20x", "netgear,readynas-204"; | |
| clock-ranges; | |
| version = "2.5"; | |
| chosen { | |
| linux,initrd-end = <0x01b38573>; | |
| linux,initrd-start = <0x01633000>; | |
| bootargs = "rootdelay=4 console=ttyS0,115200 pci=pcie_bus_perf root=UUID=a0027444-4343-4d80-afd0-ae64504cf887"; | |
| }; | |
| aliases { | |
| }; | |
| memory { | |
| device_type = "memory"; | |
| reg = <0x00000000 0x00000000 0x00000000 0x20000000 0x00000000 0x20000000 0x00000000 0x20000000 0x00000000 0x40000000 0x00000000 0x20000000 0x00000000 0x60000000 0x00000000 0x20000000>; | |
| }; | |
| cpus { | |
| #address-cells = <0x00000001>; | |
| #size-cells = <0x00000000>; | |
| enable-method = "al,alpine-smp"; | |
| cpu@0 { | |
| compatible = "arm,cortex-a15"; | |
| device_type = "cpu"; | |
| reg = <0x00000000>; | |
| clocks = <0x00000001>; | |
| clock-names = "cpu"; | |
| clock-frequency = "SrN"; | |
| }; | |
| cpu@1 { | |
| compatible = "arm,cortex-a15"; | |
| device_type = "cpu"; | |
| reg = <0x00000001>; | |
| clocks = <0x00000001>; | |
| clock-names = "cpu"; | |
| clock-frequency = "SrN"; | |
| }; | |
| cpu@2 { | |
| compatible = "arm,cortex-a15"; | |
| device_type = "cpu"; | |
| reg = <0x00000002>; | |
| clocks = <0x00000001>; | |
| clock-names = "cpu"; | |
| clock-frequency = "SrN"; | |
| }; | |
| cpu@3 { | |
| compatible = "arm,cortex-a15"; | |
| device_type = "cpu"; | |
| reg = <0x00000003>; | |
| clocks = <0x00000001>; | |
| clock-names = "cpu"; | |
| clock-frequency = "SrN"; | |
| }; | |
| }; | |
| soc { | |
| #address-cells = <0x00000002>; | |
| #size-cells = <0x00000002>; | |
| compatible = "simple-bus"; | |
| interrupt-parent = <0x00000002>; | |
| ranges; | |
| arch-timer { | |
| compatible = "arm,cortex-a15-timer", "arm,armv7-timer"; | |
| interrupts = <0x00000001 0x0000000d 0x00000f08 0x00000001 0x0000000e 0x00000f08 0x00000001 0x0000000b 0x00000f08 0x00000001 0x0000000a 0x00000f08>; | |
| clock-frequency = <0x02faf080>; | |
| }; | |
| gic_main { | |
| compatible = "arm,cortex-a15-gic"; | |
| #interrupt-cells = <0x00000003>; | |
| #size-cells = <0x00000000>; | |
| #address-cells = <0x00000000>; | |
| interrupt-controller; | |
| reg = <0x00000000 0xfb001000 0x00000000 0x00001000 0x00000000 0xfb002000 0x00000000 0x00002000 0x00000000 0xfb004000 0x00000000 0x00001000 0x00000000 0xfb006000 0x00000000 0x00002000>; | |
| interrupts = <0x00000001 0x00000009 0x00000f04>; | |
| linux,phandle = <0x00000002>; | |
| phandle = <0x00000002>; | |
| }; | |
| cpu_resume { | |
| compatible = "annapurna-labs,al-cpu-resume", "al,alpine-cpu-resume"; | |
| reg = <0x00000000 0xfbff5ec0 0x00000000 0x00000030>; | |
| }; | |
| ccu { | |
| compatible = "annapurna-labs,al-ccu", "al,alpine-ccu"; | |
| reg = <0x00000000 0xfb090000 0x00000000 0x00010000>; | |
| io_coherency = <0x00000001>; | |
| }; | |
| nb_service { | |
| compatible = "annapurna-labs,al-nb-service", "al,alpine-sysfabric-service", "syscon"; | |
| reg = <0x00000000 0xfb070000 0x00000000 0x00010000>; | |
| interrupts = <0x00000000 0x00000040 0x00000004 0x00000000 0x00000041 0x00000004 0x00000000 0x00000042 0x00000004 0x00000000 0x00000043 0x00000004>; | |
| dev_ord_relax = <0x00000000>; | |
| }; | |
| pbs { | |
| compatible = "annapurna-labs,al-pbs"; | |
| reg = <0x00000000 0xfd8a8000 0x00000000 0x00001000>; | |
| }; | |
| msix { | |
| compatible = "annapurna-labs,al-msix", "annapurna-labs,alpine-msix"; | |
| reg = <0x00000000 0xfbe00000 0x00000000 0x00100000>; | |
| interrupts = <0x00000000 0x00000060 0x00000001 0x00000000 0x0000009f 0x00000001>; | |
| interrupt-controller; | |
| msi-controller; | |
| interrupt-parent = <0x00000002>; | |
| linux,phandle = <0x00000006>; | |
| phandle = <0x00000006>; | |
| }; | |
| pmu { | |
| compatible = "arm,cortex-a15-pmu"; | |
| interrupts = <0x00000000 0x00000044 0x00000004 0x00000000 0x00000045 0x00000004 0x00000000 0x00000046 0x00000004 0x00000000 0x00000047 0x00000004>; | |
| }; | |
| timer0 { | |
| compatible = "arm,sp804", "arm,primecell"; | |
| reg = <0x00000000 0xfd890000 0x00000000 0x00001000>; | |
| interrupts = <0x00000000 0x00000009 0x00000004>; | |
| clocks = <0x00000003>; | |
| clock-names = "sbclk"; | |
| status = "disabled"; | |
| }; | |
| timer1 { | |
| compatible = "arm,sp804", "arm,primecell"; | |
| reg = <0x00000000 0xfd891000 0x00000000 0x00001000>; | |
| interrupts = <0x00000000 0x0000000a 0x00000004>; | |
| clocks = <0x00000003>; | |
| clock-names = "sbclk"; | |
| status = "disabled"; | |
| }; | |
| timer2 { | |
| compatible = "arm,sp804", "arm,primecell"; | |
| reg = <0x00000000 0xfd892000 0x00000000 0x00001000>; | |
| interrupts = <0x00000000 0x0000000b 0x00000004>; | |
| clocks = <0x00000003>; | |
| clock-names = "sbclk"; | |
| status = "disabled"; | |
| }; | |
| timer3 { | |
| compatible = "arm,sp804", "arm,primecell"; | |
| reg = <0x00000000 0xfd893000 0x00000000 0x00001000>; | |
| interrupts = <0x00000000 0x0000000c 0x00000004>; | |
| clocks = <0x00000003>; | |
| clock-names = "sbclk"; | |
| status = "disabled"; | |
| }; | |
| wdt0 { | |
| compatible = "arm,sp805", "arm,primecell"; | |
| reg = <0x00000000 0xfd88c000 0x00000000 0x00001000>; | |
| interrupts = <0x00000000 0x0000000d 0x00000004>; | |
| clocks = <0x00000003>; | |
| clock-names = "apb_pclk"; | |
| linux,phandle = <0x00000005>; | |
| phandle = <0x00000005>; | |
| }; | |
| wdt1 { | |
| compatible = "arm,sp805", "arm,primecell"; | |
| reg = <0x00000000 0xfd88d000 0x00000000 0x00001000>; | |
| interrupts = <0x00000000 0x0000000e 0x00000004>; | |
| clocks = <0x00000003>; | |
| clock-names = "apb_pclk"; | |
| status = "disabled"; | |
| }; | |
| wdt2 { | |
| compatible = "arm,sp805", "arm,primecell"; | |
| reg = <0x00000000 0xfd88e000 0x00000000 0x00001000>; | |
| interrupts = <0x00000000 0x0000000f 0x00000004>; | |
| clocks = <0x00000003>; | |
| clock-names = "apb_pclk"; | |
| status = "disabled"; | |
| }; | |
| wdt3 { | |
| compatible = "arm,sp805", "arm,primecell"; | |
| reg = <0x00000000 0xfd88f000 0x00000000 0x00001000>; | |
| interrupts = <0x00000000 0x00000010 0x00000004>; | |
| clocks = <0x00000003>; | |
| clock-names = "apb_pclk"; | |
| status = "disabled"; | |
| }; | |
| i2c-pld { | |
| #address-cells = <0x00000001>; | |
| #size-cells = <0x00000000>; | |
| compatible = "snps,designware-i2c"; | |
| reg = <0x00000000 0xfd880000 0x00000000 0x00001000>; | |
| interrupts = <0x00000000 0x00000015 0x00000004>; | |
| clocks = <0x00000003>; | |
| clock-frequency = <0x00061a80>; | |
| i2c_mux@70 { | |
| compatible = "pca9548"; | |
| reg = <0x00000070>; | |
| }; | |
| rtc@68 { | |
| compatible = "ds1337"; | |
| reg = <0x00000068>; | |
| }; | |
| g762@3e { | |
| compatible = "gmt,g762"; | |
| reg = <0x0000003e>; | |
| clocks = <0x00000004>; | |
| fan_gear_mode = <0x00000000>; | |
| fan_startv = <0x00000003>; | |
| pwm_polarity = <0x00000000>; | |
| }; | |
| }; | |
| i2c-gen { | |
| #address-cells = <0x00000001>; | |
| #size-cells = <0x00000000>; | |
| compatible = "snps,designware-i2c"; | |
| reg = <0x00000000 0xfd894000 0x00000000 0x00001000>; | |
| interrupts = <0x00000000 0x00000008 0x00000004>; | |
| clocks = <0x00000003>; | |
| clock-frequency = <0x00061a80>; | |
| status = "disabled"; | |
| }; | |
| gpio0 { | |
| #gpio-cells = <0x00000002>; | |
| compatible = "arm,pl061", "arm,primecell"; | |
| gpio-controller; | |
| reg = <0x00000000 0xfd887000 0x00000000 0x00001000>; | |
| interrupts = <0x00000000 0x00000002 0x00000004>; | |
| clocks = <0x00000003>; | |
| clock-names = "apb_pclk"; | |
| baseidx = <0x00000000>; | |
| }; | |
| gpio1 { | |
| #gpio-cells = <0x00000002>; | |
| compatible = "arm,pl061", "arm,primecell"; | |
| gpio-controller; | |
| reg = <0x00000000 0xfd888000 0x00000000 0x00001000>; | |
| interrupts = <0x00000000 0x00000003 0x00000004>; | |
| clocks = <0x00000003>; | |
| clock-names = "apb_pclk"; | |
| baseidx = <0x00000008>; | |
| }; | |
| gpio2 { | |
| #gpio-cells = <0x00000002>; | |
| compatible = "arm,pl061", "arm,primecell"; | |
| gpio-controller; | |
| reg = <0x00000000 0xfd889000 0x00000000 0x00001000>; | |
| interrupts = <0x00000000 0x00000004 0x00000004>; | |
| clocks = <0x00000003>; | |
| clock-names = "apb_pclk"; | |
| baseidx = <0x00000010>; | |
| linux,phandle = <0x0000000d>; | |
| phandle = <0x0000000d>; | |
| }; | |
| gpio3 { | |
| #gpio-cells = <0x00000002>; | |
| compatible = "arm,pl061", "arm,primecell"; | |
| gpio-controller; | |
| reg = <0x00000000 0xfd88a000 0x00000000 0x00001000>; | |
| interrupts = <0x00000000 0x00000005 0x00000004>; | |
| clocks = <0x00000003>; | |
| clock-names = "apb_pclk"; | |
| baseidx = <0x00000018>; | |
| linux,phandle = <0x0000000c>; | |
| phandle = <0x0000000c>; | |
| }; | |
| gpio4 { | |
| #gpio-cells = <0x00000002>; | |
| compatible = "arm,pl061", "arm,primecell"; | |
| gpio-controller; | |
| reg = <0x00000000 0xfd88b000 0x00000000 0x00001000>; | |
| interrupts = <0x00000000 0x00000006 0x00000004>; | |
| clocks = <0x00000003>; | |
| clock-names = "apb_pclk"; | |
| baseidx = <0x00000020>; | |
| linux,phandle = <0x0000000e>; | |
| phandle = <0x0000000e>; | |
| }; | |
| gpio5 { | |
| #gpio-cells = <0x00000002>; | |
| compatible = "arm,pl061", "arm,primecell"; | |
| gpio-controller; | |
| reg = <0x00000000 0xfd897000 0x00000000 0x00001000>; | |
| interrupts = <0x00000000 0x00000007 0x00000004>; | |
| clocks = <0x00000003>; | |
| clock-names = "apb_pclk"; | |
| baseidx = <0x00000028>; | |
| linux,phandle = <0x0000000f>; | |
| phandle = <0x0000000f>; | |
| }; | |
| uart0 { | |
| compatible = "ns16550a"; | |
| reg = <0x00000000 0xfd883000 0x00000000 0x00001000>; | |
| clock-frequency = <0x165a0bc0>; | |
| interrupts = <0x00000000 0x00000011 0x00000004>; | |
| reg-shift = <0x00000002>; | |
| reg-io-width = <0x00000004>; | |
| }; | |
| uart1 { | |
| compatible = "ns16550a"; | |
| reg = <0x00000000 0xfd884000 0x00000000 0x00001000>; | |
| clock-frequency = <0x165a0bc0>; | |
| interrupts = <0x00000000 0x00000012 0x00000004>; | |
| reg-shift = <0x00000002>; | |
| reg-io-width = <0x00000004>; | |
| }; | |
| uart2 { | |
| compatible = "ns16550a"; | |
| reg = <0x00000000 0xfd885000 0x00000000 0x00001000>; | |
| clock-frequency = <0x165a0bc0>; | |
| interrupts = <0x00000000 0x00000013 0x00000004>; | |
| reg-shift = <0x00000002>; | |
| reg-io-width = <0x00000004>; | |
| status = "disabled"; | |
| }; | |
| uart3 { | |
| compatible = "ns16550a"; | |
| reg = <0x00000000 0xfd886000 0x00000000 0x00001000>; | |
| clock-frequency = <0x165a0bc0>; | |
| interrupts = <0x00000000 0x00000014 0x00000004>; | |
| reg-shift = <0x00000002>; | |
| reg-io-width = <0x00000004>; | |
| status = "disabled"; | |
| }; | |
| reboot { | |
| compatible = "annapurna-labs,alpine-reboot"; | |
| wdt-parent = <0x00000005>; | |
| }; | |
| pcie-internal-3-10-20 { | |
| compatible = "annapurna-labs,al-internal-pcie"; | |
| device_type = "pci"; | |
| #size-cells = <0x00000002>; | |
| #address-cells = <0x00000003>; | |
| #interrupt-cells = <0x00000001>; | |
| interrupt-parent = <0x00000002>; | |
| interrupt-map-mask = <0x0000f800 0x00000000 0x00000000 0x00000007>; | |
| interrupt-map = <0x00004000 0x00000000 0x00000000 0x00000001 0x00000002 0x00000000 0x0000002b 0x00000004 0x00004800 0x00000000 0x00000000 0x00000001 0x00000002 0x00000000 0x0000002c 0x00000004>; | |
| ranges = <0x00000000 0x00000000 0xfbc00000 0x00000000 0xfbc00000 0x00000000 0x00100000 0x02000000 0x00000000 0xfe000000 0x00000000 0xfe000000 0x00000000 0x01000000>; | |
| bus-range = <0x00000000 0x00000000>; | |
| }; | |
| pcie-internal-3-19 { | |
| compatible = "annapurna-labs,alpine-internal-pcie"; | |
| device_type = "pci"; | |
| #size-cells = <0x00000002>; | |
| #address-cells = <0x00000003>; | |
| #interrupt-cells = <0x00000001>; | |
| reg = <0x00000000 0xfbc00000 0x00000000 0x00100000>; | |
| reg-names = "ecam"; | |
| interrupt-parent = <0x00000002>; | |
| interrupt-map-mask = <0x0000f800 0x00000000 0x00000000 0x00000007>; | |
| interrupt-map = <0x00004000 0x00000000 0x00000000 0x00000001 0x00000002 0x00000000 0x0000002b 0x00000004 0x00004800 0x00000000 0x00000000 0x00000001 0x00000002 0x00000000 0x0000002c 0x00000004>; | |
| msi-parent = <0x00000006>; | |
| ranges = <0x00000000 0x00000000 0xfbc00000 0x00000000 0xfbc00000 0x00000000 0x00100000 0x02000000 0x00000000 0xfe000000 0x00000000 0xfe000000 0x00000000 0x01000000>; | |
| bus-range = <0x00000000 0x00000000>; | |
| }; | |
| pcie-external0 { | |
| compatible = "annapurna-labs,alpine-external-pcie"; | |
| reg = <0x00000000 0xfd800000 0x00000000 0x00020000>; | |
| device_type = "pci"; | |
| #size-cells = <0x00000002>; | |
| #address-cells = <0x00000003>; | |
| #interrupt-cells = <0x00000001>; | |
| reg-names = "ecam"; | |
| interrupt-parent = <0x00000002>; | |
| interrupt-map-mask = <0x00000000 0x00000000 0x00000000 0x00000007>; | |
| interrupt-map = <0x00000000 0x00000000 0x00000000 0x00000001 0x00000001 0x00000000 0x00000029 0x00000004>; | |
| msi-parent = <0x00000006>; | |
| cfg-space-offset = <0x00002000>; | |
| ranges = <0x00000000 0x00000000 0xfb600000 0x00000000 0xfb600000 0x00000000 0x00200000 0x01000000 0x00000000 0x00010000 0x00000000 0xe0000000 0x00000000 0x00010000 0x02000000 0x00000000 0xe0010000 0x00000000 0xe0010000 0x00000000 0x07ff0000>; | |
| bus-range = <0x00000000 0x000000ff>; | |
| }; | |
| pcie-external1 { | |
| compatible = "annapurna-labs,alpine-external-pcie"; | |
| reg = <0x00000000 0xfd820000 0x00000000 0x00020000>; | |
| device_type = "pci"; | |
| #size-cells = <0x00000002>; | |
| #address-cells = <0x00000003>; | |
| #interrupt-cells = <0x00000001>; | |
| reg-names = "ecam"; | |
| interrupt-parent = <0x00000002>; | |
| interrupt-map-mask = <0x00000000 0x00000000 0x00000000 0x00000007>; | |
| interrupt-map = <0x00000000 0x00000000 0x00000000 0x00000001 0x00000001 0x00000000 0x0000002a 0x00000004>; | |
| msi-parent = <0x00000006>; | |
| cfg-space-offset = <0x00002000>; | |
| ranges = <0x00000000 0x00000000 0xfb800000 0x00000000 0xfb800000 0x00000000 0x00200000 0x01000000 0x00000000 0x00020000 0x00000000 0xe8000000 0x00000000 0x00010000 0x02000000 0x00000000 0xe8010000 0x00000000 0xe8010000 0x00000000 0x03ff0000>; | |
| bus-range = <0x00000000 0x000000ff>; | |
| }; | |
| pcie-external2 { | |
| status = "disabled"; | |
| compatible = "annapurna-labs,alpine-external-pcie"; | |
| reg = <0x00000000 0xfd840000 0x00000000 0x00020000>; | |
| device_type = "pci"; | |
| #size-cells = <0x00000002>; | |
| #address-cells = <0x00000003>; | |
| #interrupt-cells = <0x00000001>; | |
| reg-names = "ecam"; | |
| interrupt-parent = <0x00000002>; | |
| interrupt-map-mask = <0x00000000 0x00000000 0x00000000 0x00000007>; | |
| interrupt-map = <0x00000000 0x00000000 0x00000000 0x00000001 0x00000001 0x00000000 0x0000002b 0x00000004>; | |
| msi-parent = <0x00000006>; | |
| cfg-space-offset = <0x00002000>; | |
| ranges = <0x00000000 0x00000000 0xfba00000 0x00000000 0xfba00000 0x00000000 0x00200000 0x01000000 0x00000000 0x00030000 0x00000000 0xec000000 0x00000000 0x00010000 0x02000000 0x00000000 0xec010000 0x00000000 0xec010000 0x00000000 0x03ff0000>; | |
| bus-range = <0x00000000 0x000000ff>; | |
| }; | |
| pcie-external0-3-10 { | |
| compatible = "annapurna-labs,al-pci"; | |
| reg = <0x00000000 0xfd800000 0x00000000 0x00020000>; | |
| device_type = "pci"; | |
| #size-cells = <0x00000002>; | |
| #address-cells = <0x00000003>; | |
| #interrupt-cells = <0x00000001>; | |
| interrupt-parent = <0x00000002>; | |
| interrupt-map-mask = <0x00000000 0x00000000 0x00000000 0x00000007>; | |
| interrupt-map = <0x00000000 0x00000000 0x00000000 0x00000001 0x00000002 0x00000000 0x00000028 0x00000004>; | |
| ranges = <0x00000000 0x00000000 0xfb600000 0x00000000 0xfb600000 0x00000000 0x00200000 0x01000000 0x00000000 0x00010000 0x00000000 0xe0000000 0x00000000 0x00010000 0x02000000 0x00000000 0xe0010000 0x00000000 0xe0010000 0x00000000 0x07ff0000>; | |
| bus-range = <0x00000000 0x000000ff>; | |
| }; | |
| pcie-external1-3-10 { | |
| compatible = "annapurna-labs,al-pci"; | |
| reg = <0x00000000 0xfd820000 0x00000000 0x00020000>; | |
| device_type = "pci"; | |
| #size-cells = <0x00000002>; | |
| #address-cells = <0x00000003>; | |
| #interrupt-cells = <0x00000001>; | |
| interrupt-parent = <0x00000002>; | |
| interrupt-map-mask = <0x00000000 0x00000000 0x00000000 0x00000007>; | |
| interrupt-map = <0x00000000 0x00000000 0x00000000 0x00000001 0x00000002 0x00000000 0x00000029 0x00000004>; | |
| ranges = <0x00000000 0x00000000 0xfb800000 0x00000000 0xfb800000 0x00000000 0x00200000 0x01000000 0x00000000 0x00020000 0x00000000 0xe8000000 0x00000000 0x00010000 0x02000000 0x00000000 0xe8010000 0x00000000 0xe8010000 0x00000000 0x03ff0000>; | |
| bus-range = <0x00000000 0x000000ff>; | |
| }; | |
| pcie-external2-3-10 { | |
| compatible = "annapurna-labs,al-pci"; | |
| reg = <0x00000000 0xfd840000 0x00000000 0x00020000>; | |
| device_type = "pci"; | |
| #size-cells = <0x00000002>; | |
| #address-cells = <0x00000003>; | |
| #interrupt-cells = <0x00000001>; | |
| interrupt-parent = <0x00000002>; | |
| interrupt-map-mask = <0x00000000 0x00000000 0x00000000 0x00000007>; | |
| interrupt-map = <0x00000000 0x00000000 0x00000000 0x00000001 0x00000002 0x00000000 0x0000002a 0x00000004>; | |
| ranges = <0x00000000 0x00000000 0xfba00000 0x00000000 0xfba00000 0x00000000 0x00200000 0x01000000 0x00000000 0x00030000 0x00000000 0xec000000 0x00000000 0x00010000 0x02000000 0x00000000 0xec010000 0x00000000 0xec010000 0x00000000 0x03ff0000>; | |
| bus-range = <0x00000000 0x000000ff>; | |
| }; | |
| thermal { | |
| compatible = "annapurna-labs,al-thermal"; | |
| reg = <0x00000000 0xfd860a00 0x00000000 0x00000100>; | |
| }; | |
| nor_flash { | |
| compatible = "cfi-flash"; | |
| reg = <0x00000000 0xf4000000 0x00000000 0x04000000>; | |
| bank-width = <0x00000001>; | |
| device-width = <0x00000001>; | |
| status = "disabled"; | |
| }; | |
| nand-flash { | |
| compatible = "annapurna-labs,al-nand"; | |
| reg = <0x00000000 0xfa100000 0x00000000 0x00202000>; | |
| interrupts = <0x00000000 0x00000001 0x00000004>; | |
| #address-cells = <0x00000001>; | |
| #size-cells = <0x00000001>; | |
| partition@0 { | |
| label = "u-boot"; | |
| reg = <0x00000000 0x001c0000>; | |
| }; | |
| partition@1 { | |
| label = "u-boot-env"; | |
| reg = <0x001c0000 0x00040000>; | |
| }; | |
| partition@2 { | |
| label = "uImage"; | |
| reg = <0x00200000 0x00600000>; | |
| }; | |
| partition@3 { | |
| label = "minirootfs"; | |
| reg = <0x00800000 0x00400000>; | |
| }; | |
| partition@4 { | |
| label = "ubifs"; | |
| reg = <0x00c00000 0x06400000>; | |
| }; | |
| partition@5 { | |
| label = "dts"; | |
| reg = <0x00080000 0x00020000>; | |
| }; | |
| partition@6 { | |
| label = "factory-diag"; | |
| reg = <0x07000000 0x01000000>; | |
| }; | |
| }; | |
| spi-3-10-20 { | |
| compatible = "snps,dw-spi-mmio"; | |
| #address-cells = <0x00000001>; | |
| #size-cells = <0x00000000>; | |
| reg = <0x00000000 0xfd882000 0x00000000 0x00001000>; | |
| interrupts = <0x00000000 0x00000017 0x00000004>; | |
| num-chipselect = <0x00000004>; | |
| bus-num = <0x00000000>; | |
| clocks = <0x00000003>; | |
| clock-names = "sbclk"; | |
| }; | |
| spi { | |
| compatible = "snps,dw-apb-ssi"; | |
| #address-cells = <0x00000001>; | |
| #size-cells = <0x00000000>; | |
| reg = <0x00000000 0xfd882000 0x00000000 0x00001000>; | |
| interrupts = <0x00000000 0x00000017 0x00000004>; | |
| num-cs = <0x00000004>; | |
| bus-num = <0x00000000>; | |
| clocks = <0x00000003>; | |
| clock-names = "sbclk"; | |
| status = "disabled"; | |
| }; | |
| clocks { | |
| #address-cells = <0x00000001>; | |
| #size-cells = <0x00000000>; | |
| refclk { | |
| #clock-cells = <0x00000000>; | |
| compatible = "fixed-clock"; | |
| clock-frequency = <0x05f5e100>; | |
| }; | |
| sbclk { | |
| #clock-cells = <0x00000000>; | |
| compatible = "fixed-clock"; | |
| clock-frequency = <0x165a0bc0>; | |
| linux,phandle = <0x00000003>; | |
| phandle = <0x00000003>; | |
| }; | |
| nbclk { | |
| #clock-cells = <0x00000000>; | |
| compatible = "fixed-clock"; | |
| clock-frequency = <0x2faf0800>; | |
| }; | |
| cpuclk { | |
| #clock-cells = <0x00000000>; | |
| compatible = "fixed-clock"; | |
| clock-frequency = "SrN"; | |
| linux,phandle = <0x00000001>; | |
| phandle = <0x00000001>; | |
| }; | |
| fixedclk { | |
| #clock-cells = <0x00000000>; | |
| compatible = "fixed-clock"; | |
| clock-frequency = <0x00001964>; | |
| linux,phandle = <0x00000004>; | |
| phandle = <0x00000004>; | |
| }; | |
| }; | |
| serdes { | |
| compatible = "annapurna-labs,al-serdes"; | |
| reg = <0x00000000 0xfd8c0000 0x00000000 0x00001000>; | |
| }; | |
| mc { | |
| compatible = "annapurna-labs,al-mc"; | |
| reg = <0x00000000 0xfb080000 0x00000000 0x00010000>; | |
| }; | |
| pinctrl { | |
| compatible = "annapurna-labs,al-pinctrl"; | |
| reg = <0x00000000 0xfd8a8000 0x00000000 0x00001000>; | |
| if_nor_8 { | |
| id = "if_nor_8"; | |
| arg = <0x00000000>; | |
| }; | |
| if_nor_16 { | |
| id = "if_nor_16"; | |
| arg = <0x00000000>; | |
| }; | |
| if_nor_cs_0 { | |
| id = "if_nor_cs_0"; | |
| arg = <0x00000000>; | |
| }; | |
| if_nor_cs_1 { | |
| id = "if_nor_cs_1"; | |
| arg = <0x00000000>; | |
| }; | |
| if_nor_cs_2 { | |
| id = "if_nor_cs_2"; | |
| arg = <0x00000000>; | |
| }; | |
| if_nor_cs_3 { | |
| id = "if_nor_cs_3"; | |
| arg = <0x00000000>; | |
| }; | |
| if_nor_wp { | |
| id = "if_nor_wp"; | |
| arg = <0x00000000>; | |
| }; | |
| if_nand_8 { | |
| id = "if_nand_8"; | |
| arg = <0x00000000>; | |
| linux,phandle = <0x00000007>; | |
| phandle = <0x00000007>; | |
| }; | |
| if_nand_16 { | |
| id = "if_nand_16"; | |
| arg = <0x00000000>; | |
| }; | |
| if_nand_cs_0 { | |
| id = "if_nand_cs_0"; | |
| arg = <0x00000000>; | |
| linux,phandle = <0x00000008>; | |
| phandle = <0x00000008>; | |
| }; | |
| if_nand_cs_1 { | |
| id = "if_nand_cs_1"; | |
| arg = <0x00000000>; | |
| }; | |
| if_nand_cs_2 { | |
| id = "if_nand_cs_2"; | |
| arg = <0x00000000>; | |
| }; | |
| if_nand_cs_3 { | |
| id = "if_nand_cs_3"; | |
| arg = <0x00000000>; | |
| }; | |
| if_nand_wp { | |
| id = "if_nand_wp"; | |
| arg = <0x00000000>; | |
| }; | |
| if_sram_8 { | |
| id = "if_sram_8"; | |
| arg = <0x00000000>; | |
| }; | |
| if_sram_16 { | |
| id = "if_sram_16"; | |
| arg = <0x00000000>; | |
| }; | |
| if_sram_cs_0 { | |
| id = "if_sram_cs_0"; | |
| arg = <0x00000000>; | |
| }; | |
| if_sram_cs_1 { | |
| id = "if_sram_cs_1"; | |
| arg = <0x00000000>; | |
| }; | |
| if_sram_cs_2 { | |
| id = "if_sram_cs_2"; | |
| arg = <0x00000000>; | |
| }; | |
| if_sram_cs_3 { | |
| id = "if_sram_cs_3"; | |
| arg = <0x00000000>; | |
| }; | |
| if_sata_0_leds { | |
| id = "if_sata_0_leds"; | |
| arg = <0x00000000>; | |
| }; | |
| if_sata_1_leds { | |
| id = "if_sata_1_leds"; | |
| arg = <0x00000000>; | |
| linux,phandle = <0x00000009>; | |
| phandle = <0x00000009>; | |
| }; | |
| if_eth_leds { | |
| id = "if_eth_leds"; | |
| arg = <0x00000000>; | |
| linux,phandle = <0x0000000a>; | |
| phandle = <0x0000000a>; | |
| }; | |
| if_eth_gpio { | |
| id = "if_eth_gpio"; | |
| arg = <0x00000000>; | |
| }; | |
| if_uart_1 { | |
| id = "if_uart_1"; | |
| arg = <0x00000000>; | |
| linux,phandle = <0x0000000b>; | |
| phandle = <0x0000000b>; | |
| }; | |
| if_uart_1_modem { | |
| id = "if_uart_1_modem"; | |
| arg = <0x00000000>; | |
| }; | |
| if_uart_2 { | |
| id = "if_uart_2"; | |
| arg = <0x00000000>; | |
| }; | |
| if_uart_3 { | |
| id = "if_uart_3"; | |
| arg = <0x00000000>; | |
| }; | |
| if_i2c_gen { | |
| id = "if_i2c_gen"; | |
| arg = <0x00000000>; | |
| }; | |
| if_ulpi_0_rst_n { | |
| id = "if_ulpi_0_rst_n"; | |
| arg = <0x00000000>; | |
| }; | |
| if_ulpi_1_rst_n { | |
| id = "if_ulpi_1_rst_n"; | |
| arg = <0x00000000>; | |
| }; | |
| if_pci_ep_int_a { | |
| id = "if_pci_ep_int_a"; | |
| arg = <0x00000000>; | |
| }; | |
| if_pci_ep_reset_out { | |
| id = "if_pci_ep_reset_out"; | |
| arg = <0x00000000>; | |
| }; | |
| if_spim_a_ss_1 { | |
| id = "if_spim_a_ss_1"; | |
| arg = <0x00000000>; | |
| }; | |
| if_spim_a_ss_2 { | |
| id = "if_spim_a_ss_2"; | |
| arg = <0x00000000>; | |
| }; | |
| if_spim_a_ss_3 { | |
| id = "if_spim_a_ss_3"; | |
| arg = <0x00000000>; | |
| }; | |
| if_ulpi_1_b { | |
| id = "if_ulpi_1_b"; | |
| arg = <0x00000000>; | |
| }; | |
| if_gpio0 { | |
| id = "if_gpio"; | |
| arg = <0x00000000>; | |
| }; | |
| if_gpio1 { | |
| id = "if_gpio"; | |
| arg = <0x00000001>; | |
| }; | |
| if_gpio2 { | |
| id = "if_gpio"; | |
| arg = <0x00000002>; | |
| }; | |
| if_gpio3 { | |
| id = "if_gpio"; | |
| arg = <0x00000003>; | |
| }; | |
| if_gpio4 { | |
| id = "if_gpio"; | |
| arg = <0x00000004>; | |
| }; | |
| if_gpio5 { | |
| id = "if_gpio"; | |
| arg = <0x00000005>; | |
| }; | |
| if_gpio6 { | |
| id = "if_gpio"; | |
| arg = <0x00000006>; | |
| }; | |
| if_gpio7 { | |
| id = "if_gpio"; | |
| arg = <0x00000007>; | |
| }; | |
| if_gpio8 { | |
| id = "if_gpio"; | |
| arg = <0x00000008>; | |
| }; | |
| if_gpio9 { | |
| id = "if_gpio"; | |
| arg = <0x00000009>; | |
| }; | |
| if_gpio10 { | |
| id = "if_gpio"; | |
| arg = <0x0000000a>; | |
| }; | |
| if_gpio11 { | |
| id = "if_gpio"; | |
| arg = <0x0000000b>; | |
| }; | |
| if_gpio12 { | |
| id = "if_gpio"; | |
| arg = <0x0000000c>; | |
| }; | |
| if_gpio13 { | |
| id = "if_gpio"; | |
| arg = <0x0000000d>; | |
| }; | |
| if_gpio14 { | |
| id = "if_gpio"; | |
| arg = <0x0000000e>; | |
| }; | |
| if_gpio15 { | |
| id = "if_gpio"; | |
| arg = <0x0000000f>; | |
| }; | |
| if_gpio16 { | |
| id = "if_gpio"; | |
| arg = <0x00000010>; | |
| }; | |
| if_gpio17 { | |
| id = "if_gpio"; | |
| arg = <0x00000011>; | |
| }; | |
| if_gpio18 { | |
| id = "if_gpio"; | |
| arg = <0x00000012>; | |
| }; | |
| if_gpio19 { | |
| id = "if_gpio"; | |
| arg = <0x00000013>; | |
| }; | |
| if_gpio20 { | |
| id = "if_gpio"; | |
| arg = <0x00000014>; | |
| }; | |
| if_gpio21 { | |
| id = "if_gpio"; | |
| arg = <0x00000015>; | |
| }; | |
| if_gpio22 { | |
| id = "if_gpio"; | |
| arg = <0x00000016>; | |
| }; | |
| if_gpio23 { | |
| id = "if_gpio"; | |
| arg = <0x00000017>; | |
| }; | |
| if_gpio24 { | |
| id = "if_gpio"; | |
| arg = <0x00000018>; | |
| }; | |
| if_gpio25 { | |
| id = "if_gpio"; | |
| arg = <0x00000019>; | |
| }; | |
| if_gpio26 { | |
| id = "if_gpio"; | |
| arg = <0x0000001a>; | |
| }; | |
| if_gpio27 { | |
| id = "if_gpio"; | |
| arg = <0x0000001b>; | |
| }; | |
| if_gpio28 { | |
| id = "if_gpio"; | |
| arg = <0x0000001c>; | |
| }; | |
| if_gpio29 { | |
| id = "if_gpio"; | |
| arg = <0x0000001d>; | |
| }; | |
| if_gpio30 { | |
| id = "if_gpio"; | |
| arg = <0x0000001e>; | |
| }; | |
| if_gpio31 { | |
| id = "if_gpio"; | |
| arg = <0x0000001f>; | |
| }; | |
| if_gpio32 { | |
| id = "if_gpio"; | |
| arg = <0x00000020>; | |
| }; | |
| if_gpio33 { | |
| id = "if_gpio"; | |
| arg = <0x00000021>; | |
| }; | |
| if_gpio34 { | |
| id = "if_gpio"; | |
| arg = <0x00000022>; | |
| }; | |
| if_gpio35 { | |
| id = "if_gpio"; | |
| arg = <0x00000023>; | |
| }; | |
| if_gpio36 { | |
| id = "if_gpio"; | |
| arg = <0x00000024>; | |
| }; | |
| if_gpio37 { | |
| id = "if_gpio"; | |
| arg = <0x00000025>; | |
| }; | |
| if_gpio38 { | |
| id = "if_gpio"; | |
| arg = <0x00000026>; | |
| }; | |
| if_gpio39 { | |
| id = "if_gpio"; | |
| arg = <0x00000027>; | |
| }; | |
| if_gpio40 { | |
| id = "if_gpio"; | |
| arg = <0x00000028>; | |
| }; | |
| if_gpio41 { | |
| id = "if_gpio"; | |
| arg = <0x00000029>; | |
| }; | |
| if_gpio42 { | |
| id = "if_gpio"; | |
| arg = <0x0000002a>; | |
| }; | |
| if_gpio43 { | |
| id = "if_gpio"; | |
| arg = <0x0000002b>; | |
| }; | |
| }; | |
| board-cfg { | |
| id = "Netgear NAS RN20x"; | |
| u-boot-offset = <0x00020000>; | |
| pinctrl_init { | |
| pinctrl-0 = <0x00000007 0x00000008 0x00000009 0x0000000a 0x0000000b>; | |
| }; | |
| gpio_init { | |
| gpio-list = <0x00000004 0x00000000 0x00000000 0x00000005 0x00000000 0x00000000 0x00000014 0x00000001 0x00000000 0x00000015 0x00000001 0x00000000 0x00000016 0x00000001 0x00000000 0x00000017 0x00000001 0x00000000 0x0000001c 0x00000001 0x00000000 0x0000001d 0x00000001 0x00000001 0x0000001e 0x00000001 0x00000001 0x0000001f 0x00000001 0x00000001 0x00000020 0x00000000 0x00000000 0x00000021 0x00000001 0x00000000 0x00000022 0x00000001 0x00000000 0x00000023 0x00000001 0x00000000 0x00000024 0x00000001 0x00000000 0x00000025 0x00000001 0x00000000 0x00000026 0x00000001 0x00000000 0x00000027 0x00000001 0x00000000 0x00000028 0x00000001 0x00000000 0x00000029 0x00000001 0x00000000 0x0000002a 0x00000001 0x00000000 0x0000002b 0x00000000 0x00000000 0x0000002c 0x00000000 0x00000000 0x0000002d 0x00000001 0x00000000 0x0000002e 0x00000001 0x00000000 0x0000002f 0x00000001 0x00000001>; | |
| }; | |
| serdes { | |
| group0 { | |
| interface = "pcie_g3x4"; | |
| ref-clock = "100Mhz"; | |
| active-lanes = <0x00000000 0x00000001 0x00000002 0x00000003>; | |
| inv-tx-lanes; | |
| inv-rx-lanes; | |
| ssc = "disabled"; | |
| lane_0_params { | |
| rx { | |
| override = "disabled"; | |
| }; | |
| tx { | |
| override = "disabled"; | |
| }; | |
| }; | |
| lane_1_params { | |
| rx { | |
| override = "disabled"; | |
| }; | |
| tx { | |
| override = "disabled"; | |
| }; | |
| }; | |
| lane_2_params { | |
| rx { | |
| override = "disabled"; | |
| }; | |
| tx { | |
| override = "disabled"; | |
| }; | |
| }; | |
| lane_3_params { | |
| rx { | |
| override = "disabled"; | |
| }; | |
| tx { | |
| override = "disabled"; | |
| }; | |
| }; | |
| }; | |
| group1 { | |
| interface = "sata"; | |
| ref-clock = "100Mhz"; | |
| active-lanes = <0x00000000 0x00000001 0x00000002 0x00000003>; | |
| inv-tx-lanes; | |
| inv-rx-lanes; | |
| ssc = "disabled"; | |
| lane_0_params { | |
| rx { | |
| override = "enabled"; | |
| dcgain = <0x00000000>; | |
| dfe_3db_freq = <0x00000007>; | |
| dfe_gain = <0x00000000>; | |
| dfe_1st_tap_ctrl = <0x00000000>; | |
| dfe_2nd_tap_ctrl = <0x00000008>; | |
| dfe_3rd_tap_ctrl = <0x00000000>; | |
| dfe_4th_tap_ctrl = <0x00000008>; | |
| low_freq_agc_gain = <0x00000007>; | |
| high_freq_agc_boost = <0x00000000>; | |
| precal_code_sel = <0x00000000>; | |
| }; | |
| tx { | |
| override = "enabled"; | |
| amp = <0x00000001>; | |
| total_driver_units = <0x00000013>; | |
| post_emph = <0x00000002>; | |
| pre_emph = <0x00000000>; | |
| slew_rate = <0x00000000>; | |
| }; | |
| }; | |
| lane_1_params { | |
| rx { | |
| override = "enabled"; | |
| dcgain = <0x00000000>; | |
| dfe_3db_freq = <0x00000007>; | |
| dfe_gain = <0x00000000>; | |
| dfe_1st_tap_ctrl = <0x00000000>; | |
| dfe_2nd_tap_ctrl = <0x00000008>; | |
| dfe_3rd_tap_ctrl = <0x00000000>; | |
| dfe_4th_tap_ctrl = <0x00000008>; | |
| low_freq_agc_gain = <0x00000007>; | |
| high_freq_agc_boost = <0x00000000>; | |
| precal_code_sel = <0x00000000>; | |
| }; | |
| tx { | |
| override = "enabled"; | |
| amp = <0x00000001>; | |
| total_driver_units = <0x00000013>; | |
| post_emph = <0x00000002>; | |
| pre_emph = <0x00000000>; | |
| slew_rate = <0x00000000>; | |
| }; | |
| }; | |
| lane_2_params { | |
| rx { | |
| override = "enabled"; | |
| dcgain = <0x00000000>; | |
| dfe_3db_freq = <0x00000007>; | |
| dfe_gain = <0x00000000>; | |
| dfe_1st_tap_ctrl = <0x00000000>; | |
| dfe_2nd_tap_ctrl = <0x00000008>; | |
| dfe_3rd_tap_ctrl = <0x00000000>; | |
| dfe_4th_tap_ctrl = <0x00000008>; | |
| low_freq_agc_gain = <0x00000007>; | |
| high_freq_agc_boost = <0x00000000>; | |
| precal_code_sel = <0x00000000>; | |
| }; | |
| tx { | |
| override = "enabled"; | |
| amp = <0x00000001>; | |
| total_driver_units = <0x00000013>; | |
| post_emph = <0x00000002>; | |
| pre_emph = <0x00000000>; | |
| slew_rate = <0x00000000>; | |
| }; | |
| }; | |
| lane_3_params { | |
| rx { | |
| override = "enabled"; | |
| dcgain = <0x00000000>; | |
| dfe_3db_freq = <0x00000007>; | |
| dfe_gain = <0x00000000>; | |
| dfe_1st_tap_ctrl = <0x00000000>; | |
| dfe_2nd_tap_ctrl = <0x00000008>; | |
| dfe_3rd_tap_ctrl = <0x00000000>; | |
| dfe_4th_tap_ctrl = <0x00000008>; | |
| low_freq_agc_gain = <0x00000007>; | |
| high_freq_agc_boost = <0x00000000>; | |
| precal_code_sel = <0x00000000>; | |
| }; | |
| tx { | |
| override = "enabled"; | |
| amp = <0x00000001>; | |
| total_driver_units = <0x00000013>; | |
| post_emph = <0x00000002>; | |
| pre_emph = <0x00000000>; | |
| slew_rate = <0x00000000>; | |
| }; | |
| }; | |
| }; | |
| group2 { | |
| interface = "sata"; | |
| ref-clock = "100Mhz"; | |
| active-lanes = <0x00000000 0x00000001 0x00000002 0x00000003>; | |
| inv-tx-lanes; | |
| inv-rx-lanes; | |
| ssc = "disabled"; | |
| lane_0_params { | |
| rx { | |
| override = "enabled"; | |
| dcgain = <0x00000000>; | |
| dfe_3db_freq = <0x00000007>; | |
| dfe_gain = <0x00000000>; | |
| dfe_1st_tap_ctrl = <0x00000000>; | |
| dfe_2nd_tap_ctrl = <0x00000008>; | |
| dfe_3rd_tap_ctrl = <0x00000000>; | |
| dfe_4th_tap_ctrl = <0x00000008>; | |
| low_freq_agc_gain = <0x00000007>; | |
| high_freq_agc_boost = <0x00000000>; | |
| precal_code_sel = <0x00000000>; | |
| }; | |
| tx { | |
| override = "enabled"; | |
| amp = <0x00000001>; | |
| total_driver_units = <0x00000013>; | |
| post_emph = <0x00000002>; | |
| pre_emph = <0x00000000>; | |
| slew_rate = <0x00000000>; | |
| }; | |
| }; | |
| lane_1_params { | |
| rx { | |
| override = "enabled"; | |
| dcgain = <0x00000000>; | |
| dfe_3db_freq = <0x00000007>; | |
| dfe_gain = <0x00000000>; | |
| dfe_1st_tap_ctrl = <0x00000000>; | |
| dfe_2nd_tap_ctrl = <0x00000008>; | |
| dfe_3rd_tap_ctrl = <0x00000000>; | |
| dfe_4th_tap_ctrl = <0x00000008>; | |
| low_freq_agc_gain = <0x00000007>; | |
| high_freq_agc_boost = <0x00000000>; | |
| precal_code_sel = <0x00000000>; | |
| }; | |
| tx { | |
| override = "enabled"; | |
| amp = <0x00000001>; | |
| total_driver_units = <0x00000013>; | |
| post_emph = <0x00000002>; | |
| pre_emph = <0x00000000>; | |
| slew_rate = <0x00000000>; | |
| }; | |
| }; | |
| lane_2_params { | |
| rx { | |
| override = "enabled"; | |
| dcgain = <0x00000000>; | |
| dfe_3db_freq = <0x00000007>; | |
| dfe_gain = <0x00000000>; | |
| dfe_1st_tap_ctrl = <0x00000000>; | |
| dfe_2nd_tap_ctrl = <0x00000008>; | |
| dfe_3rd_tap_ctrl = <0x00000000>; | |
| dfe_4th_tap_ctrl = <0x00000008>; | |
| low_freq_agc_gain = <0x00000007>; | |
| high_freq_agc_boost = <0x00000000>; | |
| precal_code_sel = <0x00000000>; | |
| }; | |
| tx { | |
| override = "enabled"; | |
| amp = <0x00000001>; | |
| total_driver_units = <0x00000013>; | |
| post_emph = <0x00000002>; | |
| pre_emph = <0x00000000>; | |
| slew_rate = <0x00000000>; | |
| }; | |
| }; | |
| lane_3_params { | |
| rx { | |
| override = "enabled"; | |
| dcgain = <0x00000000>; | |
| dfe_3db_freq = <0x00000007>; | |
| dfe_gain = <0x00000000>; | |
| dfe_1st_tap_ctrl = <0x00000000>; | |
| dfe_2nd_tap_ctrl = <0x00000008>; | |
| dfe_3rd_tap_ctrl = <0x00000000>; | |
| dfe_4th_tap_ctrl = <0x00000008>; | |
| low_freq_agc_gain = <0x00000007>; | |
| high_freq_agc_boost = <0x00000000>; | |
| precal_code_sel = <0x00000000>; | |
| }; | |
| tx { | |
| override = "enabled"; | |
| amp = <0x00000001>; | |
| total_driver_units = <0x00000013>; | |
| post_emph = <0x00000002>; | |
| pre_emph = <0x00000000>; | |
| slew_rate = <0x00000000>; | |
| }; | |
| }; | |
| }; | |
| group3 { | |
| interface = "10gbe"; | |
| ref-clock = "156.25Mhz"; | |
| active-lanes = <0x00000001 0x00000003>; | |
| inv-tx-lanes; | |
| inv-rx-lanes; | |
| ssc = "disabled"; | |
| lane_0_params { | |
| rx { | |
| override = "disabled"; | |
| }; | |
| tx { | |
| override = "disabled"; | |
| }; | |
| }; | |
| lane_1_params { | |
| rx { | |
| override = "disabled"; | |
| }; | |
| tx { | |
| override = "disabled"; | |
| }; | |
| }; | |
| lane_2_params { | |
| rx { | |
| override = "disabled"; | |
| }; | |
| tx { | |
| override = "disabled"; | |
| }; | |
| }; | |
| lane_3_params { | |
| rx { | |
| override = "disabled"; | |
| }; | |
| tx { | |
| override = "disabled"; | |
| }; | |
| }; | |
| }; | |
| }; | |
| ethernet { | |
| port0 { | |
| status = "disabled"; | |
| }; | |
| port1 { | |
| status = "enabled"; | |
| mode = "rgmii"; | |
| ext_phy { | |
| phy_mgmt_if = "mdc-mdio"; | |
| phy-addr = <0x00000004>; | |
| mdc-mdio-freq = "1.0Mhz"; | |
| auto-neg-mode = "out-of-band"; | |
| }; | |
| }; | |
| port2 { | |
| status = "disabled"; | |
| }; | |
| port3 { | |
| status = "enabled"; | |
| mode = "rgmii"; | |
| ext_phy { | |
| phy_mgmt_if = "mdc-mdio"; | |
| phy-addr = <0x00000005>; | |
| mdc-mdio-freq = "1.0Mhz"; | |
| auto-neg-mode = "out-of-band"; | |
| }; | |
| }; | |
| }; | |
| pcie { | |
| ep-ports; | |
| port0 { | |
| status = "enabled"; | |
| gen = <0x00000002>; | |
| width = <0x00000002>; | |
| }; | |
| port1 { | |
| status = "enabled"; | |
| gen = <0x00000002>; | |
| width = <0x00000002>; | |
| }; | |
| port2 { | |
| status = "disabled"; | |
| gen = <0x00000003>; | |
| width = <0x00000004>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| leds { | |
| compatible = "gpio-leds"; | |
| backup-led { | |
| label = "backup"; | |
| gpios = <0x0000000c 0x00000004 0x00000000>; | |
| default-state = "off"; | |
| }; | |
| sata1-led { | |
| label = "sata1"; | |
| gpios = <0x0000000d 0x00000004 0x00000000>; | |
| default-state = "keep"; | |
| }; | |
| sata2-led { | |
| label = "sata2"; | |
| gpios = <0x0000000d 0x00000005 0x00000000>; | |
| default-state = "keep"; | |
| }; | |
| sata3-led { | |
| label = "sata3"; | |
| gpios = <0x0000000d 0x00000006 0x00000000>; | |
| default-state = "keep"; | |
| }; | |
| sata4-led { | |
| label = "sata4"; | |
| gpios = <0x0000000d 0x00000007 0x00000000>; | |
| default-state = "keep"; | |
| }; | |
| act-led { | |
| label = "act"; | |
| gpios = <0x0000000e 0x00000002 0x00000000>; | |
| default-state = "off"; | |
| }; | |
| power-led { | |
| label = "pwr"; | |
| gpios = <0x0000000e 0x00000001 0x00000000>; | |
| default-state = "keep"; | |
| }; | |
| }; | |
| gpio_keys { | |
| compatible = "gpio-keys"; | |
| #address-cells = <0x00000001>; | |
| #size-cells = <0x00000000>; | |
| button@1 { | |
| label = "Power Button"; | |
| linux,code = <0x00000074>; | |
| gpios = <0x0000000f 0x00000003 0x00000000>; | |
| }; | |
| button@2 { | |
| label = "Reset Button"; | |
| linux,code = <0x00000198>; | |
| gpios = <0x0000000f 0x00000004 0x00000001>; | |
| }; | |
| button@3 { | |
| label = "Backup Button"; | |
| linux,code = <0x00000085>; | |
| gpios = <0x0000000e 0x00000000 0x00000001>; | |
| }; | |
| }; | |
| gpio_lcd { | |
| compatible = "gpio-lcd"; | |
| lcm-data-4bit; | |
| lcm-lines = <0x00000002>; | |
| lcm-bits = <0x0000000e 0x00000004 0x00000000 0x0000000e 0x00000005 0x00000000 0x0000000e 0x00000006 0x00000000 0x0000000e 0x00000007 0x00000000>; | |
| lcm-rs = <0x0000000e 0x00000003 0x00000000>; | |
| lcm-bl = <0x0000000f 0x00000000 0x00000000>; | |
| lcm-rw = <0x0000000f 0x00000001 0x00000000>; | |
| lcm-en = <0x0000000f 0x00000002 0x00000000>; | |
| linux,phandle = <0x00000010>; | |
| phandle = <0x00000010>; | |
| }; | |
| readynas_lcd { | |
| compatible = "readynas-lcd"; | |
| lcd-device = <0x00000010>; | |
| }; | |
| gpio_pwr { | |
| compatible = "gpio-power-off"; | |
| gpios = <0x0000000c 0x00000007 0x00000000>; | |
| }; | |
| }; |
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| 3 files: | |
| - the diff of the netgear rn214 4.4.111-alpine tree against linux 4.4.111 | |
| - the extracted dts file (u-boot supplied, dumped w/ dts tools) | |
| - the extracted fdt file (same u-boot supplied, but dumped differently w/ dts tools) | |
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| diff -x .git -Naur linux-4.4.111/arch/arc/kernel/troubleshoot.c linux-4.4.111-alpine/arch/arc/kernel/troubleshoot.c | |
| --- linux-4.4.111/arch/arc/kernel/troubleshoot.c 2018-02-20 12:32:32.318048715 -0500 | |
| +++ linux-4.4.111-alpine/arch/arc/kernel/troubleshoot.c 2018-02-14 21:04:17.000000000 -0500 | |
| @@ -101,7 +101,7 @@ | |
| if (file) { | |
| nm = file_path(file, buf, PAGE_SIZE - 1); | |
| inode = file_inode(vma->vm_file); | |
| - dev = inode->i_sb->s_dev; | |
| + dev = inode_get_dev(inode); | |
| ino = inode->i_ino; | |
| } | |
| pr_info(" @off 0x%lx in [%s]\n" | |
| diff -x .git -Naur linux-4.4.111/arch/arm/boot/compressed/atags_to_fdt.c linux-4.4.111-alpine/arch/arm/boot/compressed/atags_to_fdt.c | |
| --- linux-4.4.111/arch/arm/boot/compressed/atags_to_fdt.c 2018-02-20 12:32:32.338048793 -0500 | |
| +++ linux-4.4.111-alpine/arch/arm/boot/compressed/atags_to_fdt.c 2018-02-14 21:04:17.000000000 -0500 | |
| @@ -18,7 +18,7 @@ | |
| } | |
| static int setprop(void *fdt, const char *node_path, const char *property, | |
| - uint32_t *val_array, int size) | |
| + void *val_array, int size) | |
| { | |
| int offset = node_offset(fdt, node_path); | |
| if (offset < 0) | |
| @@ -179,6 +179,12 @@ | |
| initrd_start); | |
| setprop_cell(fdt, "/chosen", "linux,initrd-end", | |
| initrd_start + initrd_size); | |
| + } else if (atag->hdr.tag == ATAG_MV_UBOOT) { | |
| + /* This ATAG provides up to 4 MAC addresses */ | |
| + setprop(fdt, "eth0", "mac-address", atag->u.mv_uboot.macaddr[0], 6); | |
| + setprop(fdt, "eth1", "mac-address", atag->u.mv_uboot.macaddr[1], 6); | |
| + setprop(fdt, "eth2", "mac-address", atag->u.mv_uboot.macaddr[2], 6); | |
| + setprop(fdt, "eth3", "mac-address", atag->u.mv_uboot.macaddr[3], 6); | |
| } | |
| } | |
| diff -x .git -Naur linux-4.4.111/arch/arm/boot/dts/alpine-db.dts linux-4.4.111-alpine/arch/arm/boot/dts/alpine-db.dts | |
| --- linux-4.4.111/arch/arm/boot/dts/alpine-db.dts 2018-02-20 12:28:40.157135776 -0500 | |
| +++ linux-4.4.111-alpine/arch/arm/boot/dts/alpine-db.dts 1969-12-31 19:00:00.000000000 -0500 | |
| @@ -1,35 +0,0 @@ | |
| -/* | |
| - * Copyright 2015 Annapurna Labs Ltd. | |
| - * | |
| - * This program is free software; you can redistribute it and/or modify it | |
| - * under the terms and conditions of the GNU General Public License, | |
| - * version 2, as published by the Free Software Foundation. | |
| - * | |
| - * Alternatively, redistribution and use in source and binary forms, with or | |
| - * without modification, are permitted provided that the following conditions | |
| - * are met: | |
| - * | |
| - * * Redistributions of source code must retain the above copyright notice, | |
| - * this list of conditions and the following disclaimer. | |
| - * | |
| - * * Redistributions in binary form must reproduce the above copyright | |
| - * notice, this list of conditions and the following disclaimer in | |
| - * the documentation and/or other materials provided with the | |
| - * distribution. | |
| - * | |
| - * This program is distributed in the hope it will be useful, but WITHOUT | |
| - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
| - * more details. | |
| - * | |
| - */ | |
| - | |
| -/dts-v1/; | |
| - | |
| -#include "alpine.dtsi" | |
| - | |
| -/ { | |
| - model = "Annapurna Labs Alpine Dev Board"; | |
| - /* no need for anything outside SOC */ | |
| -}; | |
| - | |
| diff -x .git -Naur linux-4.4.111/arch/arm/boot/dts/alpine.dtsi linux-4.4.111-alpine/arch/arm/boot/dts/alpine.dtsi | |
| --- linux-4.4.111/arch/arm/boot/dts/alpine.dtsi 2018-02-20 12:32:32.348048833 -0500 | |
| +++ linux-4.4.111-alpine/arch/arm/boot/dts/alpine.dtsi 1969-12-31 19:00:00.000000000 -0500 | |
| @@ -1,160 +0,0 @@ | |
| -/* | |
| - * Copyright 2015 Annapurna Labs Ltd. | |
| - * | |
| - * This program is free software; you can redistribute it and/or modify it | |
| - * under the terms and conditions of the GNU General Public License, | |
| - * version 2, as published by the Free Software Foundation. | |
| - * | |
| - * Alternatively, redistribution and use in source and binary forms, with or | |
| - * without modification, are permitted provided that the following conditions | |
| - * are met: | |
| - * | |
| - * * Redistributions of source code must retain the above copyright notice, | |
| - * this list of conditions and the following disclaimer. | |
| - * | |
| - * * Redistributions in binary form must reproduce the above copyright | |
| - * notice, this list of conditions and the following disclaimer in | |
| - * the documentation and/or other materials provided with the | |
| - * distribution. | |
| - * | |
| - * This program is distributed in the hope it will be useful, but WITHOUT | |
| - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
| - * more details. | |
| - * | |
| - */ | |
| - | |
| -#include <dt-bindings/interrupt-controller/arm-gic.h> | |
| -#include "skeleton64.dtsi" | |
| - | |
| -/ { | |
| - /* SOC compatibility */ | |
| - compatible = "al,alpine"; | |
| - | |
| - /* CPU Configuration */ | |
| - cpus { | |
| - #address-cells = <1>; | |
| - #size-cells = <0>; | |
| - enable-method = "al,alpine-smp"; | |
| - | |
| - cpu@0 { | |
| - compatible = "arm,cortex-a15"; | |
| - device_type = "cpu"; | |
| - reg = <0>; | |
| - clock-frequency = <0>; /* Filled by loader */ | |
| - }; | |
| - | |
| - cpu@1 { | |
| - compatible = "arm,cortex-a15"; | |
| - device_type = "cpu"; | |
| - reg = <1>; | |
| - clock-frequency = <0>; /* Filled by loader */ | |
| - }; | |
| - | |
| - cpu@2 { | |
| - compatible = "arm,cortex-a15"; | |
| - device_type = "cpu"; | |
| - reg = <2>; | |
| - clock-frequency = <0>; /* Filled by loader */ | |
| - }; | |
| - | |
| - cpu@3 { | |
| - compatible = "arm,cortex-a15"; | |
| - device_type = "cpu"; | |
| - reg = <3>; | |
| - clock-frequency = <0>; /* Filled by loader */ | |
| - }; | |
| - }; | |
| - | |
| - soc { | |
| - #address-cells = <2>; | |
| - #size-cells = <2>; | |
| - compatible = "simple-bus"; | |
| - interrupt-parent = <&gic>; | |
| - ranges; | |
| - | |
| - arch-timer { | |
| - compatible = "arm,cortex-a15-timer", | |
| - "arm,armv7-timer"; | |
| - interrupts = | |
| - <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, | |
| - <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, | |
| - <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, | |
| - <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; | |
| - clock-frequency = <0>; /* Filled by loader */ | |
| - }; | |
| - | |
| - /* Interrupt Controller */ | |
| - gic: gic@fb001000 { | |
| - compatible = "arm,cortex-a15-gic"; | |
| - #interrupt-cells = <3>; | |
| - #size-cells = <0>; | |
| - #address-cells = <0>; | |
| - interrupt-controller; | |
| - reg = <0x0 0xfb001000 0x0 0x1000>, | |
| - <0x0 0xfb002000 0x0 0x2000>, | |
| - <0x0 0xfb004000 0x0 0x1000>, | |
| - <0x0 0xfb006000 0x0 0x2000>; | |
| - interrupts = | |
| - <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; | |
| - }; | |
| - | |
| - /* CPU Resume registers */ | |
| - cpu-resume@fbff5ec0 { | |
| - compatible = "al,alpine-cpu-resume"; | |
| - reg = <0x0 0xfbff5ec0 0x0 0x30>; | |
| - }; | |
| - | |
| - /* North Bridge Service Registers */ | |
| - sysfabric-service@fb070000 { | |
| - compatible = "al,alpine-sysfabric-service", "syscon"; | |
| - reg = <0x0 0xfb070000 0x0 0x10000>; | |
| - }; | |
| - | |
| - /* Performance Monitor Unit */ | |
| - pmu { | |
| - compatible = "arm,cortex-a15-pmu"; | |
| - interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, | |
| - <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, | |
| - <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, | |
| - <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; | |
| - }; | |
| - | |
| - uart0:uart@fd883000 { | |
| - compatible = "ns16550a"; | |
| - reg = <0x0 0xfd883000 0x0 0x1000>; | |
| - clock-frequency = <0>; /* Filled by loader */ | |
| - interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; | |
| - reg-shift = <2>; | |
| - reg-io-width = <4>; | |
| - }; | |
| - | |
| - uart1:uart@0xfd884000 { | |
| - compatible = "ns16550a"; | |
| - reg = <0x0 0xfd884000 0x0 0x1000>; | |
| - clock-frequency = <0>; /* Filled by loader */ | |
| - interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; | |
| - reg-shift = <2>; | |
| - reg-io-width = <4>; | |
| - }; | |
| - | |
| - /* Internal PCIe Controller */ | |
| - pcie-internal@0xfbc00000 { | |
| - compatible = "pci-host-ecam-generic"; | |
| - device_type = "pci"; | |
| - #size-cells = <2>; | |
| - #address-cells = <3>; | |
| - #interrupt-cells = <1>; | |
| - reg = <0x0 0xfbc00000 0x0 0x100000>; | |
| - interrupt-map-mask = <0xf800 0 0 7>; | |
| - /* Add legacy interrupts for SATA devices only */ | |
| - interrupt-map = <0x4000 0 0 1 &gic 0 43 4>, | |
| - <0x4800 0 0 1 &gic 0 44 4>; | |
| - | |
| - /* 32 bit non prefetchable memory space */ | |
| - ranges = <0x02000000 0x0 0xfe000000 0x0 0xfe000000 0x0 0x1000000>; | |
| - | |
| - bus-range = <0x00 0x00>; | |
| - }; | |
| - }; | |
| -}; | |
| diff -x .git -Naur linux-4.4.111/arch/arm/boot/dts/armada-370.dtsi linux-4.4.111-alpine/arch/arm/boot/dts/armada-370.dtsi | |
| --- linux-4.4.111/arch/arm/boot/dts/armada-370.dtsi 2018-02-20 12:32:32.368048911 -0500 | |
| +++ linux-4.4.111-alpine/arch/arm/boot/dts/armada-370.dtsi 2018-02-14 21:04:17.000000000 -0500 | |
| @@ -279,7 +279,7 @@ | |
| clocks = <&coreclk 0>; | |
| }; | |
| - xor@60800 { | |
| + xor0: xor@60800 { | |
| compatible = "marvell,orion-xor"; | |
| reg = <0x60800 0x100 | |
| 0x60A00 0x100>; | |
| @@ -289,6 +289,7 @@ | |
| interrupts = <51>; | |
| dmacap,memcpy; | |
| dmacap,xor; | |
| + dmacap,crc32c; | |
| }; | |
| xor01 { | |
| interrupts = <52>; | |
| @@ -298,7 +299,7 @@ | |
| }; | |
| }; | |
| - xor@60900 { | |
| + xor1: xor@60900 { | |
| compatible = "marvell,orion-xor"; | |
| reg = <0x60900 0x100 | |
| 0x60b00 0x100>; | |
| @@ -308,6 +309,7 @@ | |
| interrupts = <94>; | |
| dmacap,memcpy; | |
| dmacap,xor; | |
| + dmacap,crc32c; | |
| }; | |
| xor11 { | |
| interrupts = <95>; | |
| diff -x .git -Naur linux-4.4.111/arch/arm/boot/dts/armada-370-netgear-rn102.dts linux-4.4.111-alpine/arch/arm/boot/dts/armada-370-netgear-rn102.dts | |
| --- linux-4.4.111/arch/arm/boot/dts/armada-370-netgear-rn102.dts 2018-02-20 12:32:32.368048911 -0500 | |
| +++ linux-4.4.111-alpine/arch/arm/boot/dts/armada-370-netgear-rn102.dts 2018-02-14 21:04:17.000000000 -0500 | |
| @@ -154,12 +154,11 @@ | |
| partition@0 { | |
| label = "u-boot"; | |
| reg = <0x0000000 0x180000>; /* 1.5MB */ | |
| - read-only; | |
| }; | |
| partition@180000 { | |
| label = "u-boot-env"; | |
| - reg = <0x180000 0x20000>; /* 128KB */ | |
| + reg = <0x180000 0x80000>; /* 512KB */ | |
| read-only; | |
| }; | |
| @@ -182,6 +181,11 @@ | |
| }; | |
| }; | |
| + xor-pref { | |
| + xor = <&xor0 &xor1>; | |
| + dmacap = "xor", "xor", "crc32c", "crc32c"; | |
| + }; | |
| + | |
| clocks { | |
| g762_clk: g762-oscillator { | |
| compatible = "fixed-clock"; | |
| @@ -207,19 +211,19 @@ | |
| blue-sata1-led { | |
| label = "rn102:blue:sata1"; | |
| gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; | |
| - default-state = "on"; | |
| + default-state = "keep"; | |
| }; | |
| blue-sata2-led { | |
| label = "rn102:blue:sata2"; | |
| gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; | |
| - default-state = "on"; | |
| + default-state = "keep"; | |
| }; | |
| blue-backup-led { | |
| label = "rn102:blue:backup"; | |
| gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; | |
| - default-state = "on"; | |
| + default-state = "off"; | |
| }; | |
| }; | |
| diff -x .git -Naur linux-4.4.111/arch/arm/boot/dts/armada-370-netgear-rn104.dts linux-4.4.111-alpine/arch/arm/boot/dts/armada-370-netgear-rn104.dts | |
| --- linux-4.4.111/arch/arm/boot/dts/armada-370-netgear-rn104.dts 2018-02-20 12:32:32.368048911 -0500 | |
| +++ linux-4.4.111-alpine/arch/arm/boot/dts/armada-370-netgear-rn104.dts 2018-02-14 21:04:17.000000000 -0500 | |
| @@ -93,6 +93,12 @@ | |
| status = "okay"; | |
| }; | |
| + /* eSATA interface */ | |
| + sata@a0000 { | |
| + nr-ports = <1>; | |
| + status = "okay"; | |
| + }; | |
| + | |
| mdio { | |
| pinctrl-0 = <&mdio_pins>; | |
| pinctrl-names = "default"; | |
| @@ -167,12 +173,11 @@ | |
| partition@0 { | |
| label = "u-boot"; | |
| reg = <0x0000000 0x180000>; /* 1.5MB */ | |
| - read-only; | |
| }; | |
| partition@180000 { | |
| label = "u-boot-env"; | |
| - reg = <0x180000 0x20000>; /* 128KB */ | |
| + reg = <0x180000 0x80000>; /* 512KB */ | |
| read-only; | |
| }; | |
| @@ -195,6 +200,11 @@ | |
| }; | |
| }; | |
| + xor-pref { | |
| + xor = <&xor0 &xor1>; | |
| + dmacap = "xor", "xor", "crc32c", "crc32c"; | |
| + }; | |
| + | |
| clocks { | |
| g762_clk: g762-oscillator { | |
| compatible = "fixed-clock"; | |
| @@ -223,25 +233,25 @@ | |
| blue-sata1-led { | |
| label = "rn104:blue:sata1"; | |
| gpios = <&pca9554 0 GPIO_ACTIVE_LOW>; | |
| - default-state = "off"; | |
| + default-state = "keep"; | |
| }; | |
| blue-sata2-led { | |
| label = "rn104:blue:sata2"; | |
| gpios = <&pca9554 1 GPIO_ACTIVE_LOW>; | |
| - default-state = "off"; | |
| + default-state = "keep"; | |
| }; | |
| blue-sata3-led { | |
| label = "rn104:blue:sata3"; | |
| gpios = <&pca9554 2 GPIO_ACTIVE_LOW>; | |
| - default-state = "off"; | |
| + default-state = "keep"; | |
| }; | |
| blue-sata4-led { | |
| label = "rn104:blue:sata4"; | |
| gpios = <&pca9554 3 GPIO_ACTIVE_LOW>; | |
| - default-state = "off"; | |
| + default-state = "keep"; | |
| }; | |
| }; | |
| @@ -277,6 +287,25 @@ | |
| pinctrl-names = "default"; | |
| gpios = <&gpio1 28 GPIO_ACTIVE_LOW>; | |
| }; | |
| + | |
| + gpio_lcd: gpio_lcd { | |
| + compatible = "gpio-lcd"; | |
| + lcm-data-4bit; | |
| + lcm-lines = <2>; | |
| + lcm-bits = <&gpio1 25 GPIO_ACTIVE_HIGH>, | |
| + <&gpio1 26 GPIO_ACTIVE_HIGH>, | |
| + <&gpio1 27 GPIO_ACTIVE_HIGH>, | |
| + <&gpio1 29 GPIO_ACTIVE_HIGH>; | |
| + lcm-rs = <&gpio1 22 GPIO_ACTIVE_HIGH>; | |
| + lcm-bl = <&gpio1 21 GPIO_ACTIVE_LOW>; | |
| + lcm-rw = <&gpio1 23 GPIO_ACTIVE_HIGH>; | |
| + lcm-en = <&gpio1 24 GPIO_ACTIVE_HIGH>; | |
| + }; | |
| + | |
| + readynas_lcd { | |
| + compatible = "readynas-lcd"; | |
| + lcd-device = <&gpio_lcd>; | |
| + }; | |
| }; | |
| &pinctrl { | |
| @@ -297,7 +326,7 @@ | |
| backup_led_pin: backup-led-pin { | |
| marvell,pins = "mpp63"; | |
| - marvell,function = "gpo"; | |
| + marvell,function = "gpio"; | |
| }; | |
| power_led_pin: power-led-pin { | |
| diff -x .git -Naur linux-4.4.111/arch/arm/boot/dts/armada-380-netgear-rn35.dts linux-4.4.111-alpine/arch/arm/boot/dts/armada-380-netgear-rn35.dts | |
| --- linux-4.4.111/arch/arm/boot/dts/armada-380-netgear-rn35.dts 1969-12-31 19:00:00.000000000 -0500 | |
| +++ linux-4.4.111-alpine/arch/arm/boot/dts/armada-380-netgear-rn35.dts 2018-02-14 21:04:17.000000000 -0500 | |
| @@ -0,0 +1,236 @@ | |
| +/* | |
| + * Device Tree file for NETGEAR ReadyNAS 35 | |
| + * | |
| + * Copyright (C) 2015, NETGEAR | |
| + * | |
| + * Justin Maggard <justin.maggard@netgear.com> | |
| + * | |
| + * This file is licensed under the terms of the GNU General Public | |
| + * License version 2. This program is licensed "as is" without any | |
| + * warranty of any kind, whether express or implied. | |
| + */ | |
| + | |
| +/dts-v1/; | |
| +#include <dt-bindings/input/input.h> | |
| +#include <dt-bindings/gpio/gpio.h> | |
| +#include "armada-380.dtsi" | |
| + | |
| +/ { | |
| + model = "NETGEAR ReadyNAS 35"; | |
| + compatible = "netgear,readynas-35", "marvell,armada380", "marvell,armada-370-xp"; | |
| + | |
| + chosen { | |
| + bootargs = "console=ttyS0,115200 earlyprintk"; | |
| + }; | |
| + | |
| + memory { | |
| + device_type = "memory"; | |
| + reg = <0x00000000 0x20000000>; /* 512 MB */ | |
| + }; | |
| + | |
| + soc { | |
| + ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000 | |
| + MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>; | |
| + | |
| + internal-regs { | |
| + spi@10600 { | |
| + status = "okay"; | |
| + | |
| + spi-flash@0 { | |
| + #address-cells = <1>; | |
| + #size-cells = <1>; | |
| + compatible = "w25q32"; | |
| + reg = <0>; /* Chip select 0 */ | |
| + spi-max-frequency = <108000000>; | |
| + }; | |
| + }; | |
| + | |
| + i2c@11000 { | |
| + status = "okay"; | |
| + clock-frequency = <100000>; | |
| + }; | |
| + | |
| + i2c@11100 { | |
| + status = "okay"; | |
| + clock-frequency = <100000>; | |
| + }; | |
| + | |
| + serial@12000 { | |
| + status = "okay"; | |
| + }; | |
| + | |
| + usb@58000 { | |
| + status = "okay"; | |
| + }; | |
| + | |
| + ethernet@70000 { | |
| + status = "okay"; | |
| + phy = <&phy0>; | |
| + phy-mode = "rgmii-id"; | |
| + }; | |
| + | |
| + mdio@72004 { | |
| + phy0: ethernet-phy@0 { | |
| + reg = <0>; | |
| + }; | |
| + | |
| + phy1: ethernet-phy@1 { | |
| + reg = <1>; | |
| + }; | |
| + }; | |
| + | |
| + sata@a8000 { | |
| + status = "okay"; | |
| + }; | |
| + | |
| + flash@d0000 { | |
| + status = "okay"; | |
| + num-cs = <1>; | |
| + marvell,nand-keep-config; | |
| + marvell,nand-enable-arbiter; | |
| + nand-on-flash-bbt; | |
| + nand-ecc-strength = <4>; | |
| + nand-ecc-step-size = <512>; | |
| + | |
| + partition@0 { | |
| + label = "u-boot"; | |
| + reg = <0x0000000 0x180000>; /* 1.5MB */ | |
| + }; | |
| + | |
| + partition@1a0000 { | |
| + label = "u-boot-env"; | |
| + reg = <0x01a0000 0x20000>; /* 128KB */ | |
| + read-only; | |
| + }; | |
| + | |
| + partition@200000 { | |
| + label = "uImage"; | |
| + reg = <0x0200000 0x600000>; /* 6MB */ | |
| + }; | |
| + | |
| + partition@800000 { | |
| + label = "minirootfs"; | |
| + reg = <0x0800000 0x400000>; /* 4MB */ | |
| + }; | |
| + | |
| + partition@c00000 { | |
| + label = "ubifs"; | |
| + reg = <0x0c00000 0x7200000>; /* 100MB */ | |
| + }; | |
| + | |
| + partition@7e00000 { | |
| + label = "dtb"; | |
| + reg = <0x7e00000 0x20000>; /* 128KB */ | |
| + }; | |
| + }; | |
| + | |
| + sdhci@d8000 { | |
| + broken-cd; | |
| + wp-inverted; | |
| + bus-width = <8>; | |
| + status = "okay"; | |
| + no-1-8-v; | |
| + }; | |
| + | |
| + usb3@f0000 { | |
| + status = "okay"; | |
| + }; | |
| + | |
| + usb3@f8000 { | |
| + status = "okay"; | |
| + }; | |
| + }; | |
| + | |
| + pcie-controller { | |
| + status = "okay"; | |
| + /* | |
| + * The two PCIe units are accessible through | |
| + * standard PCIe slots on the board. | |
| + */ | |
| + pcie@1,0 { | |
| + /* Port 0, Lane 0 */ | |
| + status = "okay"; | |
| + }; | |
| + pcie@2,0 { | |
| + /* Port 1, Lane 0 */ | |
| + status = "okay"; | |
| + }; | |
| + }; | |
| + }; | |
| + | |
| + gpio-leds{ | |
| + compatible = "gpio-leds"; | |
| + backup { | |
| + gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; | |
| + label = "backup"; | |
| + default-state = "off"; | |
| + }; | |
| + power { | |
| + gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; | |
| + label = "pwr"; | |
| + default-state = "keep"; | |
| + }; | |
| + sata1 { | |
| + gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; | |
| + label = "sata1"; | |
| + default-state = "keep"; | |
| + }; | |
| + sata2 { | |
| + gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; | |
| + label = "sata2"; | |
| + default-state = "keep"; | |
| + }; | |
| + }; | |
| + | |
| + gpio_keys { | |
| + compatible = "gpio-keys"; | |
| + #address-cells = <1>; | |
| + #size-cells = <0>; | |
| + button@1 { | |
| + label = "BT Reset"; | |
| + linux,code = <0x198>; | |
| + gpios = <&gpio0 19 GPIO_ACTIVE_LOW>; | |
| + debounce-interval = <0x64>; | |
| + }; | |
| + button@2 { | |
| + label = "BT Power"; | |
| + linux,code = <0x74>; | |
| + gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; | |
| + debounce-interval = <0x64>; | |
| + }; | |
| + button@3 { | |
| + label = "BT Backup"; | |
| + linux,code = <0x165>; | |
| + gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; | |
| + debounce-interval = <0x64>; | |
| + }; | |
| + }; | |
| + | |
| + gpio-poweroff { | |
| + compatible = "gpio-poweroff"; | |
| + gpios = <&gpio1 27 GPIO_ACTIVE_LOW>; | |
| + }; | |
| + | |
| + gpio-hdds-power { | |
| + compatible = "gpio-hdds-power"; | |
| + power-sata1 { | |
| + present-gpio = <&gpio0 24 GPIO_ACTIVE_LOW>; | |
| + power-gpio = <&gpio0 29 GPIO_ACTIVE_HIGH>; | |
| + led-gpio = <&gpio1 5 GPIO_ACTIVE_LOW>; | |
| + label = "power-sata1"; | |
| + }; | |
| + power-sata2 { | |
| + gpios = <&gpio0 26 GPIO_ACTIVE_LOW &gpio1 27 GPIO_ACTIVE_HIGH>; | |
| + present-gpio = <&gpio0 26 GPIO_ACTIVE_LOW>; | |
| + power-gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>; | |
| + led-gpio = <&gpio1 7 GPIO_ACTIVE_LOW>; | |
| + label = "power-sata2"; | |
| + }; | |
| + }; | |
| + | |
| + pwm-fan-armada-38x { | |
| + compatible = "pwm-fan-armada-38x"; | |
| + ctrl-gpio = <&gpio0 2 GPIO_ACTIVE_HIGH>; | |
| + fb-gpio = <&gpio0 3 GPIO_ACTIVE_HIGH>; | |
| + }; | |
| +}; | |
| diff -x .git -Naur linux-4.4.111/arch/arm/boot/dts/armada-385-netgear-rn112.dts linux-4.4.111-alpine/arch/arm/boot/dts/armada-385-netgear-rn112.dts | |
| --- linux-4.4.111/arch/arm/boot/dts/armada-385-netgear-rn112.dts 1969-12-31 19:00:00.000000000 -0500 | |
| +++ linux-4.4.111-alpine/arch/arm/boot/dts/armada-385-netgear-rn112.dts 2018-02-14 21:04:17.000000000 -0500 | |
| @@ -0,0 +1,247 @@ | |
| +/* | |
| + * Device Tree file for NETGEAR ReadyNAS 112 | |
| + * | |
| + * Copyright (C) 2015, NETGEAR | |
| + * | |
| + * Justin Maggard <justin.maggard@netgear.com> | |
| + * | |
| + * This file is licensed under the terms of the GNU General Public | |
| + * License version 2. This program is licensed "as is" without any | |
| + * warranty of any kind, whether express or implied. | |
| + */ | |
| + | |
| +/dts-v1/; | |
| +#include <dt-bindings/input/input.h> | |
| +#include <dt-bindings/gpio/gpio.h> | |
| +#include "armada-385.dtsi" | |
| + | |
| +/ { | |
| + model = "NETGEAR ReadyNAS 112"; | |
| + compatible = "netgear,readynas-112", "marvell,armada385", "marvell,armada-370-xp"; | |
| + | |
| + chosen { | |
| + bootargs = "console=ttyS0,115200 earlyprintk"; | |
| + }; | |
| + | |
| + memory { | |
| + device_type = "memory"; | |
| + reg = <0x00000000 0x20000000>; /* 512 MB */ | |
| + }; | |
| + | |
| + soc { | |
| + ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000 | |
| + MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>; | |
| + | |
| + internal-regs { | |
| + spi@10600 { | |
| + status = "okay"; | |
| + | |
| + spi-flash@0 { | |
| + #address-cells = <1>; | |
| + #size-cells = <1>; | |
| + compatible = "w25q32"; | |
| + reg = <0>; /* Chip select 0 */ | |
| + spi-max-frequency = <108000000>; | |
| + }; | |
| + }; | |
| + | |
| + i2c@11000 { | |
| + status = "okay"; | |
| + clock-frequency = <100000>; | |
| + }; | |
| + | |
| + i2c@11100 { | |
| + status = "okay"; | |
| + clock-frequency = <100000>; | |
| + }; | |
| + | |
| + serial@12000 { | |
| + status = "okay"; | |
| + }; | |
| + | |
| + ethernet@70000 { | |
| + status = "okay"; | |
| + phy = <&phy0>; | |
| + phy-mode = "rgmii-id"; | |
| + }; | |
| + | |
| + mdio@72004 { | |
| + phy0: ethernet-phy@0 { | |
| + reg = <0>; | |
| + }; | |
| + | |
| + phy1: ethernet-phy@1 { | |
| + reg = <1>; | |
| + }; | |
| + }; | |
| + | |
| + sata@a8000 { | |
| + status = "okay"; | |
| + }; | |
| + | |
| + flash@d0000 { | |
| + status = "okay"; | |
| + num-cs = <1>; | |
| + marvell,nand-keep-config; | |
| + marvell,nand-enable-arbiter; | |
| + nand-on-flash-bbt; | |
| + nand-ecc-strength = <4>; | |
| + nand-ecc-step-size = <512>; | |
| + | |
| + partition@0 { | |
| + label = "u-boot"; | |
| + reg = <0x0000000 0x180000>; /* 1.5MB */ | |
| + }; | |
| + | |
| + partition@1a0000 { | |
| + label = "u-boot-env"; | |
| + reg = <0x01a0000 0x20000>; /* 128KB */ | |
| + read-only; | |
| + }; | |
| + | |
| + partition@200000 { | |
| + label = "uImage"; | |
| + reg = <0x0200000 0x600000>; /* 6MB */ | |
| + }; | |
| + | |
| + partition@800000 { | |
| + label = "minirootfs"; | |
| + reg = <0x0800000 0x400000>; /* 4MB */ | |
| + }; | |
| + | |
| + partition@c00000 { | |
| + label = "ubifs"; | |
| + reg = <0x0c00000 0x7200000>; /* 100MB */ | |
| + }; | |
| + | |
| + partition@7e00000 { | |
| + label = "dtb"; | |
| + reg = <0x7e00000 0x20000>; /* 128KB */ | |
| + }; | |
| + }; | |
| + | |
| + sdhci@d8000 { | |
| + broken-cd; | |
| + wp-inverted; | |
| + bus-width = <8>; | |
| + status = "okay"; | |
| + no-1-8-v; | |
| + }; | |
| + | |
| + usb3@f0000 { | |
| + status = "okay"; | |
| + }; | |
| + | |
| + usb3@f8000 { | |
| + status = "okay"; | |
| + }; | |
| + | |
| + usb@58000 { | |
| + status = "okay"; | |
| + }; | |
| + }; | |
| + | |
| + pcie-controller { | |
| + status = "okay"; | |
| + /* | |
| + * The two PCIe units are accessible through | |
| + * standard PCIe slots on the board. | |
| + */ | |
| + pcie@1,0 { | |
| + /* Port 0, Lane 0 */ | |
| + status = "okay"; | |
| + }; | |
| + pcie@2,0 { | |
| + /* Port 1, Lane 0 */ | |
| + status = "okay"; | |
| + }; | |
| + }; | |
| + }; | |
| + | |
| + gpio-leds{ | |
| + compatible = "gpio-leds"; | |
| + backup { | |
| + gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; | |
| + label = "backup"; | |
| + default-state = "off"; | |
| + }; | |
| + power { | |
| + gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; | |
| + label = "pwr"; | |
| + default-state = "keep"; | |
| + }; | |
| + sata1 { | |
| + gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; | |
| + label = "sata1"; | |
| + default-state = "keep"; | |
| + }; | |
| + sata2 { | |
| + gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; | |
| + label = "sata2"; | |
| + default-state = "keep"; | |
| + }; | |
| + }; | |
| + | |
| + gpio_keys { | |
| + compatible = "gpio-keys"; | |
| + #address-cells = <1>; | |
| + #size-cells = <0>; | |
| + button@1 { | |
| + label = "BT Reset"; | |
| + linux,code = <0x198>; | |
| + gpios = <&gpio0 19 GPIO_ACTIVE_LOW>; | |
| + debounce-interval = <0x64>; | |
| + }; | |
| + button@2 { | |
| + label = "BT Power"; | |
| + linux,code = <0x74>; | |
| + gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; | |
| + debounce-interval = <0x64>; | |
| + }; | |
| + button@3 { | |
| + label = "BT Backup"; | |
| + linux,code = <0x165>; | |
| + gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; | |
| + debounce-interval = <0x64>; | |
| + }; | |
| + }; | |
| + | |
| + gpio-poweroff { | |
| + compatible = "gpio-poweroff"; | |
| + gpios = <&gpio1 27 GPIO_ACTIVE_LOW>; | |
| + }; | |
| + | |
| + gpio-hdds-power { | |
| + compatible = "gpio-hdds-power"; | |
| + power-sata1 { | |
| + present-gpio = <&gpio0 24 GPIO_ACTIVE_LOW>; | |
| + power-gpio = <&gpio0 29 GPIO_ACTIVE_HIGH>; | |
| + led-gpio = <&gpio1 5 GPIO_ACTIVE_LOW>; | |
| + label = "power-sata1"; | |
| + }; | |
| + power-sata2 { | |
| + present-gpio = <&gpio0 26 GPIO_ACTIVE_LOW>; | |
| + power-gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>; | |
| + led-gpio = <&gpio1 7 GPIO_ACTIVE_LOW>; | |
| + label = "power-sata2"; | |
| + }; | |
| + power-sata3 { | |
| + present-gpio = <&gpio0 27 GPIO_ACTIVE_LOW>; | |
| + power-gpio = <&gpio1 20 GPIO_ACTIVE_HIGH>; | |
| + //led-gpio = <&gpio1 7 GPIO_ACTIVE_LOW>; | |
| + label = "power-sata3"; | |
| + }; | |
| + power-sata4 { | |
| + present-gpio = <&gpio1 18 GPIO_ACTIVE_LOW>; | |
| + power-gpio = <&gpio1 15 GPIO_ACTIVE_HIGH>; | |
| + //led-gpio = <&gpio1 7 GPIO_ACTIVE_LOW>; | |
| + label = "power-sata4"; | |
| + }; | |
| + }; | |
| + | |
| + pwm-fan-armada-38x { | |
| + compatible = "pwm-fan-armada-38x"; | |
| + ctrl-gpio = <&gpio0 2 GPIO_ACTIVE_HIGH>; | |
| + fb-gpio = <&gpio0 3 GPIO_ACTIVE_HIGH>; | |
| + }; | |
| +}; | |
| diff -x .git -Naur linux-4.4.111/arch/arm/boot/dts/armada-385-netgear-rn114.dts linux-4.4.111-alpine/arch/arm/boot/dts/armada-385-netgear-rn114.dts | |
| --- linux-4.4.111/arch/arm/boot/dts/armada-385-netgear-rn114.dts 1969-12-31 19:00:00.000000000 -0500 | |
| +++ linux-4.4.111-alpine/arch/arm/boot/dts/armada-385-netgear-rn114.dts 2018-02-14 21:04:17.000000000 -0500 | |
| @@ -0,0 +1,274 @@ | |
| +/* | |
| + * Device Tree file for NETGEAR ReadyNAS 114 | |
| + * | |
| + * Copyright (C) 2015, NETGEAR | |
| + * | |
| + * Justin Maggard <justin.maggard@netgear.com> | |
| + * | |
| + * This file is licensed under the terms of the GNU General Public | |
| + * License version 2. This program is licensed "as is" without any | |
| + * warranty of any kind, whether express or implied. | |
| + */ | |
| + | |
| +/dts-v1/; | |
| +#include <dt-bindings/input/input.h> | |
| +#include <dt-bindings/gpio/gpio.h> | |
| +#include "armada-385.dtsi" | |
| + | |
| +/ { | |
| + model = "NETGEAR ReadyNAS 114"; | |
| + compatible = "netgear,readynas-114", "marvell,armada385", "marvell,armada-370-xp"; | |
| + | |
| + chosen { | |
| + bootargs = "console=ttyS0,115200 earlyprintk"; | |
| + }; | |
| + | |
| + memory { | |
| + device_type = "memory"; | |
| + reg = <0x00000000 0x10000000>; /* 1 GB */ | |
| + }; | |
| + | |
| + soc { | |
| + ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000 | |
| + MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>; | |
| + | |
| + internal-regs { | |
| + spi@10600 { | |
| + status = "okay"; | |
| + | |
| + spi-flash@0 { | |
| + #address-cells = <1>; | |
| + #size-cells = <1>; | |
| + compatible = "w25q32"; | |
| + reg = <0>; /* Chip select 0 */ | |
| + spi-max-frequency = <108000000>; | |
| + }; | |
| + }; | |
| + | |
| + i2c@11000 { | |
| + status = "okay"; | |
| + clock-frequency = <100000>; | |
| + }; | |
| + | |
| + i2c@11100 { | |
| + status = "okay"; | |
| + clock-frequency = <100000>; | |
| + }; | |
| + | |
| + serial@12000 { | |
| + status = "okay"; | |
| + }; | |
| + | |
| + ethernet@70000 { | |
| + status = "okay"; | |
| + phy = <&phy0>; | |
| + phy-mode = "rgmii-id"; | |
| + }; | |
| + | |
| + ethernet@74000 { | |
| + status = "okay"; | |
| + phy = <&phy1>; | |
| + phy-mode = "rgmii-id"; | |
| + }; | |
| + | |
| + mdio@72004 { | |
| + phy0: ethernet-phy@0 { | |
| + reg = <0>; | |
| + }; | |
| + | |
| + phy1: ethernet-phy@1 { | |
| + reg = <1>; | |
| + }; | |
| + }; | |
| + | |
| + sata@a8000 { | |
| + status = "okay"; | |
| + }; | |
| + | |
| + flash@d0000 { | |
| + status = "okay"; | |
| + num-cs = <1>; | |
| + marvell,nand-keep-config; | |
| + marvell,nand-enable-arbiter; | |
| + nand-on-flash-bbt; | |
| + nand-ecc-strength = <4>; | |
| + nand-ecc-step-size = <512>; | |
| + | |
| + partition@0 { | |
| + label = "u-boot"; | |
| + reg = <0x0000000 0x180000>; /* 1.5MB */ | |
| + }; | |
| + | |
| + partition@1a0000 { | |
| + label = "u-boot-env"; | |
| + reg = <0x01a0000 0x20000>; /* 128KB */ | |
| + read-only; | |
| + }; | |
| + | |
| + partition@200000 { | |
| + label = "uImage"; | |
| + reg = <0x0200000 0x600000>; /* 6MB */ | |
| + }; | |
| + | |
| + partition@800000 { | |
| + label = "minirootfs"; | |
| + reg = <0x0800000 0x400000>; /* 4MB */ | |
| + }; | |
| + | |
| + partition@c00000 { | |
| + label = "ubifs"; | |
| + reg = <0x0c00000 0x7200000>; /* 100MB */ | |
| + }; | |
| + | |
| + partition@7e00000 { | |
| + label = "dtb"; | |
| + reg = <0x7e00000 0x20000>; /* 128KB */ | |
| + }; | |
| + }; | |
| + | |
| + sdhci@d8000 { | |
| + broken-cd; | |
| + wp-inverted; | |
| + bus-width = <8>; | |
| + status = "okay"; | |
| + no-1-8-v; | |
| + }; | |
| + | |
| + usb3@f0000 { | |
| + status = "okay"; | |
| + }; | |
| + | |
| + usb3@f8000 { | |
| + status = "okay"; | |
| + }; | |
| + | |
| + usb@58000 { | |
| + status = "okay"; | |
| + }; | |
| + }; | |
| + | |
| + pcie-controller { | |
| + status = "okay"; | |
| + /* | |
| + * The two PCIe units are accessible through | |
| + * standard PCIe slots on the board. | |
| + */ | |
| + pcie@1,0 { | |
| + /* Port 0, Lane 0 */ | |
| + status = "okay"; | |
| + }; | |
| + pcie@2,0 { | |
| + /* Port 1, Lane 0 */ | |
| + status = "okay"; | |
| + }; | |
| + }; | |
| + }; | |
| + | |
| + gpio-leds{ | |
| + compatible = "gpio-leds"; | |
| + backup { | |
| + gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; | |
| + label = "backup"; | |
| + default-state = "off"; | |
| + }; | |
| + power { | |
| + gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; | |
| + label = "pwr"; | |
| + default-state = "keep"; | |
| + }; | |
| + sata1 { | |
| + gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; | |
| + label = "sata1"; | |
| + default-state = "keep"; | |
| + }; | |
| + sata2 { | |
| + gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; | |
| + label = "sata2"; | |
| + default-state = "keep"; | |
| + }; | |
| + }; | |
| + | |
| + gpio_keys { | |
| + compatible = "gpio-keys"; | |
| + #address-cells = <1>; | |
| + #size-cells = <0>; | |
| + button@1 { | |
| + label = "BT Reset"; | |
| + linux,code = <0x198>; | |
| + gpios = <&gpio0 19 GPIO_ACTIVE_LOW>; | |
| + debounce-interval = <0x64>; | |
| + }; | |
| + button@2 { | |
| + label = "BT Power"; | |
| + linux,code = <0x74>; | |
| + gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; | |
| + debounce-interval = <0x64>; | |
| + }; | |
| + /* | |
| + button@3 { | |
| + label = "BT Backup"; | |
| + linux,code = <0x165>; | |
| + gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; | |
| + debounce-interval = <0x64>; | |
| + }; | |
| + */ | |
| + }; | |
| + | |
| + gpio-poweroff { | |
| + compatible = "gpio-poweroff"; | |
| + gpios = <&gpio1 27 GPIO_ACTIVE_LOW>; | |
| + }; | |
| + | |
| + gpio-hdds-power { | |
| + compatible = "gpio-hdds-power"; | |
| + power-sata1 { | |
| + present-gpio = <&gpio0 24 GPIO_ACTIVE_LOW>; | |
| + power-gpio = <&gpio0 29 GPIO_ACTIVE_HIGH>; | |
| + led-gpio = <&gpio1 5 GPIO_ACTIVE_LOW>; | |
| + label = "power-sata1"; | |
| + }; | |
| + power-sata2 { | |
| + present-gpio = <&gpio0 26 GPIO_ACTIVE_LOW>; | |
| + power-gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>; | |
| + led-gpio = <&gpio1 7 GPIO_ACTIVE_LOW>; | |
| + label = "power-sata2"; | |
| + }; | |
| + power-sata3 { | |
| + present-gpio = <&gpio0 27 GPIO_ACTIVE_LOW>; | |
| + power-gpio = <&gpio1 20 GPIO_ACTIVE_HIGH>; | |
| + //led-gpio = <&gpio1 7 GPIO_ACTIVE_LOW>; | |
| + label = "power-sata3"; | |
| + }; | |
| + power-sata4 { | |
| + present-gpio = <&gpio1 18 GPIO_ACTIVE_LOW>; | |
| + power-gpio = <&gpio1 15 GPIO_ACTIVE_HIGH>; | |
| + //led-gpio = <&gpio1 7 GPIO_ACTIVE_LOW>; | |
| + label = "power-sata4"; | |
| + }; | |
| + }; | |
| + | |
| + pwm-fan-armada-38x { | |
| + compatible = "pwm-fan-armada-38x"; | |
| + ctrl-gpio = <&gpio0 2 GPIO_ACTIVE_HIGH>; | |
| + fb-gpio = <&gpio0 3 GPIO_ACTIVE_HIGH>; | |
| + }; | |
| + | |
| + gpio_lcd: gpio_lcd { | |
| + compatible = "gpio-lcd"; | |
| + lcm-data-4bit; | |
| + lcm-lines = <2>; | |
| + lcm-bits = <&gpio1 22 GPIO_ACTIVE_HIGH>, | |
| + <&gpio1 23 GPIO_ACTIVE_HIGH>, | |
| + <&gpio1 24 GPIO_ACTIVE_HIGH>, | |
| + <&gpio1 25 GPIO_ACTIVE_HIGH>; | |
| + lcm-rs = <&gpio1 12 GPIO_ACTIVE_HIGH>; | |
| + lcm-bl = <&gpio0 31 GPIO_ACTIVE_LOW>; | |
| + lcm-rw = <&gpio1 19 GPIO_ACTIVE_HIGH>; | |
| + lcm-en = <&gpio1 21 GPIO_ACTIVE_HIGH>; | |
| + }; | |
| + | |
| + readynas_lcd { | |
| + compatible = "readynas-lcd"; | |
| + lcd-device = <&gpio_lcd>; | |
| + }; | |
| +}; | |
| diff -x .git -Naur linux-4.4.111/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts linux-4.4.111-alpine/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts | |
| --- linux-4.4.111/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts 2018-02-20 12:32:32.378048950 -0500 | |
| +++ linux-4.4.111-alpine/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts 2018-02-14 21:04:17.000000000 -0500 | |
| @@ -196,12 +196,11 @@ | |
| partition@0 { | |
| label = "u-boot"; | |
| reg = <0x0000000 0x180000>; /* 1.5MB */ | |
| - read-only; | |
| }; | |
| partition@180000 { | |
| label = "u-boot-env"; | |
| - reg = <0x180000 0x20000>; /* 128KB */ | |
| + reg = <0x180000 0x80000>; /* 512KB */ | |
| read-only; | |
| }; | |
| @@ -293,6 +292,70 @@ | |
| pinctrl-names = "default"; | |
| gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; | |
| }; | |
| + | |
| + sata1_regulator: sata1-regulator { | |
| + compatible = "regulator-fixed"; | |
| + pinctrl-0 = <&sata1_power_pin &sata1_pres_pin>; | |
| + pinctrl-names = "default"; | |
| + regulator-type = "voltage"; | |
| + reg = <1>; | |
| + regulator-name = "SATA1 Power"; | |
| + regulator-min-microvolt = <5000000>; | |
| + regulator-max-microvolt = <5000000>; | |
| + | |
| + gpio = <&gpio0 24 GPIO_ACTIVE_LOW>; | |
| + toggle-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>; | |
| + | |
| + startup-delay-us = <3000000>; | |
| + }; | |
| + | |
| + sata2_regulator: sata2-regulator { | |
| + compatible = "regulator-fixed"; | |
| + pinctrl-0 = <&sata2_power_pin &sata2_pres_pin>; | |
| + pinctrl-names = "default"; | |
| + regulator-type = "voltage"; | |
| + reg = <1>; | |
| + regulator-name = "SATA2 Power"; | |
| + regulator-min-microvolt = <5000000>; | |
| + regulator-max-microvolt = <5000000>; | |
| + | |
| + gpio = <&gpio0 25 GPIO_ACTIVE_LOW>; | |
| + toggle-gpio = <&gpio1 1 GPIO_ACTIVE_LOW>; | |
| + | |
| + startup-delay-us = <3000000>; | |
| + }; | |
| + | |
| + sata3_regulator: sata3-regulator { | |
| + compatible = "regulator-fixed"; | |
| + pinctrl-0 = <&sata3_power_pin &sata3_pres_pin>; | |
| + pinctrl-names = "default"; | |
| + regulator-type = "voltage"; | |
| + reg = <1>; | |
| + regulator-name = "SATA3 Power"; | |
| + regulator-min-microvolt = <5000000>; | |
| + regulator-max-microvolt = <5000000>; | |
| + | |
| + gpio = <&gpio0 26 GPIO_ACTIVE_LOW>; | |
| + toggle-gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; | |
| + | |
| + startup-delay-us = <3000000>; | |
| + }; | |
| + | |
| + sata4_regulator: sata4-regulator { | |
| + compatible = "regulator-fixed"; | |
| + pinctrl-0 = <&sata4_power_pin &sata4_pres_pin>; | |
| + pinctrl-names = "default"; | |
| + regulator-type = "voltage"; | |
| + reg = <1>; | |
| + regulator-name = "SATA4 Power"; | |
| + regulator-min-microvolt = <5000000>; | |
| + regulator-max-microvolt = <5000000>; | |
| + | |
| + gpio = <&gpio0 28 GPIO_ACTIVE_LOW>; | |
| + toggle-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>; | |
| + | |
| + startup-delay-us = <3000000>; | |
| + }; | |
| }; | |
| &pinctrl { | |
| diff -x .git -Naur linux-4.4.111/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts linux-4.4.111-alpine/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts | |
| --- linux-4.4.111/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts 2018-02-20 12:32:32.538049576 -0500 | |
| +++ linux-4.4.111-alpine/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts 2018-02-14 21:04:17.000000000 -0500 | |
| @@ -130,29 +130,31 @@ | |
| pinctrl-names = "default"; | |
| power_led { | |
| - label = "status:blue:power_led"; | |
| + label = "status:blue:pwr"; | |
| gpios = <&gpio0 31 GPIO_ACTIVE_LOW>; | |
| default-state = "keep"; | |
| + linux,default-trigger = "timer"; | |
| }; | |
| activity_led { | |
| - label = "status:blue:activity_led"; | |
| + label = "status:blue:act"; | |
| gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; | |
| }; | |
| disk1_led { | |
| - label = "status:blue:disk1_led"; | |
| + label = "status:blue:sata1"; | |
| gpios = <&gpio0 23 GPIO_ACTIVE_LOW>; | |
| }; | |
| disk2_led { | |
| - label = "status:blue:disk2_led"; | |
| + label = "status:blue:sata2"; | |
| gpios = <&gpio0 22 GPIO_ACTIVE_LOW>; | |
| }; | |
| backup_led { | |
| - label = "status:blue:backup_led"; | |
| + label = "status:blue:backup"; | |
| gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; | |
| + default-state = "off"; | |
| }; | |
| }; | |
| diff -x .git -Naur linux-4.4.111/arch/arm/boot/dts/kirkwood-netgear_readynas_nv+_v2.dts linux-4.4.111-alpine/arch/arm/boot/dts/kirkwood-netgear_readynas_nv+_v2.dts | |
| --- linux-4.4.111/arch/arm/boot/dts/kirkwood-netgear_readynas_nv+_v2.dts 2018-02-20 12:32:32.538049576 -0500 | |
| +++ linux-4.4.111-alpine/arch/arm/boot/dts/kirkwood-netgear_readynas_nv+_v2.dts 2018-02-14 21:04:17.000000000 -0500 | |
| @@ -137,33 +137,34 @@ | |
| pinctrl-names = "default"; | |
| power_led { | |
| - label = "status:blue:power_led"; | |
| + label = "status:blue:pwr"; | |
| gpios = <&gpio0 31 GPIO_ACTIVE_LOW>; | |
| - linux,default-trigger = "default-on"; | |
| + linux,default-trigger = "timer"; | |
| }; | |
| backup_led { | |
| - label = "status:blue:backup_led"; | |
| + label = "status:blue:backup"; | |
| gpios = <&gpio0 22 GPIO_ACTIVE_LOW>; | |
| + default-state = "off"; | |
| }; | |
| disk1_led { | |
| - label = "status:blue:disk1_led"; | |
| + label = "status:blue:sata1"; | |
| gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; | |
| }; | |
| disk2_led { | |
| - label = "status:blue:disk2_led"; | |
| + label = "status:blue:sata2"; | |
| gpios = <&gpio0 23 GPIO_ACTIVE_LOW>; | |
| }; | |
| disk3_led { | |
| - label = "status:blue:disk3_led"; | |
| + label = "status:blue:sata3"; | |
| gpios = <&gpio0 24 GPIO_ACTIVE_LOW>; | |
| }; | |
| disk4_led { | |
| - label = "status:blue:disk4_led"; | |
| + label = "status:blue:sata4"; | |
| gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; | |
| }; | |
| }; | |
| diff -x .git -Naur linux-4.4.111/arch/arm/boot/dts/Makefile linux-4.4.111-alpine/arch/arm/boot/dts/Makefile | |
| --- linux-4.4.111/arch/arm/boot/dts/Makefile 2018-02-20 12:32:32.348048833 -0500 | |
| +++ linux-4.4.111-alpine/arch/arm/boot/dts/Makefile 2018-02-14 21:04:17.000000000 -0500 | |
| @@ -1,7 +1,5 @@ | |
| ifeq ($(CONFIG_OF),y) | |
| -dtb-$(CONFIG_ARCH_ALPINE) += \ | |
| - alpine-db.dtb | |
| dtb-$(CONFIG_MACH_ASM9260) += \ | |
| alphascale-asm9260-devkit.dtb | |
| # Keep at91 dtb files sorted alphabetically for each SoC | |
| @@ -745,6 +743,9 @@ | |
| dtb-$(CONFIG_MACH_ARMADA_375) += \ | |
| armada-375-db.dtb | |
| dtb-$(CONFIG_MACH_ARMADA_38X) += \ | |
| + armada-380-netgear-rn35.dtb \ | |
| + armada-385-netgear-rn114.dtb \ | |
| + armada-385-netgear-rn112.dtb \ | |
| armada-385-db-ap.dtb \ | |
| armada-385-linksys-caiman.dtb \ | |
| armada-385-linksys-cobra.dtb \ | |
| diff -x .git -Naur linux-4.4.111/arch/arm/configs/alpine_defconfig linux-4.4.111-alpine/arch/arm/configs/alpine_defconfig | |
| --- linux-4.4.111/arch/arm/configs/alpine_defconfig 1969-12-31 19:00:00.000000000 -0500 | |
| +++ linux-4.4.111-alpine/arch/arm/configs/alpine_defconfig 2018-02-14 21:04:17.000000000 -0500 | |
| @@ -0,0 +1,164 @@ | |
| +# CONFIG_LOCALVERSION_AUTO is not set | |
| +CONFIG_SYSVIPC=y | |
| +CONFIG_POSIX_MQUEUE=y | |
| +CONFIG_FHANDLE=y | |
| +CONFIG_NO_HZ=y | |
| +CONFIG_HIGH_RES_TIMERS=y | |
| +CONFIG_IKCONFIG=y | |
| +CONFIG_IKCONFIG_PROC=y | |
| +CONFIG_CGROUPS=y | |
| +CONFIG_BLK_DEV_INITRD=y | |
| +CONFIG_EXPERT=y | |
| +CONFIG_SYSCTL_SYSCALL=y | |
| +CONFIG_SLAB=y | |
| +CONFIG_PROFILING=y | |
| +CONFIG_MODULES=y | |
| +CONFIG_BLK_DEV_INTEGRITY=y | |
| +CONFIG_PARTITION_ADVANCED=y | |
| +CONFIG_LDM_PARTITION=y | |
| +CONFIG_ARCH_ALPINE=y | |
| +CONFIG_ARCH_VEXPRESS=y | |
| +CONFIG_ARM_LPAE=y | |
| +CONFIG_PCI_IOV=y | |
| +CONFIG_PCI_INTERNAL_ALPINE=y | |
| +CONFIG_PCI_EXTERNAL_ALPINE=y | |
| +CONFIG_SMP=y | |
| +CONFIG_AEABI=y | |
| +CONFIG_HIGHMEM=y | |
| +CONFIG_TRANSPARENT_HUGEPAGE=y | |
| +# CONFIG_SUSPEND is not set | |
| +CONFIG_NET=y | |
| +CONFIG_PACKET=y | |
| +CONFIG_UNIX=y | |
| +CONFIG_XFRM_USER=y | |
| +CONFIG_NET_KEY=y | |
| +CONFIG_INET=y | |
| +CONFIG_IP_MULTICAST=y | |
| +CONFIG_IP_PNP=y | |
| +CONFIG_IP_PNP_BOOTP=y | |
| +CONFIG_INET_AH=y | |
| +CONFIG_INET_ESP=y | |
| +# CONFIG_INET_DIAG is not set | |
| +# CONFIG_IPV6 is not set | |
| +CONFIG_NETFILTER=y | |
| +CONFIG_NF_CONNTRACK=y | |
| +CONFIG_NF_CONNTRACK_IPV4=y | |
| +CONFIG_IP_NF_IPTABLES=y | |
| +CONFIG_IP_NF_FILTER=y | |
| +CONFIG_IP_NF_NAT=y | |
| +CONFIG_IP_NF_TARGET_MASQUERADE=y | |
| +CONFIG_BRIDGE=y | |
| +CONFIG_DEVTMPFS=y | |
| +CONFIG_DEVTMPFS_MOUNT=y | |
| +CONFIG_MTD=y | |
| +CONFIG_MTD_NAND=y | |
| +CONFIG_MTD_NAND_AL=y | |
| +CONFIG_MTD_UBI=y | |
| +# CONFIG_BLK_DEV is not set | |
| +CONFIG_RAID_ATTRS=y | |
| +CONFIG_BLK_DEV_SD=y | |
| +CONFIG_SCSI_SAS_ATTRS=y | |
| +CONFIG_SCSI_MPT2SAS=m | |
| +CONFIG_ATA=y | |
| +# CONFIG_SATA_PMP is not set | |
| +CONFIG_SATA_AHCI=y | |
| +CONFIG_SATA_AHCI_PLATFORM=y | |
| +CONFIG_AHCI_ALPINE=y | |
| +CONFIG_SATA_SIL24=m | |
| +CONFIG_SATA_MV=y | |
| +CONFIG_MD=y | |
| +CONFIG_MD_RAID0=y | |
| +CONFIG_BLK_DEV_DM=y | |
| +CONFIG_DM_CRYPT=y | |
| +CONFIG_DM_RAID=y | |
| +CONFIG_DM_MULTIPATH=y | |
| +CONFIG_DM_UEVENT=y | |
| +CONFIG_TARGET_CORE=m | |
| +CONFIG_ISCSI_TARGET=m | |
| +CONFIG_NETDEVICES=y | |
| +CONFIG_BONDING=m | |
| +CONFIG_NET_TEAM=m | |
| +CONFIG_NET_TEAM_MODE_BROADCAST=m | |
| +CONFIG_NET_TEAM_MODE_ROUNDROBIN=m | |
| +CONFIG_NET_TEAM_MODE_RANDOM=m | |
| +CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m | |
| +CONFIG_NET_TEAM_MODE_LOADBALANCE=m | |
| +CONFIG_NET_AL_ETH=y | |
| +CONFIG_E100=m | |
| +CONFIG_E1000=m | |
| +CONFIG_E1000E=m | |
| +CONFIG_IGB=m | |
| +CONFIG_IGBVF=m | |
| +CONFIG_IXGBE=m | |
| +CONFIG_IXGBEVF=m | |
| +CONFIG_AT803X_PHY=y | |
| +CONFIG_INPUT_EVDEV=y | |
| +# CONFIG_SERIO_SERPORT is not set | |
| +CONFIG_SERIO_AMBAKMI=y | |
| +CONFIG_LEGACY_PTY_COUNT=16 | |
| +CONFIG_SERIAL_8250=y | |
| +CONFIG_SERIAL_8250_CONSOLE=y | |
| +CONFIG_SERIAL_8250_RUNTIME_UARTS=1 | |
| +CONFIG_SERIAL_8250_EXTENDED=y | |
| +CONFIG_SERIAL_8250_MANY_PORTS=y | |
| +CONFIG_SERIAL_8250_SHARE_IRQ=y | |
| +CONFIG_SERIAL_8250_RSA=y | |
| +CONFIG_SERIAL_8250_DW=y | |
| +CONFIG_SERIAL_OF_PLATFORM=y | |
| +CONFIG_HW_RANDOM=y | |
| +CONFIG_I2C=y | |
| +CONFIG_I2C_MUX=y | |
| +CONFIG_I2C_MUX_PCA9541=y | |
| +CONFIG_I2C_MUX_PCA954x=y | |
| +CONFIG_I2C_DESIGNWARE_PLATFORM=y | |
| +# CONFIG_HWMON is not set | |
| +CONFIG_THERMAL=y | |
| +CONFIG_AL_THERMAL=y | |
| +CONFIG_USB=y | |
| +CONFIG_USB_XHCI_HCD=y | |
| +CONFIG_USB_EHCI_HCD=y | |
| +CONFIG_USB_EHCI_HCD_PLATFORM=y | |
| +CONFIG_USB_OHCI_HCD=y | |
| +CONFIG_DMADEVICES=y | |
| +CONFIG_DMADEVICES_DEBUG=y | |
| +CONFIG_DMADEVICES_VDEBUG=y | |
| +CONFIG_ASYNC_TX_DMA=y | |
| +CONFIG_DMATEST=y | |
| +CONFIG_AL_DMA=y | |
| +CONFIG_AL_DMA_STATS=y | |
| +CONFIG_AL_DMA_PCI_IOV=y | |
| +CONFIG_UIO=y | |
| +# CONFIG_IOMMU_SUPPORT is not set | |
| +CONFIG_LFS_ON_32CPU=y | |
| +CONFIG_EXT2_FS=y | |
| +CONFIG_EXT3_FS=y | |
| +CONFIG_EXT4_FS=y | |
| +CONFIG_BTRFS_FS=y | |
| +CONFIG_VFAT_FS=y | |
| +CONFIG_TMPFS=y | |
| +CONFIG_TMPFS_POSIX_ACL=y | |
| +CONFIG_CONFIGFS_FS=y | |
| +CONFIG_ECRYPT_FS=y | |
| +CONFIG_UBIFS_FS=y | |
| +# CONFIG_NETWORK_FILESYSTEMS is not set | |
| +CONFIG_NLS_CODEPAGE_850=y | |
| +CONFIG_NLS_ISO8859_1=y | |
| +CONFIG_PRINTK_TIME=y | |
| +CONFIG_MESSAGE_LOGLEVEL_DEFAULT=7 | |
| +CONFIG_DYNAMIC_DEBUG=y | |
| +CONFIG_DEBUG_INFO=y | |
| +CONFIG_MAGIC_SYSRQ=y | |
| +CONFIG_PANIC_ON_OOPS=y | |
| +CONFIG_ENABLE_DEFAULT_TRACERS=y | |
| +CONFIG_DEBUG_USER=y | |
| +CONFIG_DEBUG_LL=y | |
| +CONFIG_EARLY_PRINTK=y | |
| +CONFIG_KEYS=y | |
| +CONFIG_ENCRYPTED_KEYS=y | |
| +# CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set | |
| +CONFIG_CRYPTO_CMAC=y | |
| +CONFIG_CRYPTO_MD4=y | |
| +CONFIG_CRYPTO_ARC4=y | |
| +CONFIG_CRYPTO_DEV_AL_CRYPTO=y | |
| +CONFIG_CRYPTO_DEV_AL_CRYPTO_STATS=y | |
| +CONFIG_LIBCRC32C=y | |
| diff -x .git -Naur linux-4.4.111/arch/arm/configs/defconfig.alpine linux-4.4.111-alpine/arch/arm/configs/defconfig.alpine | |
| --- linux-4.4.111/arch/arm/configs/defconfig.alpine 1969-12-31 19:00:00.000000000 -0500 | |
| +++ linux-4.4.111-alpine/arch/arm/configs/defconfig.alpine 2018-02-14 21:04:17.000000000 -0500 | |
| @@ -0,0 +1,3437 @@ | |
| +# | |
| +# Automatically generated file; DO NOT EDIT. | |
| +# Linux/arm 4.4.111 Kernel Configuration | |
| +# | |
| +CONFIG_ARM=y | |
| +CONFIG_ARM_HAS_SG_CHAIN=y | |
| +CONFIG_MIGHT_HAVE_PCI=y | |
| +CONFIG_SYS_SUPPORTS_APM_EMULATION=y | |
| +CONFIG_HAVE_PROC_CPU=y | |
| +CONFIG_STACKTRACE_SUPPORT=y | |
| +CONFIG_LOCKDEP_SUPPORT=y | |
| +CONFIG_TRACE_IRQFLAGS_SUPPORT=y | |
| +CONFIG_RWSEM_XCHGADD_ALGORITHM=y | |
| +CONFIG_FIX_EARLYCON_MEM=y | |
| +CONFIG_GENERIC_HWEIGHT=y | |
| +CONFIG_GENERIC_CALIBRATE_DELAY=y | |
| +CONFIG_NEED_DMA_MAP_STATE=y | |
| +CONFIG_ARCH_SUPPORTS_UPROBES=y | |
| +CONFIG_VECTORS_BASE=0xffff0000 | |
| +CONFIG_ARM_PATCH_PHYS_VIRT=y | |
| +CONFIG_GENERIC_BUG=y | |
| +CONFIG_PGTABLE_LEVELS=3 | |
| +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" | |
| +CONFIG_IRQ_WORK=y | |
| +CONFIG_BUILDTIME_EXTABLE_SORT=y | |
| + | |
| +# | |
| +# General setup | |
| +# | |
| +CONFIG_INIT_ENV_ARG_LIMIT=32 | |
| +CONFIG_CROSS_COMPILE="arm-linux-gnueabihf-" | |
| +# CONFIG_COMPILE_TEST is not set | |
| +CONFIG_LOCALVERSION=".alpine.1" | |
| +CONFIG_LOCALVERSION_AUTO=y | |
| +CONFIG_HAVE_KERNEL_GZIP=y | |
| +CONFIG_HAVE_KERNEL_LZMA=y | |
| +CONFIG_HAVE_KERNEL_XZ=y | |
| +CONFIG_HAVE_KERNEL_LZO=y | |
| +CONFIG_HAVE_KERNEL_LZ4=y | |
| +# CONFIG_KERNEL_GZIP is not set | |
| +# CONFIG_KERNEL_LZMA is not set | |
| +CONFIG_KERNEL_XZ=y | |
| +# CONFIG_KERNEL_LZO is not set | |
| +# CONFIG_KERNEL_LZ4 is not set | |
| +CONFIG_DEFAULT_HOSTNAME="readynasos" | |
| +CONFIG_SWAP=y | |
| +CONFIG_SYSVIPC=y | |
| +CONFIG_SYSVIPC_SYSCTL=y | |
| +CONFIG_POSIX_MQUEUE=y | |
| +CONFIG_POSIX_MQUEUE_SYSCTL=y | |
| +CONFIG_CROSS_MEMORY_ATTACH=y | |
| +CONFIG_FHANDLE=y | |
| +CONFIG_USELIB=y | |
| +# CONFIG_AUDIT is not set | |
| +CONFIG_HAVE_ARCH_AUDITSYSCALL=y | |
| + | |
| +# | |
| +# IRQ subsystem | |
| +# | |
| +CONFIG_GENERIC_IRQ_PROBE=y | |
| +CONFIG_GENERIC_IRQ_SHOW=y | |
| +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y | |
| +CONFIG_HARDIRQS_SW_RESEND=y | |
| +CONFIG_GENERIC_IRQ_CHIP=y | |
| +CONFIG_IRQ_DOMAIN=y | |
| +CONFIG_IRQ_DOMAIN_HIERARCHY=y | |
| +CONFIG_GENERIC_MSI_IRQ=y | |
| +CONFIG_GENERIC_MSI_IRQ_DOMAIN=y | |
| +CONFIG_HANDLE_DOMAIN_IRQ=y | |
| +CONFIG_IRQ_FORCED_THREADING=y | |
| +CONFIG_SPARSE_IRQ=y | |
| +CONFIG_GENERIC_TIME_VSYSCALL=y | |
| +CONFIG_GENERIC_CLOCKEVENTS=y | |
| +CONFIG_ARCH_HAS_TICK_BROADCAST=y | |
| +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y | |
| + | |
| +# | |
| +# Timers subsystem | |
| +# | |
| +CONFIG_TICK_ONESHOT=y | |
| +CONFIG_NO_HZ_COMMON=y | |
| +# CONFIG_HZ_PERIODIC is not set | |
| +CONFIG_NO_HZ_IDLE=y | |
| +# CONFIG_NO_HZ_FULL is not set | |
| +CONFIG_NO_HZ=y | |
| +# CONFIG_HIGH_RES_TIMERS is not set | |
| + | |
| +# | |
| +# CPU/Task time and stats accounting | |
| +# | |
| +CONFIG_TICK_CPU_ACCOUNTING=y | |
| +# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set | |
| +# CONFIG_IRQ_TIME_ACCOUNTING is not set | |
| +CONFIG_BSD_PROCESS_ACCT=y | |
| +# CONFIG_BSD_PROCESS_ACCT_V3 is not set | |
| +CONFIG_TASKSTATS=y | |
| +CONFIG_TASK_DELAY_ACCT=y | |
| +CONFIG_TASK_XACCT=y | |
| +CONFIG_TASK_IO_ACCOUNTING=y | |
| + | |
| +# | |
| +# RCU Subsystem | |
| +# | |
| +CONFIG_TREE_RCU=y | |
| +# CONFIG_RCU_EXPERT is not set | |
| +CONFIG_SRCU=y | |
| +# CONFIG_TASKS_RCU is not set | |
| +CONFIG_RCU_STALL_COMMON=y | |
| +# CONFIG_TREE_RCU_TRACE is not set | |
| +# CONFIG_RCU_EXPEDITE_BOOT is not set | |
| +CONFIG_BUILD_BIN2C=y | |
| +CONFIG_IKCONFIG=m | |
| +CONFIG_IKCONFIG_PROC=y | |
| +CONFIG_LOG_BUF_SHIFT=17 | |
| +CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 | |
| +CONFIG_GENERIC_SCHED_CLOCK=y | |
| +CONFIG_CGROUPS=y | |
| +# CONFIG_CGROUP_DEBUG is not set | |
| +CONFIG_CGROUP_FREEZER=y | |
| +# CONFIG_CGROUP_PIDS is not set | |
| +CONFIG_CGROUP_DEVICE=y | |
| +CONFIG_CPUSETS=y | |
| +# CONFIG_PROC_PID_CPUSET is not set | |
| +CONFIG_CGROUP_CPUACCT=y | |
| +# CONFIG_MEMCG is not set | |
| +CONFIG_CGROUP_SCHED=y | |
| +CONFIG_FAIR_GROUP_SCHED=y | |
| +CONFIG_CFS_BANDWIDTH=y | |
| +CONFIG_RT_GROUP_SCHED=y | |
| +CONFIG_BLK_CGROUP=y | |
| +# CONFIG_DEBUG_BLK_CGROUP is not set | |
| +# CONFIG_CHECKPOINT_RESTORE is not set | |
| +CONFIG_NAMESPACES=y | |
| +CONFIG_UTS_NS=y | |
| +CONFIG_IPC_NS=y | |
| +CONFIG_USER_NS=y | |
| +CONFIG_PID_NS=y | |
| +CONFIG_NET_NS=y | |
| +# CONFIG_SCHED_AUTOGROUP is not set | |
| +# CONFIG_SYSFS_DEPRECATED is not set | |
| +# CONFIG_RELAY is not set | |
| +CONFIG_BLK_DEV_INITRD=y | |
| +CONFIG_INITRAMFS_SOURCE="" | |
| +CONFIG_RD_GZIP=y | |
| +# CONFIG_RD_BZIP2 is not set | |
| +CONFIG_RD_LZMA=y | |
| +CONFIG_RD_XZ=y | |
| +# CONFIG_RD_LZO is not set | |
| +# CONFIG_RD_LZ4 is not set | |
| +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set | |
| +CONFIG_SYSCTL=y | |
| +CONFIG_ANON_INODES=y | |
| +CONFIG_HAVE_UID16=y | |
| +CONFIG_BPF=y | |
| +CONFIG_EXPERT=y | |
| +CONFIG_UID16=y | |
| +CONFIG_MULTIUSER=y | |
| +CONFIG_SGETMASK_SYSCALL=y | |
| +CONFIG_SYSFS_SYSCALL=y | |
| +CONFIG_SYSCTL_SYSCALL=y | |
| +CONFIG_KALLSYMS=y | |
| +# CONFIG_KALLSYMS_ALL is not set | |
| +CONFIG_PRINTK=y | |
| +CONFIG_BUG=y | |
| +CONFIG_ELF_CORE=y | |
| +CONFIG_BASE_FULL=y | |
| +CONFIG_FUTEX=y | |
| +CONFIG_EPOLL=y | |
| +CONFIG_SIGNALFD=y | |
| +CONFIG_TIMERFD=y | |
| +CONFIG_EVENTFD=y | |
| +# CONFIG_BPF_SYSCALL is not set | |
| +CONFIG_SHMEM=y | |
| +CONFIG_AIO=y | |
| +CONFIG_ADVISE_SYSCALLS=y | |
| +# CONFIG_USERFAULTFD is not set | |
| +CONFIG_PCI_QUIRKS=y | |
| +CONFIG_MEMBARRIER=y | |
| +CONFIG_EMBEDDED=y | |
| +CONFIG_HAVE_PERF_EVENTS=y | |
| +CONFIG_PERF_USE_VMALLOC=y | |
| + | |
| +# | |
| +# Kernel Performance Events And Counters | |
| +# | |
| +# CONFIG_PERF_EVENTS is not set | |
| +CONFIG_VM_EVENT_COUNTERS=y | |
| +CONFIG_SLUB_DEBUG=y | |
| +# CONFIG_COMPAT_BRK is not set | |
| +# CONFIG_SLAB is not set | |
| +CONFIG_SLUB=y | |
| +# CONFIG_SLOB is not set | |
| +CONFIG_SLUB_CPU_PARTIAL=y | |
| +# CONFIG_SYSTEM_DATA_VERIFICATION is not set | |
| +# CONFIG_PROFILING is not set | |
| +CONFIG_HAVE_OPROFILE=y | |
| +# CONFIG_KPROBES is not set | |
| +CONFIG_JUMP_LABEL=y | |
| +# CONFIG_STATIC_KEYS_SELFTEST is not set | |
| +# CONFIG_UPROBES is not set | |
| +# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set | |
| +CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y | |
| +CONFIG_ARCH_USE_BUILTIN_BSWAP=y | |
| +CONFIG_HAVE_KPROBES=y | |
| +CONFIG_HAVE_KRETPROBES=y | |
| +CONFIG_HAVE_OPTPROBES=y | |
| +CONFIG_HAVE_ARCH_TRACEHOOK=y | |
| +CONFIG_HAVE_DMA_ATTRS=y | |
| +CONFIG_HAVE_DMA_CONTIGUOUS=y | |
| +CONFIG_GENERIC_SMP_IDLE_THREAD=y | |
| +CONFIG_GENERIC_IDLE_POLL_SETUP=y | |
| +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y | |
| +CONFIG_HAVE_CLK=y | |
| +CONFIG_HAVE_DMA_API_DEBUG=y | |
| +CONFIG_HAVE_PERF_REGS=y | |
| +CONFIG_HAVE_PERF_USER_STACK_DUMP=y | |
| +CONFIG_HAVE_ARCH_JUMP_LABEL=y | |
| +CONFIG_HAVE_RCU_TABLE_FREE=y | |
| +CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y | |
| +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y | |
| +CONFIG_SECCOMP_FILTER=y | |
| +CONFIG_HAVE_CC_STACKPROTECTOR=y | |
| +# CONFIG_CC_STACKPROTECTOR is not set | |
| +CONFIG_CC_STACKPROTECTOR_NONE=y | |
| +# CONFIG_CC_STACKPROTECTOR_REGULAR is not set | |
| +# CONFIG_CC_STACKPROTECTOR_STRONG is not set | |
| +CONFIG_HAVE_CONTEXT_TRACKING=y | |
| +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y | |
| +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y | |
| +CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y | |
| +CONFIG_HAVE_MOD_ARCH_SPECIFIC=y | |
| +CONFIG_MODULES_USE_ELF_REL=y | |
| +CONFIG_ARCH_HAS_ELF_RANDOMIZE=y | |
| +CONFIG_CLONE_BACKWARDS=y | |
| +CONFIG_OLD_SIGSUSPEND3=y | |
| +CONFIG_OLD_SIGACTION=y | |
| + | |
| +# | |
| +# GCOV-based kernel profiling | |
| +# | |
| +CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y | |
| +CONFIG_HAVE_GENERIC_DMA_COHERENT=y | |
| +CONFIG_SLABINFO=y | |
| +CONFIG_RT_MUTEXES=y | |
| +CONFIG_BASE_SMALL=0 | |
| +CONFIG_MODULES=y | |
| +# CONFIG_MODULE_FORCE_LOAD is not set | |
| +CONFIG_MODULE_UNLOAD=y | |
| +# CONFIG_MODULE_FORCE_UNLOAD is not set | |
| +CONFIG_MODVERSIONS=y | |
| +# CONFIG_MODULE_SRCVERSION_ALL is not set | |
| +# CONFIG_MODULE_SIG is not set | |
| +# CONFIG_MODULE_COMPRESS is not set | |
| +CONFIG_BLOCK=y | |
| +CONFIG_LBDAF=y | |
| +CONFIG_BLK_DEV_BSG=y | |
| +CONFIG_BLK_DEV_BSGLIB=y | |
| +# CONFIG_BLK_DEV_INTEGRITY is not set | |
| +# CONFIG_BLK_DEV_THROTTLING is not set | |
| +# CONFIG_BLK_CMDLINE_PARSER is not set | |
| + | |
| +# | |
| +# Partition Types | |
| +# | |
| +CONFIG_PARTITION_ADVANCED=y | |
| +# CONFIG_ACORN_PARTITION is not set | |
| +# CONFIG_AIX_PARTITION is not set | |
| +# CONFIG_OSF_PARTITION is not set | |
| +# CONFIG_AMIGA_PARTITION is not set | |
| +# CONFIG_ATARI_PARTITION is not set | |
| +# CONFIG_MAC_PARTITION is not set | |
| +CONFIG_MSDOS_PARTITION=y | |
| +CONFIG_BSD_DISKLABEL=y | |
| +# CONFIG_MINIX_SUBPARTITION is not set | |
| +CONFIG_SOLARIS_X86_PARTITION=y | |
| +CONFIG_UNIXWARE_DISKLABEL=y | |
| +CONFIG_LDM_PARTITION=y | |
| +# CONFIG_LDM_DEBUG is not set | |
| +# CONFIG_SGI_PARTITION is not set | |
| +# CONFIG_ULTRIX_PARTITION is not set | |
| +# CONFIG_SUN_PARTITION is not set | |
| +# CONFIG_KARMA_PARTITION is not set | |
| +CONFIG_EFI_PARTITION=y | |
| +# CONFIG_SYSV68_PARTITION is not set | |
| +# CONFIG_CMDLINE_PARTITION is not set | |
| + | |
| +# | |
| +# IO Schedulers | |
| +# | |
| +CONFIG_IOSCHED_NOOP=y | |
| +CONFIG_IOSCHED_DEADLINE=y | |
| +CONFIG_IOSCHED_CFQ=y | |
| +# CONFIG_CFQ_GROUP_IOSCHED is not set | |
| +CONFIG_IOSCHED_BFQ=y | |
| +CONFIG_BFQ_GROUP_IOSCHED=y | |
| +# CONFIG_DEFAULT_DEADLINE is not set | |
| +CONFIG_DEFAULT_CFQ=y | |
| +# CONFIG_DEFAULT_BFQ is not set | |
| +# CONFIG_DEFAULT_NOOP is not set | |
| +CONFIG_DEFAULT_IOSCHED="cfq" | |
| +CONFIG_INLINE_SPIN_UNLOCK_IRQ=y | |
| +CONFIG_INLINE_READ_UNLOCK=y | |
| +CONFIG_INLINE_READ_UNLOCK_IRQ=y | |
| +CONFIG_INLINE_WRITE_UNLOCK=y | |
| +CONFIG_INLINE_WRITE_UNLOCK_IRQ=y | |
| +CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y | |
| +CONFIG_MUTEX_SPIN_ON_OWNER=y | |
| +CONFIG_RWSEM_SPIN_ON_OWNER=y | |
| +CONFIG_LOCK_SPIN_ON_OWNER=y | |
| +CONFIG_FREEZER=y | |
| + | |
| +# | |
| +# System Type | |
| +# | |
| +CONFIG_MMU=y | |
| +CONFIG_ARCH_MULTIPLATFORM=y | |
| +# CONFIG_ARCH_REALVIEW is not set | |
| +# CONFIG_ARCH_VERSATILE is not set | |
| +# CONFIG_ARCH_CLPS711X is not set | |
| +# CONFIG_ARCH_GEMINI is not set | |
| +# CONFIG_ARCH_EBSA110 is not set | |
| +# CONFIG_ARCH_EP93XX is not set | |
| +# CONFIG_ARCH_FOOTBRIDGE is not set | |
| +# CONFIG_ARCH_NETX is not set | |
| +# CONFIG_ARCH_IOP13XX is not set | |
| +# CONFIG_ARCH_IOP32X is not set | |
| +# CONFIG_ARCH_IOP33X is not set | |
| +# CONFIG_ARCH_IXP4XX is not set | |
| +# CONFIG_ARCH_DOVE is not set | |
| +# CONFIG_ARCH_MV78XX0 is not set | |
| +# CONFIG_ARCH_ORION5X is not set | |
| +# CONFIG_ARCH_MMP is not set | |
| +# CONFIG_ARCH_KS8695 is not set | |
| +# CONFIG_ARCH_W90X900 is not set | |
| +# CONFIG_ARCH_LPC32XX is not set | |
| +# CONFIG_ARCH_PXA is not set | |
| +# CONFIG_ARCH_RPC is not set | |
| +# CONFIG_ARCH_SA1100 is not set | |
| +# CONFIG_ARCH_S3C24XX is not set | |
| +# CONFIG_ARCH_S3C64XX is not set | |
| +# CONFIG_ARCH_DAVINCI is not set | |
| +# CONFIG_ARCH_OMAP1 is not set | |
| + | |
| +# | |
| +# Multiple platform selection | |
| +# | |
| + | |
| +# | |
| +# CPU Core family selection | |
| +# | |
| +# CONFIG_ARCH_MULTI_V6 is not set | |
| +CONFIG_ARCH_MULTI_V7=y | |
| +CONFIG_ARCH_MULTI_V6_V7=y | |
| +# CONFIG_ARCH_MULTI_CPU_AUTO is not set | |
| +# CONFIG_ARCH_VIRT is not set | |
| +# CONFIG_ARCH_MVEBU is not set | |
| +CONFIG_ARCH_ALPINE=y | |
| +# CONFIG_ARCH_AT91 is not set | |
| +# CONFIG_ARCH_AXXIA is not set | |
| +# CONFIG_ARCH_BCM is not set | |
| +# CONFIG_ARCH_BERLIN is not set | |
| +# CONFIG_ARCH_DIGICOLOR is not set | |
| +# CONFIG_ARCH_HIGHBANK is not set | |
| +# CONFIG_ARCH_HISI is not set | |
| +# CONFIG_ARCH_KEYSTONE is not set | |
| +# CONFIG_ARCH_MESON is not set | |
| +# CONFIG_ARCH_MXC is not set | |
| +# CONFIG_ARCH_MEDIATEK is not set | |
| + | |
| +# | |
| +# TI OMAP/AM/DM/DRA Family | |
| +# | |
| +# CONFIG_ARCH_OMAP3 is not set | |
| +# CONFIG_ARCH_OMAP4 is not set | |
| +# CONFIG_SOC_OMAP5 is not set | |
| +# CONFIG_SOC_AM33XX is not set | |
| +# CONFIG_SOC_AM43XX is not set | |
| +# CONFIG_SOC_DRA7XX is not set | |
| +# CONFIG_ARCH_QCOM is not set | |
| +# CONFIG_ARCH_ROCKCHIP is not set | |
| +# CONFIG_ARCH_SOCFPGA is not set | |
| +# CONFIG_PLAT_SPEAR is not set | |
| +# CONFIG_ARCH_STI is not set | |
| +# CONFIG_ARCH_S5PV210 is not set | |
| +# CONFIG_ARCH_EXYNOS is not set | |
| +# CONFIG_ARCH_SHMOBILE_MULTI is not set | |
| +# CONFIG_ARCH_SUNXI is not set | |
| +# CONFIG_ARCH_SIRF is not set | |
| +# CONFIG_ARCH_TEGRA is not set | |
| +# CONFIG_ARCH_UNIPHIER is not set | |
| +# CONFIG_ARCH_U8500 is not set | |
| +# CONFIG_ARCH_VEXPRESS is not set | |
| +# CONFIG_ARCH_WM8850 is not set | |
| +# CONFIG_ARCH_ZX is not set | |
| +# CONFIG_ARCH_ZYNQ is not set | |
| + | |
| +# | |
| +# Processor Type | |
| +# | |
| +CONFIG_CPU_V7=y | |
| +CONFIG_CPU_32v6K=y | |
| +CONFIG_CPU_32v7=y | |
| +CONFIG_CPU_ABRT_EV7=y | |
| +CONFIG_CPU_PABRT_V7=y | |
| +CONFIG_CPU_CACHE_V7=y | |
| +CONFIG_CPU_CACHE_VIPT=y | |
| +CONFIG_CPU_COPY_V6=y | |
| +CONFIG_CPU_TLB_V7=y | |
| +CONFIG_CPU_HAS_ASID=y | |
| +CONFIG_CPU_CP15=y | |
| +CONFIG_CPU_CP15_MMU=y | |
| + | |
| +# | |
| +# Processor Features | |
| +# | |
| +CONFIG_ARM_LPAE=y | |
| +CONFIG_ARCH_PHYS_ADDR_T_64BIT=y | |
| +CONFIG_ARM_THUMB=y | |
| +# CONFIG_ARM_THUMBEE is not set | |
| +CONFIG_ARM_VIRT_EXT=y | |
| +CONFIG_SWP_EMULATE=y | |
| +# CONFIG_CPU_ICACHE_DISABLE is not set | |
| +# CONFIG_CPU_BPREDICT_DISABLE is not set | |
| +CONFIG_KUSER_HELPERS=y | |
| +CONFIG_VDSO=y | |
| +CONFIG_MIGHT_HAVE_CACHE_L2X0=y | |
| +# CONFIG_CACHE_L2X0 is not set | |
| +CONFIG_ARM_L1_CACHE_SHIFT_6=y | |
| +CONFIG_ARM_L1_CACHE_SHIFT=6 | |
| +CONFIG_ARM_DMA_MEM_BUFFERABLE=y | |
| +# CONFIG_ARM_KERNMEM_PERMS is not set | |
| +CONFIG_MULTI_IRQ_HANDLER=y | |
| +# CONFIG_ARM_ERRATA_430973 is not set | |
| +# CONFIG_ARM_ERRATA_643719 is not set | |
| +CONFIG_ARM_ERRATA_720789=y | |
| +# CONFIG_ARM_ERRATA_754322 is not set | |
| +# CONFIG_ARM_ERRATA_754327 is not set | |
| +# CONFIG_ARM_ERRATA_764369 is not set | |
| +# CONFIG_ARM_ERRATA_775420 is not set | |
| +# CONFIG_ARM_ERRATA_798181 is not set | |
| +# CONFIG_ARM_ERRATA_773022 is not set | |
| + | |
| +# | |
| +# Bus support | |
| +# | |
| +CONFIG_PCI=y | |
| +CONFIG_PCI_DOMAINS=y | |
| +CONFIG_PCI_DOMAINS_GENERIC=y | |
| +CONFIG_PCI_SYSCALL=y | |
| +CONFIG_PCI_MSI=y | |
| +CONFIG_PCI_MSI_IRQ_DOMAIN=y | |
| +# CONFIG_PCI_DEBUG is not set | |
| +# CONFIG_PCI_REALLOC_ENABLE_AUTO is not set | |
| +# CONFIG_PCI_STUB is not set | |
| +CONFIG_PCI_ATS=y | |
| +CONFIG_PCI_IOV=y | |
| +# CONFIG_PCI_PRI is not set | |
| +# CONFIG_PCI_PASID is not set | |
| + | |
| +# | |
| +# PCI host controller drivers | |
| +# | |
| +CONFIG_PCI_INTERNAL_ALPINE=y | |
| +CONFIG_PCI_EXTERNAL_ALPINE=y | |
| +# CONFIG_PCI_HOST_GENERIC is not set | |
| +# CONFIG_PCI_LAYERSCAPE is not set | |
| +# CONFIG_PCIE_IPROC is not set | |
| +# CONFIG_PCIE_ALTERA is not set | |
| +# CONFIG_PCIEPORTBUS is not set | |
| +# CONFIG_PCCARD is not set | |
| + | |
| +# | |
| +# Kernel Features | |
| +# | |
| +CONFIG_HAVE_SMP=y | |
| +CONFIG_SMP=y | |
| +# CONFIG_SMP_ON_UP is not set | |
| +CONFIG_ARM_CPU_TOPOLOGY=y | |
| +# CONFIG_SCHED_MC is not set | |
| +# CONFIG_SCHED_SMT is not set | |
| +CONFIG_HAVE_ARM_ARCH_TIMER=y | |
| +# CONFIG_MCPM is not set | |
| +# CONFIG_BIG_LITTLE is not set | |
| +CONFIG_VMSPLIT_3G=y | |
| +# CONFIG_VMSPLIT_3G_OPT is not set | |
| +# CONFIG_VMSPLIT_2G is not set | |
| +# CONFIG_VMSPLIT_1G is not set | |
| +CONFIG_PAGE_OFFSET=0xC0000000 | |
| +CONFIG_NR_CPUS=4 | |
| +CONFIG_HOTPLUG_CPU=y | |
| +# CONFIG_ARM_PSCI is not set | |
| +CONFIG_ARCH_NR_GPIO=0 | |
| +# CONFIG_PREEMPT_NONE is not set | |
| +CONFIG_PREEMPT_VOLUNTARY=y | |
| +# CONFIG_PREEMPT is not set | |
| +CONFIG_HZ_FIXED=0 | |
| +CONFIG_HZ_100=y | |
| +# CONFIG_HZ_200 is not set | |
| +# CONFIG_HZ_250 is not set | |
| +# CONFIG_HZ_300 is not set | |
| +# CONFIG_HZ_500 is not set | |
| +# CONFIG_HZ_1000 is not set | |
| +CONFIG_HZ=100 | |
| +# CONFIG_SCHED_HRTICK is not set | |
| +# CONFIG_THUMB2_KERNEL is not set | |
| +CONFIG_AEABI=y | |
| +# CONFIG_OABI_COMPAT is not set | |
| +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set | |
| +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set | |
| +CONFIG_HAVE_ARCH_PFN_VALID=y | |
| +CONFIG_HAVE_GENERIC_RCU_GUP=y | |
| +CONFIG_HIGHMEM=y | |
| +# CONFIG_HIGHPTE is not set | |
| +CONFIG_SYS_SUPPORTS_HUGETLBFS=y | |
| +CONFIG_ARCH_WANT_GENERAL_HUGETLB=y | |
| +# CONFIG_ARM_MODULE_PLTS is not set | |
| +CONFIG_FLATMEM=y | |
| +CONFIG_FLAT_NODE_MEM_MAP=y | |
| +CONFIG_HAVE_MEMBLOCK=y | |
| +CONFIG_NO_BOOTMEM=y | |
| +# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set | |
| +CONFIG_SPLIT_PTLOCK_CPUS=4 | |
| +# CONFIG_COMPACTION is not set | |
| +CONFIG_PHYS_ADDR_T_64BIT=y | |
| +CONFIG_ZONE_DMA_FLAG=0 | |
| +CONFIG_BOUNCE=y | |
| +# CONFIG_KSM is not set | |
| +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 | |
| +# CONFIG_TRANSPARENT_HUGEPAGE is not set | |
| +# CONFIG_CLEANCACHE is not set | |
| +# CONFIG_FRONTSWAP is not set | |
| +# CONFIG_CMA is not set | |
| +# CONFIG_ZPOOL is not set | |
| +# CONFIG_ZBUD is not set | |
| +CONFIG_ZSMALLOC=y | |
| +CONFIG_PGTABLE_MAPPING=y | |
| +# CONFIG_ZSMALLOC_STAT is not set | |
| +# CONFIG_IDLE_PAGE_TRACKING is not set | |
| +CONFIG_FORCE_MAX_ZONEORDER=11 | |
| +CONFIG_ALIGNMENT_TRAP=y | |
| +CONFIG_UACCESS_WITH_MEMCPY=y | |
| +CONFIG_SECCOMP=y | |
| +CONFIG_SWIOTLB=y | |
| +CONFIG_IOMMU_HELPER=y | |
| +# CONFIG_XEN is not set | |
| + | |
| +# | |
| +# Boot options | |
| +# | |
| +CONFIG_USE_OF=y | |
| +CONFIG_ATAGS=y | |
| +# CONFIG_DEPRECATED_PARAM_STRUCT is not set | |
| +CONFIG_ZBOOT_ROM_TEXT=0x0 | |
| +CONFIG_ZBOOT_ROM_BSS=0x0 | |
| +# CONFIG_ARM_APPENDED_DTB is not set | |
| +CONFIG_CMDLINE="" | |
| +# CONFIG_CRASH_DUMP is not set | |
| +CONFIG_AUTO_ZRELADDR=y | |
| + | |
| +# | |
| +# CPU Power Management | |
| +# | |
| + | |
| +# | |
| +# CPU Frequency scaling | |
| +# | |
| +# CONFIG_CPU_FREQ is not set | |
| + | |
| +# | |
| +# CPU Idle | |
| +# | |
| +CONFIG_CPU_IDLE=y | |
| +CONFIG_CPU_IDLE_GOV_LADDER=y | |
| +CONFIG_CPU_IDLE_GOV_MENU=y | |
| + | |
| +# | |
| +# ARM CPU Idle Drivers | |
| +# | |
| +# CONFIG_ARM_CPUIDLE is not set | |
| +# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set | |
| + | |
| +# | |
| +# Floating point emulation | |
| +# | |
| + | |
| +# | |
| +# At least one emulation must be selected | |
| +# | |
| +CONFIG_VFP=y | |
| +CONFIG_VFPv3=y | |
| +CONFIG_NEON=y | |
| +# CONFIG_KERNEL_MODE_NEON is not set | |
| + | |
| +# | |
| +# Userspace binary formats | |
| +# | |
| +CONFIG_BINFMT_ELF=y | |
| +CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y | |
| +CONFIG_BINFMT_SCRIPT=y | |
| +# CONFIG_HAVE_AOUT is not set | |
| +# CONFIG_BINFMT_MISC is not set | |
| +CONFIG_COREDUMP=y | |
| + | |
| +# | |
| +# Power management options | |
| +# | |
| +# CONFIG_SUSPEND is not set | |
| +# CONFIG_HIBERNATION is not set | |
| +CONFIG_PM=y | |
| +# CONFIG_PM_DEBUG is not set | |
| +# CONFIG_APM_EMULATION is not set | |
| +CONFIG_PM_CLK=y | |
| +# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set | |
| +CONFIG_CPU_PM=y | |
| +CONFIG_ARCH_SUSPEND_POSSIBLE=y | |
| +# CONFIG_ARM_CPU_SUSPEND is not set | |
| +CONFIG_ARCH_HIBERNATION_POSSIBLE=y | |
| +CONFIG_NET=y | |
| + | |
| +# | |
| +# Networking options | |
| +# | |
| +CONFIG_PACKET=y | |
| +# CONFIG_PACKET_DIAG is not set | |
| +CONFIG_UNIX=y | |
| +# CONFIG_UNIX_DIAG is not set | |
| +CONFIG_XFRM=y | |
| +CONFIG_XFRM_ALGO=m | |
| +CONFIG_XFRM_USER=m | |
| +# CONFIG_XFRM_SUB_POLICY is not set | |
| +# CONFIG_XFRM_MIGRATE is not set | |
| +# CONFIG_XFRM_STATISTICS is not set | |
| +# CONFIG_NET_KEY is not set | |
| +CONFIG_INET=y | |
| +CONFIG_IP_MULTICAST=y | |
| +CONFIG_IP_ADVANCED_ROUTER=y | |
| +# CONFIG_IP_FIB_TRIE_STATS is not set | |
| +CONFIG_IP_MULTIPLE_TABLES=y | |
| +# CONFIG_IP_ROUTE_MULTIPATH is not set | |
| +# CONFIG_IP_ROUTE_VERBOSE is not set | |
| +# CONFIG_IP_PNP is not set | |
| +CONFIG_NET_IPIP=m | |
| +# CONFIG_NET_IPGRE_DEMUX is not set | |
| +CONFIG_NET_IP_TUNNEL=m | |
| +# CONFIG_IP_MROUTE is not set | |
| +# CONFIG_SYN_COOKIES is not set | |
| +CONFIG_NET_UDP_TUNNEL=m | |
| +# CONFIG_NET_FOU is not set | |
| +# CONFIG_NET_FOU_IP_TUNNELS is not set | |
| +# CONFIG_INET_AH is not set | |
| +CONFIG_INET_ESP=m | |
| +# CONFIG_INET_IPCOMP is not set | |
| +# CONFIG_INET_XFRM_TUNNEL is not set | |
| +CONFIG_INET_TUNNEL=m | |
| +CONFIG_INET_XFRM_MODE_TRANSPORT=m | |
| +# CONFIG_INET_XFRM_MODE_TUNNEL is not set | |
| +# CONFIG_INET_XFRM_MODE_BEET is not set | |
| +CONFIG_INET_LRO=y | |
| +CONFIG_INET_DIAG=y | |
| +CONFIG_INET_TCP_DIAG=y | |
| +CONFIG_INET_UDP_DIAG=y | |
| +CONFIG_TCP_CONG_ADVANCED=y | |
| +# CONFIG_TCP_CONG_BIC is not set | |
| +CONFIG_TCP_CONG_CUBIC=y | |
| +# CONFIG_TCP_CONG_WESTWOOD is not set | |
| +# CONFIG_TCP_CONG_HTCP is not set | |
| +# CONFIG_TCP_CONG_HSTCP is not set | |
| +# CONFIG_TCP_CONG_HYBLA is not set | |
| +# CONFIG_TCP_CONG_VEGAS is not set | |
| +# CONFIG_TCP_CONG_SCALABLE is not set | |
| +# CONFIG_TCP_CONG_LP is not set | |
| +# CONFIG_TCP_CONG_VENO is not set | |
| +# CONFIG_TCP_CONG_YEAH is not set | |
| +# CONFIG_TCP_CONG_ILLINOIS is not set | |
| +# CONFIG_TCP_CONG_DCTCP is not set | |
| +# CONFIG_TCP_CONG_CDG is not set | |
| +CONFIG_DEFAULT_CUBIC=y | |
| +# CONFIG_DEFAULT_RENO is not set | |
| +CONFIG_DEFAULT_TCP_CONG="cubic" | |
| +# CONFIG_TCP_MD5SIG is not set | |
| +CONFIG_IPV6=y | |
| +CONFIG_IPV6_ROUTER_PREF=y | |
| +CONFIG_IPV6_ROUTE_INFO=y | |
| +CONFIG_IPV6_OPTIMISTIC_DAD=y | |
| +# CONFIG_INET6_AH is not set | |
| +# CONFIG_INET6_ESP is not set | |
| +# CONFIG_INET6_IPCOMP is not set | |
| +# CONFIG_IPV6_MIP6 is not set | |
| +# CONFIG_IPV6_ILA is not set | |
| +# CONFIG_INET6_XFRM_TUNNEL is not set | |
| +# CONFIG_INET6_TUNNEL is not set | |
| +CONFIG_INET6_XFRM_MODE_TRANSPORT=y | |
| +CONFIG_INET6_XFRM_MODE_TUNNEL=y | |
| +CONFIG_INET6_XFRM_MODE_BEET=y | |
| +# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set | |
| +# CONFIG_IPV6_VTI is not set | |
| +# CONFIG_IPV6_SIT is not set | |
| +# CONFIG_IPV6_TUNNEL is not set | |
| +# CONFIG_IPV6_GRE is not set | |
| +# CONFIG_IPV6_MULTIPLE_TABLES is not set | |
| +# CONFIG_IPV6_MROUTE is not set | |
| +# CONFIG_NETLABEL is not set | |
| +# CONFIG_NETWORK_SECMARK is not set | |
| +# CONFIG_NET_PTP_CLASSIFY is not set | |
| +# CONFIG_NETWORK_PHY_TIMESTAMPING is not set | |
| +CONFIG_NETFILTER=y | |
| +# CONFIG_NETFILTER_DEBUG is not set | |
| +CONFIG_NETFILTER_ADVANCED=y | |
| +CONFIG_BRIDGE_NETFILTER=m | |
| + | |
| +# | |
| +# Core Netfilter Configuration | |
| +# | |
| +# CONFIG_NETFILTER_INGRESS is not set | |
| +CONFIG_NETFILTER_NETLINK=m | |
| +# CONFIG_NETFILTER_NETLINK_ACCT is not set | |
| +CONFIG_NETFILTER_NETLINK_QUEUE=m | |
| +# CONFIG_NETFILTER_NETLINK_LOG is not set | |
| +CONFIG_NF_CONNTRACK=m | |
| +CONFIG_NF_CONNTRACK_MARK=y | |
| +# CONFIG_NF_CONNTRACK_PROCFS is not set | |
| +# CONFIG_NF_CONNTRACK_EVENTS is not set | |
| +# CONFIG_NF_CONNTRACK_TIMEOUT is not set | |
| +# CONFIG_NF_CONNTRACK_TIMESTAMP is not set | |
| +# CONFIG_NF_CT_PROTO_DCCP is not set | |
| +# CONFIG_NF_CT_PROTO_SCTP is not set | |
| +# CONFIG_NF_CT_PROTO_UDPLITE is not set | |
| +# CONFIG_NF_CONNTRACK_AMANDA is not set | |
| +# CONFIG_NF_CONNTRACK_FTP is not set | |
| +# CONFIG_NF_CONNTRACK_H323 is not set | |
| +# CONFIG_NF_CONNTRACK_IRC is not set | |
| +# CONFIG_NF_CONNTRACK_NETBIOS_NS is not set | |
| +# CONFIG_NF_CONNTRACK_SNMP is not set | |
| +# CONFIG_NF_CONNTRACK_PPTP is not set | |
| +# CONFIG_NF_CONNTRACK_SANE is not set | |
| +# CONFIG_NF_CONNTRACK_SIP is not set | |
| +# CONFIG_NF_CONNTRACK_TFTP is not set | |
| +# CONFIG_NF_CT_NETLINK is not set | |
| +# CONFIG_NF_CT_NETLINK_TIMEOUT is not set | |
| +CONFIG_NF_NAT=m | |
| +CONFIG_NF_NAT_NEEDED=y | |
| +# CONFIG_NF_NAT_AMANDA is not set | |
| +# CONFIG_NF_NAT_FTP is not set | |
| +# CONFIG_NF_NAT_IRC is not set | |
| +# CONFIG_NF_NAT_SIP is not set | |
| +# CONFIG_NF_NAT_TFTP is not set | |
| +# CONFIG_NF_NAT_REDIRECT is not set | |
| +# CONFIG_NF_TABLES is not set | |
| +CONFIG_NETFILTER_XTABLES=y | |
| + | |
| +# | |
| +# Xtables combined modules | |
| +# | |
| +# CONFIG_NETFILTER_XT_MARK is not set | |
| +# CONFIG_NETFILTER_XT_CONNMARK is not set | |
| + | |
| +# | |
| +# Xtables targets | |
| +# | |
| +# CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set | |
| +# CONFIG_NETFILTER_XT_TARGET_CONNMARK is not set | |
| +# CONFIG_NETFILTER_XT_TARGET_HMARK is not set | |
| +# CONFIG_NETFILTER_XT_TARGET_IDLETIMER is not set | |
| +# CONFIG_NETFILTER_XT_TARGET_LED is not set | |
| +# CONFIG_NETFILTER_XT_TARGET_LOG is not set | |
| +# CONFIG_NETFILTER_XT_TARGET_MARK is not set | |
| +CONFIG_NETFILTER_XT_NAT=m | |
| +# CONFIG_NETFILTER_XT_TARGET_NETMAP is not set | |
| +# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set | |
| +# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set | |
| +# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set | |
| +# CONFIG_NETFILTER_XT_TARGET_REDIRECT is not set | |
| +# CONFIG_NETFILTER_XT_TARGET_TEE is not set | |
| +# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set | |
| + | |
| +# | |
| +# Xtables matches | |
| +# | |
| +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m | |
| +# CONFIG_NETFILTER_XT_MATCH_BPF is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_CGROUP is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_CLUSTER is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_CONNBYTES is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_CONNLABEL is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_CONNLIMIT is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_CONNMARK is not set | |
| +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m | |
| +# CONFIG_NETFILTER_XT_MATCH_CPU is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_DCCP is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_DEVGROUP is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_DSCP is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_ECN is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_ESP is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_HELPER is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_HL is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_IPCOMP is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set | |
| +CONFIG_NETFILTER_XT_MATCH_IPVS=m | |
| +# CONFIG_NETFILTER_XT_MATCH_L2TP is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_LIMIT is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_MAC is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_MARK is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_NFACCT is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_OSF is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_OWNER is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_POLICY is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_PHYSDEV is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_REALM is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_RECENT is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_SCTP is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_SOCKET is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_STATE is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_STRING is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_TIME is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_U32 is not set | |
| +# CONFIG_IP_SET is not set | |
| +CONFIG_IP_VS=m | |
| +# CONFIG_IP_VS_IPV6 is not set | |
| +# CONFIG_IP_VS_DEBUG is not set | |
| +CONFIG_IP_VS_TAB_BITS=12 | |
| + | |
| +# | |
| +# IPVS transport protocol load balancing support | |
| +# | |
| +# CONFIG_IP_VS_PROTO_TCP is not set | |
| +# CONFIG_IP_VS_PROTO_UDP is not set | |
| +# CONFIG_IP_VS_PROTO_AH_ESP is not set | |
| +# CONFIG_IP_VS_PROTO_ESP is not set | |
| +# CONFIG_IP_VS_PROTO_AH is not set | |
| +# CONFIG_IP_VS_PROTO_SCTP is not set | |
| + | |
| +# | |
| +# IPVS scheduler | |
| +# | |
| +# CONFIG_IP_VS_RR is not set | |
| +# CONFIG_IP_VS_WRR is not set | |
| +# CONFIG_IP_VS_LC is not set | |
| +# CONFIG_IP_VS_WLC is not set | |
| +# CONFIG_IP_VS_FO is not set | |
| +# CONFIG_IP_VS_OVF is not set | |
| +# CONFIG_IP_VS_LBLC is not set | |
| +# CONFIG_IP_VS_LBLCR is not set | |
| +# CONFIG_IP_VS_DH is not set | |
| +# CONFIG_IP_VS_SH is not set | |
| +# CONFIG_IP_VS_SED is not set | |
| +# CONFIG_IP_VS_NQ is not set | |
| + | |
| +# | |
| +# IPVS SH scheduler | |
| +# | |
| +CONFIG_IP_VS_SH_TAB_BITS=8 | |
| + | |
| +# | |
| +# IPVS application helper | |
| +# | |
| +# CONFIG_IP_VS_NFCT is not set | |
| + | |
| +# | |
| +# IP: Netfilter Configuration | |
| +# | |
| +CONFIG_NF_DEFRAG_IPV4=m | |
| +CONFIG_NF_CONNTRACK_IPV4=m | |
| +# CONFIG_NF_DUP_IPV4 is not set | |
| +# CONFIG_NF_LOG_ARP is not set | |
| +# CONFIG_NF_LOG_IPV4 is not set | |
| +CONFIG_NF_REJECT_IPV4=y | |
| +CONFIG_NF_NAT_IPV4=m | |
| +CONFIG_NF_NAT_MASQUERADE_IPV4=m | |
| +# CONFIG_NF_NAT_PPTP is not set | |
| +# CONFIG_NF_NAT_H323 is not set | |
| +CONFIG_IP_NF_IPTABLES=y | |
| +# CONFIG_IP_NF_MATCH_AH is not set | |
| +# CONFIG_IP_NF_MATCH_ECN is not set | |
| +# CONFIG_IP_NF_MATCH_TTL is not set | |
| +CONFIG_IP_NF_FILTER=y | |
| +CONFIG_IP_NF_TARGET_REJECT=y | |
| +# CONFIG_IP_NF_TARGET_SYNPROXY is not set | |
| +CONFIG_IP_NF_NAT=m | |
| +CONFIG_IP_NF_TARGET_MASQUERADE=m | |
| +# CONFIG_IP_NF_TARGET_NETMAP is not set | |
| +# CONFIG_IP_NF_TARGET_REDIRECT is not set | |
| +# CONFIG_IP_NF_MANGLE is not set | |
| +# CONFIG_IP_NF_RAW is not set | |
| +# CONFIG_IP_NF_SECURITY is not set | |
| +# CONFIG_IP_NF_ARPTABLES is not set | |
| + | |
| +# | |
| +# IPv6: Netfilter Configuration | |
| +# | |
| +CONFIG_NF_DEFRAG_IPV6=m | |
| +CONFIG_NF_CONNTRACK_IPV6=m | |
| +# CONFIG_NF_DUP_IPV6 is not set | |
| +CONFIG_NF_REJECT_IPV6=y | |
| +# CONFIG_NF_LOG_IPV6 is not set | |
| +CONFIG_NF_NAT_IPV6=m | |
| +CONFIG_NF_NAT_MASQUERADE_IPV6=m | |
| +CONFIG_IP6_NF_IPTABLES=m | |
| +# CONFIG_IP6_NF_MATCH_AH is not set | |
| +# CONFIG_IP6_NF_MATCH_EUI64 is not set | |
| +# CONFIG_IP6_NF_MATCH_FRAG is not set | |
| +# CONFIG_IP6_NF_MATCH_OPTS is not set | |
| +# CONFIG_IP6_NF_MATCH_HL is not set | |
| +# CONFIG_IP6_NF_MATCH_IPV6HEADER is not set | |
| +# CONFIG_IP6_NF_MATCH_MH is not set | |
| +# CONFIG_IP6_NF_MATCH_RT is not set | |
| +CONFIG_IP6_NF_FILTER=m | |
| +CONFIG_IP6_NF_TARGET_REJECT=m | |
| +# CONFIG_IP6_NF_TARGET_SYNPROXY is not set | |
| +# CONFIG_IP6_NF_MANGLE is not set | |
| +# CONFIG_IP6_NF_RAW is not set | |
| +# CONFIG_IP6_NF_SECURITY is not set | |
| +CONFIG_IP6_NF_NAT=m | |
| +CONFIG_IP6_NF_TARGET_MASQUERADE=m | |
| +# CONFIG_IP6_NF_TARGET_NPT is not set | |
| +# CONFIG_BRIDGE_NF_EBTABLES is not set | |
| +# CONFIG_IP_DCCP is not set | |
| +# CONFIG_IP_SCTP is not set | |
| +# CONFIG_RDS is not set | |
| +# CONFIG_TIPC is not set | |
| +# CONFIG_ATM is not set | |
| +# CONFIG_L2TP is not set | |
| +CONFIG_STP=m | |
| +CONFIG_BRIDGE=m | |
| +CONFIG_BRIDGE_IGMP_SNOOPING=y | |
| +CONFIG_BRIDGE_VLAN_FILTERING=y | |
| +CONFIG_HAVE_NET_DSA=y | |
| +# CONFIG_NET_DSA is not set | |
| +CONFIG_VLAN_8021Q=y | |
| +# CONFIG_VLAN_8021Q_GVRP is not set | |
| +# CONFIG_VLAN_8021Q_MVRP is not set | |
| +# CONFIG_DECNET is not set | |
| +CONFIG_LLC=m | |
| +# CONFIG_LLC2 is not set | |
| +# CONFIG_IPX is not set | |
| +# CONFIG_ATALK is not set | |
| +# CONFIG_X25 is not set | |
| +# CONFIG_LAPB is not set | |
| +# CONFIG_PHONET is not set | |
| +# CONFIG_6LOWPAN is not set | |
| +# CONFIG_IEEE802154 is not set | |
| +CONFIG_NET_SCHED=y | |
| + | |
| +# | |
| +# Queueing/Scheduling | |
| +# | |
| +# CONFIG_NET_SCH_CBQ is not set | |
| +# CONFIG_NET_SCH_HTB is not set | |
| +# CONFIG_NET_SCH_HFSC is not set | |
| +# CONFIG_NET_SCH_PRIO is not set | |
| +# CONFIG_NET_SCH_MULTIQ is not set | |
| +# CONFIG_NET_SCH_RED is not set | |
| +# CONFIG_NET_SCH_SFB is not set | |
| +# CONFIG_NET_SCH_SFQ is not set | |
| +# CONFIG_NET_SCH_TEQL is not set | |
| +# CONFIG_NET_SCH_TBF is not set | |
| +# CONFIG_NET_SCH_GRED is not set | |
| +# CONFIG_NET_SCH_DSMARK is not set | |
| +CONFIG_NET_SCH_NETEM=m | |
| +# CONFIG_NET_SCH_DRR is not set | |
| +# CONFIG_NET_SCH_MQPRIO is not set | |
| +# CONFIG_NET_SCH_CHOKE is not set | |
| +# CONFIG_NET_SCH_QFQ is not set | |
| +# CONFIG_NET_SCH_CODEL is not set | |
| +# CONFIG_NET_SCH_FQ_CODEL is not set | |
| +# CONFIG_NET_SCH_FQ is not set | |
| +# CONFIG_NET_SCH_HHF is not set | |
| +# CONFIG_NET_SCH_PIE is not set | |
| +# CONFIG_NET_SCH_PLUG is not set | |
| + | |
| +# | |
| +# Classification | |
| +# | |
| +# CONFIG_NET_CLS_BASIC is not set | |
| +# CONFIG_NET_CLS_TCINDEX is not set | |
| +# CONFIG_NET_CLS_ROUTE4 is not set | |
| +# CONFIG_NET_CLS_FW is not set | |
| +# CONFIG_NET_CLS_U32 is not set | |
| +# CONFIG_NET_CLS_RSVP is not set | |
| +# CONFIG_NET_CLS_RSVP6 is not set | |
| +# CONFIG_NET_CLS_FLOW is not set | |
| +# CONFIG_NET_CLS_CGROUP is not set | |
| +# CONFIG_NET_CLS_BPF is not set | |
| +# CONFIG_NET_CLS_FLOWER is not set | |
| +# CONFIG_NET_EMATCH is not set | |
| +# CONFIG_NET_CLS_ACT is not set | |
| +CONFIG_NET_SCH_FIFO=y | |
| +# CONFIG_DCB is not set | |
| +CONFIG_DNS_RESOLVER=y | |
| +# CONFIG_BATMAN_ADV is not set | |
| +# CONFIG_OPENVSWITCH is not set | |
| +# CONFIG_VSOCKETS is not set | |
| +# CONFIG_NETLINK_DIAG is not set | |
| +# CONFIG_MPLS is not set | |
| +# CONFIG_HSR is not set | |
| +# CONFIG_NET_SWITCHDEV is not set | |
| +# CONFIG_NET_L3_MASTER_DEV is not set | |
| +CONFIG_RPS=y | |
| +CONFIG_RFS_ACCEL=y | |
| +CONFIG_XPS=y | |
| +# CONFIG_CGROUP_NET_PRIO is not set | |
| +# CONFIG_CGROUP_NET_CLASSID is not set | |
| +CONFIG_NET_RX_BUSY_POLL=y | |
| +CONFIG_BQL=y | |
| +# CONFIG_BPF_JIT is not set | |
| +CONFIG_NET_FLOW_LIMIT=y | |
| + | |
| +# | |
| +# Network testing | |
| +# | |
| +# CONFIG_NET_PKTGEN is not set | |
| +# CONFIG_HAMRADIO is not set | |
| +# CONFIG_CAN is not set | |
| +# CONFIG_IRDA is not set | |
| +CONFIG_BT=y | |
| +CONFIG_BT_BREDR=y | |
| +CONFIG_BT_RFCOMM=m | |
| +# CONFIG_BT_RFCOMM_TTY is not set | |
| +CONFIG_BT_BNEP=m | |
| +# CONFIG_BT_BNEP_MC_FILTER is not set | |
| +# CONFIG_BT_BNEP_PROTO_FILTER is not set | |
| +# CONFIG_BT_HIDP is not set | |
| +CONFIG_BT_HS=y | |
| +CONFIG_BT_LE=y | |
| +# CONFIG_BT_SELFTEST is not set | |
| + | |
| +# | |
| +# Bluetooth device drivers | |
| +# | |
| +CONFIG_BT_INTEL=y | |
| +CONFIG_BT_HCIBTUSB=y | |
| +# CONFIG_BT_HCIBTUSB_BCM is not set | |
| +# CONFIG_BT_HCIBTUSB_RTL is not set | |
| +# CONFIG_BT_HCIUART is not set | |
| +# CONFIG_BT_HCIBCM203X is not set | |
| +# CONFIG_BT_HCIBFUSB is not set | |
| +# CONFIG_BT_HCIVHCI is not set | |
| +# CONFIG_BT_MRVL is not set | |
| +# CONFIG_BT_ATH3K is not set | |
| +# CONFIG_AF_RXRPC is not set | |
| +CONFIG_FIB_RULES=y | |
| +# CONFIG_WIRELESS is not set | |
| +# CONFIG_WIMAX is not set | |
| +CONFIG_RFKILL=y | |
| +CONFIG_RFKILL_LEDS=y | |
| +# CONFIG_RFKILL_INPUT is not set | |
| +# CONFIG_RFKILL_GPIO is not set | |
| +# CONFIG_NET_9P is not set | |
| +# CONFIG_CAIF is not set | |
| +# CONFIG_CEPH_LIB is not set | |
| +# CONFIG_NFC is not set | |
| +# CONFIG_LWTUNNEL is not set | |
| +CONFIG_HAVE_BPF_JIT=y | |
| + | |
| +# | |
| +# Device Drivers | |
| +# | |
| +CONFIG_ARM_AMBA=y | |
| +# CONFIG_TEGRA_AHB is not set | |
| + | |
| +# | |
| +# Generic Driver Options | |
| +# | |
| +CONFIG_UEVENT_HELPER=y | |
| +CONFIG_UEVENT_HELPER_PATH="/sbin/mdev" | |
| +CONFIG_DEVTMPFS=y | |
| +# CONFIG_DEVTMPFS_MOUNT is not set | |
| +CONFIG_STANDALONE=y | |
| +CONFIG_PREVENT_FIRMWARE_BUILD=y | |
| +CONFIG_FW_LOADER=y | |
| +# CONFIG_FIRMWARE_IN_KERNEL is not set | |
| +CONFIG_EXTRA_FIRMWARE="" | |
| +# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set | |
| +# CONFIG_ALLOW_DEV_COREDUMP is not set | |
| +# CONFIG_DEBUG_DRIVER is not set | |
| +# CONFIG_DEBUG_DEVRES is not set | |
| +# CONFIG_SYS_HYPERVISOR is not set | |
| +# CONFIG_GENERIC_CPU_DEVICES is not set | |
| +CONFIG_REGMAP=y | |
| +CONFIG_REGMAP_MMIO=y | |
| +# CONFIG_DMA_SHARED_BUFFER is not set | |
| + | |
| +# | |
| +# Bus devices | |
| +# | |
| +# CONFIG_BRCMSTB_GISB_ARB is not set | |
| +CONFIG_VEXPRESS_CONFIG=y | |
| +# CONFIG_CONNECTOR is not set | |
| +CONFIG_MTD=y | |
| +# CONFIG_MTD_TESTS is not set | |
| +# CONFIG_MTD_REDBOOT_PARTS is not set | |
| +CONFIG_MTD_CMDLINE_PARTS=y | |
| +# CONFIG_MTD_AFS_PARTS is not set | |
| +CONFIG_MTD_OF_PARTS=y | |
| +# CONFIG_MTD_AR7_PARTS is not set | |
| + | |
| +# | |
| +# User Modules And Translation Layers | |
| +# | |
| +CONFIG_MTD_BLKDEVS=y | |
| +CONFIG_MTD_BLOCK=y | |
| +# CONFIG_FTL is not set | |
| +# CONFIG_NFTL is not set | |
| +# CONFIG_INFTL is not set | |
| +# CONFIG_RFD_FTL is not set | |
| +# CONFIG_SSFDC is not set | |
| +# CONFIG_SM_FTL is not set | |
| +# CONFIG_MTD_OOPS is not set | |
| +# CONFIG_MTD_SWAP is not set | |
| +# CONFIG_MTD_PARTITIONED_MASTER is not set | |
| + | |
| +# | |
| +# RAM/ROM/Flash chip drivers | |
| +# | |
| +CONFIG_MTD_CFI=y | |
| +CONFIG_MTD_JEDECPROBE=y | |
| +CONFIG_MTD_GEN_PROBE=y | |
| +CONFIG_MTD_CFI_ADV_OPTIONS=y | |
| +CONFIG_MTD_CFI_NOSWAP=y | |
| +# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set | |
| +# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set | |
| +CONFIG_MTD_CFI_GEOMETRY=y | |
| +CONFIG_MTD_MAP_BANK_WIDTH_1=y | |
| +CONFIG_MTD_MAP_BANK_WIDTH_2=y | |
| +# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set | |
| +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set | |
| +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set | |
| +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set | |
| +CONFIG_MTD_CFI_I1=y | |
| +CONFIG_MTD_CFI_I2=y | |
| +# CONFIG_MTD_CFI_I4 is not set | |
| +# CONFIG_MTD_CFI_I8 is not set | |
| +# CONFIG_MTD_OTP is not set | |
| +CONFIG_MTD_CFI_INTELEXT=y | |
| +# CONFIG_MTD_CFI_AMDSTD is not set | |
| +CONFIG_MTD_CFI_STAA=y | |
| +CONFIG_MTD_CFI_UTIL=y | |
| +# CONFIG_MTD_RAM is not set | |
| +# CONFIG_MTD_ROM is not set | |
| +# CONFIG_MTD_ABSENT is not set | |
| + | |
| +# | |
| +# Mapping drivers for chip access | |
| +# | |
| +# CONFIG_MTD_COMPLEX_MAPPINGS is not set | |
| +CONFIG_MTD_PHYSMAP=y | |
| +# CONFIG_MTD_PHYSMAP_COMPAT is not set | |
| +CONFIG_MTD_PHYSMAP_OF=y | |
| +# CONFIG_MTD_IMPA7 is not set | |
| +# CONFIG_MTD_INTEL_VR_NOR is not set | |
| +# CONFIG_MTD_PLATRAM is not set | |
| + | |
| +# | |
| +# Self-contained MTD device drivers | |
| +# | |
| +# CONFIG_MTD_PMC551 is not set | |
| +# CONFIG_MTD_SLRAM is not set | |
| +# CONFIG_MTD_PHRAM is not set | |
| +# CONFIG_MTD_MTDRAM is not set | |
| +# CONFIG_MTD_BLOCK2MTD is not set | |
| + | |
| +# | |
| +# Disk-On-Chip Device Drivers | |
| +# | |
| +# CONFIG_MTD_DOCG3 is not set | |
| +CONFIG_MTD_NAND_ECC=y | |
| +# CONFIG_MTD_NAND_ECC_SMC is not set | |
| +CONFIG_MTD_NAND=y | |
| +# CONFIG_MTD_NAND_ECC_BCH is not set | |
| +# CONFIG_MTD_SM_COMMON is not set | |
| +# CONFIG_MTD_NAND_DENALI_PCI is not set | |
| +# CONFIG_MTD_NAND_DENALI_DT is not set | |
| +# CONFIG_MTD_NAND_GPIO is not set | |
| +# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set | |
| +CONFIG_MTD_NAND_IDS=y | |
| +# CONFIG_MTD_NAND_RICOH is not set | |
| +# CONFIG_MTD_NAND_DISKONCHIP is not set | |
| +# CONFIG_MTD_NAND_DOCG4 is not set | |
| +# CONFIG_MTD_NAND_CAFE is not set | |
| +# CONFIG_MTD_NAND_NANDSIM is not set | |
| +# CONFIG_MTD_NAND_BRCMNAND is not set | |
| +# CONFIG_MTD_NAND_PLATFORM is not set | |
| +# CONFIG_MTD_NAND_HISI504 is not set | |
| +CONFIG_MTD_NAND_AL=y | |
| +# CONFIG_MTD_ONENAND is not set | |
| + | |
| +# | |
| +# LPDDR & LPDDR2 PCM memory drivers | |
| +# | |
| +# CONFIG_MTD_LPDDR is not set | |
| +# CONFIG_MTD_LPDDR2_NVM is not set | |
| +# CONFIG_MTD_SPI_NOR is not set | |
| +CONFIG_MTD_UBI=y | |
| +CONFIG_MTD_UBI_WL_THRESHOLD=4096 | |
| +CONFIG_MTD_UBI_BEB_LIMIT=20 | |
| +# CONFIG_MTD_UBI_FASTMAP is not set | |
| +# CONFIG_MTD_UBI_GLUEBI is not set | |
| +# CONFIG_MTD_UBI_BLOCK is not set | |
| +CONFIG_DTC=y | |
| +CONFIG_OF=y | |
| +# CONFIG_OF_UNITTEST is not set | |
| +CONFIG_OF_FLATTREE=y | |
| +CONFIG_OF_EARLY_FLATTREE=y | |
| +CONFIG_OF_ADDRESS=y | |
| +CONFIG_OF_ADDRESS_PCI=y | |
| +CONFIG_OF_IRQ=y | |
| +CONFIG_OF_NET=y | |
| +CONFIG_OF_MDIO=y | |
| +CONFIG_OF_PCI=y | |
| +CONFIG_OF_PCI_IRQ=y | |
| +CONFIG_OF_MTD=y | |
| +CONFIG_OF_RESERVED_MEM=y | |
| +# CONFIG_OF_OVERLAY is not set | |
| +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y | |
| +# CONFIG_PARPORT is not set | |
| +CONFIG_BLK_DEV=y | |
| +# CONFIG_BLK_DEV_NULL_BLK is not set | |
| +# CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set | |
| +CONFIG_ZRAM=m | |
| +# CONFIG_ZRAM_LZ4_COMPRESS is not set | |
| +# CONFIG_BLK_CPQ_CISS_DA is not set | |
| +# CONFIG_BLK_DEV_DAC960 is not set | |
| +# CONFIG_BLK_DEV_UMEM is not set | |
| +# CONFIG_BLK_DEV_COW_COMMON is not set | |
| +CONFIG_BLK_DEV_LOOP=y | |
| +CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 | |
| +# CONFIG_BLK_DEV_CRYPTOLOOP is not set | |
| +# CONFIG_BLK_DEV_DRBD is not set | |
| +# CONFIG_BLK_DEV_NBD is not set | |
| +# CONFIG_BLK_DEV_SX8 is not set | |
| +# CONFIG_BLK_DEV_RAM is not set | |
| +# CONFIG_CDROM_PKTCDVD is not set | |
| +# CONFIG_ATA_OVER_ETH is not set | |
| +# CONFIG_MG_DISK is not set | |
| +# CONFIG_BLK_DEV_RBD is not set | |
| +# CONFIG_BLK_DEV_RSXX is not set | |
| +# CONFIG_BLK_DEV_NVME is not set | |
| + | |
| +# | |
| +# Misc devices | |
| +# | |
| +# CONFIG_SENSORS_LIS3LV02D is not set | |
| +# CONFIG_AD525X_DPOT is not set | |
| +# CONFIG_DUMMY_IRQ is not set | |
| +# CONFIG_PHANTOM is not set | |
| +# CONFIG_SGI_IOC4 is not set | |
| +# CONFIG_TIFM_CORE is not set | |
| +# CONFIG_ICS932S401 is not set | |
| +# CONFIG_ENCLOSURE_SERVICES is not set | |
| +# CONFIG_HP_ILO is not set | |
| +# CONFIG_APDS9802ALS is not set | |
| +# CONFIG_ISL29003 is not set | |
| +# CONFIG_ISL29020 is not set | |
| +# CONFIG_SENSORS_TSL2550 is not set | |
| +# CONFIG_SENSORS_BH1780 is not set | |
| +# CONFIG_SENSORS_BH1770 is not set | |
| +# CONFIG_SENSORS_APDS990X is not set | |
| +# CONFIG_HMC6352 is not set | |
| +# CONFIG_DS1682 is not set | |
| +# CONFIG_BMP085_I2C is not set | |
| +# CONFIG_USB_SWITCH_FSA9480 is not set | |
| +# CONFIG_SRAM is not set | |
| +CONFIG_VEXPRESS_SYSCFG=y | |
| +# CONFIG_C2PORT is not set | |
| + | |
| +# | |
| +# EEPROM support | |
| +# | |
| +# CONFIG_EEPROM_AT24 is not set | |
| +# CONFIG_EEPROM_LEGACY is not set | |
| +# CONFIG_EEPROM_MAX6875 is not set | |
| +# CONFIG_EEPROM_93CX6 is not set | |
| +# CONFIG_CB710_CORE is not set | |
| + | |
| +# | |
| +# Texas Instruments shared transport line discipline | |
| +# | |
| +# CONFIG_TI_ST is not set | |
| +# CONFIG_SENSORS_LIS3_I2C is not set | |
| + | |
| +# | |
| +# Altera FPGA firmware download module | |
| +# | |
| +# CONFIG_ALTERA_STAPL is not set | |
| + | |
| +# | |
| +# Intel MIC Bus Driver | |
| +# | |
| + | |
| +# | |
| +# SCIF Bus Driver | |
| +# | |
| + | |
| +# | |
| +# Intel MIC Host Driver | |
| +# | |
| + | |
| +# | |
| +# Intel MIC Card Driver | |
| +# | |
| + | |
| +# | |
| +# SCIF Driver | |
| +# | |
| + | |
| +# | |
| +# Intel MIC Coprocessor State Management (COSM) Drivers | |
| +# | |
| +# CONFIG_ECHO is not set | |
| +# CONFIG_CXL_BASE is not set | |
| +# CONFIG_CXL_KERNEL_API is not set | |
| +# CONFIG_CXL_EEH is not set | |
| +CONFIG_HAVE_IDE=y | |
| +# CONFIG_IDE is not set | |
| + | |
| +# | |
| +# SCSI device support | |
| +# | |
| +CONFIG_SCSI_MOD=y | |
| +# CONFIG_RAID_ATTRS is not set | |
| +CONFIG_SCSI=y | |
| +CONFIG_SCSI_DMA=y | |
| +# CONFIG_SCSI_NETLINK is not set | |
| +# CONFIG_SCSI_MQ_DEFAULT is not set | |
| +# CONFIG_SCSI_PROC_FS is not set | |
| + | |
| +# | |
| +# SCSI support type (disk, tape, CD-ROM) | |
| +# | |
| +CONFIG_BLK_DEV_SD=y | |
| +# CONFIG_CHR_DEV_ST is not set | |
| +# CONFIG_CHR_DEV_OSST is not set | |
| +# CONFIG_BLK_DEV_SR is not set | |
| +# CONFIG_CHR_DEV_SG is not set | |
| +# CONFIG_CHR_DEV_SCH is not set | |
| +# CONFIG_SCSI_CONSTANTS is not set | |
| +# CONFIG_SCSI_LOGGING is not set | |
| +# CONFIG_SCSI_SCAN_ASYNC is not set | |
| +CONFIG_MV_STAGGERED_SPINUP=y | |
| + | |
| +# | |
| +# SCSI Transports | |
| +# | |
| +# CONFIG_SCSI_SPI_ATTRS is not set | |
| +# CONFIG_SCSI_FC_ATTRS is not set | |
| +CONFIG_SCSI_ISCSI_ATTRS=m | |
| +# CONFIG_SCSI_SAS_ATTRS is not set | |
| +# CONFIG_SCSI_SAS_LIBSAS is not set | |
| +# CONFIG_SCSI_SRP_ATTRS is not set | |
| +CONFIG_SCSI_LOWLEVEL=y | |
| +CONFIG_ISCSI_TCP=m | |
| +# CONFIG_ISCSI_BOOT_SYSFS is not set | |
| +# CONFIG_SCSI_CXGB3_ISCSI is not set | |
| +# CONFIG_SCSI_CXGB4_ISCSI is not set | |
| +# CONFIG_SCSI_BNX2_ISCSI is not set | |
| +# CONFIG_BE2ISCSI is not set | |
| +# CONFIG_BLK_DEV_3W_XXXX_RAID is not set | |
| +# CONFIG_SCSI_HPSA is not set | |
| +# CONFIG_SCSI_3W_9XXX is not set | |
| +# CONFIG_SCSI_3W_SAS is not set | |
| +# CONFIG_SCSI_ACARD is not set | |
| +# CONFIG_SCSI_AACRAID is not set | |
| +# CONFIG_SCSI_AIC7XXX is not set | |
| +# CONFIG_SCSI_AIC79XX is not set | |
| +# CONFIG_SCSI_AIC94XX is not set | |
| +# CONFIG_SCSI_MVSAS is not set | |
| +# CONFIG_SCSI_MVUMI is not set | |
| +# CONFIG_SCSI_ADVANSYS is not set | |
| +# CONFIG_SCSI_ARCMSR is not set | |
| +# CONFIG_SCSI_ESAS2R is not set | |
| +# CONFIG_MEGARAID_NEWGEN is not set | |
| +# CONFIG_MEGARAID_LEGACY is not set | |
| +# CONFIG_MEGARAID_SAS is not set | |
| +# CONFIG_SCSI_MPT3SAS is not set | |
| +# CONFIG_SCSI_MPT2SAS is not set | |
| +# CONFIG_SCSI_UFSHCD is not set | |
| +# CONFIG_SCSI_HPTIOP is not set | |
| +# CONFIG_SCSI_SNIC is not set | |
| +# CONFIG_SCSI_DMX3191D is not set | |
| +# CONFIG_SCSI_FUTURE_DOMAIN is not set | |
| +# CONFIG_SCSI_IPS is not set | |
| +# CONFIG_SCSI_INITIO is not set | |
| +# CONFIG_SCSI_INIA100 is not set | |
| +# CONFIG_SCSI_STEX is not set | |
| +# CONFIG_SCSI_SYM53C8XX_2 is not set | |
| +# CONFIG_SCSI_IPR is not set | |
| +# CONFIG_SCSI_QLOGIC_1280 is not set | |
| +# CONFIG_SCSI_QLA_ISCSI is not set | |
| +# CONFIG_SCSI_DC395x is not set | |
| +# CONFIG_SCSI_AM53C974 is not set | |
| +# CONFIG_SCSI_NSP32 is not set | |
| +# CONFIG_SCSI_WD719X is not set | |
| +# CONFIG_SCSI_DEBUG is not set | |
| +# CONFIG_SCSI_PMCRAID is not set | |
| +# CONFIG_SCSI_PM8001 is not set | |
| +CONFIG_SCSI_DH=y | |
| +# CONFIG_SCSI_DH_RDAC is not set | |
| +# CONFIG_SCSI_DH_HP_SW is not set | |
| +# CONFIG_SCSI_DH_EMC is not set | |
| +# CONFIG_SCSI_DH_ALUA is not set | |
| +# CONFIG_SCSI_OSD_INITIATOR is not set | |
| +CONFIG_ATA=y | |
| +# CONFIG_ATA_NONSTANDARD is not set | |
| +CONFIG_ATA_VERBOSE_ERROR=y | |
| +CONFIG_SATA_PMP=y | |
| + | |
| +# | |
| +# Controllers with non-SFF native interface | |
| +# | |
| +CONFIG_SATA_AHCI=y | |
| +CONFIG_SATA_AHCI_PLATFORM=y | |
| +# CONFIG_AHCI_CEVA is not set | |
| +CONFIG_AHCI_ALPINE=y | |
| +# CONFIG_AHCI_QORIQ is not set | |
| +# CONFIG_SATA_INIC162X is not set | |
| +# CONFIG_SATA_ACARD_AHCI is not set | |
| +# CONFIG_SATA_SIL24 is not set | |
| +CONFIG_ATA_SFF=y | |
| + | |
| +# | |
| +# SFF controllers with custom DMA interface | |
| +# | |
| +# CONFIG_PDC_ADMA is not set | |
| +# CONFIG_SATA_QSTOR is not set | |
| +# CONFIG_SATA_SX4 is not set | |
| +CONFIG_ATA_BMDMA=y | |
| + | |
| +# | |
| +# SATA SFF controllers with BMDMA | |
| +# | |
| +# CONFIG_ATA_PIIX is not set | |
| +# CONFIG_SATA_MV is not set | |
| +# CONFIG_SATA_NV is not set | |
| +# CONFIG_SATA_PROMISE is not set | |
| +# CONFIG_SATA_SIL is not set | |
| +# CONFIG_SATA_SIS is not set | |
| +# CONFIG_SATA_SVW is not set | |
| +# CONFIG_SATA_ULI is not set | |
| +# CONFIG_SATA_VIA is not set | |
| +# CONFIG_SATA_VITESSE is not set | |
| + | |
| +# | |
| +# PATA SFF controllers with BMDMA | |
| +# | |
| +# CONFIG_PATA_ALI is not set | |
| +# CONFIG_PATA_AMD is not set | |
| +# CONFIG_PATA_ARTOP is not set | |
| +# CONFIG_PATA_ATIIXP is not set | |
| +# CONFIG_PATA_ATP867X is not set | |
| +# CONFIG_PATA_CMD64X is not set | |
| +# CONFIG_PATA_CYPRESS is not set | |
| +# CONFIG_PATA_EFAR is not set | |
| +# CONFIG_PATA_HPT366 is not set | |
| +# CONFIG_PATA_HPT37X is not set | |
| +# CONFIG_PATA_HPT3X2N is not set | |
| +# CONFIG_PATA_HPT3X3 is not set | |
| +# CONFIG_PATA_IT8213 is not set | |
| +# CONFIG_PATA_IT821X is not set | |
| +# CONFIG_PATA_JMICRON is not set | |
| +# CONFIG_PATA_MARVELL is not set | |
| +# CONFIG_PATA_NETCELL is not set | |
| +# CONFIG_PATA_NINJA32 is not set | |
| +# CONFIG_PATA_NS87415 is not set | |
| +# CONFIG_PATA_OLDPIIX is not set | |
| +# CONFIG_PATA_OPTIDMA is not set | |
| +# CONFIG_PATA_PDC2027X is not set | |
| +# CONFIG_PATA_PDC_OLD is not set | |
| +# CONFIG_PATA_RADISYS is not set | |
| +# CONFIG_PATA_RDC is not set | |
| +# CONFIG_PATA_SCH is not set | |
| +# CONFIG_PATA_SERVERWORKS is not set | |
| +# CONFIG_PATA_SIL680 is not set | |
| +# CONFIG_PATA_SIS is not set | |
| +# CONFIG_PATA_TOSHIBA is not set | |
| +# CONFIG_PATA_TRIFLEX is not set | |
| +# CONFIG_PATA_VIA is not set | |
| +# CONFIG_PATA_WINBOND is not set | |
| + | |
| +# | |
| +# PIO-only SFF controllers | |
| +# | |
| +# CONFIG_PATA_CMD640_PCI is not set | |
| +# CONFIG_PATA_MPIIX is not set | |
| +# CONFIG_PATA_NS87410 is not set | |
| +# CONFIG_PATA_OPTI is not set | |
| +# CONFIG_PATA_PLATFORM is not set | |
| +# CONFIG_PATA_RZ1000 is not set | |
| + | |
| +# | |
| +# Generic fallback / legacy drivers | |
| +# | |
| +# CONFIG_ATA_GENERIC is not set | |
| +# CONFIG_PATA_LEGACY is not set | |
| +CONFIG_MD=y | |
| +CONFIG_BLK_DEV_MD=y | |
| +# CONFIG_MD_AUTODETECT is not set | |
| +# CONFIG_MD_LINEAR is not set | |
| +CONFIG_MD_RAID0=y | |
| +CONFIG_MD_RAID1=y | |
| +CONFIG_MD_RAID10=y | |
| +CONFIG_MD_RAID456=y | |
| +# CONFIG_MD_MULTIPATH is not set | |
| +# CONFIG_MD_FAULTY is not set | |
| +# CONFIG_BCACHE is not set | |
| +CONFIG_BLK_DEV_DM_BUILTIN=y | |
| +CONFIG_BLK_DEV_DM=y | |
| +# CONFIG_DM_MQ_DEFAULT is not set | |
| +# CONFIG_DM_DEBUG is not set | |
| +CONFIG_DM_BUFIO=y | |
| +CONFIG_DM_BIO_PRISON=m | |
| +CONFIG_DM_PERSISTENT_DATA=m | |
| +# CONFIG_DM_DEBUG_BLOCK_STACK_TRACING is not set | |
| +CONFIG_DM_CRYPT=y | |
| +CONFIG_DM_SNAPSHOT=y | |
| +CONFIG_DM_THIN_PROVISIONING=m | |
| +# CONFIG_DM_CACHE is not set | |
| +# CONFIG_DM_ERA is not set | |
| +# CONFIG_DM_MIRROR is not set | |
| +# CONFIG_DM_RAID is not set | |
| +# CONFIG_DM_ZERO is not set | |
| +# CONFIG_DM_MULTIPATH is not set | |
| +# CONFIG_DM_DELAY is not set | |
| +# CONFIG_DM_UEVENT is not set | |
| +# CONFIG_DM_FLAKEY is not set | |
| +# CONFIG_DM_VERITY is not set | |
| +# CONFIG_DM_SWITCH is not set | |
| +# CONFIG_DM_LOG_WRITES is not set | |
| +CONFIG_TARGET_CORE=y | |
| +# CONFIG_TCM_IBLOCK is not set | |
| +CONFIG_TCM_FILEIO=y | |
| +# CONFIG_TCM_PSCSI is not set | |
| +# CONFIG_LOOPBACK_TARGET is not set | |
| +CONFIG_ISCSI_TARGET=y | |
| +# CONFIG_FUSION is not set | |
| + | |
| +# | |
| +# IEEE 1394 (FireWire) support | |
| +# | |
| +# CONFIG_FIREWIRE is not set | |
| +# CONFIG_FIREWIRE_NOSY is not set | |
| +CONFIG_NETDEVICES=y | |
| +CONFIG_NET_CORE=y | |
| +CONFIG_BONDING=y | |
| +CONFIG_DUMMY=m | |
| +# CONFIG_EQUALIZER is not set | |
| +# CONFIG_NET_FC is not set | |
| +# CONFIG_NET_TEAM is not set | |
| +CONFIG_MACVLAN=m | |
| +# CONFIG_MACVTAP is not set | |
| +CONFIG_IPVLAN=m | |
| +CONFIG_VXLAN=m | |
| +CONFIG_GENEVE=m | |
| +CONFIG_NETCONSOLE=m | |
| +# CONFIG_NETCONSOLE_DYNAMIC is not set | |
| +CONFIG_NETPOLL=y | |
| +CONFIG_NET_POLL_CONTROLLER=y | |
| +CONFIG_TUN=y | |
| +# CONFIG_TUN_VNET_CROSS_LE is not set | |
| +CONFIG_VETH=m | |
| +# CONFIG_NLMON is not set | |
| +# CONFIG_ARCNET is not set | |
| + | |
| +# | |
| +# CAIF transport drivers | |
| +# | |
| + | |
| +# | |
| +# Distributed Switch Architecture drivers | |
| +# | |
| +# CONFIG_NET_DSA_MV88E6XXX is not set | |
| +# CONFIG_NET_DSA_MV88E6XXX_NEED_PPU is not set | |
| +CONFIG_ETHERNET=y | |
| +# CONFIG_NET_VENDOR_3COM is not set | |
| +# CONFIG_NET_VENDOR_ADAPTEC is not set | |
| +# CONFIG_NET_VENDOR_AGERE is not set | |
| +# CONFIG_NET_VENDOR_ALTEON is not set | |
| +# CONFIG_ALTERA_TSE is not set | |
| +CONFIG_NET_AL_ETH=y | |
| +CONFIG_AL_ETH_ALLOC_FRAG=y | |
| +# CONFIG_AL_ETH_ALLOC_PAGE is not set | |
| +# CONFIG_AL_ETH_ALLOC_SKB is not set | |
| +# CONFIG_NET_VENDOR_AMD is not set | |
| +# CONFIG_NET_VENDOR_ARC is not set | |
| +# CONFIG_NET_VENDOR_ATHEROS is not set | |
| +# CONFIG_NET_VENDOR_AURORA is not set | |
| +# CONFIG_NET_CADENCE is not set | |
| +# CONFIG_NET_VENDOR_BROADCOM is not set | |
| +# CONFIG_NET_VENDOR_BROCADE is not set | |
| +# CONFIG_NET_VENDOR_CAVIUM is not set | |
| +# CONFIG_NET_VENDOR_CHELSIO is not set | |
| +# CONFIG_NET_VENDOR_CIRRUS is not set | |
| +# CONFIG_NET_VENDOR_CISCO is not set | |
| +# CONFIG_DM9000 is not set | |
| +# CONFIG_DNET is not set | |
| +# CONFIG_NET_VENDOR_DEC is not set | |
| +# CONFIG_NET_VENDOR_DLINK is not set | |
| +# CONFIG_NET_VENDOR_EMULEX is not set | |
| +# CONFIG_NET_VENDOR_EZCHIP is not set | |
| +# CONFIG_NET_VENDOR_EXAR is not set | |
| +# CONFIG_NET_VENDOR_FARADAY is not set | |
| +# CONFIG_NET_VENDOR_HISILICON is not set | |
| +# CONFIG_NET_VENDOR_HP is not set | |
| +# CONFIG_NET_VENDOR_INTEL is not set | |
| +# CONFIG_JME is not set | |
| +# CONFIG_NET_VENDOR_MARVELL is not set | |
| +# CONFIG_NET_VENDOR_MELLANOX is not set | |
| +# CONFIG_NET_VENDOR_MICREL is not set | |
| +# CONFIG_NET_VENDOR_MYRI is not set | |
| +# CONFIG_FEALNX is not set | |
| +# CONFIG_NET_VENDOR_NATSEMI is not set | |
| +# CONFIG_NET_VENDOR_NVIDIA is not set | |
| +# CONFIG_NET_VENDOR_OKI is not set | |
| +# CONFIG_ETHOC is not set | |
| +# CONFIG_NET_PACKET_ENGINE is not set | |
| +# CONFIG_NET_VENDOR_QLOGIC is not set | |
| +# CONFIG_NET_VENDOR_QUALCOMM is not set | |
| +# CONFIG_NET_VENDOR_REALTEK is not set | |
| +# CONFIG_NET_VENDOR_RENESAS is not set | |
| +# CONFIG_NET_VENDOR_RDC is not set | |
| +# CONFIG_NET_VENDOR_ROCKER is not set | |
| +# CONFIG_NET_VENDOR_SAMSUNG is not set | |
| +# CONFIG_NET_VENDOR_SEEQ is not set | |
| +# CONFIG_NET_VENDOR_SILAN is not set | |
| +# CONFIG_NET_VENDOR_SIS is not set | |
| +# CONFIG_SFC is not set | |
| +# CONFIG_NET_VENDOR_SMSC is not set | |
| +# CONFIG_NET_VENDOR_STMICRO is not set | |
| +# CONFIG_NET_VENDOR_SUN is not set | |
| +# CONFIG_NET_VENDOR_SYNOPSYS is not set | |
| +# CONFIG_NET_VENDOR_TEHUTI is not set | |
| +# CONFIG_NET_VENDOR_TI is not set | |
| +# CONFIG_NET_VENDOR_VIA is not set | |
| +# CONFIG_NET_VENDOR_WIZNET is not set | |
| +# CONFIG_FDDI is not set | |
| +# CONFIG_HIPPI is not set | |
| +CONFIG_PHYLIB=y | |
| + | |
| +# | |
| +# MII PHY device drivers | |
| +# | |
| +# CONFIG_AQUANTIA_PHY is not set | |
| +CONFIG_AT803X_PHY=y | |
| +# CONFIG_AMD_PHY is not set | |
| +# CONFIG_MARVELL_PHY is not set | |
| +# CONFIG_DAVICOM_PHY is not set | |
| +# CONFIG_QSEMI_PHY is not set | |
| +# CONFIG_LXT_PHY is not set | |
| +# CONFIG_CICADA_PHY is not set | |
| +# CONFIG_VITESSE_PHY is not set | |
| +# CONFIG_TERANETICS_PHY is not set | |
| +# CONFIG_SMSC_PHY is not set | |
| +# CONFIG_BROADCOM_PHY is not set | |
| +# CONFIG_BCM7XXX_PHY is not set | |
| +# CONFIG_BCM87XX_PHY is not set | |
| +# CONFIG_ICPLUS_PHY is not set | |
| +# CONFIG_REALTEK_PHY is not set | |
| +# CONFIG_NATIONAL_PHY is not set | |
| +# CONFIG_STE10XP is not set | |
| +# CONFIG_LSI_ET1011C_PHY is not set | |
| +# CONFIG_MICREL_PHY is not set | |
| +# CONFIG_DP83848_PHY is not set | |
| +# CONFIG_DP83867_PHY is not set | |
| +# CONFIG_MICROCHIP_PHY is not set | |
| +# CONFIG_FIXED_PHY is not set | |
| +# CONFIG_MDIO_BITBANG is not set | |
| +# CONFIG_MDIO_BUS_MUX_GPIO is not set | |
| +# CONFIG_MDIO_BUS_MUX_MMIOREG is not set | |
| +# CONFIG_MDIO_BCM_UNIMAC is not set | |
| +# CONFIG_PPP is not set | |
| +# CONFIG_SLIP is not set | |
| +# CONFIG_USB_NET_DRIVERS is not set | |
| +# CONFIG_WLAN is not set | |
| + | |
| +# | |
| +# Enable WiMAX (Networking options) to see the WiMAX drivers | |
| +# | |
| +# CONFIG_WAN is not set | |
| +# CONFIG_VMXNET3 is not set | |
| +# CONFIG_ISDN is not set | |
| +# CONFIG_NVM is not set | |
| + | |
| +# | |
| +# Input device support | |
| +# | |
| +CONFIG_INPUT=y | |
| +# CONFIG_INPUT_LEDS is not set | |
| +# CONFIG_INPUT_FF_MEMLESS is not set | |
| +# CONFIG_INPUT_POLLDEV is not set | |
| +# CONFIG_INPUT_SPARSEKMAP is not set | |
| +# CONFIG_INPUT_MATRIXKMAP is not set | |
| + | |
| +# | |
| +# Userland interfaces | |
| +# | |
| +# CONFIG_INPUT_MOUSEDEV is not set | |
| +# CONFIG_INPUT_JOYDEV is not set | |
| +CONFIG_INPUT_EVDEV=y | |
| +# CONFIG_INPUT_EVBUG is not set | |
| + | |
| +# | |
| +# Input Device Drivers | |
| +# | |
| +CONFIG_INPUT_KEYBOARD=y | |
| +# CONFIG_KEYBOARD_ADP5588 is not set | |
| +# CONFIG_KEYBOARD_ADP5589 is not set | |
| +# CONFIG_KEYBOARD_ATKBD is not set | |
| +# CONFIG_KEYBOARD_QT1070 is not set | |
| +# CONFIG_KEYBOARD_QT2160 is not set | |
| +# CONFIG_KEYBOARD_LKKBD is not set | |
| +CONFIG_KEYBOARD_GPIO=y | |
| +# CONFIG_KEYBOARD_GPIO_POLLED is not set | |
| +# CONFIG_KEYBOARD_TCA6416 is not set | |
| +# CONFIG_KEYBOARD_TCA8418 is not set | |
| +# CONFIG_KEYBOARD_MATRIX is not set | |
| +# CONFIG_KEYBOARD_LM8323 is not set | |
| +# CONFIG_KEYBOARD_LM8333 is not set | |
| +# CONFIG_KEYBOARD_MAX7359 is not set | |
| +# CONFIG_KEYBOARD_MCS is not set | |
| +# CONFIG_KEYBOARD_MPR121 is not set | |
| +# CONFIG_KEYBOARD_NEWTON is not set | |
| +# CONFIG_KEYBOARD_OPENCORES is not set | |
| +# CONFIG_KEYBOARD_SAMSUNG is not set | |
| +# CONFIG_KEYBOARD_STOWAWAY is not set | |
| +# CONFIG_KEYBOARD_SUNKBD is not set | |
| +# CONFIG_KEYBOARD_OMAP4 is not set | |
| +# CONFIG_KEYBOARD_XTKBD is not set | |
| +# CONFIG_KEYBOARD_CAP11XX is not set | |
| +# CONFIG_KEYBOARD_BCM is not set | |
| +# CONFIG_INPUT_MOUSE is not set | |
| +# CONFIG_INPUT_JOYSTICK is not set | |
| +# CONFIG_INPUT_TABLET is not set | |
| +# CONFIG_INPUT_TOUCHSCREEN is not set | |
| +# CONFIG_INPUT_MISC is not set | |
| + | |
| +# | |
| +# Hardware I/O ports | |
| +# | |
| +CONFIG_SERIO=y | |
| +# CONFIG_SERIO_SERPORT is not set | |
| +# CONFIG_SERIO_AMBAKMI is not set | |
| +# CONFIG_SERIO_PCIPS2 is not set | |
| +CONFIG_SERIO_LIBPS2=y | |
| +# CONFIG_SERIO_RAW is not set | |
| +# CONFIG_SERIO_ALTERA_PS2 is not set | |
| +# CONFIG_SERIO_PS2MULT is not set | |
| +# CONFIG_SERIO_ARC_PS2 is not set | |
| +# CONFIG_SERIO_APBPS2 is not set | |
| +# CONFIG_USERIO is not set | |
| +# CONFIG_GAMEPORT is not set | |
| + | |
| +# | |
| +# Character devices | |
| +# | |
| +CONFIG_TTY=y | |
| +# CONFIG_VT is not set | |
| +CONFIG_UNIX98_PTYS=y | |
| +CONFIG_DEVPTS_MULTIPLE_INSTANCES=y | |
| +# CONFIG_LEGACY_PTYS is not set | |
| +# CONFIG_SERIAL_NONSTANDARD is not set | |
| +# CONFIG_NOZOMI is not set | |
| +# CONFIG_N_GSM is not set | |
| +# CONFIG_TRACE_SINK is not set | |
| +CONFIG_DEVMEM=y | |
| +# CONFIG_DEVKMEM is not set | |
| + | |
| +# | |
| +# Serial drivers | |
| +# | |
| +CONFIG_SERIAL_EARLYCON=y | |
| +CONFIG_SERIAL_8250=y | |
| +CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y | |
| +CONFIG_SERIAL_8250_CONSOLE=y | |
| +CONFIG_SERIAL_8250_DMA=y | |
| +# CONFIG_SERIAL_8250_PCI is not set | |
| +CONFIG_SERIAL_8250_NR_UARTS=4 | |
| +CONFIG_SERIAL_8250_RUNTIME_UARTS=2 | |
| +# CONFIG_SERIAL_8250_EXTENDED is not set | |
| +CONFIG_SERIAL_8250_FSL=y | |
| +CONFIG_SERIAL_8250_DW=y | |
| +# CONFIG_SERIAL_8250_EM is not set | |
| +# CONFIG_SERIAL_8250_RT288X is not set | |
| +# CONFIG_SERIAL_8250_INGENIC is not set | |
| +# CONFIG_SERIAL_8250_MID is not set | |
| + | |
| +# | |
| +# Non-8250 serial port support | |
| +# | |
| +# CONFIG_SERIAL_AMBA_PL010 is not set | |
| +CONFIG_SERIAL_AMBA_PL011=y | |
| +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y | |
| +# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set | |
| +# CONFIG_SERIAL_UARTLITE is not set | |
| +CONFIG_SERIAL_CORE=y | |
| +CONFIG_SERIAL_CORE_CONSOLE=y | |
| +# CONFIG_SERIAL_JSM is not set | |
| +CONFIG_SERIAL_OF_PLATFORM=y | |
| +# CONFIG_SERIAL_SCCNXP is not set | |
| +# CONFIG_SERIAL_SC16IS7XX is not set | |
| +# CONFIG_SERIAL_BCM63XX is not set | |
| +# CONFIG_SERIAL_ALTERA_JTAGUART is not set | |
| +# CONFIG_SERIAL_ALTERA_UART is not set | |
| +# CONFIG_SERIAL_XILINX_PS_UART is not set | |
| +# CONFIG_SERIAL_ARC is not set | |
| +# CONFIG_SERIAL_RP2 is not set | |
| +# CONFIG_SERIAL_FSL_LPUART is not set | |
| +# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set | |
| +# CONFIG_SERIAL_ST_ASC is not set | |
| +# CONFIG_SERIAL_STM32 is not set | |
| +# CONFIG_TTY_PRINTK is not set | |
| +# CONFIG_HVC_DCC is not set | |
| +# CONFIG_IPMI_HANDLER is not set | |
| +# CONFIG_HW_RANDOM is not set | |
| +# CONFIG_R3964 is not set | |
| +# CONFIG_APPLICOM is not set | |
| +# CONFIG_RAW_DRIVER is not set | |
| +# CONFIG_TCG_TPM is not set | |
| +CONFIG_DEVPORT=y | |
| +# CONFIG_XILLYBUS is not set | |
| + | |
| +# | |
| +# I2C support | |
| +# | |
| +CONFIG_I2C=y | |
| +CONFIG_I2C_BOARDINFO=y | |
| +CONFIG_I2C_COMPAT=y | |
| +CONFIG_I2C_CHARDEV=y | |
| +# CONFIG_I2C_MUX is not set | |
| +CONFIG_I2C_HELPER_AUTO=y | |
| + | |
| +# | |
| +# I2C Hardware Bus support | |
| +# | |
| + | |
| +# | |
| +# PC SMBus host controller drivers | |
| +# | |
| +# CONFIG_I2C_ALI1535 is not set | |
| +# CONFIG_I2C_ALI1563 is not set | |
| +# CONFIG_I2C_ALI15X3 is not set | |
| +# CONFIG_I2C_AMD756 is not set | |
| +# CONFIG_I2C_AMD8111 is not set | |
| +# CONFIG_I2C_I801 is not set | |
| +# CONFIG_I2C_ISCH is not set | |
| +# CONFIG_I2C_PIIX4 is not set | |
| +# CONFIG_I2C_NFORCE2 is not set | |
| +# CONFIG_I2C_SIS5595 is not set | |
| +# CONFIG_I2C_SIS630 is not set | |
| +# CONFIG_I2C_SIS96X is not set | |
| +# CONFIG_I2C_VIA is not set | |
| +# CONFIG_I2C_VIAPRO is not set | |
| + | |
| +# | |
| +# I2C system bus drivers (mostly embedded / system-on-chip) | |
| +# | |
| +# CONFIG_I2C_CBUS_GPIO is not set | |
| +CONFIG_I2C_DESIGNWARE_CORE=y | |
| +CONFIG_I2C_DESIGNWARE_PLATFORM=y | |
| +# CONFIG_I2C_DESIGNWARE_PCI is not set | |
| +# CONFIG_I2C_EMEV2 is not set | |
| +# CONFIG_I2C_GPIO is not set | |
| +# CONFIG_I2C_NOMADIK is not set | |
| +# CONFIG_I2C_OCORES is not set | |
| +# CONFIG_I2C_PCA_PLATFORM is not set | |
| +# CONFIG_I2C_PXA_PCI is not set | |
| +# CONFIG_I2C_RK3X is not set | |
| +# CONFIG_I2C_SIMTEC is not set | |
| +# CONFIG_I2C_XILINX is not set | |
| + | |
| +# | |
| +# External I2C/SMBus adapter drivers | |
| +# | |
| +# CONFIG_I2C_DIOLAN_U2C is not set | |
| +# CONFIG_I2C_PARPORT_LIGHT is not set | |
| +# CONFIG_I2C_ROBOTFUZZ_OSIF is not set | |
| +# CONFIG_I2C_TAOS_EVM is not set | |
| +# CONFIG_I2C_TINY_USB is not set | |
| + | |
| +# | |
| +# Other I2C/SMBus bus drivers | |
| +# | |
| +# CONFIG_I2C_STUB is not set | |
| +# CONFIG_I2C_SLAVE is not set | |
| +# CONFIG_I2C_DEBUG_CORE is not set | |
| +# CONFIG_I2C_DEBUG_ALGO is not set | |
| +# CONFIG_I2C_DEBUG_BUS is not set | |
| +# CONFIG_SPI is not set | |
| +# CONFIG_SPMI is not set | |
| +# CONFIG_HSI is not set | |
| + | |
| +# | |
| +# PPS support | |
| +# | |
| +# CONFIG_PPS is not set | |
| + | |
| +# | |
| +# PPS generators support | |
| +# | |
| + | |
| +# | |
| +# PTP clock support | |
| +# | |
| +# CONFIG_PTP_1588_CLOCK is not set | |
| + | |
| +# | |
| +# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. | |
| +# | |
| +CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y | |
| +CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y | |
| +CONFIG_GPIOLIB=y | |
| +CONFIG_GPIO_DEVRES=y | |
| +CONFIG_OF_GPIO=y | |
| +CONFIG_GPIOLIB_IRQCHIP=y | |
| +# CONFIG_DEBUG_GPIO is not set | |
| +CONFIG_GPIO_SYSFS=y | |
| +CONFIG_GPIO_GENERIC=y | |
| + | |
| +# | |
| +# Memory mapped GPIO drivers | |
| +# | |
| +# CONFIG_GPIO_74XX_MMIO is not set | |
| +# CONFIG_GPIO_ALTERA is not set | |
| +# CONFIG_GPIO_DWAPB is not set | |
| +# CONFIG_GPIO_EM is not set | |
| +CONFIG_GPIO_GENERIC_PLATFORM=y | |
| +# CONFIG_GPIO_GRGPIO is not set | |
| +CONFIG_GPIO_PL061=y | |
| +# CONFIG_GPIO_SYSCON is not set | |
| +# CONFIG_GPIO_VX855 is not set | |
| +# CONFIG_GPIO_XILINX is not set | |
| +# CONFIG_GPIO_ZEVIO is not set | |
| +# CONFIG_GPIO_ZX is not set | |
| + | |
| +# | |
| +# I2C GPIO expanders | |
| +# | |
| +# CONFIG_GPIO_ADP5588 is not set | |
| +# CONFIG_GPIO_ADNP is not set | |
| +# CONFIG_GPIO_MAX7300 is not set | |
| +# CONFIG_GPIO_MAX732X is not set | |
| +CONFIG_GPIO_PCA953X=y | |
| +# CONFIG_GPIO_PCA953X_IRQ is not set | |
| +# CONFIG_GPIO_PCF857X is not set | |
| +# CONFIG_GPIO_SX150X is not set | |
| + | |
| +# | |
| +# MFD GPIO expanders | |
| +# | |
| + | |
| +# | |
| +# PCI GPIO expanders | |
| +# | |
| +# CONFIG_GPIO_AMD8111 is not set | |
| +# CONFIG_GPIO_BT8XX is not set | |
| +# CONFIG_GPIO_ML_IOH is not set | |
| +# CONFIG_GPIO_RDC321X is not set | |
| + | |
| +# | |
| +# SPI or I2C GPIO expanders | |
| +# | |
| +# CONFIG_GPIO_MCP23S08 is not set | |
| + | |
| +# | |
| +# USB GPIO expanders | |
| +# | |
| +# CONFIG_W1 is not set | |
| +CONFIG_POWER_SUPPLY=y | |
| +# CONFIG_POWER_SUPPLY_DEBUG is not set | |
| +# CONFIG_PDA_POWER is not set | |
| +# CONFIG_TEST_POWER is not set | |
| +# CONFIG_BATTERY_DS2780 is not set | |
| +# CONFIG_BATTERY_DS2781 is not set | |
| +# CONFIG_BATTERY_DS2782 is not set | |
| +# CONFIG_BATTERY_SBS is not set | |
| +# CONFIG_BATTERY_BQ27XXX is not set | |
| +# CONFIG_BATTERY_MAX17040 is not set | |
| +# CONFIG_BATTERY_MAX17042 is not set | |
| +# CONFIG_CHARGER_MAX8903 is not set | |
| +# CONFIG_CHARGER_LP8727 is not set | |
| +# CONFIG_CHARGER_GPIO is not set | |
| +# CONFIG_CHARGER_BQ2415X is not set | |
| +# CONFIG_CHARGER_BQ24190 is not set | |
| +# CONFIG_CHARGER_BQ24735 is not set | |
| +# CONFIG_CHARGER_BQ25890 is not set | |
| +# CONFIG_CHARGER_SMB347 is not set | |
| +# CONFIG_BATTERY_GAUGE_LTC2941 is not set | |
| +# CONFIG_CHARGER_RT9455 is not set | |
| +CONFIG_POWER_RESET=y | |
| +# CONFIG_POWER_RESET_BRCMSTB is not set | |
| +# CONFIG_POWER_RESET_GPIO is not set | |
| +# CONFIG_POWER_RESET_GPIO_RESTART is not set | |
| +# CONFIG_POWER_RESET_LTC2952 is not set | |
| +# CONFIG_POWER_RESET_RESTART is not set | |
| +# CONFIG_POWER_RESET_VERSATILE is not set | |
| +CONFIG_POWER_RESET_VEXPRESS=y | |
| +# CONFIG_POWER_RESET_SYSCON is not set | |
| +# CONFIG_POWER_RESET_SYSCON_POWEROFF is not set | |
| +CONFIG_POWER_RESET_ALPINE=y | |
| +# CONFIG_POWER_AVS is not set | |
| +CONFIG_HWMON=y | |
| +# CONFIG_HWMON_VID is not set | |
| +# CONFIG_HWMON_DEBUG_CHIP is not set | |
| + | |
| +# | |
| +# Native drivers | |
| +# | |
| +# CONFIG_SENSORS_AD7414 is not set | |
| +# CONFIG_SENSORS_AD7418 is not set | |
| +# CONFIG_SENSORS_ADM1021 is not set | |
| +# CONFIG_SENSORS_ADM1025 is not set | |
| +# CONFIG_SENSORS_ADM1026 is not set | |
| +# CONFIG_SENSORS_ADM1029 is not set | |
| +# CONFIG_SENSORS_ADM1031 is not set | |
| +# CONFIG_SENSORS_ADM9240 is not set | |
| +# CONFIG_SENSORS_ADT7410 is not set | |
| +# CONFIG_SENSORS_ADT7411 is not set | |
| +# CONFIG_SENSORS_ADT7462 is not set | |
| +# CONFIG_SENSORS_ADT7470 is not set | |
| +# CONFIG_SENSORS_ADT7475 is not set | |
| +# CONFIG_SENSORS_ASC7621 is not set | |
| +# CONFIG_SENSORS_ATXP1 is not set | |
| +# CONFIG_SENSORS_DS620 is not set | |
| +# CONFIG_SENSORS_DS1621 is not set | |
| +# CONFIG_SENSORS_I5K_AMB is not set | |
| +# CONFIG_SENSORS_F71805F is not set | |
| +# CONFIG_SENSORS_F71882FG is not set | |
| +# CONFIG_SENSORS_F75375S is not set | |
| +# CONFIG_SENSORS_GL518SM is not set | |
| +# CONFIG_SENSORS_GL520SM is not set | |
| +CONFIG_SENSORS_G760A=y | |
| +CONFIG_SENSORS_G762=y | |
| +# CONFIG_SENSORS_GPIO_FAN is not set | |
| +# CONFIG_SENSORS_HIH6130 is not set | |
| +# CONFIG_SENSORS_IT87 is not set | |
| +# CONFIG_SENSORS_JC42 is not set | |
| +# CONFIG_SENSORS_POWR1220 is not set | |
| +# CONFIG_SENSORS_LINEAGE is not set | |
| +# CONFIG_SENSORS_LTC2945 is not set | |
| +# CONFIG_SENSORS_LTC4151 is not set | |
| +# CONFIG_SENSORS_LTC4215 is not set | |
| +# CONFIG_SENSORS_LTC4222 is not set | |
| +# CONFIG_SENSORS_LTC4245 is not set | |
| +# CONFIG_SENSORS_LTC4260 is not set | |
| +# CONFIG_SENSORS_LTC4261 is not set | |
| +# CONFIG_SENSORS_MAX16065 is not set | |
| +# CONFIG_SENSORS_MAX1619 is not set | |
| +# CONFIG_SENSORS_MAX1668 is not set | |
| +# CONFIG_SENSORS_MAX197 is not set | |
| +# CONFIG_SENSORS_MAX6639 is not set | |
| +# CONFIG_SENSORS_MAX6642 is not set | |
| +# CONFIG_SENSORS_MAX6650 is not set | |
| +# CONFIG_SENSORS_MAX6697 is not set | |
| +# CONFIG_SENSORS_MAX31790 is not set | |
| +# CONFIG_SENSORS_HTU21 is not set | |
| +# CONFIG_SENSORS_MCP3021 is not set | |
| +# CONFIG_SENSORS_LM63 is not set | |
| +# CONFIG_SENSORS_LM73 is not set | |
| +# CONFIG_SENSORS_LM75 is not set | |
| +# CONFIG_SENSORS_LM77 is not set | |
| +# CONFIG_SENSORS_LM78 is not set | |
| +# CONFIG_SENSORS_LM80 is not set | |
| +# CONFIG_SENSORS_LM83 is not set | |
| +# CONFIG_SENSORS_LM85 is not set | |
| +# CONFIG_SENSORS_LM87 is not set | |
| +# CONFIG_SENSORS_LM90 is not set | |
| +# CONFIG_SENSORS_LM92 is not set | |
| +# CONFIG_SENSORS_LM93 is not set | |
| +# CONFIG_SENSORS_LM95234 is not set | |
| +# CONFIG_SENSORS_LM95241 is not set | |
| +# CONFIG_SENSORS_LM95245 is not set | |
| +# CONFIG_SENSORS_PC87360 is not set | |
| +# CONFIG_SENSORS_PC87427 is not set | |
| +# CONFIG_SENSORS_NTC_THERMISTOR is not set | |
| +# CONFIG_SENSORS_NCT6683 is not set | |
| +# CONFIG_SENSORS_NCT6775 is not set | |
| +# CONFIG_SENSORS_NCT7802 is not set | |
| +# CONFIG_SENSORS_NCT7904 is not set | |
| +# CONFIG_SENSORS_PCF8591 is not set | |
| +# CONFIG_PMBUS is not set | |
| +# CONFIG_SENSORS_SHT15 is not set | |
| +# CONFIG_SENSORS_SHT21 is not set | |
| +# CONFIG_SENSORS_SHTC1 is not set | |
| +# CONFIG_SENSORS_SIS5595 is not set | |
| +# CONFIG_SENSORS_DME1737 is not set | |
| +# CONFIG_SENSORS_EMC1403 is not set | |
| +# CONFIG_SENSORS_EMC2103 is not set | |
| +# CONFIG_SENSORS_EMC6W201 is not set | |
| +# CONFIG_SENSORS_SMSC47M1 is not set | |
| +# CONFIG_SENSORS_SMSC47M192 is not set | |
| +# CONFIG_SENSORS_SMSC47B397 is not set | |
| +# CONFIG_SENSORS_SCH56XX_COMMON is not set | |
| +# CONFIG_SENSORS_SMM665 is not set | |
| +# CONFIG_SENSORS_ADC128D818 is not set | |
| +# CONFIG_SENSORS_ADS1015 is not set | |
| +# CONFIG_SENSORS_ADS7828 is not set | |
| +# CONFIG_SENSORS_AMC6821 is not set | |
| +# CONFIG_SENSORS_INA209 is not set | |
| +# CONFIG_SENSORS_INA2XX is not set | |
| +# CONFIG_SENSORS_TC74 is not set | |
| +# CONFIG_SENSORS_THMC50 is not set | |
| +# CONFIG_SENSORS_TMP102 is not set | |
| +# CONFIG_SENSORS_TMP103 is not set | |
| +# CONFIG_SENSORS_TMP401 is not set | |
| +# CONFIG_SENSORS_TMP421 is not set | |
| +# CONFIG_SENSORS_VEXPRESS is not set | |
| +# CONFIG_SENSORS_VIA686A is not set | |
| +# CONFIG_SENSORS_VT1211 is not set | |
| +# CONFIG_SENSORS_VT8231 is not set | |
| +# CONFIG_SENSORS_W83781D is not set | |
| +# CONFIG_SENSORS_W83791D is not set | |
| +# CONFIG_SENSORS_W83792D is not set | |
| +# CONFIG_SENSORS_W83793 is not set | |
| +# CONFIG_SENSORS_W83795 is not set | |
| +# CONFIG_SENSORS_W83L785TS is not set | |
| +# CONFIG_SENSORS_W83L786NG is not set | |
| +# CONFIG_SENSORS_W83627HF is not set | |
| +# CONFIG_SENSORS_W83627EHF is not set | |
| +CONFIG_THERMAL=y | |
| +CONFIG_THERMAL_HWMON=y | |
| +# CONFIG_THERMAL_OF is not set | |
| +# CONFIG_THERMAL_WRITABLE_TRIPS is not set | |
| +CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y | |
| +# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set | |
| +# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set | |
| +# CONFIG_THERMAL_DEFAULT_GOV_POWER_ALLOCATOR is not set | |
| +# CONFIG_THERMAL_GOV_FAIR_SHARE is not set | |
| +CONFIG_THERMAL_GOV_STEP_WISE=y | |
| +# CONFIG_THERMAL_GOV_BANG_BANG is not set | |
| +# CONFIG_THERMAL_GOV_USER_SPACE is not set | |
| +# CONFIG_THERMAL_GOV_POWER_ALLOCATOR is not set | |
| +# CONFIG_THERMAL_EMULATION is not set | |
| +CONFIG_AL_THERMAL=y | |
| +# CONFIG_WATCHDOG is not set | |
| +CONFIG_SSB_POSSIBLE=y | |
| + | |
| +# | |
| +# Sonics Silicon Backplane | |
| +# | |
| +# CONFIG_SSB is not set | |
| +CONFIG_BCMA_POSSIBLE=y | |
| + | |
| +# | |
| +# Broadcom specific AMBA | |
| +# | |
| +# CONFIG_BCMA is not set | |
| + | |
| +# | |
| +# Multifunction device drivers | |
| +# | |
| +CONFIG_MFD_CORE=y | |
| +# CONFIG_MFD_AS3711 is not set | |
| +# CONFIG_MFD_AS3722 is not set | |
| +# CONFIG_PMIC_ADP5520 is not set | |
| +# CONFIG_MFD_AAT2870_CORE is not set | |
| +# CONFIG_MFD_ATMEL_FLEXCOM is not set | |
| +# CONFIG_MFD_ATMEL_HLCDC is not set | |
| +# CONFIG_MFD_BCM590XX is not set | |
| +# CONFIG_MFD_AXP20X is not set | |
| +# CONFIG_MFD_CROS_EC is not set | |
| +# CONFIG_MFD_ASIC3 is not set | |
| +# CONFIG_PMIC_DA903X is not set | |
| +# CONFIG_MFD_DA9052_I2C is not set | |
| +# CONFIG_MFD_DA9055 is not set | |
| +# CONFIG_MFD_DA9062 is not set | |
| +# CONFIG_MFD_DA9063 is not set | |
| +# CONFIG_MFD_DA9150 is not set | |
| +# CONFIG_MFD_DLN2 is not set | |
| +# CONFIG_MFD_MC13XXX_I2C is not set | |
| +# CONFIG_MFD_HI6421_PMIC is not set | |
| +# CONFIG_HTC_EGPIO is not set | |
| +# CONFIG_HTC_PASIC3 is not set | |
| +# CONFIG_HTC_I2CPLD is not set | |
| +# CONFIG_LPC_ICH is not set | |
| +# CONFIG_LPC_SCH is not set | |
| +# CONFIG_INTEL_SOC_PMIC is not set | |
| +# CONFIG_MFD_JANZ_CMODIO is not set | |
| +# CONFIG_MFD_KEMPLD is not set | |
| +# CONFIG_MFD_88PM800 is not set | |
| +# CONFIG_MFD_88PM805 is not set | |
| +# CONFIG_MFD_88PM860X is not set | |
| +# CONFIG_MFD_MAX14577 is not set | |
| +# CONFIG_MFD_MAX77686 is not set | |
| +# CONFIG_MFD_MAX77693 is not set | |
| +# CONFIG_MFD_MAX77843 is not set | |
| +# CONFIG_MFD_MAX8907 is not set | |
| +# CONFIG_MFD_MAX8925 is not set | |
| +# CONFIG_MFD_MAX8997 is not set | |
| +# CONFIG_MFD_MAX8998 is not set | |
| +# CONFIG_MFD_MT6397 is not set | |
| +# CONFIG_MFD_MENF21BMC is not set | |
| +# CONFIG_MFD_VIPERBOARD is not set | |
| +# CONFIG_MFD_RETU is not set | |
| +# CONFIG_MFD_PCF50633 is not set | |
| +# CONFIG_MFD_PM8921_CORE is not set | |
| +# CONFIG_MFD_RDC321X is not set | |
| +# CONFIG_MFD_RTSX_PCI is not set | |
| +# CONFIG_MFD_RT5033 is not set | |
| +# CONFIG_MFD_RTSX_USB is not set | |
| +# CONFIG_MFD_RC5T583 is not set | |
| +# CONFIG_MFD_RK808 is not set | |
| +# CONFIG_MFD_RN5T618 is not set | |
| +# CONFIG_MFD_SEC_CORE is not set | |
| +# CONFIG_MFD_SI476X_CORE is not set | |
| +# CONFIG_MFD_SM501 is not set | |
| +# CONFIG_MFD_SKY81452 is not set | |
| +# CONFIG_MFD_SMSC is not set | |
| +# CONFIG_ABX500_CORE is not set | |
| +# CONFIG_MFD_STMPE is not set | |
| +CONFIG_MFD_SYSCON=y | |
| +# CONFIG_MFD_TI_AM335X_TSCADC is not set | |
| +# CONFIG_MFD_LP3943 is not set | |
| +# CONFIG_MFD_LP8788 is not set | |
| +# CONFIG_MFD_PALMAS is not set | |
| +# CONFIG_TPS6105X is not set | |
| +# CONFIG_TPS65010 is not set | |
| +# CONFIG_TPS6507X is not set | |
| +# CONFIG_MFD_TPS65090 is not set | |
| +# CONFIG_MFD_TPS65217 is not set | |
| +# CONFIG_MFD_TPS65218 is not set | |
| +# CONFIG_MFD_TPS6586X is not set | |
| +# CONFIG_MFD_TPS65910 is not set | |
| +# CONFIG_MFD_TPS65912 is not set | |
| +# CONFIG_MFD_TPS65912_I2C is not set | |
| +# CONFIG_MFD_TPS80031 is not set | |
| +# CONFIG_TWL4030_CORE is not set | |
| +# CONFIG_TWL6040_CORE is not set | |
| +# CONFIG_MFD_WL1273_CORE is not set | |
| +# CONFIG_MFD_LM3533 is not set | |
| +# CONFIG_MFD_TC3589X is not set | |
| +# CONFIG_MFD_TMIO is not set | |
| +# CONFIG_MFD_T7L66XB is not set | |
| +# CONFIG_MFD_TC6387XB is not set | |
| +# CONFIG_MFD_TC6393XB is not set | |
| +# CONFIG_MFD_VX855 is not set | |
| +# CONFIG_MFD_ARIZONA_I2C is not set | |
| +# CONFIG_MFD_WM8400 is not set | |
| +# CONFIG_MFD_WM831X_I2C is not set | |
| +# CONFIG_MFD_WM8350_I2C is not set | |
| +# CONFIG_MFD_WM8994 is not set | |
| +CONFIG_MFD_VEXPRESS_SYSREG=y | |
| +# CONFIG_REGULATOR is not set | |
| +# CONFIG_MEDIA_SUPPORT is not set | |
| + | |
| +# | |
| +# Graphics support | |
| +# | |
| +# CONFIG_VGA_ARB is not set | |
| +# CONFIG_DRM is not set | |
| + | |
| +# | |
| +# Frame buffer Devices | |
| +# | |
| +# CONFIG_FB is not set | |
| +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set | |
| +# CONFIG_VGASTATE is not set | |
| +# CONFIG_SOUND is not set | |
| + | |
| +# | |
| +# HID support | |
| +# | |
| +CONFIG_HID=y | |
| +# CONFIG_HID_BATTERY_STRENGTH is not set | |
| +# CONFIG_HIDRAW is not set | |
| +# CONFIG_UHID is not set | |
| +# CONFIG_HID_GENERIC is not set | |
| + | |
| +# | |
| +# Special HID drivers | |
| +# | |
| +# CONFIG_HID_A4TECH is not set | |
| +# CONFIG_HID_ACRUX is not set | |
| +# CONFIG_HID_APPLE is not set | |
| +# CONFIG_HID_APPLEIR is not set | |
| +# CONFIG_HID_AUREAL is not set | |
| +# CONFIG_HID_BELKIN is not set | |
| +# CONFIG_HID_BETOP_FF is not set | |
| +# CONFIG_HID_CHERRY is not set | |
| +# CONFIG_HID_CHICONY is not set | |
| +# CONFIG_HID_CORSAIR is not set | |
| +# CONFIG_HID_CP2112 is not set | |
| +# CONFIG_HID_CYPRESS is not set | |
| +# CONFIG_HID_DRAGONRISE is not set | |
| +# CONFIG_HID_EMS_FF is not set | |
| +# CONFIG_HID_ELECOM is not set | |
| +# CONFIG_HID_ELO is not set | |
| +# CONFIG_HID_EZKEY is not set | |
| +# CONFIG_HID_GEMBIRD is not set | |
| +# CONFIG_HID_GFRM is not set | |
| +# CONFIG_HID_HOLTEK is not set | |
| +# CONFIG_HID_GT683R is not set | |
| +# CONFIG_HID_KEYTOUCH is not set | |
| +# CONFIG_HID_KYE is not set | |
| +# CONFIG_HID_UCLOGIC is not set | |
| +# CONFIG_HID_WALTOP is not set | |
| +# CONFIG_HID_GYRATION is not set | |
| +# CONFIG_HID_ICADE is not set | |
| +# CONFIG_HID_TWINHAN is not set | |
| +# CONFIG_HID_KENSINGTON is not set | |
| +# CONFIG_HID_LCPOWER is not set | |
| +# CONFIG_HID_LENOVO is not set | |
| +# CONFIG_HID_LOGITECH is not set | |
| +# CONFIG_HID_MAGICMOUSE is not set | |
| +# CONFIG_HID_MICROSOFT is not set | |
| +# CONFIG_HID_MONTEREY is not set | |
| +# CONFIG_HID_MULTITOUCH is not set | |
| +# CONFIG_HID_NTRIG is not set | |
| +# CONFIG_HID_ORTEK is not set | |
| +# CONFIG_HID_PANTHERLORD is not set | |
| +# CONFIG_HID_PENMOUNT is not set | |
| +# CONFIG_HID_PETALYNX is not set | |
| +# CONFIG_HID_PICOLCD is not set | |
| +# CONFIG_HID_PLANTRONICS is not set | |
| +# CONFIG_HID_PRIMAX is not set | |
| +# CONFIG_HID_ROCCAT is not set | |
| +# CONFIG_HID_SAITEK is not set | |
| +# CONFIG_HID_SAMSUNG is not set | |
| +# CONFIG_HID_SONY is not set | |
| +# CONFIG_HID_SPEEDLINK is not set | |
| +# CONFIG_HID_STEELSERIES is not set | |
| +# CONFIG_HID_SUNPLUS is not set | |
| +# CONFIG_HID_RMI is not set | |
| +# CONFIG_HID_GREENASIA is not set | |
| +# CONFIG_HID_SMARTJOYPLUS is not set | |
| +# CONFIG_HID_TIVO is not set | |
| +# CONFIG_HID_TOPSEED is not set | |
| +# CONFIG_HID_THINGM is not set | |
| +# CONFIG_HID_THRUSTMASTER is not set | |
| +# CONFIG_HID_WACOM is not set | |
| +# CONFIG_HID_WIIMOTE is not set | |
| +# CONFIG_HID_XINMO is not set | |
| +# CONFIG_HID_ZEROPLUS is not set | |
| +# CONFIG_HID_ZYDACRON is not set | |
| +# CONFIG_HID_SENSOR_HUB is not set | |
| + | |
| +# | |
| +# USB HID support | |
| +# | |
| +CONFIG_USB_HID=y | |
| +# CONFIG_HID_PID is not set | |
| +CONFIG_USB_HIDDEV=y | |
| + | |
| +# | |
| +# I2C HID support | |
| +# | |
| +# CONFIG_I2C_HID is not set | |
| +CONFIG_USB_OHCI_LITTLE_ENDIAN=y | |
| +CONFIG_USB_SUPPORT=y | |
| +CONFIG_USB_COMMON=y | |
| +CONFIG_USB_ARCH_HAS_HCD=y | |
| +CONFIG_USB=y | |
| +# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set | |
| + | |
| +# | |
| +# Miscellaneous USB options | |
| +# | |
| +CONFIG_USB_DEFAULT_PERSIST=y | |
| +# CONFIG_USB_DYNAMIC_MINORS is not set | |
| +# CONFIG_USB_OTG is not set | |
| +# CONFIG_USB_OTG_WHITELIST is not set | |
| +# CONFIG_USB_OTG_BLACKLIST_HUB is not set | |
| +# CONFIG_USB_ULPI_BUS is not set | |
| +# CONFIG_USB_MON is not set | |
| +# CONFIG_USB_WUSB_CBAF is not set | |
| + | |
| +# | |
| +# USB Host Controller Drivers | |
| +# | |
| +# CONFIG_USB_C67X00_HCD is not set | |
| +CONFIG_USB_XHCI_HCD=y | |
| +CONFIG_USB_XHCI_PCI=y | |
| +CONFIG_USB_XHCI_PLATFORM=y | |
| +CONFIG_USB_EHCI_HCD=y | |
| +CONFIG_USB_EHCI_ROOT_HUB_TT=y | |
| +CONFIG_USB_EHCI_TT_NEWSCHED=y | |
| +CONFIG_USB_EHCI_PCI=y | |
| +# CONFIG_USB_EHCI_HCD_PLATFORM is not set | |
| +# CONFIG_USB_OXU210HP_HCD is not set | |
| +# CONFIG_USB_ISP116X_HCD is not set | |
| +# CONFIG_USB_ISP1362_HCD is not set | |
| +# CONFIG_USB_FOTG210_HCD is not set | |
| +# CONFIG_USB_OHCI_HCD is not set | |
| +# CONFIG_USB_UHCI_HCD is not set | |
| +# CONFIG_USB_SL811_HCD is not set | |
| +# CONFIG_USB_R8A66597_HCD is not set | |
| +# CONFIG_USB_HCD_TEST_MODE is not set | |
| + | |
| +# | |
| +# USB Device Class drivers | |
| +# | |
| +CONFIG_USB_ACM=y | |
| +CONFIG_USB_PRINTER=y | |
| +# CONFIG_USB_WDM is not set | |
| +# CONFIG_USB_TMC is not set | |
| + | |
| +# | |
| +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may | |
| +# | |
| + | |
| +# | |
| +# also be needed; see USB_STORAGE Help for more info | |
| +# | |
| +CONFIG_USB_STORAGE=y | |
| +# CONFIG_USB_STORAGE_DEBUG is not set | |
| +# CONFIG_USB_STORAGE_REALTEK is not set | |
| +CONFIG_USB_STORAGE_DATAFAB=y | |
| +CONFIG_USB_STORAGE_FREECOM=y | |
| +# CONFIG_USB_STORAGE_ISD200 is not set | |
| +# CONFIG_USB_STORAGE_USBAT is not set | |
| +CONFIG_USB_STORAGE_SDDR09=y | |
| +CONFIG_USB_STORAGE_SDDR55=y | |
| +CONFIG_USB_STORAGE_JUMPSHOT=y | |
| +# CONFIG_USB_STORAGE_ALAUDA is not set | |
| +# CONFIG_USB_STORAGE_ONETOUCH is not set | |
| +# CONFIG_USB_STORAGE_KARMA is not set | |
| +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set | |
| +# CONFIG_USB_STORAGE_ENE_UB6250 is not set | |
| +# CONFIG_USB_UAS is not set | |
| + | |
| +# | |
| +# USB Imaging devices | |
| +# | |
| +# CONFIG_USB_MDC800 is not set | |
| +# CONFIG_USB_MICROTEK is not set | |
| +# CONFIG_USBIP_CORE is not set | |
| +# CONFIG_USB_MUSB_HDRC is not set | |
| +CONFIG_USB_DWC3=y | |
| +CONFIG_USB_DWC3_HOST=y | |
| + | |
| +# | |
| +# Platform Glue Driver Support | |
| +# | |
| +CONFIG_USB_DWC3_PCI=y | |
| +# CONFIG_USB_DWC2 is not set | |
| +# CONFIG_USB_CHIPIDEA is not set | |
| +# CONFIG_USB_ISP1760 is not set | |
| + | |
| +# | |
| +# USB port drivers | |
| +# | |
| +CONFIG_USB_SERIAL=m | |
| +CONFIG_USB_SERIAL_GENERIC=y | |
| +# CONFIG_USB_SERIAL_SIMPLE is not set | |
| +# CONFIG_USB_SERIAL_AIRCABLE is not set | |
| +# CONFIG_USB_SERIAL_ARK3116 is not set | |
| +# CONFIG_USB_SERIAL_BELKIN is not set | |
| +# CONFIG_USB_SERIAL_CH341 is not set | |
| +# CONFIG_USB_SERIAL_WHITEHEAT is not set | |
| +# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set | |
| +# CONFIG_USB_SERIAL_CP210X is not set | |
| +# CONFIG_USB_SERIAL_CYPRESS_M8 is not set | |
| +# CONFIG_USB_SERIAL_EMPEG is not set | |
| +CONFIG_USB_SERIAL_FTDI_SIO=m | |
| +# CONFIG_USB_SERIAL_VISOR is not set | |
| +# CONFIG_USB_SERIAL_IPAQ is not set | |
| +# CONFIG_USB_SERIAL_IR is not set | |
| +# CONFIG_USB_SERIAL_EDGEPORT is not set | |
| +# CONFIG_USB_SERIAL_EDGEPORT_TI is not set | |
| +# CONFIG_USB_SERIAL_F81232 is not set | |
| +# CONFIG_USB_SERIAL_GARMIN is not set | |
| +# CONFIG_USB_SERIAL_IPW is not set | |
| +# CONFIG_USB_SERIAL_IUU is not set | |
| +# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set | |
| +# CONFIG_USB_SERIAL_KEYSPAN is not set | |
| +# CONFIG_USB_SERIAL_KLSI is not set | |
| +# CONFIG_USB_SERIAL_KOBIL_SCT is not set | |
| +# CONFIG_USB_SERIAL_MCT_U232 is not set | |
| +# CONFIG_USB_SERIAL_METRO is not set | |
| +# CONFIG_USB_SERIAL_MOS7720 is not set | |
| +# CONFIG_USB_SERIAL_MOS7840 is not set | |
| +# CONFIG_USB_SERIAL_MXUPORT is not set | |
| +# CONFIG_USB_SERIAL_NAVMAN is not set | |
| +CONFIG_USB_SERIAL_PL2303=m | |
| +# CONFIG_USB_SERIAL_OTI6858 is not set | |
| +# CONFIG_USB_SERIAL_QCAUX is not set | |
| +# CONFIG_USB_SERIAL_QUALCOMM is not set | |
| +# CONFIG_USB_SERIAL_SPCP8X5 is not set | |
| +# CONFIG_USB_SERIAL_SAFE is not set | |
| +# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set | |
| +# CONFIG_USB_SERIAL_SYMBOL is not set | |
| +# CONFIG_USB_SERIAL_TI is not set | |
| +# CONFIG_USB_SERIAL_CYBERJACK is not set | |
| +# CONFIG_USB_SERIAL_XIRCOM is not set | |
| +# CONFIG_USB_SERIAL_OPTION is not set | |
| +# CONFIG_USB_SERIAL_OMNINET is not set | |
| +# CONFIG_USB_SERIAL_OPTICON is not set | |
| +# CONFIG_USB_SERIAL_XSENS_MT is not set | |
| +# CONFIG_USB_SERIAL_WISHBONE is not set | |
| +# CONFIG_USB_SERIAL_SSU100 is not set | |
| +# CONFIG_USB_SERIAL_QT2 is not set | |
| +# CONFIG_USB_SERIAL_DEBUG is not set | |
| + | |
| +# | |
| +# USB Miscellaneous drivers | |
| +# | |
| +# CONFIG_USB_EMI62 is not set | |
| +# CONFIG_USB_EMI26 is not set | |
| +# CONFIG_USB_ADUTUX is not set | |
| +# CONFIG_USB_SEVSEG is not set | |
| +# CONFIG_USB_RIO500 is not set | |
| +# CONFIG_USB_LEGOTOWER is not set | |
| +# CONFIG_USB_LCD is not set | |
| +# CONFIG_USB_LED is not set | |
| +# CONFIG_USB_CYPRESS_CY7C63 is not set | |
| +# CONFIG_USB_CYTHERM is not set | |
| +# CONFIG_USB_IDMOUSE is not set | |
| +# CONFIG_USB_FTDI_ELAN is not set | |
| +# CONFIG_USB_APPLEDISPLAY is not set | |
| +# CONFIG_USB_SISUSBVGA is not set | |
| +# CONFIG_USB_LD is not set | |
| +# CONFIG_USB_TRANCEVIBRATOR is not set | |
| +# CONFIG_USB_IOWARRIOR is not set | |
| +# CONFIG_USB_TEST is not set | |
| +# CONFIG_USB_EHSET_TEST_FIXTURE is not set | |
| +# CONFIG_USB_ISIGHTFW is not set | |
| +# CONFIG_USB_YUREX is not set | |
| +# CONFIG_USB_EZUSB_FX2 is not set | |
| +# CONFIG_USB_HSIC_USB3503 is not set | |
| +# CONFIG_USB_LINK_LAYER_TEST is not set | |
| + | |
| +# | |
| +# USB Physical Layer drivers | |
| +# | |
| +# CONFIG_USB_PHY is not set | |
| +# CONFIG_NOP_USB_XCEIV is not set | |
| +# CONFIG_AM335X_PHY_USB is not set | |
| +# CONFIG_USB_GPIO_VBUS is not set | |
| +# CONFIG_USB_ISP1301 is not set | |
| +# CONFIG_USB_ULPI is not set | |
| +# CONFIG_USB_GADGET is not set | |
| +# CONFIG_USB_LED_TRIG is not set | |
| +# CONFIG_UWB is not set | |
| +# CONFIG_MMC is not set | |
| +# CONFIG_MEMSTICK is not set | |
| +CONFIG_NEW_LEDS=y | |
| +CONFIG_LEDS_CLASS=y | |
| +# CONFIG_LEDS_CLASS_FLASH is not set | |
| + | |
| +# | |
| +# LED drivers | |
| +# | |
| +# CONFIG_LEDS_BCM6328 is not set | |
| +# CONFIG_LEDS_BCM6358 is not set | |
| +# CONFIG_LEDS_LM3530 is not set | |
| +# CONFIG_LEDS_LM3642 is not set | |
| +# CONFIG_LEDS_PCA9532 is not set | |
| +CONFIG_LEDS_GPIO=y | |
| +# CONFIG_LEDS_LP3944 is not set | |
| +# CONFIG_LEDS_LP5521 is not set | |
| +# CONFIG_LEDS_LP5523 is not set | |
| +# CONFIG_LEDS_LP5562 is not set | |
| +# CONFIG_LEDS_LP8501 is not set | |
| +# CONFIG_LEDS_LP8860 is not set | |
| +# CONFIG_LEDS_PCA955X is not set | |
| +# CONFIG_LEDS_PCA963X is not set | |
| +# CONFIG_LEDS_BD2802 is not set | |
| +# CONFIG_LEDS_LT3593 is not set | |
| +# CONFIG_LEDS_TCA6507 is not set | |
| +# CONFIG_LEDS_TLC591XX is not set | |
| +# CONFIG_LEDS_LM355x is not set | |
| + | |
| +# | |
| +# LED driver for blink(1) USB RGB LED is under Special HID drivers (HID_THINGM) | |
| +# | |
| +# CONFIG_LEDS_BLINKM is not set | |
| +# CONFIG_LEDS_SYSCON is not set | |
| + | |
| +# | |
| +# LED Triggers | |
| +# | |
| +CONFIG_LEDS_TRIGGERS=y | |
| +CONFIG_LEDS_TRIGGER_TIMER=y | |
| +# CONFIG_LEDS_TRIGGER_ONESHOT is not set | |
| +# CONFIG_LEDS_TRIGGER_HEARTBEAT is not set | |
| +# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set | |
| +# CONFIG_LEDS_TRIGGER_CPU is not set | |
| +CONFIG_LEDS_TRIGGER_GPIO=y | |
| +# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set | |
| + | |
| +# | |
| +# iptables trigger is under Netfilter config (LED target) | |
| +# | |
| +# CONFIG_LEDS_TRIGGER_TRANSIENT is not set | |
| +# CONFIG_LEDS_TRIGGER_CAMERA is not set | |
| +# CONFIG_ACCESSIBILITY is not set | |
| +# CONFIG_INFINIBAND is not set | |
| +CONFIG_EDAC_ATOMIC_SCRUB=y | |
| +CONFIG_EDAC_SUPPORT=y | |
| +CONFIG_EDAC=y | |
| +# CONFIG_EDAC_LEGACY_SYSFS is not set | |
| +# CONFIG_EDAC_DEBUG is not set | |
| +CONFIG_EDAC_MM_EDAC=y | |
| +CONFIG_RTC_LIB=y | |
| +CONFIG_RTC_CLASS=y | |
| +CONFIG_RTC_HCTOSYS=y | |
| +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" | |
| +CONFIG_RTC_SYSTOHC=y | |
| +CONFIG_RTC_SYSTOHC_DEVICE="rtc0" | |
| +# CONFIG_RTC_DEBUG is not set | |
| + | |
| +# | |
| +# RTC interfaces | |
| +# | |
| +CONFIG_RTC_INTF_SYSFS=y | |
| +CONFIG_RTC_INTF_PROC=y | |
| +CONFIG_RTC_INTF_DEV=y | |
| +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set | |
| +# CONFIG_RTC_DRV_TEST is not set | |
| + | |
| +# | |
| +# I2C RTC drivers | |
| +# | |
| +# CONFIG_RTC_DRV_ABB5ZES3 is not set | |
| +# CONFIG_RTC_DRV_ABX80X is not set | |
| +CONFIG_RTC_DRV_DS1307=y | |
| +# CONFIG_RTC_DRV_DS1374 is not set | |
| +# CONFIG_RTC_DRV_DS1672 is not set | |
| +# CONFIG_RTC_DRV_DS3232 is not set | |
| +# CONFIG_RTC_DRV_HYM8563 is not set | |
| +# CONFIG_RTC_DRV_MAX6900 is not set | |
| +# CONFIG_RTC_DRV_RS5C372 is not set | |
| +# CONFIG_RTC_DRV_ISL1208 is not set | |
| +# CONFIG_RTC_DRV_ISL12022 is not set | |
| +# CONFIG_RTC_DRV_ISL12057 is not set | |
| +# CONFIG_RTC_DRV_X1205 is not set | |
| +# CONFIG_RTC_DRV_PCF2127 is not set | |
| +# CONFIG_RTC_DRV_PCF8523 is not set | |
| +# CONFIG_RTC_DRV_PCF8563 is not set | |
| +# CONFIG_RTC_DRV_PCF85063 is not set | |
| +# CONFIG_RTC_DRV_PCF8583 is not set | |
| +# CONFIG_RTC_DRV_M41T80 is not set | |
| +# CONFIG_RTC_DRV_BQ32K is not set | |
| +# CONFIG_RTC_DRV_S35390A is not set | |
| +# CONFIG_RTC_DRV_FM3130 is not set | |
| +# CONFIG_RTC_DRV_RX8581 is not set | |
| +# CONFIG_RTC_DRV_RX8025 is not set | |
| +# CONFIG_RTC_DRV_EM3027 is not set | |
| +# CONFIG_RTC_DRV_RV3029C2 is not set | |
| +# CONFIG_RTC_DRV_RV8803 is not set | |
| + | |
| +# | |
| +# SPI RTC drivers | |
| +# | |
| + | |
| +# | |
| +# Platform RTC drivers | |
| +# | |
| +# CONFIG_RTC_DRV_CMOS is not set | |
| +# CONFIG_RTC_DRV_DS1286 is not set | |
| +# CONFIG_RTC_DRV_DS1511 is not set | |
| +# CONFIG_RTC_DRV_DS1553 is not set | |
| +# CONFIG_RTC_DRV_DS1685_FAMILY is not set | |
| +# CONFIG_RTC_DRV_DS1742 is not set | |
| +# CONFIG_RTC_DRV_DS2404 is not set | |
| +# CONFIG_RTC_DRV_STK17TA8 is not set | |
| +# CONFIG_RTC_DRV_M48T86 is not set | |
| +# CONFIG_RTC_DRV_M48T35 is not set | |
| +# CONFIG_RTC_DRV_M48T59 is not set | |
| +# CONFIG_RTC_DRV_MSM6242 is not set | |
| +# CONFIG_RTC_DRV_BQ4802 is not set | |
| +# CONFIG_RTC_DRV_RP5C01 is not set | |
| +# CONFIG_RTC_DRV_V3020 is not set | |
| +# CONFIG_RTC_DRV_ZYNQMP is not set | |
| + | |
| +# | |
| +# on-CPU RTC drivers | |
| +# | |
| +# CONFIG_RTC_DRV_PL030 is not set | |
| +# CONFIG_RTC_DRV_PL031 is not set | |
| +# CONFIG_RTC_DRV_SNVS is not set | |
| + | |
| +# | |
| +# HID Sensor RTC drivers | |
| +# | |
| +# CONFIG_RTC_DRV_HID_SENSOR_TIME is not set | |
| +CONFIG_DMADEVICES=y | |
| +# CONFIG_DMADEVICES_DEBUG is not set | |
| + | |
| +# | |
| +# DMA Devices | |
| +# | |
| +CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=y | |
| +CONFIG_DMA_ENGINE=y | |
| +CONFIG_DMA_OF=y | |
| +# CONFIG_AMBA_PL08X is not set | |
| +# CONFIG_FSL_EDMA is not set | |
| +# CONFIG_INTEL_IDMA64 is not set | |
| +# CONFIG_NBPFAXI_DMA is not set | |
| +# CONFIG_PL330_DMA is not set | |
| +# CONFIG_DW_DMAC is not set | |
| +# CONFIG_DW_DMAC_PCI is not set | |
| + | |
| +# | |
| +# DMA Clients | |
| +# | |
| +CONFIG_ASYNC_TX_DMA=y | |
| +# CONFIG_DMATEST is not set | |
| +CONFIG_DMA_ENGINE_RAID=y | |
| +CONFIG_AL_DMA=y | |
| +# CONFIG_AL_DMA_STATS is not set | |
| +CONFIG_AL_DMA_PCI_IOV=y | |
| +# CONFIG_AUXDISPLAY is not set | |
| +# CONFIG_UIO is not set | |
| +# CONFIG_VIRT_DRIVERS is not set | |
| + | |
| +# | |
| +# Virtio drivers | |
| +# | |
| +# CONFIG_VIRTIO_PCI is not set | |
| +# CONFIG_VIRTIO_MMIO is not set | |
| + | |
| +# | |
| +# Microsoft Hyper-V guest support | |
| +# | |
| +# CONFIG_STAGING is not set | |
| +# CONFIG_CHROME_PLATFORMS is not set | |
| +CONFIG_READYNAS_PLATFORMS=y | |
| +CONFIG_GPIO_PWR=y | |
| +CONFIG_HD44780_LCD=y | |
| +CONFIG_READYNAS_LCD=y | |
| +CONFIG_CLKDEV_LOOKUP=y | |
| +CONFIG_HAVE_CLK_PREPARE=y | |
| +CONFIG_COMMON_CLK=y | |
| + | |
| +# | |
| +# Common Clock Framework | |
| +# | |
| +# CONFIG_COMMON_CLK_SI5351 is not set | |
| +# CONFIG_COMMON_CLK_SI514 is not set | |
| +# CONFIG_COMMON_CLK_SI570 is not set | |
| +# CONFIG_COMMON_CLK_CDCE925 is not set | |
| +# CONFIG_CLK_QORIQ is not set | |
| +# CONFIG_COMMON_CLK_PXA is not set | |
| +# CONFIG_COMMON_CLK_CDCE706 is not set | |
| + | |
| +# | |
| +# Hardware Spinlock drivers | |
| +# | |
| + | |
| +# | |
| +# Clock Source drivers | |
| +# | |
| +CONFIG_CLKSRC_OF=y | |
| +CONFIG_CLKSRC_PROBE=y | |
| +CONFIG_CLKSRC_MMIO=y | |
| +CONFIG_ARM_ARCH_TIMER=y | |
| +CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y | |
| +# CONFIG_ARM_TIMER_SP804 is not set | |
| +# CONFIG_ATMEL_PIT is not set | |
| +# CONFIG_SH_TIMER_CMT is not set | |
| +# CONFIG_SH_TIMER_MTU2 is not set | |
| +# CONFIG_SH_TIMER_TMU is not set | |
| +# CONFIG_EM_TIMER_STI is not set | |
| +# CONFIG_MAILBOX is not set | |
| +# CONFIG_IOMMU_SUPPORT is not set | |
| + | |
| +# | |
| +# Remoteproc drivers | |
| +# | |
| +# CONFIG_STE_MODEM_RPROC is not set | |
| + | |
| +# | |
| +# Rpmsg drivers | |
| +# | |
| + | |
| +# | |
| +# SOC (System On Chip) specific Drivers | |
| +# | |
| +# CONFIG_SOC_BRCMSTB is not set | |
| +# CONFIG_SUNXI_SRAM is not set | |
| +# CONFIG_SOC_TI is not set | |
| +# CONFIG_PM_DEVFREQ is not set | |
| +# CONFIG_EXTCON is not set | |
| +# CONFIG_MEMORY is not set | |
| +# CONFIG_IIO is not set | |
| +# CONFIG_NTB is not set | |
| +# CONFIG_VME_BUS is not set | |
| +# CONFIG_PWM is not set | |
| +CONFIG_IRQCHIP=y | |
| +CONFIG_ARM_GIC=y | |
| +# CONFIG_IPACK_BUS is not set | |
| +# CONFIG_RESET_CONTROLLER is not set | |
| +# CONFIG_FMC is not set | |
| + | |
| +# | |
| +# PHY Subsystem | |
| +# | |
| +# CONFIG_GENERIC_PHY is not set | |
| +# CONFIG_PHY_PXA_28NM_HSIC is not set | |
| +# CONFIG_PHY_PXA_28NM_USB2 is not set | |
| +# CONFIG_BCM_KONA_USB2_PHY is not set | |
| +# CONFIG_POWERCAP is not set | |
| +# CONFIG_MCB is not set | |
| + | |
| +# | |
| +# Performance monitor support | |
| +# | |
| +CONFIG_RAS=y | |
| +# CONFIG_THUNDERBOLT is not set | |
| + | |
| +# | |
| +# Android | |
| +# | |
| +# CONFIG_ANDROID is not set | |
| +# CONFIG_LIBNVDIMM is not set | |
| +# CONFIG_NVMEM is not set | |
| +# CONFIG_STM is not set | |
| +# CONFIG_STM_DUMMY is not set | |
| +# CONFIG_STM_SOURCE_CONSOLE is not set | |
| +# CONFIG_INTEL_TH is not set | |
| + | |
| +# | |
| +# FPGA Configuration Support | |
| +# | |
| +# CONFIG_FPGA is not set | |
| + | |
| +# | |
| +# Firmware Drivers | |
| +# | |
| +# CONFIG_FIRMWARE_MEMMAP is not set | |
| + | |
| +# | |
| +# File systems | |
| +# | |
| +CONFIG_DCACHE_WORD_ACCESS=y | |
| +CONFIG_LFS_ON_32CPU=y | |
| +# CONFIG_EXT2_FS is not set | |
| +# CONFIG_EXT3_FS is not set | |
| +CONFIG_EXT4_FS=y | |
| +CONFIG_EXT4_USE_FOR_EXT2=y | |
| +CONFIG_EXT4_FS_POSIX_ACL=y | |
| +CONFIG_EXT4_FS_SECURITY=y | |
| +# CONFIG_EXT4_ENCRYPTION is not set | |
| +# CONFIG_EXT4_DEBUG is not set | |
| +CONFIG_JBD2=y | |
| +# CONFIG_JBD2_DEBUG is not set | |
| +CONFIG_FS_MBCACHE=y | |
| +# CONFIG_REISERFS_FS is not set | |
| +# CONFIG_JFS_FS is not set | |
| +CONFIG_XFS_FS=m | |
| +CONFIG_XFS_QUOTA=y | |
| +CONFIG_XFS_POSIX_ACL=y | |
| +CONFIG_XFS_RT=y | |
| +# CONFIG_XFS_WARN is not set | |
| +# CONFIG_XFS_DEBUG is not set | |
| +# CONFIG_GFS2_FS is not set | |
| +# CONFIG_OCFS2_FS is not set | |
| +CONFIG_BTRFS_FS=y | |
| +CONFIG_BTRFS_FS_POSIX_ACL=y | |
| +# CONFIG_BTRFS_FS_CHECK_INTEGRITY is not set | |
| +# CONFIG_BTRFS_FS_RUN_SANITY_TESTS is not set | |
| +# CONFIG_BTRFS_DEBUG is not set | |
| +# CONFIG_BTRFS_ASSERT is not set | |
| +CONFIG_BTRFS_MDCSREPAIR=y | |
| +CONFIG_BTRFS_FIEMAP_PHYSICAL=y | |
| +# CONFIG_NILFS2_FS is not set | |
| +# CONFIG_F2FS_FS is not set | |
| +CONFIG_FS_POSIX_ACL=y | |
| +CONFIG_EXPORTFS=y | |
| +CONFIG_FILE_LOCKING=y | |
| +CONFIG_FSNOTIFY=y | |
| +CONFIG_DNOTIFY=y | |
| +CONFIG_INOTIFY_USER=y | |
| +CONFIG_FANOTIFY=y | |
| +CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y | |
| +CONFIG_QUOTA=y | |
| +CONFIG_QUOTA_NETLINK_INTERFACE=y | |
| +# CONFIG_PRINT_QUOTA_WARNING is not set | |
| +# CONFIG_QUOTA_DEBUG is not set | |
| +CONFIG_QUOTA_TREE=y | |
| +# CONFIG_QFMT_V1 is not set | |
| +CONFIG_QFMT_V2=y | |
| +CONFIG_QUOTACTL=y | |
| +CONFIG_AUTOFS4_FS=y | |
| +CONFIG_FUSE_FS=y | |
| +# CONFIG_CUSE is not set | |
| +CONFIG_OVERLAY_FS=y | |
| + | |
| +# | |
| +# Caches | |
| +# | |
| +CONFIG_FSCACHE=y | |
| +# CONFIG_FSCACHE_STATS is not set | |
| +# CONFIG_FSCACHE_HISTOGRAM is not set | |
| +# CONFIG_FSCACHE_DEBUG is not set | |
| +# CONFIG_FSCACHE_OBJECT_LIST is not set | |
| +# CONFIG_CACHEFILES is not set | |
| + | |
| +# | |
| +# CD-ROM/DVD Filesystems | |
| +# | |
| +CONFIG_ISO9660_FS=m | |
| +CONFIG_JOLIET=y | |
| +# CONFIG_ZISOFS is not set | |
| +CONFIG_UDF_FS=m | |
| +CONFIG_UDF_NLS=y | |
| + | |
| +# | |
| +# DOS/FAT/NT Filesystems | |
| +# | |
| +CONFIG_FAT_FS=y | |
| +CONFIG_MSDOS_FS=y | |
| +CONFIG_VFAT_FS=y | |
| +CONFIG_FAT_DEFAULT_CODEPAGE=437 | |
| +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" | |
| +# CONFIG_NTFS_FS is not set | |
| + | |
| +# | |
| +# Pseudo filesystems | |
| +# | |
| +CONFIG_PROC_FS=y | |
| +CONFIG_PROC_SYSCTL=y | |
| +CONFIG_PROC_PAGE_MONITOR=y | |
| +# CONFIG_PROC_CHILDREN is not set | |
| +CONFIG_KERNFS=y | |
| +CONFIG_SYSFS=y | |
| +CONFIG_TMPFS=y | |
| +CONFIG_TMPFS_POSIX_ACL=y | |
| +CONFIG_TMPFS_XATTR=y | |
| +# CONFIG_HUGETLBFS is not set | |
| +# CONFIG_HUGETLB_PAGE is not set | |
| +CONFIG_CONFIGFS_FS=y | |
| +CONFIG_MISC_FILESYSTEMS=y | |
| +# CONFIG_ADFS_FS is not set | |
| +# CONFIG_AFFS_FS is not set | |
| +# CONFIG_ECRYPT_FS is not set | |
| +# CONFIG_HFS_FS is not set | |
| +# CONFIG_HFSPLUS_FS is not set | |
| +# CONFIG_BEFS_FS is not set | |
| +# CONFIG_BFS_FS is not set | |
| +# CONFIG_EFS_FS is not set | |
| +# CONFIG_JFFS2_FS is not set | |
| +CONFIG_UBIFS_FS=y | |
| +# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set | |
| +CONFIG_UBIFS_FS_LZO=y | |
| +CONFIG_UBIFS_FS_ZLIB=y | |
| +# CONFIG_UBIFS_ATIME_SUPPORT is not set | |
| +# CONFIG_LOGFS is not set | |
| +# CONFIG_CRAMFS is not set | |
| +# CONFIG_SQUASHFS is not set | |
| +# CONFIG_VXFS_FS is not set | |
| +# CONFIG_MINIX_FS is not set | |
| +# CONFIG_OMFS_FS is not set | |
| +# CONFIG_HPFS_FS is not set | |
| +# CONFIG_QNX4FS_FS is not set | |
| +# CONFIG_QNX6FS_FS is not set | |
| +# CONFIG_ROMFS_FS is not set | |
| +# CONFIG_PSTORE is not set | |
| +# CONFIG_SYSV_FS is not set | |
| +# CONFIG_UFS_FS is not set | |
| +CONFIG_NETWORK_FILESYSTEMS=y | |
| +CONFIG_NFS_FS=y | |
| +CONFIG_NFS_V2=y | |
| +CONFIG_NFS_V3=y | |
| +CONFIG_NFS_V3_ACL=y | |
| +CONFIG_NFS_V4=y | |
| +# CONFIG_NFS_SWAP is not set | |
| +# CONFIG_NFS_V4_1 is not set | |
| +# CONFIG_NFS_FSCACHE is not set | |
| +# CONFIG_NFS_USE_LEGACY_DNS is not set | |
| +CONFIG_NFS_USE_KERNEL_DNS=y | |
| +CONFIG_NFSD=y | |
| +CONFIG_NFSD_V2_ACL=y | |
| +CONFIG_NFSD_V3=y | |
| +CONFIG_NFSD_V3_ACL=y | |
| +CONFIG_NFSD_V4=y | |
| +# CONFIG_NFSD_PNFS is not set | |
| +CONFIG_NFSD_V4_SECURITY_LABEL=y | |
| +CONFIG_GRACE_PERIOD=y | |
| +CONFIG_LOCKD=y | |
| +CONFIG_LOCKD_V4=y | |
| +CONFIG_NFS_ACL_SUPPORT=y | |
| +CONFIG_NFS_COMMON=y | |
| +CONFIG_SUNRPC=y | |
| +CONFIG_SUNRPC_GSS=y | |
| +# CONFIG_SUNRPC_DEBUG is not set | |
| +# CONFIG_CEPH_FS is not set | |
| +CONFIG_CIFS=y | |
| +# CONFIG_CIFS_STATS is not set | |
| +CONFIG_CIFS_WEAK_PW_HASH=y | |
| +CONFIG_CIFS_UPCALL=y | |
| +CONFIG_CIFS_XATTR=y | |
| +CONFIG_CIFS_POSIX=y | |
| +CONFIG_CIFS_ACL=y | |
| +CONFIG_CIFS_DEBUG=y | |
| +# CONFIG_CIFS_DEBUG2 is not set | |
| +CONFIG_CIFS_DFS_UPCALL=y | |
| +CONFIG_CIFS_SMB2=y | |
| +# CONFIG_CIFS_SMB311 is not set | |
| +# CONFIG_CIFS_FSCACHE is not set | |
| +# CONFIG_NCP_FS is not set | |
| +# CONFIG_CODA_FS is not set | |
| +# CONFIG_AFS_FS is not set | |
| +CONFIG_NLS=y | |
| +CONFIG_NLS_DEFAULT="iso8859-1" | |
| +CONFIG_NLS_CODEPAGE_437=y | |
| +# CONFIG_NLS_CODEPAGE_737 is not set | |
| +# CONFIG_NLS_CODEPAGE_775 is not set | |
| +CONFIG_NLS_CODEPAGE_850=y | |
| +# CONFIG_NLS_CODEPAGE_852 is not set | |
| +# CONFIG_NLS_CODEPAGE_855 is not set | |
| +# CONFIG_NLS_CODEPAGE_857 is not set | |
| +# CONFIG_NLS_CODEPAGE_860 is not set | |
| +# CONFIG_NLS_CODEPAGE_861 is not set | |
| +# CONFIG_NLS_CODEPAGE_862 is not set | |
| +# CONFIG_NLS_CODEPAGE_863 is not set | |
| +# CONFIG_NLS_CODEPAGE_864 is not set | |
| +# CONFIG_NLS_CODEPAGE_865 is not set | |
| +# CONFIG_NLS_CODEPAGE_866 is not set | |
| +# CONFIG_NLS_CODEPAGE_869 is not set | |
| +# CONFIG_NLS_CODEPAGE_936 is not set | |
| +# CONFIG_NLS_CODEPAGE_950 is not set | |
| +# CONFIG_NLS_CODEPAGE_932 is not set | |
| +# CONFIG_NLS_CODEPAGE_949 is not set | |
| +# CONFIG_NLS_CODEPAGE_874 is not set | |
| +# CONFIG_NLS_ISO8859_8 is not set | |
| +# CONFIG_NLS_CODEPAGE_1250 is not set | |
| +# CONFIG_NLS_CODEPAGE_1251 is not set | |
| +# CONFIG_NLS_ASCII is not set | |
| +CONFIG_NLS_ISO8859_1=y | |
| +CONFIG_NLS_ISO8859_2=y | |
| +# CONFIG_NLS_ISO8859_3 is not set | |
| +# CONFIG_NLS_ISO8859_4 is not set | |
| +# CONFIG_NLS_ISO8859_5 is not set | |
| +# CONFIG_NLS_ISO8859_6 is not set | |
| +# CONFIG_NLS_ISO8859_7 is not set | |
| +# CONFIG_NLS_ISO8859_9 is not set | |
| +# CONFIG_NLS_ISO8859_13 is not set | |
| +# CONFIG_NLS_ISO8859_14 is not set | |
| +# CONFIG_NLS_ISO8859_15 is not set | |
| +# CONFIG_NLS_KOI8_R is not set | |
| +# CONFIG_NLS_KOI8_U is not set | |
| +# CONFIG_NLS_MAC_ROMAN is not set | |
| +# CONFIG_NLS_MAC_CELTIC is not set | |
| +# CONFIG_NLS_MAC_CENTEURO is not set | |
| +# CONFIG_NLS_MAC_CROATIAN is not set | |
| +# CONFIG_NLS_MAC_CYRILLIC is not set | |
| +# CONFIG_NLS_MAC_GAELIC is not set | |
| +# CONFIG_NLS_MAC_GREEK is not set | |
| +# CONFIG_NLS_MAC_ICELAND is not set | |
| +# CONFIG_NLS_MAC_INUIT is not set | |
| +# CONFIG_NLS_MAC_ROMANIAN is not set | |
| +# CONFIG_NLS_MAC_TURKISH is not set | |
| +CONFIG_NLS_UTF8=y | |
| +# CONFIG_DLM is not set | |
| + | |
| +# | |
| +# Kernel hacking | |
| +# | |
| + | |
| +# | |
| +# printk and dmesg options | |
| +# | |
| +CONFIG_PRINTK_TIME=y | |
| +CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 | |
| +# CONFIG_BOOT_PRINTK_DELAY is not set | |
| + | |
| +# | |
| +# Compile-time checks and compiler options | |
| +# | |
| +CONFIG_DEBUG_INFO=y | |
| +CONFIG_DEBUG_INFO_REDUCED=y | |
| +# CONFIG_DEBUG_INFO_SPLIT is not set | |
| +# CONFIG_DEBUG_INFO_DWARF4 is not set | |
| +# CONFIG_GDB_SCRIPTS is not set | |
| +CONFIG_ENABLE_WARN_DEPRECATED=y | |
| +CONFIG_ENABLE_MUST_CHECK=y | |
| +CONFIG_FRAME_WARN=1024 | |
| +# CONFIG_STRIP_ASM_SYMS is not set | |
| +# CONFIG_READABLE_ASM is not set | |
| +# CONFIG_UNUSED_SYMBOLS is not set | |
| +# CONFIG_PAGE_OWNER is not set | |
| +# CONFIG_DEBUG_FS is not set | |
| +# CONFIG_HEADERS_CHECK is not set | |
| +# CONFIG_DEBUG_SECTION_MISMATCH is not set | |
| +CONFIG_SECTION_MISMATCH_WARN_ONLY=y | |
| +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set | |
| +CONFIG_MAGIC_SYSRQ=y | |
| +CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1 | |
| +CONFIG_DEBUG_KERNEL=y | |
| + | |
| +# | |
| +# Memory Debugging | |
| +# | |
| +# CONFIG_PAGE_EXTENSION is not set | |
| +# CONFIG_DEBUG_PAGEALLOC is not set | |
| +# CONFIG_DEBUG_OBJECTS is not set | |
| +# CONFIG_SLUB_DEBUG_ON is not set | |
| +# CONFIG_SLUB_STATS is not set | |
| +CONFIG_HAVE_DEBUG_KMEMLEAK=y | |
| +# CONFIG_DEBUG_KMEMLEAK is not set | |
| +# CONFIG_DEBUG_STACK_USAGE is not set | |
| +# CONFIG_DEBUG_VM is not set | |
| +# CONFIG_DEBUG_MEMORY_INIT is not set | |
| +# CONFIG_DEBUG_PER_CPU_MAPS is not set | |
| +# CONFIG_DEBUG_HIGHMEM is not set | |
| +# CONFIG_DEBUG_SHIRQ is not set | |
| + | |
| +# | |
| +# Debug Lockups and Hangs | |
| +# | |
| +CONFIG_LOCKUP_DETECTOR=y | |
| +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set | |
| +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 | |
| +# CONFIG_DETECT_HUNG_TASK is not set | |
| +CONFIG_PANIC_ON_OOPS=y | |
| +CONFIG_PANIC_ON_OOPS_VALUE=1 | |
| +CONFIG_PANIC_TIMEOUT=0 | |
| +CONFIG_SCHED_DEBUG=y | |
| +CONFIG_SCHED_INFO=y | |
| +# CONFIG_SCHEDSTATS is not set | |
| +# CONFIG_SCHED_STACK_END_CHECK is not set | |
| +# CONFIG_DEBUG_TIMEKEEPING is not set | |
| +# CONFIG_TIMER_STATS is not set | |
| + | |
| +# | |
| +# Lock Debugging (spinlocks, mutexes, etc...) | |
| +# | |
| +# CONFIG_DEBUG_RT_MUTEXES is not set | |
| +# CONFIG_DEBUG_SPINLOCK is not set | |
| +# CONFIG_DEBUG_MUTEXES is not set | |
| +# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set | |
| +# CONFIG_DEBUG_LOCK_ALLOC is not set | |
| +# CONFIG_PROVE_LOCKING is not set | |
| +# CONFIG_LOCK_STAT is not set | |
| +# CONFIG_DEBUG_ATOMIC_SLEEP is not set | |
| +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set | |
| +# CONFIG_LOCK_TORTURE_TEST is not set | |
| +CONFIG_STACKTRACE=y | |
| +# CONFIG_DEBUG_KOBJECT is not set | |
| +CONFIG_DEBUG_BUGVERBOSE=y | |
| +# CONFIG_DEBUG_LIST is not set | |
| +# CONFIG_DEBUG_PI_LIST is not set | |
| +# CONFIG_DEBUG_SG is not set | |
| +# CONFIG_DEBUG_NOTIFIERS is not set | |
| +# CONFIG_DEBUG_CREDENTIALS is not set | |
| + | |
| +# | |
| +# RCU Debugging | |
| +# | |
| +# CONFIG_PROVE_RCU is not set | |
| +# CONFIG_SPARSE_RCU_POINTER is not set | |
| +# CONFIG_TORTURE_TEST is not set | |
| +# CONFIG_RCU_TORTURE_TEST is not set | |
| +CONFIG_RCU_CPU_STALL_TIMEOUT=21 | |
| +# CONFIG_RCU_TRACE is not set | |
| +# CONFIG_RCU_EQS_DEBUG is not set | |
| +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set | |
| +# CONFIG_NOTIFIER_ERROR_INJECTION is not set | |
| +# CONFIG_FAULT_INJECTION is not set | |
| +CONFIG_HAVE_FUNCTION_TRACER=y | |
| +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y | |
| +CONFIG_HAVE_DYNAMIC_FTRACE=y | |
| +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y | |
| +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y | |
| +CONFIG_HAVE_C_RECORDMCOUNT=y | |
| +CONFIG_TRACING_SUPPORT=y | |
| +# CONFIG_FTRACE is not set | |
| + | |
| +# | |
| +# Runtime Testing | |
| +# | |
| +# CONFIG_TEST_LIST_SORT is not set | |
| +# CONFIG_BACKTRACE_SELF_TEST is not set | |
| +# CONFIG_RBTREE_TEST is not set | |
| +# CONFIG_INTERVAL_TREE_TEST is not set | |
| +# CONFIG_PERCPU_TEST is not set | |
| +# CONFIG_ATOMIC64_SELFTEST is not set | |
| +# CONFIG_ASYNC_RAID6_TEST is not set | |
| +# CONFIG_TEST_HEXDUMP is not set | |
| +# CONFIG_TEST_STRING_HELPERS is not set | |
| +# CONFIG_TEST_KSTRTOX is not set | |
| +# CONFIG_TEST_PRINTF is not set | |
| +# CONFIG_TEST_RHASHTABLE is not set | |
| +# CONFIG_DMA_API_DEBUG is not set | |
| +# CONFIG_TEST_LKM is not set | |
| +# CONFIG_TEST_USER_COPY is not set | |
| +# CONFIG_TEST_BPF is not set | |
| +# CONFIG_TEST_FIRMWARE is not set | |
| +# CONFIG_TEST_UDELAY is not set | |
| +# CONFIG_MEMTEST is not set | |
| +# CONFIG_TEST_STATIC_KEYS is not set | |
| +# CONFIG_SAMPLES is not set | |
| +CONFIG_HAVE_ARCH_KGDB=y | |
| +# CONFIG_KGDB is not set | |
| +# CONFIG_ARM_PTDUMP is not set | |
| +# CONFIG_STRICT_DEVMEM is not set | |
| +CONFIG_ARM_UNWIND=y | |
| +CONFIG_DEBUG_USER=y | |
| +# CONFIG_DEBUG_LL is not set | |
| +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" | |
| +# CONFIG_DEBUG_UART_8250 is not set | |
| +CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" | |
| +# CONFIG_PID_IN_CONTEXTIDR is not set | |
| +# CONFIG_DEBUG_SET_MODULE_RONX is not set | |
| +# CONFIG_CORESIGHT is not set | |
| + | |
| +# | |
| +# Security options | |
| +# | |
| +CONFIG_KEYS=y | |
| +# CONFIG_PERSISTENT_KEYRINGS is not set | |
| +# CONFIG_BIG_KEYS is not set | |
| +# CONFIG_ENCRYPTED_KEYS is not set | |
| +# CONFIG_SECURITY_DMESG_RESTRICT is not set | |
| +CONFIG_SECURITY=y | |
| +# CONFIG_SECURITYFS is not set | |
| +# CONFIG_SECURITY_NETWORK is not set | |
| +# CONFIG_SECURITY_PATH is not set | |
| +# CONFIG_SECURITY_SMACK is not set | |
| +# CONFIG_SECURITY_TOMOYO is not set | |
| +# CONFIG_SECURITY_APPARMOR is not set | |
| +# CONFIG_SECURITY_YAMA is not set | |
| +# CONFIG_INTEGRITY is not set | |
| +CONFIG_DEFAULT_SECURITY_DAC=y | |
| +CONFIG_DEFAULT_SECURITY="" | |
| +CONFIG_XOR_BLOCKS=y | |
| +CONFIG_ASYNC_CORE=y | |
| +CONFIG_ASYNC_MEMCPY=y | |
| +CONFIG_ASYNC_XOR=y | |
| +CONFIG_ASYNC_PQ=y | |
| +CONFIG_ASYNC_RAID6_RECOV=y | |
| +CONFIG_CRYPTO=y | |
| + | |
| +# | |
| +# Crypto core or helper | |
| +# | |
| +CONFIG_CRYPTO_ALGAPI=y | |
| +CONFIG_CRYPTO_ALGAPI2=y | |
| +CONFIG_CRYPTO_AEAD=y | |
| +CONFIG_CRYPTO_AEAD2=y | |
| +CONFIG_CRYPTO_BLKCIPHER=y | |
| +CONFIG_CRYPTO_BLKCIPHER2=y | |
| +CONFIG_CRYPTO_HASH=y | |
| +CONFIG_CRYPTO_HASH2=y | |
| +CONFIG_CRYPTO_RNG=y | |
| +CONFIG_CRYPTO_RNG2=y | |
| +CONFIG_CRYPTO_RNG_DEFAULT=y | |
| +CONFIG_CRYPTO_PCOMP2=y | |
| +CONFIG_CRYPTO_AKCIPHER2=y | |
| +# CONFIG_CRYPTO_RSA is not set | |
| +CONFIG_CRYPTO_MANAGER=y | |
| +CONFIG_CRYPTO_MANAGER2=y | |
| +CONFIG_CRYPTO_USER=y | |
| +CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y | |
| +# CONFIG_CRYPTO_GF128MUL is not set | |
| +CONFIG_CRYPTO_NULL=y | |
| +CONFIG_CRYPTO_NULL2=y | |
| +# CONFIG_CRYPTO_PCRYPT is not set | |
| +CONFIG_CRYPTO_WORKQUEUE=y | |
| +# CONFIG_CRYPTO_CRYPTD is not set | |
| +# CONFIG_CRYPTO_MCRYPTD is not set | |
| +CONFIG_CRYPTO_AUTHENC=y | |
| +# CONFIG_CRYPTO_TEST is not set | |
| + | |
| +# | |
| +# Authenticated Encryption with Associated Data | |
| +# | |
| +CONFIG_CRYPTO_CCM=y | |
| +# CONFIG_CRYPTO_GCM is not set | |
| +# CONFIG_CRYPTO_CHACHA20POLY1305 is not set | |
| +CONFIG_CRYPTO_SEQIV=y | |
| +# CONFIG_CRYPTO_ECHAINIV is not set | |
| + | |
| +# | |
| +# Block modes | |
| +# | |
| +CONFIG_CRYPTO_CBC=y | |
| +CONFIG_CRYPTO_CTR=y | |
| +# CONFIG_CRYPTO_CTS is not set | |
| +CONFIG_CRYPTO_ECB=y | |
| +# CONFIG_CRYPTO_LRW is not set | |
| +# CONFIG_CRYPTO_PCBC is not set | |
| +# CONFIG_CRYPTO_XTS is not set | |
| +# CONFIG_CRYPTO_KEYWRAP is not set | |
| + | |
| +# | |
| +# Hash modes | |
| +# | |
| +CONFIG_CRYPTO_CMAC=y | |
| +CONFIG_CRYPTO_HMAC=y | |
| +# CONFIG_CRYPTO_XCBC is not set | |
| +# CONFIG_CRYPTO_VMAC is not set | |
| + | |
| +# | |
| +# Digest | |
| +# | |
| +CONFIG_CRYPTO_CRC32C=y | |
| +# CONFIG_CRYPTO_CRC32 is not set | |
| +CONFIG_CRYPTO_CRCT10DIF=y | |
| +# CONFIG_CRYPTO_GHASH is not set | |
| +# CONFIG_CRYPTO_POLY1305 is not set | |
| +CONFIG_CRYPTO_MD4=y | |
| +CONFIG_CRYPTO_MD5=y | |
| +# CONFIG_CRYPTO_MICHAEL_MIC is not set | |
| +# CONFIG_CRYPTO_RMD128 is not set | |
| +# CONFIG_CRYPTO_RMD160 is not set | |
| +# CONFIG_CRYPTO_RMD256 is not set | |
| +# CONFIG_CRYPTO_RMD320 is not set | |
| +CONFIG_CRYPTO_SHA1=y | |
| +CONFIG_CRYPTO_SHA256=y | |
| +CONFIG_CRYPTO_SHA512=y | |
| +# CONFIG_CRYPTO_TGR192 is not set | |
| +# CONFIG_CRYPTO_WP512 is not set | |
| + | |
| +# | |
| +# Ciphers | |
| +# | |
| +CONFIG_CRYPTO_AES=y | |
| +# CONFIG_CRYPTO_ANUBIS is not set | |
| +CONFIG_CRYPTO_ARC4=y | |
| +CONFIG_CRYPTO_BLOWFISH=y | |
| +CONFIG_CRYPTO_BLOWFISH_COMMON=y | |
| +# CONFIG_CRYPTO_CAMELLIA is not set | |
| +# CONFIG_CRYPTO_CAST5 is not set | |
| +# CONFIG_CRYPTO_CAST6 is not set | |
| +CONFIG_CRYPTO_DES=y | |
| +# CONFIG_CRYPTO_FCRYPT is not set | |
| +# CONFIG_CRYPTO_KHAZAD is not set | |
| +# CONFIG_CRYPTO_SALSA20 is not set | |
| +# CONFIG_CRYPTO_CHACHA20 is not set | |
| +# CONFIG_CRYPTO_SEED is not set | |
| +# CONFIG_CRYPTO_SERPENT is not set | |
| +# CONFIG_CRYPTO_TEA is not set | |
| +# CONFIG_CRYPTO_TWOFISH is not set | |
| + | |
| +# | |
| +# Compression | |
| +# | |
| +CONFIG_CRYPTO_DEFLATE=y | |
| +# CONFIG_CRYPTO_ZLIB is not set | |
| +CONFIG_CRYPTO_LZO=y | |
| +# CONFIG_CRYPTO_842 is not set | |
| +# CONFIG_CRYPTO_LZ4 is not set | |
| +# CONFIG_CRYPTO_LZ4HC is not set | |
| + | |
| +# | |
| +# Random Number Generation | |
| +# | |
| +# CONFIG_CRYPTO_ANSI_CPRNG is not set | |
| +CONFIG_CRYPTO_DRBG_MENU=y | |
| +CONFIG_CRYPTO_DRBG_HMAC=y | |
| +# CONFIG_CRYPTO_DRBG_HASH is not set | |
| +# CONFIG_CRYPTO_DRBG_CTR is not set | |
| +CONFIG_CRYPTO_DRBG=y | |
| +CONFIG_CRYPTO_JITTERENTROPY=y | |
| +CONFIG_CRYPTO_USER_API=y | |
| +CONFIG_CRYPTO_USER_API_HASH=y | |
| +CONFIG_CRYPTO_USER_API_SKCIPHER=y | |
| +# CONFIG_CRYPTO_USER_API_RNG is not set | |
| +# CONFIG_CRYPTO_USER_API_AEAD is not set | |
| +CONFIG_CRYPTO_HW=y | |
| +# CONFIG_CRYPTO_DEV_HIFN_795X is not set | |
| +CONFIG_CRYPTO_DEV_AL_CRYPTO=y | |
| +CONFIG_CRYPTO_DEV_AL_CRYPTO_STATS=y | |
| +CONFIG_CRYPTO_DEV_AL_AHASH_CRC=y | |
| +# CONFIG_ASYMMETRIC_KEY_TYPE is not set | |
| + | |
| +# | |
| +# Certificates for signature checking | |
| +# | |
| +# CONFIG_SYSTEM_TRUSTED_KEYRING is not set | |
| +CONFIG_ARM_CRYPTO=y | |
| +# CONFIG_CRYPTO_SHA1_ARM is not set | |
| +CONFIG_CRYPTO_SHA256_ARM=y | |
| +# CONFIG_CRYPTO_SHA512_ARM is not set | |
| +# CONFIG_CRYPTO_AES_ARM is not set | |
| +# CONFIG_BINARY_PRINTF is not set | |
| + | |
| +# | |
| +# Library routines | |
| +# | |
| +CONFIG_RAID6_PQ=y | |
| +CONFIG_BITREVERSE=y | |
| +CONFIG_HAVE_ARCH_BITREVERSE=y | |
| +CONFIG_RATIONAL=y | |
| +CONFIG_GENERIC_STRNCPY_FROM_USER=y | |
| +CONFIG_GENERIC_STRNLEN_USER=y | |
| +CONFIG_GENERIC_NET_UTILS=y | |
| +CONFIG_GENERIC_PCI_IOMAP=y | |
| +CONFIG_GENERIC_IO=y | |
| +CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y | |
| +# CONFIG_CRC_CCITT is not set | |
| +CONFIG_CRC16=y | |
| +CONFIG_CRC_T10DIF=y | |
| +CONFIG_CRC_ITU_T=y | |
| +CONFIG_CRC32=y | |
| +# CONFIG_CRC32_SELFTEST is not set | |
| +CONFIG_CRC32_SLICEBY8=y | |
| +# CONFIG_CRC32_SLICEBY4 is not set | |
| +# CONFIG_CRC32_SARWATE is not set | |
| +# CONFIG_CRC32_BIT is not set | |
| +# CONFIG_CRC7 is not set | |
| +CONFIG_LIBCRC32C=y | |
| +# CONFIG_CRC8 is not set | |
| +# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set | |
| +# CONFIG_RANDOM32_SELFTEST is not set | |
| +CONFIG_ZLIB_INFLATE=y | |
| +CONFIG_ZLIB_DEFLATE=y | |
| +CONFIG_LZO_COMPRESS=y | |
| +CONFIG_LZO_DECOMPRESS=y | |
| +CONFIG_XZ_DEC=y | |
| +CONFIG_XZ_DEC_X86=y | |
| +CONFIG_XZ_DEC_POWERPC=y | |
| +CONFIG_XZ_DEC_IA64=y | |
| +CONFIG_XZ_DEC_ARM=y | |
| +CONFIG_XZ_DEC_ARMTHUMB=y | |
| +CONFIG_XZ_DEC_SPARC=y | |
| +CONFIG_XZ_DEC_BCJ=y | |
| +# CONFIG_XZ_DEC_TEST is not set | |
| +CONFIG_DECOMPRESS_GZIP=y | |
| +CONFIG_DECOMPRESS_LZMA=y | |
| +CONFIG_DECOMPRESS_XZ=y | |
| +CONFIG_GENERIC_ALLOCATOR=y | |
| +CONFIG_ASSOCIATIVE_ARRAY=y | |
| +CONFIG_HAS_IOMEM=y | |
| +CONFIG_HAS_IOPORT_MAP=y | |
| +CONFIG_HAS_DMA=y | |
| +CONFIG_CPU_RMAP=y | |
| +CONFIG_DQL=y | |
| +CONFIG_GLOB=y | |
| +# CONFIG_GLOB_SELFTEST is not set | |
| +CONFIG_NLATTR=y | |
| +CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y | |
| +# CONFIG_CORDIC is not set | |
| +# CONFIG_DDR is not set | |
| +CONFIG_LIBFDT=y | |
| +CONFIG_OID_REGISTRY=y | |
| +# CONFIG_SG_SPLIT is not set | |
| +CONFIG_ARCH_HAS_SG_CHAIN=y | |
| +# CONFIG_VIRTUALIZATION is not set | |
| diff -x .git -Naur linux-4.4.111/arch/arm/configs/readynas_defconfig linux-4.4.111-alpine/arch/arm/configs/readynas_defconfig | |
| --- linux-4.4.111/arch/arm/configs/readynas_defconfig 1969-12-31 19:00:00.000000000 -0500 | |
| +++ linux-4.4.111-alpine/arch/arm/configs/readynas_defconfig 2018-02-14 21:04:17.000000000 -0500 | |
| @@ -0,0 +1,3437 @@ | |
| +# | |
| +# Automatically generated file; DO NOT EDIT. | |
| +# Linux/arm 4.4.111 Kernel Configuration | |
| +# | |
| +CONFIG_ARM=y | |
| +CONFIG_ARM_HAS_SG_CHAIN=y | |
| +CONFIG_MIGHT_HAVE_PCI=y | |
| +CONFIG_SYS_SUPPORTS_APM_EMULATION=y | |
| +CONFIG_HAVE_PROC_CPU=y | |
| +CONFIG_STACKTRACE_SUPPORT=y | |
| +CONFIG_LOCKDEP_SUPPORT=y | |
| +CONFIG_TRACE_IRQFLAGS_SUPPORT=y | |
| +CONFIG_RWSEM_XCHGADD_ALGORITHM=y | |
| +CONFIG_FIX_EARLYCON_MEM=y | |
| +CONFIG_GENERIC_HWEIGHT=y | |
| +CONFIG_GENERIC_CALIBRATE_DELAY=y | |
| +CONFIG_NEED_DMA_MAP_STATE=y | |
| +CONFIG_ARCH_SUPPORTS_UPROBES=y | |
| +CONFIG_VECTORS_BASE=0xffff0000 | |
| +CONFIG_ARM_PATCH_PHYS_VIRT=y | |
| +CONFIG_GENERIC_BUG=y | |
| +CONFIG_PGTABLE_LEVELS=3 | |
| +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" | |
| +CONFIG_IRQ_WORK=y | |
| +CONFIG_BUILDTIME_EXTABLE_SORT=y | |
| + | |
| +# | |
| +# General setup | |
| +# | |
| +CONFIG_INIT_ENV_ARG_LIMIT=32 | |
| +CONFIG_CROSS_COMPILE="arm-linux-gnueabihf-" | |
| +# CONFIG_COMPILE_TEST is not set | |
| +CONFIG_LOCALVERSION=".alpine.1" | |
| +CONFIG_LOCALVERSION_AUTO=y | |
| +CONFIG_HAVE_KERNEL_GZIP=y | |
| +CONFIG_HAVE_KERNEL_LZMA=y | |
| +CONFIG_HAVE_KERNEL_XZ=y | |
| +CONFIG_HAVE_KERNEL_LZO=y | |
| +CONFIG_HAVE_KERNEL_LZ4=y | |
| +# CONFIG_KERNEL_GZIP is not set | |
| +# CONFIG_KERNEL_LZMA is not set | |
| +CONFIG_KERNEL_XZ=y | |
| +# CONFIG_KERNEL_LZO is not set | |
| +# CONFIG_KERNEL_LZ4 is not set | |
| +CONFIG_DEFAULT_HOSTNAME="readynasos" | |
| +CONFIG_SWAP=y | |
| +CONFIG_SYSVIPC=y | |
| +CONFIG_SYSVIPC_SYSCTL=y | |
| +CONFIG_POSIX_MQUEUE=y | |
| +CONFIG_POSIX_MQUEUE_SYSCTL=y | |
| +CONFIG_CROSS_MEMORY_ATTACH=y | |
| +CONFIG_FHANDLE=y | |
| +CONFIG_USELIB=y | |
| +# CONFIG_AUDIT is not set | |
| +CONFIG_HAVE_ARCH_AUDITSYSCALL=y | |
| + | |
| +# | |
| +# IRQ subsystem | |
| +# | |
| +CONFIG_GENERIC_IRQ_PROBE=y | |
| +CONFIG_GENERIC_IRQ_SHOW=y | |
| +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y | |
| +CONFIG_HARDIRQS_SW_RESEND=y | |
| +CONFIG_GENERIC_IRQ_CHIP=y | |
| +CONFIG_IRQ_DOMAIN=y | |
| +CONFIG_IRQ_DOMAIN_HIERARCHY=y | |
| +CONFIG_GENERIC_MSI_IRQ=y | |
| +CONFIG_GENERIC_MSI_IRQ_DOMAIN=y | |
| +CONFIG_HANDLE_DOMAIN_IRQ=y | |
| +CONFIG_IRQ_FORCED_THREADING=y | |
| +CONFIG_SPARSE_IRQ=y | |
| +CONFIG_GENERIC_TIME_VSYSCALL=y | |
| +CONFIG_GENERIC_CLOCKEVENTS=y | |
| +CONFIG_ARCH_HAS_TICK_BROADCAST=y | |
| +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y | |
| + | |
| +# | |
| +# Timers subsystem | |
| +# | |
| +CONFIG_TICK_ONESHOT=y | |
| +CONFIG_NO_HZ_COMMON=y | |
| +# CONFIG_HZ_PERIODIC is not set | |
| +CONFIG_NO_HZ_IDLE=y | |
| +# CONFIG_NO_HZ_FULL is not set | |
| +CONFIG_NO_HZ=y | |
| +# CONFIG_HIGH_RES_TIMERS is not set | |
| + | |
| +# | |
| +# CPU/Task time and stats accounting | |
| +# | |
| +CONFIG_TICK_CPU_ACCOUNTING=y | |
| +# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set | |
| +# CONFIG_IRQ_TIME_ACCOUNTING is not set | |
| +CONFIG_BSD_PROCESS_ACCT=y | |
| +# CONFIG_BSD_PROCESS_ACCT_V3 is not set | |
| +CONFIG_TASKSTATS=y | |
| +CONFIG_TASK_DELAY_ACCT=y | |
| +CONFIG_TASK_XACCT=y | |
| +CONFIG_TASK_IO_ACCOUNTING=y | |
| + | |
| +# | |
| +# RCU Subsystem | |
| +# | |
| +CONFIG_TREE_RCU=y | |
| +# CONFIG_RCU_EXPERT is not set | |
| +CONFIG_SRCU=y | |
| +# CONFIG_TASKS_RCU is not set | |
| +CONFIG_RCU_STALL_COMMON=y | |
| +# CONFIG_TREE_RCU_TRACE is not set | |
| +# CONFIG_RCU_EXPEDITE_BOOT is not set | |
| +CONFIG_BUILD_BIN2C=y | |
| +CONFIG_IKCONFIG=m | |
| +CONFIG_IKCONFIG_PROC=y | |
| +CONFIG_LOG_BUF_SHIFT=17 | |
| +CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 | |
| +CONFIG_GENERIC_SCHED_CLOCK=y | |
| +CONFIG_CGROUPS=y | |
| +# CONFIG_CGROUP_DEBUG is not set | |
| +CONFIG_CGROUP_FREEZER=y | |
| +# CONFIG_CGROUP_PIDS is not set | |
| +CONFIG_CGROUP_DEVICE=y | |
| +CONFIG_CPUSETS=y | |
| +# CONFIG_PROC_PID_CPUSET is not set | |
| +CONFIG_CGROUP_CPUACCT=y | |
| +# CONFIG_MEMCG is not set | |
| +CONFIG_CGROUP_SCHED=y | |
| +CONFIG_FAIR_GROUP_SCHED=y | |
| +CONFIG_CFS_BANDWIDTH=y | |
| +CONFIG_RT_GROUP_SCHED=y | |
| +CONFIG_BLK_CGROUP=y | |
| +# CONFIG_DEBUG_BLK_CGROUP is not set | |
| +# CONFIG_CHECKPOINT_RESTORE is not set | |
| +CONFIG_NAMESPACES=y | |
| +CONFIG_UTS_NS=y | |
| +CONFIG_IPC_NS=y | |
| +CONFIG_USER_NS=y | |
| +CONFIG_PID_NS=y | |
| +CONFIG_NET_NS=y | |
| +# CONFIG_SCHED_AUTOGROUP is not set | |
| +# CONFIG_SYSFS_DEPRECATED is not set | |
| +# CONFIG_RELAY is not set | |
| +CONFIG_BLK_DEV_INITRD=y | |
| +CONFIG_INITRAMFS_SOURCE="" | |
| +CONFIG_RD_GZIP=y | |
| +# CONFIG_RD_BZIP2 is not set | |
| +CONFIG_RD_LZMA=y | |
| +CONFIG_RD_XZ=y | |
| +# CONFIG_RD_LZO is not set | |
| +# CONFIG_RD_LZ4 is not set | |
| +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set | |
| +CONFIG_SYSCTL=y | |
| +CONFIG_ANON_INODES=y | |
| +CONFIG_HAVE_UID16=y | |
| +CONFIG_BPF=y | |
| +CONFIG_EXPERT=y | |
| +CONFIG_UID16=y | |
| +CONFIG_MULTIUSER=y | |
| +CONFIG_SGETMASK_SYSCALL=y | |
| +CONFIG_SYSFS_SYSCALL=y | |
| +CONFIG_SYSCTL_SYSCALL=y | |
| +CONFIG_KALLSYMS=y | |
| +# CONFIG_KALLSYMS_ALL is not set | |
| +CONFIG_PRINTK=y | |
| +CONFIG_BUG=y | |
| +CONFIG_ELF_CORE=y | |
| +CONFIG_BASE_FULL=y | |
| +CONFIG_FUTEX=y | |
| +CONFIG_EPOLL=y | |
| +CONFIG_SIGNALFD=y | |
| +CONFIG_TIMERFD=y | |
| +CONFIG_EVENTFD=y | |
| +# CONFIG_BPF_SYSCALL is not set | |
| +CONFIG_SHMEM=y | |
| +CONFIG_AIO=y | |
| +CONFIG_ADVISE_SYSCALLS=y | |
| +# CONFIG_USERFAULTFD is not set | |
| +CONFIG_PCI_QUIRKS=y | |
| +CONFIG_MEMBARRIER=y | |
| +CONFIG_EMBEDDED=y | |
| +CONFIG_HAVE_PERF_EVENTS=y | |
| +CONFIG_PERF_USE_VMALLOC=y | |
| + | |
| +# | |
| +# Kernel Performance Events And Counters | |
| +# | |
| +# CONFIG_PERF_EVENTS is not set | |
| +CONFIG_VM_EVENT_COUNTERS=y | |
| +CONFIG_SLUB_DEBUG=y | |
| +# CONFIG_COMPAT_BRK is not set | |
| +# CONFIG_SLAB is not set | |
| +CONFIG_SLUB=y | |
| +# CONFIG_SLOB is not set | |
| +CONFIG_SLUB_CPU_PARTIAL=y | |
| +# CONFIG_SYSTEM_DATA_VERIFICATION is not set | |
| +# CONFIG_PROFILING is not set | |
| +CONFIG_HAVE_OPROFILE=y | |
| +# CONFIG_KPROBES is not set | |
| +CONFIG_JUMP_LABEL=y | |
| +# CONFIG_STATIC_KEYS_SELFTEST is not set | |
| +# CONFIG_UPROBES is not set | |
| +# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set | |
| +CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y | |
| +CONFIG_ARCH_USE_BUILTIN_BSWAP=y | |
| +CONFIG_HAVE_KPROBES=y | |
| +CONFIG_HAVE_KRETPROBES=y | |
| +CONFIG_HAVE_OPTPROBES=y | |
| +CONFIG_HAVE_ARCH_TRACEHOOK=y | |
| +CONFIG_HAVE_DMA_ATTRS=y | |
| +CONFIG_HAVE_DMA_CONTIGUOUS=y | |
| +CONFIG_GENERIC_SMP_IDLE_THREAD=y | |
| +CONFIG_GENERIC_IDLE_POLL_SETUP=y | |
| +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y | |
| +CONFIG_HAVE_CLK=y | |
| +CONFIG_HAVE_DMA_API_DEBUG=y | |
| +CONFIG_HAVE_PERF_REGS=y | |
| +CONFIG_HAVE_PERF_USER_STACK_DUMP=y | |
| +CONFIG_HAVE_ARCH_JUMP_LABEL=y | |
| +CONFIG_HAVE_RCU_TABLE_FREE=y | |
| +CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y | |
| +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y | |
| +CONFIG_SECCOMP_FILTER=y | |
| +CONFIG_HAVE_CC_STACKPROTECTOR=y | |
| +# CONFIG_CC_STACKPROTECTOR is not set | |
| +CONFIG_CC_STACKPROTECTOR_NONE=y | |
| +# CONFIG_CC_STACKPROTECTOR_REGULAR is not set | |
| +# CONFIG_CC_STACKPROTECTOR_STRONG is not set | |
| +CONFIG_HAVE_CONTEXT_TRACKING=y | |
| +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y | |
| +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y | |
| +CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y | |
| +CONFIG_HAVE_MOD_ARCH_SPECIFIC=y | |
| +CONFIG_MODULES_USE_ELF_REL=y | |
| +CONFIG_ARCH_HAS_ELF_RANDOMIZE=y | |
| +CONFIG_CLONE_BACKWARDS=y | |
| +CONFIG_OLD_SIGSUSPEND3=y | |
| +CONFIG_OLD_SIGACTION=y | |
| + | |
| +# | |
| +# GCOV-based kernel profiling | |
| +# | |
| +CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y | |
| +CONFIG_HAVE_GENERIC_DMA_COHERENT=y | |
| +CONFIG_SLABINFO=y | |
| +CONFIG_RT_MUTEXES=y | |
| +CONFIG_BASE_SMALL=0 | |
| +CONFIG_MODULES=y | |
| +# CONFIG_MODULE_FORCE_LOAD is not set | |
| +CONFIG_MODULE_UNLOAD=y | |
| +# CONFIG_MODULE_FORCE_UNLOAD is not set | |
| +CONFIG_MODVERSIONS=y | |
| +# CONFIG_MODULE_SRCVERSION_ALL is not set | |
| +# CONFIG_MODULE_SIG is not set | |
| +# CONFIG_MODULE_COMPRESS is not set | |
| +CONFIG_BLOCK=y | |
| +CONFIG_LBDAF=y | |
| +CONFIG_BLK_DEV_BSG=y | |
| +CONFIG_BLK_DEV_BSGLIB=y | |
| +# CONFIG_BLK_DEV_INTEGRITY is not set | |
| +# CONFIG_BLK_DEV_THROTTLING is not set | |
| +# CONFIG_BLK_CMDLINE_PARSER is not set | |
| + | |
| +# | |
| +# Partition Types | |
| +# | |
| +CONFIG_PARTITION_ADVANCED=y | |
| +# CONFIG_ACORN_PARTITION is not set | |
| +# CONFIG_AIX_PARTITION is not set | |
| +# CONFIG_OSF_PARTITION is not set | |
| +# CONFIG_AMIGA_PARTITION is not set | |
| +# CONFIG_ATARI_PARTITION is not set | |
| +# CONFIG_MAC_PARTITION is not set | |
| +CONFIG_MSDOS_PARTITION=y | |
| +CONFIG_BSD_DISKLABEL=y | |
| +# CONFIG_MINIX_SUBPARTITION is not set | |
| +CONFIG_SOLARIS_X86_PARTITION=y | |
| +CONFIG_UNIXWARE_DISKLABEL=y | |
| +CONFIG_LDM_PARTITION=y | |
| +# CONFIG_LDM_DEBUG is not set | |
| +# CONFIG_SGI_PARTITION is not set | |
| +# CONFIG_ULTRIX_PARTITION is not set | |
| +# CONFIG_SUN_PARTITION is not set | |
| +# CONFIG_KARMA_PARTITION is not set | |
| +CONFIG_EFI_PARTITION=y | |
| +# CONFIG_SYSV68_PARTITION is not set | |
| +# CONFIG_CMDLINE_PARTITION is not set | |
| + | |
| +# | |
| +# IO Schedulers | |
| +# | |
| +CONFIG_IOSCHED_NOOP=y | |
| +CONFIG_IOSCHED_DEADLINE=y | |
| +CONFIG_IOSCHED_CFQ=y | |
| +# CONFIG_CFQ_GROUP_IOSCHED is not set | |
| +CONFIG_IOSCHED_BFQ=y | |
| +CONFIG_BFQ_GROUP_IOSCHED=y | |
| +# CONFIG_DEFAULT_DEADLINE is not set | |
| +CONFIG_DEFAULT_CFQ=y | |
| +# CONFIG_DEFAULT_BFQ is not set | |
| +# CONFIG_DEFAULT_NOOP is not set | |
| +CONFIG_DEFAULT_IOSCHED="cfq" | |
| +CONFIG_INLINE_SPIN_UNLOCK_IRQ=y | |
| +CONFIG_INLINE_READ_UNLOCK=y | |
| +CONFIG_INLINE_READ_UNLOCK_IRQ=y | |
| +CONFIG_INLINE_WRITE_UNLOCK=y | |
| +CONFIG_INLINE_WRITE_UNLOCK_IRQ=y | |
| +CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y | |
| +CONFIG_MUTEX_SPIN_ON_OWNER=y | |
| +CONFIG_RWSEM_SPIN_ON_OWNER=y | |
| +CONFIG_LOCK_SPIN_ON_OWNER=y | |
| +CONFIG_FREEZER=y | |
| + | |
| +# | |
| +# System Type | |
| +# | |
| +CONFIG_MMU=y | |
| +CONFIG_ARCH_MULTIPLATFORM=y | |
| +# CONFIG_ARCH_REALVIEW is not set | |
| +# CONFIG_ARCH_VERSATILE is not set | |
| +# CONFIG_ARCH_CLPS711X is not set | |
| +# CONFIG_ARCH_GEMINI is not set | |
| +# CONFIG_ARCH_EBSA110 is not set | |
| +# CONFIG_ARCH_EP93XX is not set | |
| +# CONFIG_ARCH_FOOTBRIDGE is not set | |
| +# CONFIG_ARCH_NETX is not set | |
| +# CONFIG_ARCH_IOP13XX is not set | |
| +# CONFIG_ARCH_IOP32X is not set | |
| +# CONFIG_ARCH_IOP33X is not set | |
| +# CONFIG_ARCH_IXP4XX is not set | |
| +# CONFIG_ARCH_DOVE is not set | |
| +# CONFIG_ARCH_MV78XX0 is not set | |
| +# CONFIG_ARCH_ORION5X is not set | |
| +# CONFIG_ARCH_MMP is not set | |
| +# CONFIG_ARCH_KS8695 is not set | |
| +# CONFIG_ARCH_W90X900 is not set | |
| +# CONFIG_ARCH_LPC32XX is not set | |
| +# CONFIG_ARCH_PXA is not set | |
| +# CONFIG_ARCH_RPC is not set | |
| +# CONFIG_ARCH_SA1100 is not set | |
| +# CONFIG_ARCH_S3C24XX is not set | |
| +# CONFIG_ARCH_S3C64XX is not set | |
| +# CONFIG_ARCH_DAVINCI is not set | |
| +# CONFIG_ARCH_OMAP1 is not set | |
| + | |
| +# | |
| +# Multiple platform selection | |
| +# | |
| + | |
| +# | |
| +# CPU Core family selection | |
| +# | |
| +# CONFIG_ARCH_MULTI_V6 is not set | |
| +CONFIG_ARCH_MULTI_V7=y | |
| +CONFIG_ARCH_MULTI_V6_V7=y | |
| +# CONFIG_ARCH_MULTI_CPU_AUTO is not set | |
| +# CONFIG_ARCH_VIRT is not set | |
| +# CONFIG_ARCH_MVEBU is not set | |
| +CONFIG_ARCH_ALPINE=y | |
| +# CONFIG_ARCH_AT91 is not set | |
| +# CONFIG_ARCH_AXXIA is not set | |
| +# CONFIG_ARCH_BCM is not set | |
| +# CONFIG_ARCH_BERLIN is not set | |
| +# CONFIG_ARCH_DIGICOLOR is not set | |
| +# CONFIG_ARCH_HIGHBANK is not set | |
| +# CONFIG_ARCH_HISI is not set | |
| +# CONFIG_ARCH_KEYSTONE is not set | |
| +# CONFIG_ARCH_MESON is not set | |
| +# CONFIG_ARCH_MXC is not set | |
| +# CONFIG_ARCH_MEDIATEK is not set | |
| + | |
| +# | |
| +# TI OMAP/AM/DM/DRA Family | |
| +# | |
| +# CONFIG_ARCH_OMAP3 is not set | |
| +# CONFIG_ARCH_OMAP4 is not set | |
| +# CONFIG_SOC_OMAP5 is not set | |
| +# CONFIG_SOC_AM33XX is not set | |
| +# CONFIG_SOC_AM43XX is not set | |
| +# CONFIG_SOC_DRA7XX is not set | |
| +# CONFIG_ARCH_QCOM is not set | |
| +# CONFIG_ARCH_ROCKCHIP is not set | |
| +# CONFIG_ARCH_SOCFPGA is not set | |
| +# CONFIG_PLAT_SPEAR is not set | |
| +# CONFIG_ARCH_STI is not set | |
| +# CONFIG_ARCH_S5PV210 is not set | |
| +# CONFIG_ARCH_EXYNOS is not set | |
| +# CONFIG_ARCH_SHMOBILE_MULTI is not set | |
| +# CONFIG_ARCH_SUNXI is not set | |
| +# CONFIG_ARCH_SIRF is not set | |
| +# CONFIG_ARCH_TEGRA is not set | |
| +# CONFIG_ARCH_UNIPHIER is not set | |
| +# CONFIG_ARCH_U8500 is not set | |
| +# CONFIG_ARCH_VEXPRESS is not set | |
| +# CONFIG_ARCH_WM8850 is not set | |
| +# CONFIG_ARCH_ZX is not set | |
| +# CONFIG_ARCH_ZYNQ is not set | |
| + | |
| +# | |
| +# Processor Type | |
| +# | |
| +CONFIG_CPU_V7=y | |
| +CONFIG_CPU_32v6K=y | |
| +CONFIG_CPU_32v7=y | |
| +CONFIG_CPU_ABRT_EV7=y | |
| +CONFIG_CPU_PABRT_V7=y | |
| +CONFIG_CPU_CACHE_V7=y | |
| +CONFIG_CPU_CACHE_VIPT=y | |
| +CONFIG_CPU_COPY_V6=y | |
| +CONFIG_CPU_TLB_V7=y | |
| +CONFIG_CPU_HAS_ASID=y | |
| +CONFIG_CPU_CP15=y | |
| +CONFIG_CPU_CP15_MMU=y | |
| + | |
| +# | |
| +# Processor Features | |
| +# | |
| +CONFIG_ARM_LPAE=y | |
| +CONFIG_ARCH_PHYS_ADDR_T_64BIT=y | |
| +CONFIG_ARM_THUMB=y | |
| +# CONFIG_ARM_THUMBEE is not set | |
| +CONFIG_ARM_VIRT_EXT=y | |
| +CONFIG_SWP_EMULATE=y | |
| +# CONFIG_CPU_ICACHE_DISABLE is not set | |
| +# CONFIG_CPU_BPREDICT_DISABLE is not set | |
| +CONFIG_KUSER_HELPERS=y | |
| +CONFIG_VDSO=y | |
| +CONFIG_MIGHT_HAVE_CACHE_L2X0=y | |
| +# CONFIG_CACHE_L2X0 is not set | |
| +CONFIG_ARM_L1_CACHE_SHIFT_6=y | |
| +CONFIG_ARM_L1_CACHE_SHIFT=6 | |
| +CONFIG_ARM_DMA_MEM_BUFFERABLE=y | |
| +# CONFIG_ARM_KERNMEM_PERMS is not set | |
| +CONFIG_MULTI_IRQ_HANDLER=y | |
| +# CONFIG_ARM_ERRATA_430973 is not set | |
| +# CONFIG_ARM_ERRATA_643719 is not set | |
| +CONFIG_ARM_ERRATA_720789=y | |
| +# CONFIG_ARM_ERRATA_754322 is not set | |
| +# CONFIG_ARM_ERRATA_754327 is not set | |
| +# CONFIG_ARM_ERRATA_764369 is not set | |
| +# CONFIG_ARM_ERRATA_775420 is not set | |
| +# CONFIG_ARM_ERRATA_798181 is not set | |
| +# CONFIG_ARM_ERRATA_773022 is not set | |
| + | |
| +# | |
| +# Bus support | |
| +# | |
| +CONFIG_PCI=y | |
| +CONFIG_PCI_DOMAINS=y | |
| +CONFIG_PCI_DOMAINS_GENERIC=y | |
| +CONFIG_PCI_SYSCALL=y | |
| +CONFIG_PCI_MSI=y | |
| +CONFIG_PCI_MSI_IRQ_DOMAIN=y | |
| +# CONFIG_PCI_DEBUG is not set | |
| +# CONFIG_PCI_REALLOC_ENABLE_AUTO is not set | |
| +# CONFIG_PCI_STUB is not set | |
| +CONFIG_PCI_ATS=y | |
| +CONFIG_PCI_IOV=y | |
| +# CONFIG_PCI_PRI is not set | |
| +# CONFIG_PCI_PASID is not set | |
| + | |
| +# | |
| +# PCI host controller drivers | |
| +# | |
| +CONFIG_PCI_INTERNAL_ALPINE=y | |
| +CONFIG_PCI_EXTERNAL_ALPINE=y | |
| +# CONFIG_PCI_HOST_GENERIC is not set | |
| +# CONFIG_PCI_LAYERSCAPE is not set | |
| +# CONFIG_PCIE_IPROC is not set | |
| +# CONFIG_PCIE_ALTERA is not set | |
| +# CONFIG_PCIEPORTBUS is not set | |
| +# CONFIG_PCCARD is not set | |
| + | |
| +# | |
| +# Kernel Features | |
| +# | |
| +CONFIG_HAVE_SMP=y | |
| +CONFIG_SMP=y | |
| +# CONFIG_SMP_ON_UP is not set | |
| +CONFIG_ARM_CPU_TOPOLOGY=y | |
| +# CONFIG_SCHED_MC is not set | |
| +# CONFIG_SCHED_SMT is not set | |
| +CONFIG_HAVE_ARM_ARCH_TIMER=y | |
| +# CONFIG_MCPM is not set | |
| +# CONFIG_BIG_LITTLE is not set | |
| +CONFIG_VMSPLIT_3G=y | |
| +# CONFIG_VMSPLIT_3G_OPT is not set | |
| +# CONFIG_VMSPLIT_2G is not set | |
| +# CONFIG_VMSPLIT_1G is not set | |
| +CONFIG_PAGE_OFFSET=0xC0000000 | |
| +CONFIG_NR_CPUS=4 | |
| +CONFIG_HOTPLUG_CPU=y | |
| +# CONFIG_ARM_PSCI is not set | |
| +CONFIG_ARCH_NR_GPIO=0 | |
| +# CONFIG_PREEMPT_NONE is not set | |
| +CONFIG_PREEMPT_VOLUNTARY=y | |
| +# CONFIG_PREEMPT is not set | |
| +CONFIG_HZ_FIXED=0 | |
| +CONFIG_HZ_100=y | |
| +# CONFIG_HZ_200 is not set | |
| +# CONFIG_HZ_250 is not set | |
| +# CONFIG_HZ_300 is not set | |
| +# CONFIG_HZ_500 is not set | |
| +# CONFIG_HZ_1000 is not set | |
| +CONFIG_HZ=100 | |
| +# CONFIG_SCHED_HRTICK is not set | |
| +# CONFIG_THUMB2_KERNEL is not set | |
| +CONFIG_AEABI=y | |
| +# CONFIG_OABI_COMPAT is not set | |
| +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set | |
| +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set | |
| +CONFIG_HAVE_ARCH_PFN_VALID=y | |
| +CONFIG_HAVE_GENERIC_RCU_GUP=y | |
| +CONFIG_HIGHMEM=y | |
| +# CONFIG_HIGHPTE is not set | |
| +CONFIG_SYS_SUPPORTS_HUGETLBFS=y | |
| +CONFIG_ARCH_WANT_GENERAL_HUGETLB=y | |
| +# CONFIG_ARM_MODULE_PLTS is not set | |
| +CONFIG_FLATMEM=y | |
| +CONFIG_FLAT_NODE_MEM_MAP=y | |
| +CONFIG_HAVE_MEMBLOCK=y | |
| +CONFIG_NO_BOOTMEM=y | |
| +# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set | |
| +CONFIG_SPLIT_PTLOCK_CPUS=4 | |
| +# CONFIG_COMPACTION is not set | |
| +CONFIG_PHYS_ADDR_T_64BIT=y | |
| +CONFIG_ZONE_DMA_FLAG=0 | |
| +CONFIG_BOUNCE=y | |
| +# CONFIG_KSM is not set | |
| +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 | |
| +# CONFIG_TRANSPARENT_HUGEPAGE is not set | |
| +# CONFIG_CLEANCACHE is not set | |
| +# CONFIG_FRONTSWAP is not set | |
| +# CONFIG_CMA is not set | |
| +# CONFIG_ZPOOL is not set | |
| +# CONFIG_ZBUD is not set | |
| +CONFIG_ZSMALLOC=y | |
| +CONFIG_PGTABLE_MAPPING=y | |
| +# CONFIG_ZSMALLOC_STAT is not set | |
| +# CONFIG_IDLE_PAGE_TRACKING is not set | |
| +CONFIG_FORCE_MAX_ZONEORDER=11 | |
| +CONFIG_ALIGNMENT_TRAP=y | |
| +CONFIG_UACCESS_WITH_MEMCPY=y | |
| +CONFIG_SECCOMP=y | |
| +CONFIG_SWIOTLB=y | |
| +CONFIG_IOMMU_HELPER=y | |
| +# CONFIG_XEN is not set | |
| + | |
| +# | |
| +# Boot options | |
| +# | |
| +CONFIG_USE_OF=y | |
| +CONFIG_ATAGS=y | |
| +# CONFIG_DEPRECATED_PARAM_STRUCT is not set | |
| +CONFIG_ZBOOT_ROM_TEXT=0x0 | |
| +CONFIG_ZBOOT_ROM_BSS=0x0 | |
| +# CONFIG_ARM_APPENDED_DTB is not set | |
| +CONFIG_CMDLINE="" | |
| +# CONFIG_CRASH_DUMP is not set | |
| +CONFIG_AUTO_ZRELADDR=y | |
| + | |
| +# | |
| +# CPU Power Management | |
| +# | |
| + | |
| +# | |
| +# CPU Frequency scaling | |
| +# | |
| +# CONFIG_CPU_FREQ is not set | |
| + | |
| +# | |
| +# CPU Idle | |
| +# | |
| +CONFIG_CPU_IDLE=y | |
| +CONFIG_CPU_IDLE_GOV_LADDER=y | |
| +CONFIG_CPU_IDLE_GOV_MENU=y | |
| + | |
| +# | |
| +# ARM CPU Idle Drivers | |
| +# | |
| +# CONFIG_ARM_CPUIDLE is not set | |
| +# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set | |
| + | |
| +# | |
| +# Floating point emulation | |
| +# | |
| + | |
| +# | |
| +# At least one emulation must be selected | |
| +# | |
| +CONFIG_VFP=y | |
| +CONFIG_VFPv3=y | |
| +CONFIG_NEON=y | |
| +# CONFIG_KERNEL_MODE_NEON is not set | |
| + | |
| +# | |
| +# Userspace binary formats | |
| +# | |
| +CONFIG_BINFMT_ELF=y | |
| +CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y | |
| +CONFIG_BINFMT_SCRIPT=y | |
| +# CONFIG_HAVE_AOUT is not set | |
| +# CONFIG_BINFMT_MISC is not set | |
| +CONFIG_COREDUMP=y | |
| + | |
| +# | |
| +# Power management options | |
| +# | |
| +# CONFIG_SUSPEND is not set | |
| +# CONFIG_HIBERNATION is not set | |
| +CONFIG_PM=y | |
| +# CONFIG_PM_DEBUG is not set | |
| +# CONFIG_APM_EMULATION is not set | |
| +CONFIG_PM_CLK=y | |
| +# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set | |
| +CONFIG_CPU_PM=y | |
| +CONFIG_ARCH_SUSPEND_POSSIBLE=y | |
| +# CONFIG_ARM_CPU_SUSPEND is not set | |
| +CONFIG_ARCH_HIBERNATION_POSSIBLE=y | |
| +CONFIG_NET=y | |
| + | |
| +# | |
| +# Networking options | |
| +# | |
| +CONFIG_PACKET=y | |
| +# CONFIG_PACKET_DIAG is not set | |
| +CONFIG_UNIX=y | |
| +# CONFIG_UNIX_DIAG is not set | |
| +CONFIG_XFRM=y | |
| +CONFIG_XFRM_ALGO=m | |
| +CONFIG_XFRM_USER=m | |
| +# CONFIG_XFRM_SUB_POLICY is not set | |
| +# CONFIG_XFRM_MIGRATE is not set | |
| +# CONFIG_XFRM_STATISTICS is not set | |
| +# CONFIG_NET_KEY is not set | |
| +CONFIG_INET=y | |
| +CONFIG_IP_MULTICAST=y | |
| +CONFIG_IP_ADVANCED_ROUTER=y | |
| +# CONFIG_IP_FIB_TRIE_STATS is not set | |
| +CONFIG_IP_MULTIPLE_TABLES=y | |
| +# CONFIG_IP_ROUTE_MULTIPATH is not set | |
| +# CONFIG_IP_ROUTE_VERBOSE is not set | |
| +# CONFIG_IP_PNP is not set | |
| +CONFIG_NET_IPIP=m | |
| +# CONFIG_NET_IPGRE_DEMUX is not set | |
| +CONFIG_NET_IP_TUNNEL=m | |
| +# CONFIG_IP_MROUTE is not set | |
| +# CONFIG_SYN_COOKIES is not set | |
| +CONFIG_NET_UDP_TUNNEL=m | |
| +# CONFIG_NET_FOU is not set | |
| +# CONFIG_NET_FOU_IP_TUNNELS is not set | |
| +# CONFIG_INET_AH is not set | |
| +CONFIG_INET_ESP=m | |
| +# CONFIG_INET_IPCOMP is not set | |
| +# CONFIG_INET_XFRM_TUNNEL is not set | |
| +CONFIG_INET_TUNNEL=m | |
| +CONFIG_INET_XFRM_MODE_TRANSPORT=m | |
| +# CONFIG_INET_XFRM_MODE_TUNNEL is not set | |
| +# CONFIG_INET_XFRM_MODE_BEET is not set | |
| +CONFIG_INET_LRO=y | |
| +CONFIG_INET_DIAG=y | |
| +CONFIG_INET_TCP_DIAG=y | |
| +CONFIG_INET_UDP_DIAG=y | |
| +CONFIG_TCP_CONG_ADVANCED=y | |
| +# CONFIG_TCP_CONG_BIC is not set | |
| +CONFIG_TCP_CONG_CUBIC=y | |
| +# CONFIG_TCP_CONG_WESTWOOD is not set | |
| +# CONFIG_TCP_CONG_HTCP is not set | |
| +# CONFIG_TCP_CONG_HSTCP is not set | |
| +# CONFIG_TCP_CONG_HYBLA is not set | |
| +# CONFIG_TCP_CONG_VEGAS is not set | |
| +# CONFIG_TCP_CONG_SCALABLE is not set | |
| +# CONFIG_TCP_CONG_LP is not set | |
| +# CONFIG_TCP_CONG_VENO is not set | |
| +# CONFIG_TCP_CONG_YEAH is not set | |
| +# CONFIG_TCP_CONG_ILLINOIS is not set | |
| +# CONFIG_TCP_CONG_DCTCP is not set | |
| +# CONFIG_TCP_CONG_CDG is not set | |
| +CONFIG_DEFAULT_CUBIC=y | |
| +# CONFIG_DEFAULT_RENO is not set | |
| +CONFIG_DEFAULT_TCP_CONG="cubic" | |
| +# CONFIG_TCP_MD5SIG is not set | |
| +CONFIG_IPV6=y | |
| +CONFIG_IPV6_ROUTER_PREF=y | |
| +CONFIG_IPV6_ROUTE_INFO=y | |
| +CONFIG_IPV6_OPTIMISTIC_DAD=y | |
| +# CONFIG_INET6_AH is not set | |
| +# CONFIG_INET6_ESP is not set | |
| +# CONFIG_INET6_IPCOMP is not set | |
| +# CONFIG_IPV6_MIP6 is not set | |
| +# CONFIG_IPV6_ILA is not set | |
| +# CONFIG_INET6_XFRM_TUNNEL is not set | |
| +# CONFIG_INET6_TUNNEL is not set | |
| +CONFIG_INET6_XFRM_MODE_TRANSPORT=y | |
| +CONFIG_INET6_XFRM_MODE_TUNNEL=y | |
| +CONFIG_INET6_XFRM_MODE_BEET=y | |
| +# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set | |
| +# CONFIG_IPV6_VTI is not set | |
| +# CONFIG_IPV6_SIT is not set | |
| +# CONFIG_IPV6_TUNNEL is not set | |
| +# CONFIG_IPV6_GRE is not set | |
| +# CONFIG_IPV6_MULTIPLE_TABLES is not set | |
| +# CONFIG_IPV6_MROUTE is not set | |
| +# CONFIG_NETLABEL is not set | |
| +# CONFIG_NETWORK_SECMARK is not set | |
| +# CONFIG_NET_PTP_CLASSIFY is not set | |
| +# CONFIG_NETWORK_PHY_TIMESTAMPING is not set | |
| +CONFIG_NETFILTER=y | |
| +# CONFIG_NETFILTER_DEBUG is not set | |
| +CONFIG_NETFILTER_ADVANCED=y | |
| +CONFIG_BRIDGE_NETFILTER=m | |
| + | |
| +# | |
| +# Core Netfilter Configuration | |
| +# | |
| +# CONFIG_NETFILTER_INGRESS is not set | |
| +CONFIG_NETFILTER_NETLINK=m | |
| +# CONFIG_NETFILTER_NETLINK_ACCT is not set | |
| +CONFIG_NETFILTER_NETLINK_QUEUE=m | |
| +# CONFIG_NETFILTER_NETLINK_LOG is not set | |
| +CONFIG_NF_CONNTRACK=m | |
| +CONFIG_NF_CONNTRACK_MARK=y | |
| +# CONFIG_NF_CONNTRACK_PROCFS is not set | |
| +# CONFIG_NF_CONNTRACK_EVENTS is not set | |
| +# CONFIG_NF_CONNTRACK_TIMEOUT is not set | |
| +# CONFIG_NF_CONNTRACK_TIMESTAMP is not set | |
| +# CONFIG_NF_CT_PROTO_DCCP is not set | |
| +# CONFIG_NF_CT_PROTO_SCTP is not set | |
| +# CONFIG_NF_CT_PROTO_UDPLITE is not set | |
| +# CONFIG_NF_CONNTRACK_AMANDA is not set | |
| +# CONFIG_NF_CONNTRACK_FTP is not set | |
| +# CONFIG_NF_CONNTRACK_H323 is not set | |
| +# CONFIG_NF_CONNTRACK_IRC is not set | |
| +# CONFIG_NF_CONNTRACK_NETBIOS_NS is not set | |
| +# CONFIG_NF_CONNTRACK_SNMP is not set | |
| +# CONFIG_NF_CONNTRACK_PPTP is not set | |
| +# CONFIG_NF_CONNTRACK_SANE is not set | |
| +# CONFIG_NF_CONNTRACK_SIP is not set | |
| +# CONFIG_NF_CONNTRACK_TFTP is not set | |
| +# CONFIG_NF_CT_NETLINK is not set | |
| +# CONFIG_NF_CT_NETLINK_TIMEOUT is not set | |
| +CONFIG_NF_NAT=m | |
| +CONFIG_NF_NAT_NEEDED=y | |
| +# CONFIG_NF_NAT_AMANDA is not set | |
| +# CONFIG_NF_NAT_FTP is not set | |
| +# CONFIG_NF_NAT_IRC is not set | |
| +# CONFIG_NF_NAT_SIP is not set | |
| +# CONFIG_NF_NAT_TFTP is not set | |
| +# CONFIG_NF_NAT_REDIRECT is not set | |
| +# CONFIG_NF_TABLES is not set | |
| +CONFIG_NETFILTER_XTABLES=y | |
| + | |
| +# | |
| +# Xtables combined modules | |
| +# | |
| +# CONFIG_NETFILTER_XT_MARK is not set | |
| +# CONFIG_NETFILTER_XT_CONNMARK is not set | |
| + | |
| +# | |
| +# Xtables targets | |
| +# | |
| +# CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set | |
| +# CONFIG_NETFILTER_XT_TARGET_CONNMARK is not set | |
| +# CONFIG_NETFILTER_XT_TARGET_HMARK is not set | |
| +# CONFIG_NETFILTER_XT_TARGET_IDLETIMER is not set | |
| +# CONFIG_NETFILTER_XT_TARGET_LED is not set | |
| +# CONFIG_NETFILTER_XT_TARGET_LOG is not set | |
| +# CONFIG_NETFILTER_XT_TARGET_MARK is not set | |
| +CONFIG_NETFILTER_XT_NAT=m | |
| +# CONFIG_NETFILTER_XT_TARGET_NETMAP is not set | |
| +# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set | |
| +# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set | |
| +# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set | |
| +# CONFIG_NETFILTER_XT_TARGET_REDIRECT is not set | |
| +# CONFIG_NETFILTER_XT_TARGET_TEE is not set | |
| +# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set | |
| + | |
| +# | |
| +# Xtables matches | |
| +# | |
| +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m | |
| +# CONFIG_NETFILTER_XT_MATCH_BPF is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_CGROUP is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_CLUSTER is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_CONNBYTES is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_CONNLABEL is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_CONNLIMIT is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_CONNMARK is not set | |
| +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m | |
| +# CONFIG_NETFILTER_XT_MATCH_CPU is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_DCCP is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_DEVGROUP is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_DSCP is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_ECN is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_ESP is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_HELPER is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_HL is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_IPCOMP is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set | |
| +CONFIG_NETFILTER_XT_MATCH_IPVS=m | |
| +# CONFIG_NETFILTER_XT_MATCH_L2TP is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_LIMIT is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_MAC is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_MARK is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_NFACCT is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_OSF is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_OWNER is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_POLICY is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_PHYSDEV is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_REALM is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_RECENT is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_SCTP is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_SOCKET is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_STATE is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_STRING is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_TIME is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_U32 is not set | |
| +# CONFIG_IP_SET is not set | |
| +CONFIG_IP_VS=m | |
| +# CONFIG_IP_VS_IPV6 is not set | |
| +# CONFIG_IP_VS_DEBUG is not set | |
| +CONFIG_IP_VS_TAB_BITS=12 | |
| + | |
| +# | |
| +# IPVS transport protocol load balancing support | |
| +# | |
| +# CONFIG_IP_VS_PROTO_TCP is not set | |
| +# CONFIG_IP_VS_PROTO_UDP is not set | |
| +# CONFIG_IP_VS_PROTO_AH_ESP is not set | |
| +# CONFIG_IP_VS_PROTO_ESP is not set | |
| +# CONFIG_IP_VS_PROTO_AH is not set | |
| +# CONFIG_IP_VS_PROTO_SCTP is not set | |
| + | |
| +# | |
| +# IPVS scheduler | |
| +# | |
| +# CONFIG_IP_VS_RR is not set | |
| +# CONFIG_IP_VS_WRR is not set | |
| +# CONFIG_IP_VS_LC is not set | |
| +# CONFIG_IP_VS_WLC is not set | |
| +# CONFIG_IP_VS_FO is not set | |
| +# CONFIG_IP_VS_OVF is not set | |
| +# CONFIG_IP_VS_LBLC is not set | |
| +# CONFIG_IP_VS_LBLCR is not set | |
| +# CONFIG_IP_VS_DH is not set | |
| +# CONFIG_IP_VS_SH is not set | |
| +# CONFIG_IP_VS_SED is not set | |
| +# CONFIG_IP_VS_NQ is not set | |
| + | |
| +# | |
| +# IPVS SH scheduler | |
| +# | |
| +CONFIG_IP_VS_SH_TAB_BITS=8 | |
| + | |
| +# | |
| +# IPVS application helper | |
| +# | |
| +# CONFIG_IP_VS_NFCT is not set | |
| + | |
| +# | |
| +# IP: Netfilter Configuration | |
| +# | |
| +CONFIG_NF_DEFRAG_IPV4=m | |
| +CONFIG_NF_CONNTRACK_IPV4=m | |
| +# CONFIG_NF_DUP_IPV4 is not set | |
| +# CONFIG_NF_LOG_ARP is not set | |
| +# CONFIG_NF_LOG_IPV4 is not set | |
| +CONFIG_NF_REJECT_IPV4=y | |
| +CONFIG_NF_NAT_IPV4=m | |
| +CONFIG_NF_NAT_MASQUERADE_IPV4=m | |
| +# CONFIG_NF_NAT_PPTP is not set | |
| +# CONFIG_NF_NAT_H323 is not set | |
| +CONFIG_IP_NF_IPTABLES=y | |
| +# CONFIG_IP_NF_MATCH_AH is not set | |
| +# CONFIG_IP_NF_MATCH_ECN is not set | |
| +# CONFIG_IP_NF_MATCH_TTL is not set | |
| +CONFIG_IP_NF_FILTER=y | |
| +CONFIG_IP_NF_TARGET_REJECT=y | |
| +# CONFIG_IP_NF_TARGET_SYNPROXY is not set | |
| +CONFIG_IP_NF_NAT=m | |
| +CONFIG_IP_NF_TARGET_MASQUERADE=m | |
| +# CONFIG_IP_NF_TARGET_NETMAP is not set | |
| +# CONFIG_IP_NF_TARGET_REDIRECT is not set | |
| +# CONFIG_IP_NF_MANGLE is not set | |
| +# CONFIG_IP_NF_RAW is not set | |
| +# CONFIG_IP_NF_SECURITY is not set | |
| +# CONFIG_IP_NF_ARPTABLES is not set | |
| + | |
| +# | |
| +# IPv6: Netfilter Configuration | |
| +# | |
| +CONFIG_NF_DEFRAG_IPV6=m | |
| +CONFIG_NF_CONNTRACK_IPV6=m | |
| +# CONFIG_NF_DUP_IPV6 is not set | |
| +CONFIG_NF_REJECT_IPV6=y | |
| +# CONFIG_NF_LOG_IPV6 is not set | |
| +CONFIG_NF_NAT_IPV6=m | |
| +CONFIG_NF_NAT_MASQUERADE_IPV6=m | |
| +CONFIG_IP6_NF_IPTABLES=m | |
| +# CONFIG_IP6_NF_MATCH_AH is not set | |
| +# CONFIG_IP6_NF_MATCH_EUI64 is not set | |
| +# CONFIG_IP6_NF_MATCH_FRAG is not set | |
| +# CONFIG_IP6_NF_MATCH_OPTS is not set | |
| +# CONFIG_IP6_NF_MATCH_HL is not set | |
| +# CONFIG_IP6_NF_MATCH_IPV6HEADER is not set | |
| +# CONFIG_IP6_NF_MATCH_MH is not set | |
| +# CONFIG_IP6_NF_MATCH_RT is not set | |
| +CONFIG_IP6_NF_FILTER=m | |
| +CONFIG_IP6_NF_TARGET_REJECT=m | |
| +# CONFIG_IP6_NF_TARGET_SYNPROXY is not set | |
| +# CONFIG_IP6_NF_MANGLE is not set | |
| +# CONFIG_IP6_NF_RAW is not set | |
| +# CONFIG_IP6_NF_SECURITY is not set | |
| +CONFIG_IP6_NF_NAT=m | |
| +CONFIG_IP6_NF_TARGET_MASQUERADE=m | |
| +# CONFIG_IP6_NF_TARGET_NPT is not set | |
| +# CONFIG_BRIDGE_NF_EBTABLES is not set | |
| +# CONFIG_IP_DCCP is not set | |
| +# CONFIG_IP_SCTP is not set | |
| +# CONFIG_RDS is not set | |
| +# CONFIG_TIPC is not set | |
| +# CONFIG_ATM is not set | |
| +# CONFIG_L2TP is not set | |
| +CONFIG_STP=m | |
| +CONFIG_BRIDGE=m | |
| +CONFIG_BRIDGE_IGMP_SNOOPING=y | |
| +CONFIG_BRIDGE_VLAN_FILTERING=y | |
| +CONFIG_HAVE_NET_DSA=y | |
| +# CONFIG_NET_DSA is not set | |
| +CONFIG_VLAN_8021Q=y | |
| +# CONFIG_VLAN_8021Q_GVRP is not set | |
| +# CONFIG_VLAN_8021Q_MVRP is not set | |
| +# CONFIG_DECNET is not set | |
| +CONFIG_LLC=m | |
| +# CONFIG_LLC2 is not set | |
| +# CONFIG_IPX is not set | |
| +# CONFIG_ATALK is not set | |
| +# CONFIG_X25 is not set | |
| +# CONFIG_LAPB is not set | |
| +# CONFIG_PHONET is not set | |
| +# CONFIG_6LOWPAN is not set | |
| +# CONFIG_IEEE802154 is not set | |
| +CONFIG_NET_SCHED=y | |
| + | |
| +# | |
| +# Queueing/Scheduling | |
| +# | |
| +# CONFIG_NET_SCH_CBQ is not set | |
| +# CONFIG_NET_SCH_HTB is not set | |
| +# CONFIG_NET_SCH_HFSC is not set | |
| +# CONFIG_NET_SCH_PRIO is not set | |
| +# CONFIG_NET_SCH_MULTIQ is not set | |
| +# CONFIG_NET_SCH_RED is not set | |
| +# CONFIG_NET_SCH_SFB is not set | |
| +# CONFIG_NET_SCH_SFQ is not set | |
| +# CONFIG_NET_SCH_TEQL is not set | |
| +# CONFIG_NET_SCH_TBF is not set | |
| +# CONFIG_NET_SCH_GRED is not set | |
| +# CONFIG_NET_SCH_DSMARK is not set | |
| +CONFIG_NET_SCH_NETEM=m | |
| +# CONFIG_NET_SCH_DRR is not set | |
| +# CONFIG_NET_SCH_MQPRIO is not set | |
| +# CONFIG_NET_SCH_CHOKE is not set | |
| +# CONFIG_NET_SCH_QFQ is not set | |
| +# CONFIG_NET_SCH_CODEL is not set | |
| +# CONFIG_NET_SCH_FQ_CODEL is not set | |
| +# CONFIG_NET_SCH_FQ is not set | |
| +# CONFIG_NET_SCH_HHF is not set | |
| +# CONFIG_NET_SCH_PIE is not set | |
| +# CONFIG_NET_SCH_PLUG is not set | |
| + | |
| +# | |
| +# Classification | |
| +# | |
| +# CONFIG_NET_CLS_BASIC is not set | |
| +# CONFIG_NET_CLS_TCINDEX is not set | |
| +# CONFIG_NET_CLS_ROUTE4 is not set | |
| +# CONFIG_NET_CLS_FW is not set | |
| +# CONFIG_NET_CLS_U32 is not set | |
| +# CONFIG_NET_CLS_RSVP is not set | |
| +# CONFIG_NET_CLS_RSVP6 is not set | |
| +# CONFIG_NET_CLS_FLOW is not set | |
| +# CONFIG_NET_CLS_CGROUP is not set | |
| +# CONFIG_NET_CLS_BPF is not set | |
| +# CONFIG_NET_CLS_FLOWER is not set | |
| +# CONFIG_NET_EMATCH is not set | |
| +# CONFIG_NET_CLS_ACT is not set | |
| +CONFIG_NET_SCH_FIFO=y | |
| +# CONFIG_DCB is not set | |
| +CONFIG_DNS_RESOLVER=y | |
| +# CONFIG_BATMAN_ADV is not set | |
| +# CONFIG_OPENVSWITCH is not set | |
| +# CONFIG_VSOCKETS is not set | |
| +# CONFIG_NETLINK_DIAG is not set | |
| +# CONFIG_MPLS is not set | |
| +# CONFIG_HSR is not set | |
| +# CONFIG_NET_SWITCHDEV is not set | |
| +# CONFIG_NET_L3_MASTER_DEV is not set | |
| +CONFIG_RPS=y | |
| +CONFIG_RFS_ACCEL=y | |
| +CONFIG_XPS=y | |
| +# CONFIG_CGROUP_NET_PRIO is not set | |
| +# CONFIG_CGROUP_NET_CLASSID is not set | |
| +CONFIG_NET_RX_BUSY_POLL=y | |
| +CONFIG_BQL=y | |
| +# CONFIG_BPF_JIT is not set | |
| +CONFIG_NET_FLOW_LIMIT=y | |
| + | |
| +# | |
| +# Network testing | |
| +# | |
| +# CONFIG_NET_PKTGEN is not set | |
| +# CONFIG_HAMRADIO is not set | |
| +# CONFIG_CAN is not set | |
| +# CONFIG_IRDA is not set | |
| +CONFIG_BT=y | |
| +CONFIG_BT_BREDR=y | |
| +CONFIG_BT_RFCOMM=m | |
| +# CONFIG_BT_RFCOMM_TTY is not set | |
| +CONFIG_BT_BNEP=m | |
| +# CONFIG_BT_BNEP_MC_FILTER is not set | |
| +# CONFIG_BT_BNEP_PROTO_FILTER is not set | |
| +# CONFIG_BT_HIDP is not set | |
| +CONFIG_BT_HS=y | |
| +CONFIG_BT_LE=y | |
| +# CONFIG_BT_SELFTEST is not set | |
| + | |
| +# | |
| +# Bluetooth device drivers | |
| +# | |
| +CONFIG_BT_INTEL=y | |
| +CONFIG_BT_HCIBTUSB=y | |
| +# CONFIG_BT_HCIBTUSB_BCM is not set | |
| +# CONFIG_BT_HCIBTUSB_RTL is not set | |
| +# CONFIG_BT_HCIUART is not set | |
| +# CONFIG_BT_HCIBCM203X is not set | |
| +# CONFIG_BT_HCIBFUSB is not set | |
| +# CONFIG_BT_HCIVHCI is not set | |
| +# CONFIG_BT_MRVL is not set | |
| +# CONFIG_BT_ATH3K is not set | |
| +# CONFIG_AF_RXRPC is not set | |
| +CONFIG_FIB_RULES=y | |
| +# CONFIG_WIRELESS is not set | |
| +# CONFIG_WIMAX is not set | |
| +CONFIG_RFKILL=y | |
| +CONFIG_RFKILL_LEDS=y | |
| +# CONFIG_RFKILL_INPUT is not set | |
| +# CONFIG_RFKILL_GPIO is not set | |
| +# CONFIG_NET_9P is not set | |
| +# CONFIG_CAIF is not set | |
| +# CONFIG_CEPH_LIB is not set | |
| +# CONFIG_NFC is not set | |
| +# CONFIG_LWTUNNEL is not set | |
| +CONFIG_HAVE_BPF_JIT=y | |
| + | |
| +# | |
| +# Device Drivers | |
| +# | |
| +CONFIG_ARM_AMBA=y | |
| +# CONFIG_TEGRA_AHB is not set | |
| + | |
| +# | |
| +# Generic Driver Options | |
| +# | |
| +CONFIG_UEVENT_HELPER=y | |
| +CONFIG_UEVENT_HELPER_PATH="/sbin/mdev" | |
| +CONFIG_DEVTMPFS=y | |
| +# CONFIG_DEVTMPFS_MOUNT is not set | |
| +CONFIG_STANDALONE=y | |
| +CONFIG_PREVENT_FIRMWARE_BUILD=y | |
| +CONFIG_FW_LOADER=y | |
| +# CONFIG_FIRMWARE_IN_KERNEL is not set | |
| +CONFIG_EXTRA_FIRMWARE="" | |
| +# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set | |
| +# CONFIG_ALLOW_DEV_COREDUMP is not set | |
| +# CONFIG_DEBUG_DRIVER is not set | |
| +# CONFIG_DEBUG_DEVRES is not set | |
| +# CONFIG_SYS_HYPERVISOR is not set | |
| +# CONFIG_GENERIC_CPU_DEVICES is not set | |
| +CONFIG_REGMAP=y | |
| +CONFIG_REGMAP_MMIO=y | |
| +# CONFIG_DMA_SHARED_BUFFER is not set | |
| + | |
| +# | |
| +# Bus devices | |
| +# | |
| +# CONFIG_BRCMSTB_GISB_ARB is not set | |
| +CONFIG_VEXPRESS_CONFIG=y | |
| +# CONFIG_CONNECTOR is not set | |
| +CONFIG_MTD=y | |
| +# CONFIG_MTD_TESTS is not set | |
| +# CONFIG_MTD_REDBOOT_PARTS is not set | |
| +CONFIG_MTD_CMDLINE_PARTS=y | |
| +# CONFIG_MTD_AFS_PARTS is not set | |
| +CONFIG_MTD_OF_PARTS=y | |
| +# CONFIG_MTD_AR7_PARTS is not set | |
| + | |
| +# | |
| +# User Modules And Translation Layers | |
| +# | |
| +CONFIG_MTD_BLKDEVS=y | |
| +CONFIG_MTD_BLOCK=y | |
| +# CONFIG_FTL is not set | |
| +# CONFIG_NFTL is not set | |
| +# CONFIG_INFTL is not set | |
| +# CONFIG_RFD_FTL is not set | |
| +# CONFIG_SSFDC is not set | |
| +# CONFIG_SM_FTL is not set | |
| +# CONFIG_MTD_OOPS is not set | |
| +# CONFIG_MTD_SWAP is not set | |
| +# CONFIG_MTD_PARTITIONED_MASTER is not set | |
| + | |
| +# | |
| +# RAM/ROM/Flash chip drivers | |
| +# | |
| +CONFIG_MTD_CFI=y | |
| +CONFIG_MTD_JEDECPROBE=y | |
| +CONFIG_MTD_GEN_PROBE=y | |
| +CONFIG_MTD_CFI_ADV_OPTIONS=y | |
| +CONFIG_MTD_CFI_NOSWAP=y | |
| +# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set | |
| +# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set | |
| +CONFIG_MTD_CFI_GEOMETRY=y | |
| +CONFIG_MTD_MAP_BANK_WIDTH_1=y | |
| +CONFIG_MTD_MAP_BANK_WIDTH_2=y | |
| +# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set | |
| +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set | |
| +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set | |
| +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set | |
| +CONFIG_MTD_CFI_I1=y | |
| +CONFIG_MTD_CFI_I2=y | |
| +# CONFIG_MTD_CFI_I4 is not set | |
| +# CONFIG_MTD_CFI_I8 is not set | |
| +# CONFIG_MTD_OTP is not set | |
| +CONFIG_MTD_CFI_INTELEXT=y | |
| +# CONFIG_MTD_CFI_AMDSTD is not set | |
| +CONFIG_MTD_CFI_STAA=y | |
| +CONFIG_MTD_CFI_UTIL=y | |
| +# CONFIG_MTD_RAM is not set | |
| +# CONFIG_MTD_ROM is not set | |
| +# CONFIG_MTD_ABSENT is not set | |
| + | |
| +# | |
| +# Mapping drivers for chip access | |
| +# | |
| +# CONFIG_MTD_COMPLEX_MAPPINGS is not set | |
| +CONFIG_MTD_PHYSMAP=y | |
| +# CONFIG_MTD_PHYSMAP_COMPAT is not set | |
| +CONFIG_MTD_PHYSMAP_OF=y | |
| +# CONFIG_MTD_IMPA7 is not set | |
| +# CONFIG_MTD_INTEL_VR_NOR is not set | |
| +# CONFIG_MTD_PLATRAM is not set | |
| + | |
| +# | |
| +# Self-contained MTD device drivers | |
| +# | |
| +# CONFIG_MTD_PMC551 is not set | |
| +# CONFIG_MTD_SLRAM is not set | |
| +# CONFIG_MTD_PHRAM is not set | |
| +# CONFIG_MTD_MTDRAM is not set | |
| +# CONFIG_MTD_BLOCK2MTD is not set | |
| + | |
| +# | |
| +# Disk-On-Chip Device Drivers | |
| +# | |
| +# CONFIG_MTD_DOCG3 is not set | |
| +CONFIG_MTD_NAND_ECC=y | |
| +# CONFIG_MTD_NAND_ECC_SMC is not set | |
| +CONFIG_MTD_NAND=y | |
| +# CONFIG_MTD_NAND_ECC_BCH is not set | |
| +# CONFIG_MTD_SM_COMMON is not set | |
| +# CONFIG_MTD_NAND_DENALI_PCI is not set | |
| +# CONFIG_MTD_NAND_DENALI_DT is not set | |
| +# CONFIG_MTD_NAND_GPIO is not set | |
| +# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set | |
| +CONFIG_MTD_NAND_IDS=y | |
| +# CONFIG_MTD_NAND_RICOH is not set | |
| +# CONFIG_MTD_NAND_DISKONCHIP is not set | |
| +# CONFIG_MTD_NAND_DOCG4 is not set | |
| +# CONFIG_MTD_NAND_CAFE is not set | |
| +# CONFIG_MTD_NAND_NANDSIM is not set | |
| +# CONFIG_MTD_NAND_BRCMNAND is not set | |
| +# CONFIG_MTD_NAND_PLATFORM is not set | |
| +# CONFIG_MTD_NAND_HISI504 is not set | |
| +CONFIG_MTD_NAND_AL=y | |
| +# CONFIG_MTD_ONENAND is not set | |
| + | |
| +# | |
| +# LPDDR & LPDDR2 PCM memory drivers | |
| +# | |
| +# CONFIG_MTD_LPDDR is not set | |
| +# CONFIG_MTD_LPDDR2_NVM is not set | |
| +# CONFIG_MTD_SPI_NOR is not set | |
| +CONFIG_MTD_UBI=y | |
| +CONFIG_MTD_UBI_WL_THRESHOLD=4096 | |
| +CONFIG_MTD_UBI_BEB_LIMIT=20 | |
| +# CONFIG_MTD_UBI_FASTMAP is not set | |
| +# CONFIG_MTD_UBI_GLUEBI is not set | |
| +# CONFIG_MTD_UBI_BLOCK is not set | |
| +CONFIG_DTC=y | |
| +CONFIG_OF=y | |
| +# CONFIG_OF_UNITTEST is not set | |
| +CONFIG_OF_FLATTREE=y | |
| +CONFIG_OF_EARLY_FLATTREE=y | |
| +CONFIG_OF_ADDRESS=y | |
| +CONFIG_OF_ADDRESS_PCI=y | |
| +CONFIG_OF_IRQ=y | |
| +CONFIG_OF_NET=y | |
| +CONFIG_OF_MDIO=y | |
| +CONFIG_OF_PCI=y | |
| +CONFIG_OF_PCI_IRQ=y | |
| +CONFIG_OF_MTD=y | |
| +CONFIG_OF_RESERVED_MEM=y | |
| +# CONFIG_OF_OVERLAY is not set | |
| +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y | |
| +# CONFIG_PARPORT is not set | |
| +CONFIG_BLK_DEV=y | |
| +# CONFIG_BLK_DEV_NULL_BLK is not set | |
| +# CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set | |
| +CONFIG_ZRAM=m | |
| +# CONFIG_ZRAM_LZ4_COMPRESS is not set | |
| +# CONFIG_BLK_CPQ_CISS_DA is not set | |
| +# CONFIG_BLK_DEV_DAC960 is not set | |
| +# CONFIG_BLK_DEV_UMEM is not set | |
| +# CONFIG_BLK_DEV_COW_COMMON is not set | |
| +CONFIG_BLK_DEV_LOOP=y | |
| +CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 | |
| +# CONFIG_BLK_DEV_CRYPTOLOOP is not set | |
| +# CONFIG_BLK_DEV_DRBD is not set | |
| +# CONFIG_BLK_DEV_NBD is not set | |
| +# CONFIG_BLK_DEV_SX8 is not set | |
| +# CONFIG_BLK_DEV_RAM is not set | |
| +# CONFIG_CDROM_PKTCDVD is not set | |
| +# CONFIG_ATA_OVER_ETH is not set | |
| +# CONFIG_MG_DISK is not set | |
| +# CONFIG_BLK_DEV_RBD is not set | |
| +# CONFIG_BLK_DEV_RSXX is not set | |
| +# CONFIG_BLK_DEV_NVME is not set | |
| + | |
| +# | |
| +# Misc devices | |
| +# | |
| +# CONFIG_SENSORS_LIS3LV02D is not set | |
| +# CONFIG_AD525X_DPOT is not set | |
| +# CONFIG_DUMMY_IRQ is not set | |
| +# CONFIG_PHANTOM is not set | |
| +# CONFIG_SGI_IOC4 is not set | |
| +# CONFIG_TIFM_CORE is not set | |
| +# CONFIG_ICS932S401 is not set | |
| +# CONFIG_ENCLOSURE_SERVICES is not set | |
| +# CONFIG_HP_ILO is not set | |
| +# CONFIG_APDS9802ALS is not set | |
| +# CONFIG_ISL29003 is not set | |
| +# CONFIG_ISL29020 is not set | |
| +# CONFIG_SENSORS_TSL2550 is not set | |
| +# CONFIG_SENSORS_BH1780 is not set | |
| +# CONFIG_SENSORS_BH1770 is not set | |
| +# CONFIG_SENSORS_APDS990X is not set | |
| +# CONFIG_HMC6352 is not set | |
| +# CONFIG_DS1682 is not set | |
| +# CONFIG_BMP085_I2C is not set | |
| +# CONFIG_USB_SWITCH_FSA9480 is not set | |
| +# CONFIG_SRAM is not set | |
| +CONFIG_VEXPRESS_SYSCFG=y | |
| +# CONFIG_C2PORT is not set | |
| + | |
| +# | |
| +# EEPROM support | |
| +# | |
| +# CONFIG_EEPROM_AT24 is not set | |
| +# CONFIG_EEPROM_LEGACY is not set | |
| +# CONFIG_EEPROM_MAX6875 is not set | |
| +# CONFIG_EEPROM_93CX6 is not set | |
| +# CONFIG_CB710_CORE is not set | |
| + | |
| +# | |
| +# Texas Instruments shared transport line discipline | |
| +# | |
| +# CONFIG_TI_ST is not set | |
| +# CONFIG_SENSORS_LIS3_I2C is not set | |
| + | |
| +# | |
| +# Altera FPGA firmware download module | |
| +# | |
| +# CONFIG_ALTERA_STAPL is not set | |
| + | |
| +# | |
| +# Intel MIC Bus Driver | |
| +# | |
| + | |
| +# | |
| +# SCIF Bus Driver | |
| +# | |
| + | |
| +# | |
| +# Intel MIC Host Driver | |
| +# | |
| + | |
| +# | |
| +# Intel MIC Card Driver | |
| +# | |
| + | |
| +# | |
| +# SCIF Driver | |
| +# | |
| + | |
| +# | |
| +# Intel MIC Coprocessor State Management (COSM) Drivers | |
| +# | |
| +# CONFIG_ECHO is not set | |
| +# CONFIG_CXL_BASE is not set | |
| +# CONFIG_CXL_KERNEL_API is not set | |
| +# CONFIG_CXL_EEH is not set | |
| +CONFIG_HAVE_IDE=y | |
| +# CONFIG_IDE is not set | |
| + | |
| +# | |
| +# SCSI device support | |
| +# | |
| +CONFIG_SCSI_MOD=y | |
| +# CONFIG_RAID_ATTRS is not set | |
| +CONFIG_SCSI=y | |
| +CONFIG_SCSI_DMA=y | |
| +# CONFIG_SCSI_NETLINK is not set | |
| +# CONFIG_SCSI_MQ_DEFAULT is not set | |
| +# CONFIG_SCSI_PROC_FS is not set | |
| + | |
| +# | |
| +# SCSI support type (disk, tape, CD-ROM) | |
| +# | |
| +CONFIG_BLK_DEV_SD=y | |
| +# CONFIG_CHR_DEV_ST is not set | |
| +# CONFIG_CHR_DEV_OSST is not set | |
| +# CONFIG_BLK_DEV_SR is not set | |
| +# CONFIG_CHR_DEV_SG is not set | |
| +# CONFIG_CHR_DEV_SCH is not set | |
| +# CONFIG_SCSI_CONSTANTS is not set | |
| +# CONFIG_SCSI_LOGGING is not set | |
| +# CONFIG_SCSI_SCAN_ASYNC is not set | |
| +CONFIG_MV_STAGGERED_SPINUP=y | |
| + | |
| +# | |
| +# SCSI Transports | |
| +# | |
| +# CONFIG_SCSI_SPI_ATTRS is not set | |
| +# CONFIG_SCSI_FC_ATTRS is not set | |
| +CONFIG_SCSI_ISCSI_ATTRS=m | |
| +# CONFIG_SCSI_SAS_ATTRS is not set | |
| +# CONFIG_SCSI_SAS_LIBSAS is not set | |
| +# CONFIG_SCSI_SRP_ATTRS is not set | |
| +CONFIG_SCSI_LOWLEVEL=y | |
| +CONFIG_ISCSI_TCP=m | |
| +# CONFIG_ISCSI_BOOT_SYSFS is not set | |
| +# CONFIG_SCSI_CXGB3_ISCSI is not set | |
| +# CONFIG_SCSI_CXGB4_ISCSI is not set | |
| +# CONFIG_SCSI_BNX2_ISCSI is not set | |
| +# CONFIG_BE2ISCSI is not set | |
| +# CONFIG_BLK_DEV_3W_XXXX_RAID is not set | |
| +# CONFIG_SCSI_HPSA is not set | |
| +# CONFIG_SCSI_3W_9XXX is not set | |
| +# CONFIG_SCSI_3W_SAS is not set | |
| +# CONFIG_SCSI_ACARD is not set | |
| +# CONFIG_SCSI_AACRAID is not set | |
| +# CONFIG_SCSI_AIC7XXX is not set | |
| +# CONFIG_SCSI_AIC79XX is not set | |
| +# CONFIG_SCSI_AIC94XX is not set | |
| +# CONFIG_SCSI_MVSAS is not set | |
| +# CONFIG_SCSI_MVUMI is not set | |
| +# CONFIG_SCSI_ADVANSYS is not set | |
| +# CONFIG_SCSI_ARCMSR is not set | |
| +# CONFIG_SCSI_ESAS2R is not set | |
| +# CONFIG_MEGARAID_NEWGEN is not set | |
| +# CONFIG_MEGARAID_LEGACY is not set | |
| +# CONFIG_MEGARAID_SAS is not set | |
| +# CONFIG_SCSI_MPT3SAS is not set | |
| +# CONFIG_SCSI_MPT2SAS is not set | |
| +# CONFIG_SCSI_UFSHCD is not set | |
| +# CONFIG_SCSI_HPTIOP is not set | |
| +# CONFIG_SCSI_SNIC is not set | |
| +# CONFIG_SCSI_DMX3191D is not set | |
| +# CONFIG_SCSI_FUTURE_DOMAIN is not set | |
| +# CONFIG_SCSI_IPS is not set | |
| +# CONFIG_SCSI_INITIO is not set | |
| +# CONFIG_SCSI_INIA100 is not set | |
| +# CONFIG_SCSI_STEX is not set | |
| +# CONFIG_SCSI_SYM53C8XX_2 is not set | |
| +# CONFIG_SCSI_IPR is not set | |
| +# CONFIG_SCSI_QLOGIC_1280 is not set | |
| +# CONFIG_SCSI_QLA_ISCSI is not set | |
| +# CONFIG_SCSI_DC395x is not set | |
| +# CONFIG_SCSI_AM53C974 is not set | |
| +# CONFIG_SCSI_NSP32 is not set | |
| +# CONFIG_SCSI_WD719X is not set | |
| +# CONFIG_SCSI_DEBUG is not set | |
| +# CONFIG_SCSI_PMCRAID is not set | |
| +# CONFIG_SCSI_PM8001 is not set | |
| +CONFIG_SCSI_DH=y | |
| +# CONFIG_SCSI_DH_RDAC is not set | |
| +# CONFIG_SCSI_DH_HP_SW is not set | |
| +# CONFIG_SCSI_DH_EMC is not set | |
| +# CONFIG_SCSI_DH_ALUA is not set | |
| +# CONFIG_SCSI_OSD_INITIATOR is not set | |
| +CONFIG_ATA=y | |
| +# CONFIG_ATA_NONSTANDARD is not set | |
| +CONFIG_ATA_VERBOSE_ERROR=y | |
| +CONFIG_SATA_PMP=y | |
| + | |
| +# | |
| +# Controllers with non-SFF native interface | |
| +# | |
| +CONFIG_SATA_AHCI=y | |
| +CONFIG_SATA_AHCI_PLATFORM=y | |
| +# CONFIG_AHCI_CEVA is not set | |
| +CONFIG_AHCI_ALPINE=y | |
| +# CONFIG_AHCI_QORIQ is not set | |
| +# CONFIG_SATA_INIC162X is not set | |
| +# CONFIG_SATA_ACARD_AHCI is not set | |
| +# CONFIG_SATA_SIL24 is not set | |
| +CONFIG_ATA_SFF=y | |
| + | |
| +# | |
| +# SFF controllers with custom DMA interface | |
| +# | |
| +# CONFIG_PDC_ADMA is not set | |
| +# CONFIG_SATA_QSTOR is not set | |
| +# CONFIG_SATA_SX4 is not set | |
| +CONFIG_ATA_BMDMA=y | |
| + | |
| +# | |
| +# SATA SFF controllers with BMDMA | |
| +# | |
| +# CONFIG_ATA_PIIX is not set | |
| +# CONFIG_SATA_MV is not set | |
| +# CONFIG_SATA_NV is not set | |
| +# CONFIG_SATA_PROMISE is not set | |
| +# CONFIG_SATA_SIL is not set | |
| +# CONFIG_SATA_SIS is not set | |
| +# CONFIG_SATA_SVW is not set | |
| +# CONFIG_SATA_ULI is not set | |
| +# CONFIG_SATA_VIA is not set | |
| +# CONFIG_SATA_VITESSE is not set | |
| + | |
| +# | |
| +# PATA SFF controllers with BMDMA | |
| +# | |
| +# CONFIG_PATA_ALI is not set | |
| +# CONFIG_PATA_AMD is not set | |
| +# CONFIG_PATA_ARTOP is not set | |
| +# CONFIG_PATA_ATIIXP is not set | |
| +# CONFIG_PATA_ATP867X is not set | |
| +# CONFIG_PATA_CMD64X is not set | |
| +# CONFIG_PATA_CYPRESS is not set | |
| +# CONFIG_PATA_EFAR is not set | |
| +# CONFIG_PATA_HPT366 is not set | |
| +# CONFIG_PATA_HPT37X is not set | |
| +# CONFIG_PATA_HPT3X2N is not set | |
| +# CONFIG_PATA_HPT3X3 is not set | |
| +# CONFIG_PATA_IT8213 is not set | |
| +# CONFIG_PATA_IT821X is not set | |
| +# CONFIG_PATA_JMICRON is not set | |
| +# CONFIG_PATA_MARVELL is not set | |
| +# CONFIG_PATA_NETCELL is not set | |
| +# CONFIG_PATA_NINJA32 is not set | |
| +# CONFIG_PATA_NS87415 is not set | |
| +# CONFIG_PATA_OLDPIIX is not set | |
| +# CONFIG_PATA_OPTIDMA is not set | |
| +# CONFIG_PATA_PDC2027X is not set | |
| +# CONFIG_PATA_PDC_OLD is not set | |
| +# CONFIG_PATA_RADISYS is not set | |
| +# CONFIG_PATA_RDC is not set | |
| +# CONFIG_PATA_SCH is not set | |
| +# CONFIG_PATA_SERVERWORKS is not set | |
| +# CONFIG_PATA_SIL680 is not set | |
| +# CONFIG_PATA_SIS is not set | |
| +# CONFIG_PATA_TOSHIBA is not set | |
| +# CONFIG_PATA_TRIFLEX is not set | |
| +# CONFIG_PATA_VIA is not set | |
| +# CONFIG_PATA_WINBOND is not set | |
| + | |
| +# | |
| +# PIO-only SFF controllers | |
| +# | |
| +# CONFIG_PATA_CMD640_PCI is not set | |
| +# CONFIG_PATA_MPIIX is not set | |
| +# CONFIG_PATA_NS87410 is not set | |
| +# CONFIG_PATA_OPTI is not set | |
| +# CONFIG_PATA_PLATFORM is not set | |
| +# CONFIG_PATA_RZ1000 is not set | |
| + | |
| +# | |
| +# Generic fallback / legacy drivers | |
| +# | |
| +# CONFIG_ATA_GENERIC is not set | |
| +# CONFIG_PATA_LEGACY is not set | |
| +CONFIG_MD=y | |
| +CONFIG_BLK_DEV_MD=y | |
| +# CONFIG_MD_AUTODETECT is not set | |
| +# CONFIG_MD_LINEAR is not set | |
| +CONFIG_MD_RAID0=y | |
| +CONFIG_MD_RAID1=y | |
| +CONFIG_MD_RAID10=y | |
| +CONFIG_MD_RAID456=y | |
| +# CONFIG_MD_MULTIPATH is not set | |
| +# CONFIG_MD_FAULTY is not set | |
| +# CONFIG_BCACHE is not set | |
| +CONFIG_BLK_DEV_DM_BUILTIN=y | |
| +CONFIG_BLK_DEV_DM=y | |
| +# CONFIG_DM_MQ_DEFAULT is not set | |
| +# CONFIG_DM_DEBUG is not set | |
| +CONFIG_DM_BUFIO=y | |
| +CONFIG_DM_BIO_PRISON=m | |
| +CONFIG_DM_PERSISTENT_DATA=m | |
| +# CONFIG_DM_DEBUG_BLOCK_STACK_TRACING is not set | |
| +CONFIG_DM_CRYPT=y | |
| +CONFIG_DM_SNAPSHOT=y | |
| +CONFIG_DM_THIN_PROVISIONING=m | |
| +# CONFIG_DM_CACHE is not set | |
| +# CONFIG_DM_ERA is not set | |
| +# CONFIG_DM_MIRROR is not set | |
| +# CONFIG_DM_RAID is not set | |
| +# CONFIG_DM_ZERO is not set | |
| +# CONFIG_DM_MULTIPATH is not set | |
| +# CONFIG_DM_DELAY is not set | |
| +# CONFIG_DM_UEVENT is not set | |
| +# CONFIG_DM_FLAKEY is not set | |
| +# CONFIG_DM_VERITY is not set | |
| +# CONFIG_DM_SWITCH is not set | |
| +# CONFIG_DM_LOG_WRITES is not set | |
| +CONFIG_TARGET_CORE=y | |
| +# CONFIG_TCM_IBLOCK is not set | |
| +CONFIG_TCM_FILEIO=y | |
| +# CONFIG_TCM_PSCSI is not set | |
| +# CONFIG_LOOPBACK_TARGET is not set | |
| +CONFIG_ISCSI_TARGET=y | |
| +# CONFIG_FUSION is not set | |
| + | |
| +# | |
| +# IEEE 1394 (FireWire) support | |
| +# | |
| +# CONFIG_FIREWIRE is not set | |
| +# CONFIG_FIREWIRE_NOSY is not set | |
| +CONFIG_NETDEVICES=y | |
| +CONFIG_NET_CORE=y | |
| +CONFIG_BONDING=y | |
| +CONFIG_DUMMY=m | |
| +# CONFIG_EQUALIZER is not set | |
| +# CONFIG_NET_FC is not set | |
| +# CONFIG_NET_TEAM is not set | |
| +CONFIG_MACVLAN=m | |
| +# CONFIG_MACVTAP is not set | |
| +CONFIG_IPVLAN=m | |
| +CONFIG_VXLAN=m | |
| +CONFIG_GENEVE=m | |
| +CONFIG_NETCONSOLE=m | |
| +# CONFIG_NETCONSOLE_DYNAMIC is not set | |
| +CONFIG_NETPOLL=y | |
| +CONFIG_NET_POLL_CONTROLLER=y | |
| +CONFIG_TUN=y | |
| +# CONFIG_TUN_VNET_CROSS_LE is not set | |
| +CONFIG_VETH=m | |
| +# CONFIG_NLMON is not set | |
| +# CONFIG_ARCNET is not set | |
| + | |
| +# | |
| +# CAIF transport drivers | |
| +# | |
| + | |
| +# | |
| +# Distributed Switch Architecture drivers | |
| +# | |
| +# CONFIG_NET_DSA_MV88E6XXX is not set | |
| +# CONFIG_NET_DSA_MV88E6XXX_NEED_PPU is not set | |
| +CONFIG_ETHERNET=y | |
| +# CONFIG_NET_VENDOR_3COM is not set | |
| +# CONFIG_NET_VENDOR_ADAPTEC is not set | |
| +# CONFIG_NET_VENDOR_AGERE is not set | |
| +# CONFIG_NET_VENDOR_ALTEON is not set | |
| +# CONFIG_ALTERA_TSE is not set | |
| +CONFIG_NET_AL_ETH=y | |
| +CONFIG_AL_ETH_ALLOC_FRAG=y | |
| +# CONFIG_AL_ETH_ALLOC_PAGE is not set | |
| +# CONFIG_AL_ETH_ALLOC_SKB is not set | |
| +# CONFIG_NET_VENDOR_AMD is not set | |
| +# CONFIG_NET_VENDOR_ARC is not set | |
| +# CONFIG_NET_VENDOR_ATHEROS is not set | |
| +# CONFIG_NET_VENDOR_AURORA is not set | |
| +# CONFIG_NET_CADENCE is not set | |
| +# CONFIG_NET_VENDOR_BROADCOM is not set | |
| +# CONFIG_NET_VENDOR_BROCADE is not set | |
| +# CONFIG_NET_VENDOR_CAVIUM is not set | |
| +# CONFIG_NET_VENDOR_CHELSIO is not set | |
| +# CONFIG_NET_VENDOR_CIRRUS is not set | |
| +# CONFIG_NET_VENDOR_CISCO is not set | |
| +# CONFIG_DM9000 is not set | |
| +# CONFIG_DNET is not set | |
| +# CONFIG_NET_VENDOR_DEC is not set | |
| +# CONFIG_NET_VENDOR_DLINK is not set | |
| +# CONFIG_NET_VENDOR_EMULEX is not set | |
| +# CONFIG_NET_VENDOR_EZCHIP is not set | |
| +# CONFIG_NET_VENDOR_EXAR is not set | |
| +# CONFIG_NET_VENDOR_FARADAY is not set | |
| +# CONFIG_NET_VENDOR_HISILICON is not set | |
| +# CONFIG_NET_VENDOR_HP is not set | |
| +# CONFIG_NET_VENDOR_INTEL is not set | |
| +# CONFIG_JME is not set | |
| +# CONFIG_NET_VENDOR_MARVELL is not set | |
| +# CONFIG_NET_VENDOR_MELLANOX is not set | |
| +# CONFIG_NET_VENDOR_MICREL is not set | |
| +# CONFIG_NET_VENDOR_MYRI is not set | |
| +# CONFIG_FEALNX is not set | |
| +# CONFIG_NET_VENDOR_NATSEMI is not set | |
| +# CONFIG_NET_VENDOR_NVIDIA is not set | |
| +# CONFIG_NET_VENDOR_OKI is not set | |
| +# CONFIG_ETHOC is not set | |
| +# CONFIG_NET_PACKET_ENGINE is not set | |
| +# CONFIG_NET_VENDOR_QLOGIC is not set | |
| +# CONFIG_NET_VENDOR_QUALCOMM is not set | |
| +# CONFIG_NET_VENDOR_REALTEK is not set | |
| +# CONFIG_NET_VENDOR_RENESAS is not set | |
| +# CONFIG_NET_VENDOR_RDC is not set | |
| +# CONFIG_NET_VENDOR_ROCKER is not set | |
| +# CONFIG_NET_VENDOR_SAMSUNG is not set | |
| +# CONFIG_NET_VENDOR_SEEQ is not set | |
| +# CONFIG_NET_VENDOR_SILAN is not set | |
| +# CONFIG_NET_VENDOR_SIS is not set | |
| +# CONFIG_SFC is not set | |
| +# CONFIG_NET_VENDOR_SMSC is not set | |
| +# CONFIG_NET_VENDOR_STMICRO is not set | |
| +# CONFIG_NET_VENDOR_SUN is not set | |
| +# CONFIG_NET_VENDOR_SYNOPSYS is not set | |
| +# CONFIG_NET_VENDOR_TEHUTI is not set | |
| +# CONFIG_NET_VENDOR_TI is not set | |
| +# CONFIG_NET_VENDOR_VIA is not set | |
| +# CONFIG_NET_VENDOR_WIZNET is not set | |
| +# CONFIG_FDDI is not set | |
| +# CONFIG_HIPPI is not set | |
| +CONFIG_PHYLIB=y | |
| + | |
| +# | |
| +# MII PHY device drivers | |
| +# | |
| +# CONFIG_AQUANTIA_PHY is not set | |
| +CONFIG_AT803X_PHY=y | |
| +# CONFIG_AMD_PHY is not set | |
| +# CONFIG_MARVELL_PHY is not set | |
| +# CONFIG_DAVICOM_PHY is not set | |
| +# CONFIG_QSEMI_PHY is not set | |
| +# CONFIG_LXT_PHY is not set | |
| +# CONFIG_CICADA_PHY is not set | |
| +# CONFIG_VITESSE_PHY is not set | |
| +# CONFIG_TERANETICS_PHY is not set | |
| +# CONFIG_SMSC_PHY is not set | |
| +# CONFIG_BROADCOM_PHY is not set | |
| +# CONFIG_BCM7XXX_PHY is not set | |
| +# CONFIG_BCM87XX_PHY is not set | |
| +# CONFIG_ICPLUS_PHY is not set | |
| +# CONFIG_REALTEK_PHY is not set | |
| +# CONFIG_NATIONAL_PHY is not set | |
| +# CONFIG_STE10XP is not set | |
| +# CONFIG_LSI_ET1011C_PHY is not set | |
| +# CONFIG_MICREL_PHY is not set | |
| +# CONFIG_DP83848_PHY is not set | |
| +# CONFIG_DP83867_PHY is not set | |
| +# CONFIG_MICROCHIP_PHY is not set | |
| +# CONFIG_FIXED_PHY is not set | |
| +# CONFIG_MDIO_BITBANG is not set | |
| +# CONFIG_MDIO_BUS_MUX_GPIO is not set | |
| +# CONFIG_MDIO_BUS_MUX_MMIOREG is not set | |
| +# CONFIG_MDIO_BCM_UNIMAC is not set | |
| +# CONFIG_PPP is not set | |
| +# CONFIG_SLIP is not set | |
| +# CONFIG_USB_NET_DRIVERS is not set | |
| +# CONFIG_WLAN is not set | |
| + | |
| +# | |
| +# Enable WiMAX (Networking options) to see the WiMAX drivers | |
| +# | |
| +# CONFIG_WAN is not set | |
| +# CONFIG_VMXNET3 is not set | |
| +# CONFIG_ISDN is not set | |
| +# CONFIG_NVM is not set | |
| + | |
| +# | |
| +# Input device support | |
| +# | |
| +CONFIG_INPUT=y | |
| +# CONFIG_INPUT_LEDS is not set | |
| +# CONFIG_INPUT_FF_MEMLESS is not set | |
| +# CONFIG_INPUT_POLLDEV is not set | |
| +# CONFIG_INPUT_SPARSEKMAP is not set | |
| +# CONFIG_INPUT_MATRIXKMAP is not set | |
| + | |
| +# | |
| +# Userland interfaces | |
| +# | |
| +# CONFIG_INPUT_MOUSEDEV is not set | |
| +# CONFIG_INPUT_JOYDEV is not set | |
| +CONFIG_INPUT_EVDEV=y | |
| +# CONFIG_INPUT_EVBUG is not set | |
| + | |
| +# | |
| +# Input Device Drivers | |
| +# | |
| +CONFIG_INPUT_KEYBOARD=y | |
| +# CONFIG_KEYBOARD_ADP5588 is not set | |
| +# CONFIG_KEYBOARD_ADP5589 is not set | |
| +# CONFIG_KEYBOARD_ATKBD is not set | |
| +# CONFIG_KEYBOARD_QT1070 is not set | |
| +# CONFIG_KEYBOARD_QT2160 is not set | |
| +# CONFIG_KEYBOARD_LKKBD is not set | |
| +CONFIG_KEYBOARD_GPIO=y | |
| +# CONFIG_KEYBOARD_GPIO_POLLED is not set | |
| +# CONFIG_KEYBOARD_TCA6416 is not set | |
| +# CONFIG_KEYBOARD_TCA8418 is not set | |
| +# CONFIG_KEYBOARD_MATRIX is not set | |
| +# CONFIG_KEYBOARD_LM8323 is not set | |
| +# CONFIG_KEYBOARD_LM8333 is not set | |
| +# CONFIG_KEYBOARD_MAX7359 is not set | |
| +# CONFIG_KEYBOARD_MCS is not set | |
| +# CONFIG_KEYBOARD_MPR121 is not set | |
| +# CONFIG_KEYBOARD_NEWTON is not set | |
| +# CONFIG_KEYBOARD_OPENCORES is not set | |
| +# CONFIG_KEYBOARD_SAMSUNG is not set | |
| +# CONFIG_KEYBOARD_STOWAWAY is not set | |
| +# CONFIG_KEYBOARD_SUNKBD is not set | |
| +# CONFIG_KEYBOARD_OMAP4 is not set | |
| +# CONFIG_KEYBOARD_XTKBD is not set | |
| +# CONFIG_KEYBOARD_CAP11XX is not set | |
| +# CONFIG_KEYBOARD_BCM is not set | |
| +# CONFIG_INPUT_MOUSE is not set | |
| +# CONFIG_INPUT_JOYSTICK is not set | |
| +# CONFIG_INPUT_TABLET is not set | |
| +# CONFIG_INPUT_TOUCHSCREEN is not set | |
| +# CONFIG_INPUT_MISC is not set | |
| + | |
| +# | |
| +# Hardware I/O ports | |
| +# | |
| +CONFIG_SERIO=y | |
| +# CONFIG_SERIO_SERPORT is not set | |
| +# CONFIG_SERIO_AMBAKMI is not set | |
| +# CONFIG_SERIO_PCIPS2 is not set | |
| +CONFIG_SERIO_LIBPS2=y | |
| +# CONFIG_SERIO_RAW is not set | |
| +# CONFIG_SERIO_ALTERA_PS2 is not set | |
| +# CONFIG_SERIO_PS2MULT is not set | |
| +# CONFIG_SERIO_ARC_PS2 is not set | |
| +# CONFIG_SERIO_APBPS2 is not set | |
| +# CONFIG_USERIO is not set | |
| +# CONFIG_GAMEPORT is not set | |
| + | |
| +# | |
| +# Character devices | |
| +# | |
| +CONFIG_TTY=y | |
| +# CONFIG_VT is not set | |
| +CONFIG_UNIX98_PTYS=y | |
| +CONFIG_DEVPTS_MULTIPLE_INSTANCES=y | |
| +# CONFIG_LEGACY_PTYS is not set | |
| +# CONFIG_SERIAL_NONSTANDARD is not set | |
| +# CONFIG_NOZOMI is not set | |
| +# CONFIG_N_GSM is not set | |
| +# CONFIG_TRACE_SINK is not set | |
| +CONFIG_DEVMEM=y | |
| +# CONFIG_DEVKMEM is not set | |
| + | |
| +# | |
| +# Serial drivers | |
| +# | |
| +CONFIG_SERIAL_EARLYCON=y | |
| +CONFIG_SERIAL_8250=y | |
| +CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y | |
| +CONFIG_SERIAL_8250_CONSOLE=y | |
| +CONFIG_SERIAL_8250_DMA=y | |
| +# CONFIG_SERIAL_8250_PCI is not set | |
| +CONFIG_SERIAL_8250_NR_UARTS=4 | |
| +CONFIG_SERIAL_8250_RUNTIME_UARTS=2 | |
| +# CONFIG_SERIAL_8250_EXTENDED is not set | |
| +CONFIG_SERIAL_8250_FSL=y | |
| +CONFIG_SERIAL_8250_DW=y | |
| +# CONFIG_SERIAL_8250_EM is not set | |
| +# CONFIG_SERIAL_8250_RT288X is not set | |
| +# CONFIG_SERIAL_8250_INGENIC is not set | |
| +# CONFIG_SERIAL_8250_MID is not set | |
| + | |
| +# | |
| +# Non-8250 serial port support | |
| +# | |
| +# CONFIG_SERIAL_AMBA_PL010 is not set | |
| +CONFIG_SERIAL_AMBA_PL011=y | |
| +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y | |
| +# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set | |
| +# CONFIG_SERIAL_UARTLITE is not set | |
| +CONFIG_SERIAL_CORE=y | |
| +CONFIG_SERIAL_CORE_CONSOLE=y | |
| +# CONFIG_SERIAL_JSM is not set | |
| +CONFIG_SERIAL_OF_PLATFORM=y | |
| +# CONFIG_SERIAL_SCCNXP is not set | |
| +# CONFIG_SERIAL_SC16IS7XX is not set | |
| +# CONFIG_SERIAL_BCM63XX is not set | |
| +# CONFIG_SERIAL_ALTERA_JTAGUART is not set | |
| +# CONFIG_SERIAL_ALTERA_UART is not set | |
| +# CONFIG_SERIAL_XILINX_PS_UART is not set | |
| +# CONFIG_SERIAL_ARC is not set | |
| +# CONFIG_SERIAL_RP2 is not set | |
| +# CONFIG_SERIAL_FSL_LPUART is not set | |
| +# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set | |
| +# CONFIG_SERIAL_ST_ASC is not set | |
| +# CONFIG_SERIAL_STM32 is not set | |
| +# CONFIG_TTY_PRINTK is not set | |
| +# CONFIG_HVC_DCC is not set | |
| +# CONFIG_IPMI_HANDLER is not set | |
| +# CONFIG_HW_RANDOM is not set | |
| +# CONFIG_R3964 is not set | |
| +# CONFIG_APPLICOM is not set | |
| +# CONFIG_RAW_DRIVER is not set | |
| +# CONFIG_TCG_TPM is not set | |
| +CONFIG_DEVPORT=y | |
| +# CONFIG_XILLYBUS is not set | |
| + | |
| +# | |
| +# I2C support | |
| +# | |
| +CONFIG_I2C=y | |
| +CONFIG_I2C_BOARDINFO=y | |
| +CONFIG_I2C_COMPAT=y | |
| +CONFIG_I2C_CHARDEV=y | |
| +# CONFIG_I2C_MUX is not set | |
| +CONFIG_I2C_HELPER_AUTO=y | |
| + | |
| +# | |
| +# I2C Hardware Bus support | |
| +# | |
| + | |
| +# | |
| +# PC SMBus host controller drivers | |
| +# | |
| +# CONFIG_I2C_ALI1535 is not set | |
| +# CONFIG_I2C_ALI1563 is not set | |
| +# CONFIG_I2C_ALI15X3 is not set | |
| +# CONFIG_I2C_AMD756 is not set | |
| +# CONFIG_I2C_AMD8111 is not set | |
| +# CONFIG_I2C_I801 is not set | |
| +# CONFIG_I2C_ISCH is not set | |
| +# CONFIG_I2C_PIIX4 is not set | |
| +# CONFIG_I2C_NFORCE2 is not set | |
| +# CONFIG_I2C_SIS5595 is not set | |
| +# CONFIG_I2C_SIS630 is not set | |
| +# CONFIG_I2C_SIS96X is not set | |
| +# CONFIG_I2C_VIA is not set | |
| +# CONFIG_I2C_VIAPRO is not set | |
| + | |
| +# | |
| +# I2C system bus drivers (mostly embedded / system-on-chip) | |
| +# | |
| +# CONFIG_I2C_CBUS_GPIO is not set | |
| +CONFIG_I2C_DESIGNWARE_CORE=y | |
| +CONFIG_I2C_DESIGNWARE_PLATFORM=y | |
| +# CONFIG_I2C_DESIGNWARE_PCI is not set | |
| +# CONFIG_I2C_EMEV2 is not set | |
| +# CONFIG_I2C_GPIO is not set | |
| +# CONFIG_I2C_NOMADIK is not set | |
| +# CONFIG_I2C_OCORES is not set | |
| +# CONFIG_I2C_PCA_PLATFORM is not set | |
| +# CONFIG_I2C_PXA_PCI is not set | |
| +# CONFIG_I2C_RK3X is not set | |
| +# CONFIG_I2C_SIMTEC is not set | |
| +# CONFIG_I2C_XILINX is not set | |
| + | |
| +# | |
| +# External I2C/SMBus adapter drivers | |
| +# | |
| +# CONFIG_I2C_DIOLAN_U2C is not set | |
| +# CONFIG_I2C_PARPORT_LIGHT is not set | |
| +# CONFIG_I2C_ROBOTFUZZ_OSIF is not set | |
| +# CONFIG_I2C_TAOS_EVM is not set | |
| +# CONFIG_I2C_TINY_USB is not set | |
| + | |
| +# | |
| +# Other I2C/SMBus bus drivers | |
| +# | |
| +# CONFIG_I2C_STUB is not set | |
| +# CONFIG_I2C_SLAVE is not set | |
| +# CONFIG_I2C_DEBUG_CORE is not set | |
| +# CONFIG_I2C_DEBUG_ALGO is not set | |
| +# CONFIG_I2C_DEBUG_BUS is not set | |
| +# CONFIG_SPI is not set | |
| +# CONFIG_SPMI is not set | |
| +# CONFIG_HSI is not set | |
| + | |
| +# | |
| +# PPS support | |
| +# | |
| +# CONFIG_PPS is not set | |
| + | |
| +# | |
| +# PPS generators support | |
| +# | |
| + | |
| +# | |
| +# PTP clock support | |
| +# | |
| +# CONFIG_PTP_1588_CLOCK is not set | |
| + | |
| +# | |
| +# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. | |
| +# | |
| +CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y | |
| +CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y | |
| +CONFIG_GPIOLIB=y | |
| +CONFIG_GPIO_DEVRES=y | |
| +CONFIG_OF_GPIO=y | |
| +CONFIG_GPIOLIB_IRQCHIP=y | |
| +# CONFIG_DEBUG_GPIO is not set | |
| +CONFIG_GPIO_SYSFS=y | |
| +CONFIG_GPIO_GENERIC=y | |
| + | |
| +# | |
| +# Memory mapped GPIO drivers | |
| +# | |
| +# CONFIG_GPIO_74XX_MMIO is not set | |
| +# CONFIG_GPIO_ALTERA is not set | |
| +# CONFIG_GPIO_DWAPB is not set | |
| +# CONFIG_GPIO_EM is not set | |
| +CONFIG_GPIO_GENERIC_PLATFORM=y | |
| +# CONFIG_GPIO_GRGPIO is not set | |
| +CONFIG_GPIO_PL061=y | |
| +# CONFIG_GPIO_SYSCON is not set | |
| +# CONFIG_GPIO_VX855 is not set | |
| +# CONFIG_GPIO_XILINX is not set | |
| +# CONFIG_GPIO_ZEVIO is not set | |
| +# CONFIG_GPIO_ZX is not set | |
| + | |
| +# | |
| +# I2C GPIO expanders | |
| +# | |
| +# CONFIG_GPIO_ADP5588 is not set | |
| +# CONFIG_GPIO_ADNP is not set | |
| +# CONFIG_GPIO_MAX7300 is not set | |
| +# CONFIG_GPIO_MAX732X is not set | |
| +CONFIG_GPIO_PCA953X=y | |
| +# CONFIG_GPIO_PCA953X_IRQ is not set | |
| +# CONFIG_GPIO_PCF857X is not set | |
| +# CONFIG_GPIO_SX150X is not set | |
| + | |
| +# | |
| +# MFD GPIO expanders | |
| +# | |
| + | |
| +# | |
| +# PCI GPIO expanders | |
| +# | |
| +# CONFIG_GPIO_AMD8111 is not set | |
| +# CONFIG_GPIO_BT8XX is not set | |
| +# CONFIG_GPIO_ML_IOH is not set | |
| +# CONFIG_GPIO_RDC321X is not set | |
| + | |
| +# | |
| +# SPI or I2C GPIO expanders | |
| +# | |
| +# CONFIG_GPIO_MCP23S08 is not set | |
| + | |
| +# | |
| +# USB GPIO expanders | |
| +# | |
| +# CONFIG_W1 is not set | |
| +CONFIG_POWER_SUPPLY=y | |
| +# CONFIG_POWER_SUPPLY_DEBUG is not set | |
| +# CONFIG_PDA_POWER is not set | |
| +# CONFIG_TEST_POWER is not set | |
| +# CONFIG_BATTERY_DS2780 is not set | |
| +# CONFIG_BATTERY_DS2781 is not set | |
| +# CONFIG_BATTERY_DS2782 is not set | |
| +# CONFIG_BATTERY_SBS is not set | |
| +# CONFIG_BATTERY_BQ27XXX is not set | |
| +# CONFIG_BATTERY_MAX17040 is not set | |
| +# CONFIG_BATTERY_MAX17042 is not set | |
| +# CONFIG_CHARGER_MAX8903 is not set | |
| +# CONFIG_CHARGER_LP8727 is not set | |
| +# CONFIG_CHARGER_GPIO is not set | |
| +# CONFIG_CHARGER_BQ2415X is not set | |
| +# CONFIG_CHARGER_BQ24190 is not set | |
| +# CONFIG_CHARGER_BQ24735 is not set | |
| +# CONFIG_CHARGER_BQ25890 is not set | |
| +# CONFIG_CHARGER_SMB347 is not set | |
| +# CONFIG_BATTERY_GAUGE_LTC2941 is not set | |
| +# CONFIG_CHARGER_RT9455 is not set | |
| +CONFIG_POWER_RESET=y | |
| +# CONFIG_POWER_RESET_BRCMSTB is not set | |
| +# CONFIG_POWER_RESET_GPIO is not set | |
| +# CONFIG_POWER_RESET_GPIO_RESTART is not set | |
| +# CONFIG_POWER_RESET_LTC2952 is not set | |
| +# CONFIG_POWER_RESET_RESTART is not set | |
| +# CONFIG_POWER_RESET_VERSATILE is not set | |
| +CONFIG_POWER_RESET_VEXPRESS=y | |
| +# CONFIG_POWER_RESET_SYSCON is not set | |
| +# CONFIG_POWER_RESET_SYSCON_POWEROFF is not set | |
| +CONFIG_POWER_RESET_ALPINE=y | |
| +# CONFIG_POWER_AVS is not set | |
| +CONFIG_HWMON=y | |
| +# CONFIG_HWMON_VID is not set | |
| +# CONFIG_HWMON_DEBUG_CHIP is not set | |
| + | |
| +# | |
| +# Native drivers | |
| +# | |
| +# CONFIG_SENSORS_AD7414 is not set | |
| +# CONFIG_SENSORS_AD7418 is not set | |
| +# CONFIG_SENSORS_ADM1021 is not set | |
| +# CONFIG_SENSORS_ADM1025 is not set | |
| +# CONFIG_SENSORS_ADM1026 is not set | |
| +# CONFIG_SENSORS_ADM1029 is not set | |
| +# CONFIG_SENSORS_ADM1031 is not set | |
| +# CONFIG_SENSORS_ADM9240 is not set | |
| +# CONFIG_SENSORS_ADT7410 is not set | |
| +# CONFIG_SENSORS_ADT7411 is not set | |
| +# CONFIG_SENSORS_ADT7462 is not set | |
| +# CONFIG_SENSORS_ADT7470 is not set | |
| +# CONFIG_SENSORS_ADT7475 is not set | |
| +# CONFIG_SENSORS_ASC7621 is not set | |
| +# CONFIG_SENSORS_ATXP1 is not set | |
| +# CONFIG_SENSORS_DS620 is not set | |
| +# CONFIG_SENSORS_DS1621 is not set | |
| +# CONFIG_SENSORS_I5K_AMB is not set | |
| +# CONFIG_SENSORS_F71805F is not set | |
| +# CONFIG_SENSORS_F71882FG is not set | |
| +# CONFIG_SENSORS_F75375S is not set | |
| +# CONFIG_SENSORS_GL518SM is not set | |
| +# CONFIG_SENSORS_GL520SM is not set | |
| +CONFIG_SENSORS_G760A=y | |
| +CONFIG_SENSORS_G762=y | |
| +# CONFIG_SENSORS_GPIO_FAN is not set | |
| +# CONFIG_SENSORS_HIH6130 is not set | |
| +# CONFIG_SENSORS_IT87 is not set | |
| +# CONFIG_SENSORS_JC42 is not set | |
| +# CONFIG_SENSORS_POWR1220 is not set | |
| +# CONFIG_SENSORS_LINEAGE is not set | |
| +# CONFIG_SENSORS_LTC2945 is not set | |
| +# CONFIG_SENSORS_LTC4151 is not set | |
| +# CONFIG_SENSORS_LTC4215 is not set | |
| +# CONFIG_SENSORS_LTC4222 is not set | |
| +# CONFIG_SENSORS_LTC4245 is not set | |
| +# CONFIG_SENSORS_LTC4260 is not set | |
| +# CONFIG_SENSORS_LTC4261 is not set | |
| +# CONFIG_SENSORS_MAX16065 is not set | |
| +# CONFIG_SENSORS_MAX1619 is not set | |
| +# CONFIG_SENSORS_MAX1668 is not set | |
| +# CONFIG_SENSORS_MAX197 is not set | |
| +# CONFIG_SENSORS_MAX6639 is not set | |
| +# CONFIG_SENSORS_MAX6642 is not set | |
| +# CONFIG_SENSORS_MAX6650 is not set | |
| +# CONFIG_SENSORS_MAX6697 is not set | |
| +# CONFIG_SENSORS_MAX31790 is not set | |
| +# CONFIG_SENSORS_HTU21 is not set | |
| +# CONFIG_SENSORS_MCP3021 is not set | |
| +# CONFIG_SENSORS_LM63 is not set | |
| +# CONFIG_SENSORS_LM73 is not set | |
| +# CONFIG_SENSORS_LM75 is not set | |
| +# CONFIG_SENSORS_LM77 is not set | |
| +# CONFIG_SENSORS_LM78 is not set | |
| +# CONFIG_SENSORS_LM80 is not set | |
| +# CONFIG_SENSORS_LM83 is not set | |
| +# CONFIG_SENSORS_LM85 is not set | |
| +# CONFIG_SENSORS_LM87 is not set | |
| +# CONFIG_SENSORS_LM90 is not set | |
| +# CONFIG_SENSORS_LM92 is not set | |
| +# CONFIG_SENSORS_LM93 is not set | |
| +# CONFIG_SENSORS_LM95234 is not set | |
| +# CONFIG_SENSORS_LM95241 is not set | |
| +# CONFIG_SENSORS_LM95245 is not set | |
| +# CONFIG_SENSORS_PC87360 is not set | |
| +# CONFIG_SENSORS_PC87427 is not set | |
| +# CONFIG_SENSORS_NTC_THERMISTOR is not set | |
| +# CONFIG_SENSORS_NCT6683 is not set | |
| +# CONFIG_SENSORS_NCT6775 is not set | |
| +# CONFIG_SENSORS_NCT7802 is not set | |
| +# CONFIG_SENSORS_NCT7904 is not set | |
| +# CONFIG_SENSORS_PCF8591 is not set | |
| +# CONFIG_PMBUS is not set | |
| +# CONFIG_SENSORS_SHT15 is not set | |
| +# CONFIG_SENSORS_SHT21 is not set | |
| +# CONFIG_SENSORS_SHTC1 is not set | |
| +# CONFIG_SENSORS_SIS5595 is not set | |
| +# CONFIG_SENSORS_DME1737 is not set | |
| +# CONFIG_SENSORS_EMC1403 is not set | |
| +# CONFIG_SENSORS_EMC2103 is not set | |
| +# CONFIG_SENSORS_EMC6W201 is not set | |
| +# CONFIG_SENSORS_SMSC47M1 is not set | |
| +# CONFIG_SENSORS_SMSC47M192 is not set | |
| +# CONFIG_SENSORS_SMSC47B397 is not set | |
| +# CONFIG_SENSORS_SCH56XX_COMMON is not set | |
| +# CONFIG_SENSORS_SMM665 is not set | |
| +# CONFIG_SENSORS_ADC128D818 is not set | |
| +# CONFIG_SENSORS_ADS1015 is not set | |
| +# CONFIG_SENSORS_ADS7828 is not set | |
| +# CONFIG_SENSORS_AMC6821 is not set | |
| +# CONFIG_SENSORS_INA209 is not set | |
| +# CONFIG_SENSORS_INA2XX is not set | |
| +# CONFIG_SENSORS_TC74 is not set | |
| +# CONFIG_SENSORS_THMC50 is not set | |
| +# CONFIG_SENSORS_TMP102 is not set | |
| +# CONFIG_SENSORS_TMP103 is not set | |
| +# CONFIG_SENSORS_TMP401 is not set | |
| +# CONFIG_SENSORS_TMP421 is not set | |
| +# CONFIG_SENSORS_VEXPRESS is not set | |
| +# CONFIG_SENSORS_VIA686A is not set | |
| +# CONFIG_SENSORS_VT1211 is not set | |
| +# CONFIG_SENSORS_VT8231 is not set | |
| +# CONFIG_SENSORS_W83781D is not set | |
| +# CONFIG_SENSORS_W83791D is not set | |
| +# CONFIG_SENSORS_W83792D is not set | |
| +# CONFIG_SENSORS_W83793 is not set | |
| +# CONFIG_SENSORS_W83795 is not set | |
| +# CONFIG_SENSORS_W83L785TS is not set | |
| +# CONFIG_SENSORS_W83L786NG is not set | |
| +# CONFIG_SENSORS_W83627HF is not set | |
| +# CONFIG_SENSORS_W83627EHF is not set | |
| +CONFIG_THERMAL=y | |
| +CONFIG_THERMAL_HWMON=y | |
| +# CONFIG_THERMAL_OF is not set | |
| +# CONFIG_THERMAL_WRITABLE_TRIPS is not set | |
| +CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y | |
| +# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set | |
| +# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set | |
| +# CONFIG_THERMAL_DEFAULT_GOV_POWER_ALLOCATOR is not set | |
| +# CONFIG_THERMAL_GOV_FAIR_SHARE is not set | |
| +CONFIG_THERMAL_GOV_STEP_WISE=y | |
| +# CONFIG_THERMAL_GOV_BANG_BANG is not set | |
| +# CONFIG_THERMAL_GOV_USER_SPACE is not set | |
| +# CONFIG_THERMAL_GOV_POWER_ALLOCATOR is not set | |
| +# CONFIG_THERMAL_EMULATION is not set | |
| +CONFIG_AL_THERMAL=y | |
| +# CONFIG_WATCHDOG is not set | |
| +CONFIG_SSB_POSSIBLE=y | |
| + | |
| +# | |
| +# Sonics Silicon Backplane | |
| +# | |
| +# CONFIG_SSB is not set | |
| +CONFIG_BCMA_POSSIBLE=y | |
| + | |
| +# | |
| +# Broadcom specific AMBA | |
| +# | |
| +# CONFIG_BCMA is not set | |
| + | |
| +# | |
| +# Multifunction device drivers | |
| +# | |
| +CONFIG_MFD_CORE=y | |
| +# CONFIG_MFD_AS3711 is not set | |
| +# CONFIG_MFD_AS3722 is not set | |
| +# CONFIG_PMIC_ADP5520 is not set | |
| +# CONFIG_MFD_AAT2870_CORE is not set | |
| +# CONFIG_MFD_ATMEL_FLEXCOM is not set | |
| +# CONFIG_MFD_ATMEL_HLCDC is not set | |
| +# CONFIG_MFD_BCM590XX is not set | |
| +# CONFIG_MFD_AXP20X is not set | |
| +# CONFIG_MFD_CROS_EC is not set | |
| +# CONFIG_MFD_ASIC3 is not set | |
| +# CONFIG_PMIC_DA903X is not set | |
| +# CONFIG_MFD_DA9052_I2C is not set | |
| +# CONFIG_MFD_DA9055 is not set | |
| +# CONFIG_MFD_DA9062 is not set | |
| +# CONFIG_MFD_DA9063 is not set | |
| +# CONFIG_MFD_DA9150 is not set | |
| +# CONFIG_MFD_DLN2 is not set | |
| +# CONFIG_MFD_MC13XXX_I2C is not set | |
| +# CONFIG_MFD_HI6421_PMIC is not set | |
| +# CONFIG_HTC_EGPIO is not set | |
| +# CONFIG_HTC_PASIC3 is not set | |
| +# CONFIG_HTC_I2CPLD is not set | |
| +# CONFIG_LPC_ICH is not set | |
| +# CONFIG_LPC_SCH is not set | |
| +# CONFIG_INTEL_SOC_PMIC is not set | |
| +# CONFIG_MFD_JANZ_CMODIO is not set | |
| +# CONFIG_MFD_KEMPLD is not set | |
| +# CONFIG_MFD_88PM800 is not set | |
| +# CONFIG_MFD_88PM805 is not set | |
| +# CONFIG_MFD_88PM860X is not set | |
| +# CONFIG_MFD_MAX14577 is not set | |
| +# CONFIG_MFD_MAX77686 is not set | |
| +# CONFIG_MFD_MAX77693 is not set | |
| +# CONFIG_MFD_MAX77843 is not set | |
| +# CONFIG_MFD_MAX8907 is not set | |
| +# CONFIG_MFD_MAX8925 is not set | |
| +# CONFIG_MFD_MAX8997 is not set | |
| +# CONFIG_MFD_MAX8998 is not set | |
| +# CONFIG_MFD_MT6397 is not set | |
| +# CONFIG_MFD_MENF21BMC is not set | |
| +# CONFIG_MFD_VIPERBOARD is not set | |
| +# CONFIG_MFD_RETU is not set | |
| +# CONFIG_MFD_PCF50633 is not set | |
| +# CONFIG_MFD_PM8921_CORE is not set | |
| +# CONFIG_MFD_RDC321X is not set | |
| +# CONFIG_MFD_RTSX_PCI is not set | |
| +# CONFIG_MFD_RT5033 is not set | |
| +# CONFIG_MFD_RTSX_USB is not set | |
| +# CONFIG_MFD_RC5T583 is not set | |
| +# CONFIG_MFD_RK808 is not set | |
| +# CONFIG_MFD_RN5T618 is not set | |
| +# CONFIG_MFD_SEC_CORE is not set | |
| +# CONFIG_MFD_SI476X_CORE is not set | |
| +# CONFIG_MFD_SM501 is not set | |
| +# CONFIG_MFD_SKY81452 is not set | |
| +# CONFIG_MFD_SMSC is not set | |
| +# CONFIG_ABX500_CORE is not set | |
| +# CONFIG_MFD_STMPE is not set | |
| +CONFIG_MFD_SYSCON=y | |
| +# CONFIG_MFD_TI_AM335X_TSCADC is not set | |
| +# CONFIG_MFD_LP3943 is not set | |
| +# CONFIG_MFD_LP8788 is not set | |
| +# CONFIG_MFD_PALMAS is not set | |
| +# CONFIG_TPS6105X is not set | |
| +# CONFIG_TPS65010 is not set | |
| +# CONFIG_TPS6507X is not set | |
| +# CONFIG_MFD_TPS65090 is not set | |
| +# CONFIG_MFD_TPS65217 is not set | |
| +# CONFIG_MFD_TPS65218 is not set | |
| +# CONFIG_MFD_TPS6586X is not set | |
| +# CONFIG_MFD_TPS65910 is not set | |
| +# CONFIG_MFD_TPS65912 is not set | |
| +# CONFIG_MFD_TPS65912_I2C is not set | |
| +# CONFIG_MFD_TPS80031 is not set | |
| +# CONFIG_TWL4030_CORE is not set | |
| +# CONFIG_TWL6040_CORE is not set | |
| +# CONFIG_MFD_WL1273_CORE is not set | |
| +# CONFIG_MFD_LM3533 is not set | |
| +# CONFIG_MFD_TC3589X is not set | |
| +# CONFIG_MFD_TMIO is not set | |
| +# CONFIG_MFD_T7L66XB is not set | |
| +# CONFIG_MFD_TC6387XB is not set | |
| +# CONFIG_MFD_TC6393XB is not set | |
| +# CONFIG_MFD_VX855 is not set | |
| +# CONFIG_MFD_ARIZONA_I2C is not set | |
| +# CONFIG_MFD_WM8400 is not set | |
| +# CONFIG_MFD_WM831X_I2C is not set | |
| +# CONFIG_MFD_WM8350_I2C is not set | |
| +# CONFIG_MFD_WM8994 is not set | |
| +CONFIG_MFD_VEXPRESS_SYSREG=y | |
| +# CONFIG_REGULATOR is not set | |
| +# CONFIG_MEDIA_SUPPORT is not set | |
| + | |
| +# | |
| +# Graphics support | |
| +# | |
| +# CONFIG_VGA_ARB is not set | |
| +# CONFIG_DRM is not set | |
| + | |
| +# | |
| +# Frame buffer Devices | |
| +# | |
| +# CONFIG_FB is not set | |
| +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set | |
| +# CONFIG_VGASTATE is not set | |
| +# CONFIG_SOUND is not set | |
| + | |
| +# | |
| +# HID support | |
| +# | |
| +CONFIG_HID=y | |
| +# CONFIG_HID_BATTERY_STRENGTH is not set | |
| +# CONFIG_HIDRAW is not set | |
| +# CONFIG_UHID is not set | |
| +# CONFIG_HID_GENERIC is not set | |
| + | |
| +# | |
| +# Special HID drivers | |
| +# | |
| +# CONFIG_HID_A4TECH is not set | |
| +# CONFIG_HID_ACRUX is not set | |
| +# CONFIG_HID_APPLE is not set | |
| +# CONFIG_HID_APPLEIR is not set | |
| +# CONFIG_HID_AUREAL is not set | |
| +# CONFIG_HID_BELKIN is not set | |
| +# CONFIG_HID_BETOP_FF is not set | |
| +# CONFIG_HID_CHERRY is not set | |
| +# CONFIG_HID_CHICONY is not set | |
| +# CONFIG_HID_CORSAIR is not set | |
| +# CONFIG_HID_CP2112 is not set | |
| +# CONFIG_HID_CYPRESS is not set | |
| +# CONFIG_HID_DRAGONRISE is not set | |
| +# CONFIG_HID_EMS_FF is not set | |
| +# CONFIG_HID_ELECOM is not set | |
| +# CONFIG_HID_ELO is not set | |
| +# CONFIG_HID_EZKEY is not set | |
| +# CONFIG_HID_GEMBIRD is not set | |
| +# CONFIG_HID_GFRM is not set | |
| +# CONFIG_HID_HOLTEK is not set | |
| +# CONFIG_HID_GT683R is not set | |
| +# CONFIG_HID_KEYTOUCH is not set | |
| +# CONFIG_HID_KYE is not set | |
| +# CONFIG_HID_UCLOGIC is not set | |
| +# CONFIG_HID_WALTOP is not set | |
| +# CONFIG_HID_GYRATION is not set | |
| +# CONFIG_HID_ICADE is not set | |
| +# CONFIG_HID_TWINHAN is not set | |
| +# CONFIG_HID_KENSINGTON is not set | |
| +# CONFIG_HID_LCPOWER is not set | |
| +# CONFIG_HID_LENOVO is not set | |
| +# CONFIG_HID_LOGITECH is not set | |
| +# CONFIG_HID_MAGICMOUSE is not set | |
| +# CONFIG_HID_MICROSOFT is not set | |
| +# CONFIG_HID_MONTEREY is not set | |
| +# CONFIG_HID_MULTITOUCH is not set | |
| +# CONFIG_HID_NTRIG is not set | |
| +# CONFIG_HID_ORTEK is not set | |
| +# CONFIG_HID_PANTHERLORD is not set | |
| +# CONFIG_HID_PENMOUNT is not set | |
| +# CONFIG_HID_PETALYNX is not set | |
| +# CONFIG_HID_PICOLCD is not set | |
| +# CONFIG_HID_PLANTRONICS is not set | |
| +# CONFIG_HID_PRIMAX is not set | |
| +# CONFIG_HID_ROCCAT is not set | |
| +# CONFIG_HID_SAITEK is not set | |
| +# CONFIG_HID_SAMSUNG is not set | |
| +# CONFIG_HID_SONY is not set | |
| +# CONFIG_HID_SPEEDLINK is not set | |
| +# CONFIG_HID_STEELSERIES is not set | |
| +# CONFIG_HID_SUNPLUS is not set | |
| +# CONFIG_HID_RMI is not set | |
| +# CONFIG_HID_GREENASIA is not set | |
| +# CONFIG_HID_SMARTJOYPLUS is not set | |
| +# CONFIG_HID_TIVO is not set | |
| +# CONFIG_HID_TOPSEED is not set | |
| +# CONFIG_HID_THINGM is not set | |
| +# CONFIG_HID_THRUSTMASTER is not set | |
| +# CONFIG_HID_WACOM is not set | |
| +# CONFIG_HID_WIIMOTE is not set | |
| +# CONFIG_HID_XINMO is not set | |
| +# CONFIG_HID_ZEROPLUS is not set | |
| +# CONFIG_HID_ZYDACRON is not set | |
| +# CONFIG_HID_SENSOR_HUB is not set | |
| + | |
| +# | |
| +# USB HID support | |
| +# | |
| +CONFIG_USB_HID=y | |
| +# CONFIG_HID_PID is not set | |
| +CONFIG_USB_HIDDEV=y | |
| + | |
| +# | |
| +# I2C HID support | |
| +# | |
| +# CONFIG_I2C_HID is not set | |
| +CONFIG_USB_OHCI_LITTLE_ENDIAN=y | |
| +CONFIG_USB_SUPPORT=y | |
| +CONFIG_USB_COMMON=y | |
| +CONFIG_USB_ARCH_HAS_HCD=y | |
| +CONFIG_USB=y | |
| +# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set | |
| + | |
| +# | |
| +# Miscellaneous USB options | |
| +# | |
| +CONFIG_USB_DEFAULT_PERSIST=y | |
| +# CONFIG_USB_DYNAMIC_MINORS is not set | |
| +# CONFIG_USB_OTG is not set | |
| +# CONFIG_USB_OTG_WHITELIST is not set | |
| +# CONFIG_USB_OTG_BLACKLIST_HUB is not set | |
| +# CONFIG_USB_ULPI_BUS is not set | |
| +# CONFIG_USB_MON is not set | |
| +# CONFIG_USB_WUSB_CBAF is not set | |
| + | |
| +# | |
| +# USB Host Controller Drivers | |
| +# | |
| +# CONFIG_USB_C67X00_HCD is not set | |
| +CONFIG_USB_XHCI_HCD=y | |
| +CONFIG_USB_XHCI_PCI=y | |
| +CONFIG_USB_XHCI_PLATFORM=y | |
| +CONFIG_USB_EHCI_HCD=y | |
| +CONFIG_USB_EHCI_ROOT_HUB_TT=y | |
| +CONFIG_USB_EHCI_TT_NEWSCHED=y | |
| +CONFIG_USB_EHCI_PCI=y | |
| +# CONFIG_USB_EHCI_HCD_PLATFORM is not set | |
| +# CONFIG_USB_OXU210HP_HCD is not set | |
| +# CONFIG_USB_ISP116X_HCD is not set | |
| +# CONFIG_USB_ISP1362_HCD is not set | |
| +# CONFIG_USB_FOTG210_HCD is not set | |
| +# CONFIG_USB_OHCI_HCD is not set | |
| +# CONFIG_USB_UHCI_HCD is not set | |
| +# CONFIG_USB_SL811_HCD is not set | |
| +# CONFIG_USB_R8A66597_HCD is not set | |
| +# CONFIG_USB_HCD_TEST_MODE is not set | |
| + | |
| +# | |
| +# USB Device Class drivers | |
| +# | |
| +CONFIG_USB_ACM=y | |
| +CONFIG_USB_PRINTER=y | |
| +# CONFIG_USB_WDM is not set | |
| +# CONFIG_USB_TMC is not set | |
| + | |
| +# | |
| +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may | |
| +# | |
| + | |
| +# | |
| +# also be needed; see USB_STORAGE Help for more info | |
| +# | |
| +CONFIG_USB_STORAGE=y | |
| +# CONFIG_USB_STORAGE_DEBUG is not set | |
| +# CONFIG_USB_STORAGE_REALTEK is not set | |
| +CONFIG_USB_STORAGE_DATAFAB=y | |
| +CONFIG_USB_STORAGE_FREECOM=y | |
| +# CONFIG_USB_STORAGE_ISD200 is not set | |
| +# CONFIG_USB_STORAGE_USBAT is not set | |
| +CONFIG_USB_STORAGE_SDDR09=y | |
| +CONFIG_USB_STORAGE_SDDR55=y | |
| +CONFIG_USB_STORAGE_JUMPSHOT=y | |
| +# CONFIG_USB_STORAGE_ALAUDA is not set | |
| +# CONFIG_USB_STORAGE_ONETOUCH is not set | |
| +# CONFIG_USB_STORAGE_KARMA is not set | |
| +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set | |
| +# CONFIG_USB_STORAGE_ENE_UB6250 is not set | |
| +# CONFIG_USB_UAS is not set | |
| + | |
| +# | |
| +# USB Imaging devices | |
| +# | |
| +# CONFIG_USB_MDC800 is not set | |
| +# CONFIG_USB_MICROTEK is not set | |
| +# CONFIG_USBIP_CORE is not set | |
| +# CONFIG_USB_MUSB_HDRC is not set | |
| +CONFIG_USB_DWC3=y | |
| +CONFIG_USB_DWC3_HOST=y | |
| + | |
| +# | |
| +# Platform Glue Driver Support | |
| +# | |
| +CONFIG_USB_DWC3_PCI=y | |
| +# CONFIG_USB_DWC2 is not set | |
| +# CONFIG_USB_CHIPIDEA is not set | |
| +# CONFIG_USB_ISP1760 is not set | |
| + | |
| +# | |
| +# USB port drivers | |
| +# | |
| +CONFIG_USB_SERIAL=m | |
| +CONFIG_USB_SERIAL_GENERIC=y | |
| +# CONFIG_USB_SERIAL_SIMPLE is not set | |
| +# CONFIG_USB_SERIAL_AIRCABLE is not set | |
| +# CONFIG_USB_SERIAL_ARK3116 is not set | |
| +# CONFIG_USB_SERIAL_BELKIN is not set | |
| +# CONFIG_USB_SERIAL_CH341 is not set | |
| +# CONFIG_USB_SERIAL_WHITEHEAT is not set | |
| +# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set | |
| +# CONFIG_USB_SERIAL_CP210X is not set | |
| +# CONFIG_USB_SERIAL_CYPRESS_M8 is not set | |
| +# CONFIG_USB_SERIAL_EMPEG is not set | |
| +CONFIG_USB_SERIAL_FTDI_SIO=m | |
| +# CONFIG_USB_SERIAL_VISOR is not set | |
| +# CONFIG_USB_SERIAL_IPAQ is not set | |
| +# CONFIG_USB_SERIAL_IR is not set | |
| +# CONFIG_USB_SERIAL_EDGEPORT is not set | |
| +# CONFIG_USB_SERIAL_EDGEPORT_TI is not set | |
| +# CONFIG_USB_SERIAL_F81232 is not set | |
| +# CONFIG_USB_SERIAL_GARMIN is not set | |
| +# CONFIG_USB_SERIAL_IPW is not set | |
| +# CONFIG_USB_SERIAL_IUU is not set | |
| +# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set | |
| +# CONFIG_USB_SERIAL_KEYSPAN is not set | |
| +# CONFIG_USB_SERIAL_KLSI is not set | |
| +# CONFIG_USB_SERIAL_KOBIL_SCT is not set | |
| +# CONFIG_USB_SERIAL_MCT_U232 is not set | |
| +# CONFIG_USB_SERIAL_METRO is not set | |
| +# CONFIG_USB_SERIAL_MOS7720 is not set | |
| +# CONFIG_USB_SERIAL_MOS7840 is not set | |
| +# CONFIG_USB_SERIAL_MXUPORT is not set | |
| +# CONFIG_USB_SERIAL_NAVMAN is not set | |
| +CONFIG_USB_SERIAL_PL2303=m | |
| +# CONFIG_USB_SERIAL_OTI6858 is not set | |
| +# CONFIG_USB_SERIAL_QCAUX is not set | |
| +# CONFIG_USB_SERIAL_QUALCOMM is not set | |
| +# CONFIG_USB_SERIAL_SPCP8X5 is not set | |
| +# CONFIG_USB_SERIAL_SAFE is not set | |
| +# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set | |
| +# CONFIG_USB_SERIAL_SYMBOL is not set | |
| +# CONFIG_USB_SERIAL_TI is not set | |
| +# CONFIG_USB_SERIAL_CYBERJACK is not set | |
| +# CONFIG_USB_SERIAL_XIRCOM is not set | |
| +# CONFIG_USB_SERIAL_OPTION is not set | |
| +# CONFIG_USB_SERIAL_OMNINET is not set | |
| +# CONFIG_USB_SERIAL_OPTICON is not set | |
| +# CONFIG_USB_SERIAL_XSENS_MT is not set | |
| +# CONFIG_USB_SERIAL_WISHBONE is not set | |
| +# CONFIG_USB_SERIAL_SSU100 is not set | |
| +# CONFIG_USB_SERIAL_QT2 is not set | |
| +# CONFIG_USB_SERIAL_DEBUG is not set | |
| + | |
| +# | |
| +# USB Miscellaneous drivers | |
| +# | |
| +# CONFIG_USB_EMI62 is not set | |
| +# CONFIG_USB_EMI26 is not set | |
| +# CONFIG_USB_ADUTUX is not set | |
| +# CONFIG_USB_SEVSEG is not set | |
| +# CONFIG_USB_RIO500 is not set | |
| +# CONFIG_USB_LEGOTOWER is not set | |
| +# CONFIG_USB_LCD is not set | |
| +# CONFIG_USB_LED is not set | |
| +# CONFIG_USB_CYPRESS_CY7C63 is not set | |
| +# CONFIG_USB_CYTHERM is not set | |
| +# CONFIG_USB_IDMOUSE is not set | |
| +# CONFIG_USB_FTDI_ELAN is not set | |
| +# CONFIG_USB_APPLEDISPLAY is not set | |
| +# CONFIG_USB_SISUSBVGA is not set | |
| +# CONFIG_USB_LD is not set | |
| +# CONFIG_USB_TRANCEVIBRATOR is not set | |
| +# CONFIG_USB_IOWARRIOR is not set | |
| +# CONFIG_USB_TEST is not set | |
| +# CONFIG_USB_EHSET_TEST_FIXTURE is not set | |
| +# CONFIG_USB_ISIGHTFW is not set | |
| +# CONFIG_USB_YUREX is not set | |
| +# CONFIG_USB_EZUSB_FX2 is not set | |
| +# CONFIG_USB_HSIC_USB3503 is not set | |
| +# CONFIG_USB_LINK_LAYER_TEST is not set | |
| + | |
| +# | |
| +# USB Physical Layer drivers | |
| +# | |
| +# CONFIG_USB_PHY is not set | |
| +# CONFIG_NOP_USB_XCEIV is not set | |
| +# CONFIG_AM335X_PHY_USB is not set | |
| +# CONFIG_USB_GPIO_VBUS is not set | |
| +# CONFIG_USB_ISP1301 is not set | |
| +# CONFIG_USB_ULPI is not set | |
| +# CONFIG_USB_GADGET is not set | |
| +# CONFIG_USB_LED_TRIG is not set | |
| +# CONFIG_UWB is not set | |
| +# CONFIG_MMC is not set | |
| +# CONFIG_MEMSTICK is not set | |
| +CONFIG_NEW_LEDS=y | |
| +CONFIG_LEDS_CLASS=y | |
| +# CONFIG_LEDS_CLASS_FLASH is not set | |
| + | |
| +# | |
| +# LED drivers | |
| +# | |
| +# CONFIG_LEDS_BCM6328 is not set | |
| +# CONFIG_LEDS_BCM6358 is not set | |
| +# CONFIG_LEDS_LM3530 is not set | |
| +# CONFIG_LEDS_LM3642 is not set | |
| +# CONFIG_LEDS_PCA9532 is not set | |
| +CONFIG_LEDS_GPIO=y | |
| +# CONFIG_LEDS_LP3944 is not set | |
| +# CONFIG_LEDS_LP5521 is not set | |
| +# CONFIG_LEDS_LP5523 is not set | |
| +# CONFIG_LEDS_LP5562 is not set | |
| +# CONFIG_LEDS_LP8501 is not set | |
| +# CONFIG_LEDS_LP8860 is not set | |
| +# CONFIG_LEDS_PCA955X is not set | |
| +# CONFIG_LEDS_PCA963X is not set | |
| +# CONFIG_LEDS_BD2802 is not set | |
| +# CONFIG_LEDS_LT3593 is not set | |
| +# CONFIG_LEDS_TCA6507 is not set | |
| +# CONFIG_LEDS_TLC591XX is not set | |
| +# CONFIG_LEDS_LM355x is not set | |
| + | |
| +# | |
| +# LED driver for blink(1) USB RGB LED is under Special HID drivers (HID_THINGM) | |
| +# | |
| +# CONFIG_LEDS_BLINKM is not set | |
| +# CONFIG_LEDS_SYSCON is not set | |
| + | |
| +# | |
| +# LED Triggers | |
| +# | |
| +CONFIG_LEDS_TRIGGERS=y | |
| +CONFIG_LEDS_TRIGGER_TIMER=y | |
| +# CONFIG_LEDS_TRIGGER_ONESHOT is not set | |
| +# CONFIG_LEDS_TRIGGER_HEARTBEAT is not set | |
| +# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set | |
| +# CONFIG_LEDS_TRIGGER_CPU is not set | |
| +CONFIG_LEDS_TRIGGER_GPIO=y | |
| +# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set | |
| + | |
| +# | |
| +# iptables trigger is under Netfilter config (LED target) | |
| +# | |
| +# CONFIG_LEDS_TRIGGER_TRANSIENT is not set | |
| +# CONFIG_LEDS_TRIGGER_CAMERA is not set | |
| +# CONFIG_ACCESSIBILITY is not set | |
| +# CONFIG_INFINIBAND is not set | |
| +CONFIG_EDAC_ATOMIC_SCRUB=y | |
| +CONFIG_EDAC_SUPPORT=y | |
| +CONFIG_EDAC=y | |
| +# CONFIG_EDAC_LEGACY_SYSFS is not set | |
| +# CONFIG_EDAC_DEBUG is not set | |
| +CONFIG_EDAC_MM_EDAC=y | |
| +CONFIG_RTC_LIB=y | |
| +CONFIG_RTC_CLASS=y | |
| +CONFIG_RTC_HCTOSYS=y | |
| +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" | |
| +CONFIG_RTC_SYSTOHC=y | |
| +CONFIG_RTC_SYSTOHC_DEVICE="rtc0" | |
| +# CONFIG_RTC_DEBUG is not set | |
| + | |
| +# | |
| +# RTC interfaces | |
| +# | |
| +CONFIG_RTC_INTF_SYSFS=y | |
| +CONFIG_RTC_INTF_PROC=y | |
| +CONFIG_RTC_INTF_DEV=y | |
| +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set | |
| +# CONFIG_RTC_DRV_TEST is not set | |
| + | |
| +# | |
| +# I2C RTC drivers | |
| +# | |
| +# CONFIG_RTC_DRV_ABB5ZES3 is not set | |
| +# CONFIG_RTC_DRV_ABX80X is not set | |
| +CONFIG_RTC_DRV_DS1307=y | |
| +# CONFIG_RTC_DRV_DS1374 is not set | |
| +# CONFIG_RTC_DRV_DS1672 is not set | |
| +# CONFIG_RTC_DRV_DS3232 is not set | |
| +# CONFIG_RTC_DRV_HYM8563 is not set | |
| +# CONFIG_RTC_DRV_MAX6900 is not set | |
| +# CONFIG_RTC_DRV_RS5C372 is not set | |
| +# CONFIG_RTC_DRV_ISL1208 is not set | |
| +# CONFIG_RTC_DRV_ISL12022 is not set | |
| +# CONFIG_RTC_DRV_ISL12057 is not set | |
| +# CONFIG_RTC_DRV_X1205 is not set | |
| +# CONFIG_RTC_DRV_PCF2127 is not set | |
| +# CONFIG_RTC_DRV_PCF8523 is not set | |
| +# CONFIG_RTC_DRV_PCF8563 is not set | |
| +# CONFIG_RTC_DRV_PCF85063 is not set | |
| +# CONFIG_RTC_DRV_PCF8583 is not set | |
| +# CONFIG_RTC_DRV_M41T80 is not set | |
| +# CONFIG_RTC_DRV_BQ32K is not set | |
| +# CONFIG_RTC_DRV_S35390A is not set | |
| +# CONFIG_RTC_DRV_FM3130 is not set | |
| +# CONFIG_RTC_DRV_RX8581 is not set | |
| +# CONFIG_RTC_DRV_RX8025 is not set | |
| +# CONFIG_RTC_DRV_EM3027 is not set | |
| +# CONFIG_RTC_DRV_RV3029C2 is not set | |
| +# CONFIG_RTC_DRV_RV8803 is not set | |
| + | |
| +# | |
| +# SPI RTC drivers | |
| +# | |
| + | |
| +# | |
| +# Platform RTC drivers | |
| +# | |
| +# CONFIG_RTC_DRV_CMOS is not set | |
| +# CONFIG_RTC_DRV_DS1286 is not set | |
| +# CONFIG_RTC_DRV_DS1511 is not set | |
| +# CONFIG_RTC_DRV_DS1553 is not set | |
| +# CONFIG_RTC_DRV_DS1685_FAMILY is not set | |
| +# CONFIG_RTC_DRV_DS1742 is not set | |
| +# CONFIG_RTC_DRV_DS2404 is not set | |
| +# CONFIG_RTC_DRV_STK17TA8 is not set | |
| +# CONFIG_RTC_DRV_M48T86 is not set | |
| +# CONFIG_RTC_DRV_M48T35 is not set | |
| +# CONFIG_RTC_DRV_M48T59 is not set | |
| +# CONFIG_RTC_DRV_MSM6242 is not set | |
| +# CONFIG_RTC_DRV_BQ4802 is not set | |
| +# CONFIG_RTC_DRV_RP5C01 is not set | |
| +# CONFIG_RTC_DRV_V3020 is not set | |
| +# CONFIG_RTC_DRV_ZYNQMP is not set | |
| + | |
| +# | |
| +# on-CPU RTC drivers | |
| +# | |
| +# CONFIG_RTC_DRV_PL030 is not set | |
| +# CONFIG_RTC_DRV_PL031 is not set | |
| +# CONFIG_RTC_DRV_SNVS is not set | |
| + | |
| +# | |
| +# HID Sensor RTC drivers | |
| +# | |
| +# CONFIG_RTC_DRV_HID_SENSOR_TIME is not set | |
| +CONFIG_DMADEVICES=y | |
| +# CONFIG_DMADEVICES_DEBUG is not set | |
| + | |
| +# | |
| +# DMA Devices | |
| +# | |
| +CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=y | |
| +CONFIG_DMA_ENGINE=y | |
| +CONFIG_DMA_OF=y | |
| +# CONFIG_AMBA_PL08X is not set | |
| +# CONFIG_FSL_EDMA is not set | |
| +# CONFIG_INTEL_IDMA64 is not set | |
| +# CONFIG_NBPFAXI_DMA is not set | |
| +# CONFIG_PL330_DMA is not set | |
| +# CONFIG_DW_DMAC is not set | |
| +# CONFIG_DW_DMAC_PCI is not set | |
| + | |
| +# | |
| +# DMA Clients | |
| +# | |
| +CONFIG_ASYNC_TX_DMA=y | |
| +# CONFIG_DMATEST is not set | |
| +CONFIG_DMA_ENGINE_RAID=y | |
| +CONFIG_AL_DMA=y | |
| +# CONFIG_AL_DMA_STATS is not set | |
| +CONFIG_AL_DMA_PCI_IOV=y | |
| +# CONFIG_AUXDISPLAY is not set | |
| +# CONFIG_UIO is not set | |
| +# CONFIG_VIRT_DRIVERS is not set | |
| + | |
| +# | |
| +# Virtio drivers | |
| +# | |
| +# CONFIG_VIRTIO_PCI is not set | |
| +# CONFIG_VIRTIO_MMIO is not set | |
| + | |
| +# | |
| +# Microsoft Hyper-V guest support | |
| +# | |
| +# CONFIG_STAGING is not set | |
| +# CONFIG_CHROME_PLATFORMS is not set | |
| +CONFIG_READYNAS_PLATFORMS=y | |
| +CONFIG_GPIO_PWR=y | |
| +CONFIG_HD44780_LCD=y | |
| +CONFIG_READYNAS_LCD=y | |
| +CONFIG_CLKDEV_LOOKUP=y | |
| +CONFIG_HAVE_CLK_PREPARE=y | |
| +CONFIG_COMMON_CLK=y | |
| + | |
| +# | |
| +# Common Clock Framework | |
| +# | |
| +# CONFIG_COMMON_CLK_SI5351 is not set | |
| +# CONFIG_COMMON_CLK_SI514 is not set | |
| +# CONFIG_COMMON_CLK_SI570 is not set | |
| +# CONFIG_COMMON_CLK_CDCE925 is not set | |
| +# CONFIG_CLK_QORIQ is not set | |
| +# CONFIG_COMMON_CLK_PXA is not set | |
| +# CONFIG_COMMON_CLK_CDCE706 is not set | |
| + | |
| +# | |
| +# Hardware Spinlock drivers | |
| +# | |
| + | |
| +# | |
| +# Clock Source drivers | |
| +# | |
| +CONFIG_CLKSRC_OF=y | |
| +CONFIG_CLKSRC_PROBE=y | |
| +CONFIG_CLKSRC_MMIO=y | |
| +CONFIG_ARM_ARCH_TIMER=y | |
| +CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y | |
| +# CONFIG_ARM_TIMER_SP804 is not set | |
| +# CONFIG_ATMEL_PIT is not set | |
| +# CONFIG_SH_TIMER_CMT is not set | |
| +# CONFIG_SH_TIMER_MTU2 is not set | |
| +# CONFIG_SH_TIMER_TMU is not set | |
| +# CONFIG_EM_TIMER_STI is not set | |
| +# CONFIG_MAILBOX is not set | |
| +# CONFIG_IOMMU_SUPPORT is not set | |
| + | |
| +# | |
| +# Remoteproc drivers | |
| +# | |
| +# CONFIG_STE_MODEM_RPROC is not set | |
| + | |
| +# | |
| +# Rpmsg drivers | |
| +# | |
| + | |
| +# | |
| +# SOC (System On Chip) specific Drivers | |
| +# | |
| +# CONFIG_SOC_BRCMSTB is not set | |
| +# CONFIG_SUNXI_SRAM is not set | |
| +# CONFIG_SOC_TI is not set | |
| +# CONFIG_PM_DEVFREQ is not set | |
| +# CONFIG_EXTCON is not set | |
| +# CONFIG_MEMORY is not set | |
| +# CONFIG_IIO is not set | |
| +# CONFIG_NTB is not set | |
| +# CONFIG_VME_BUS is not set | |
| +# CONFIG_PWM is not set | |
| +CONFIG_IRQCHIP=y | |
| +CONFIG_ARM_GIC=y | |
| +# CONFIG_IPACK_BUS is not set | |
| +# CONFIG_RESET_CONTROLLER is not set | |
| +# CONFIG_FMC is not set | |
| + | |
| +# | |
| +# PHY Subsystem | |
| +# | |
| +# CONFIG_GENERIC_PHY is not set | |
| +# CONFIG_PHY_PXA_28NM_HSIC is not set | |
| +# CONFIG_PHY_PXA_28NM_USB2 is not set | |
| +# CONFIG_BCM_KONA_USB2_PHY is not set | |
| +# CONFIG_POWERCAP is not set | |
| +# CONFIG_MCB is not set | |
| + | |
| +# | |
| +# Performance monitor support | |
| +# | |
| +CONFIG_RAS=y | |
| +# CONFIG_THUNDERBOLT is not set | |
| + | |
| +# | |
| +# Android | |
| +# | |
| +# CONFIG_ANDROID is not set | |
| +# CONFIG_LIBNVDIMM is not set | |
| +# CONFIG_NVMEM is not set | |
| +# CONFIG_STM is not set | |
| +# CONFIG_STM_DUMMY is not set | |
| +# CONFIG_STM_SOURCE_CONSOLE is not set | |
| +# CONFIG_INTEL_TH is not set | |
| + | |
| +# | |
| +# FPGA Configuration Support | |
| +# | |
| +# CONFIG_FPGA is not set | |
| + | |
| +# | |
| +# Firmware Drivers | |
| +# | |
| +# CONFIG_FIRMWARE_MEMMAP is not set | |
| + | |
| +# | |
| +# File systems | |
| +# | |
| +CONFIG_DCACHE_WORD_ACCESS=y | |
| +CONFIG_LFS_ON_32CPU=y | |
| +# CONFIG_EXT2_FS is not set | |
| +# CONFIG_EXT3_FS is not set | |
| +CONFIG_EXT4_FS=y | |
| +CONFIG_EXT4_USE_FOR_EXT2=y | |
| +CONFIG_EXT4_FS_POSIX_ACL=y | |
| +CONFIG_EXT4_FS_SECURITY=y | |
| +# CONFIG_EXT4_ENCRYPTION is not set | |
| +# CONFIG_EXT4_DEBUG is not set | |
| +CONFIG_JBD2=y | |
| +# CONFIG_JBD2_DEBUG is not set | |
| +CONFIG_FS_MBCACHE=y | |
| +# CONFIG_REISERFS_FS is not set | |
| +# CONFIG_JFS_FS is not set | |
| +CONFIG_XFS_FS=m | |
| +CONFIG_XFS_QUOTA=y | |
| +CONFIG_XFS_POSIX_ACL=y | |
| +CONFIG_XFS_RT=y | |
| +# CONFIG_XFS_WARN is not set | |
| +# CONFIG_XFS_DEBUG is not set | |
| +# CONFIG_GFS2_FS is not set | |
| +# CONFIG_OCFS2_FS is not set | |
| +CONFIG_BTRFS_FS=y | |
| +CONFIG_BTRFS_FS_POSIX_ACL=y | |
| +# CONFIG_BTRFS_FS_CHECK_INTEGRITY is not set | |
| +# CONFIG_BTRFS_FS_RUN_SANITY_TESTS is not set | |
| +# CONFIG_BTRFS_DEBUG is not set | |
| +# CONFIG_BTRFS_ASSERT is not set | |
| +CONFIG_BTRFS_MDCSREPAIR=y | |
| +CONFIG_BTRFS_FIEMAP_PHYSICAL=y | |
| +# CONFIG_NILFS2_FS is not set | |
| +# CONFIG_F2FS_FS is not set | |
| +CONFIG_FS_POSIX_ACL=y | |
| +CONFIG_EXPORTFS=y | |
| +CONFIG_FILE_LOCKING=y | |
| +CONFIG_FSNOTIFY=y | |
| +CONFIG_DNOTIFY=y | |
| +CONFIG_INOTIFY_USER=y | |
| +CONFIG_FANOTIFY=y | |
| +CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y | |
| +CONFIG_QUOTA=y | |
| +CONFIG_QUOTA_NETLINK_INTERFACE=y | |
| +# CONFIG_PRINT_QUOTA_WARNING is not set | |
| +# CONFIG_QUOTA_DEBUG is not set | |
| +CONFIG_QUOTA_TREE=y | |
| +# CONFIG_QFMT_V1 is not set | |
| +CONFIG_QFMT_V2=y | |
| +CONFIG_QUOTACTL=y | |
| +CONFIG_AUTOFS4_FS=y | |
| +CONFIG_FUSE_FS=y | |
| +# CONFIG_CUSE is not set | |
| +CONFIG_OVERLAY_FS=y | |
| + | |
| +# | |
| +# Caches | |
| +# | |
| +CONFIG_FSCACHE=y | |
| +# CONFIG_FSCACHE_STATS is not set | |
| +# CONFIG_FSCACHE_HISTOGRAM is not set | |
| +# CONFIG_FSCACHE_DEBUG is not set | |
| +# CONFIG_FSCACHE_OBJECT_LIST is not set | |
| +# CONFIG_CACHEFILES is not set | |
| + | |
| +# | |
| +# CD-ROM/DVD Filesystems | |
| +# | |
| +CONFIG_ISO9660_FS=m | |
| +CONFIG_JOLIET=y | |
| +# CONFIG_ZISOFS is not set | |
| +CONFIG_UDF_FS=m | |
| +CONFIG_UDF_NLS=y | |
| + | |
| +# | |
| +# DOS/FAT/NT Filesystems | |
| +# | |
| +CONFIG_FAT_FS=y | |
| +CONFIG_MSDOS_FS=y | |
| +CONFIG_VFAT_FS=y | |
| +CONFIG_FAT_DEFAULT_CODEPAGE=437 | |
| +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" | |
| +# CONFIG_NTFS_FS is not set | |
| + | |
| +# | |
| +# Pseudo filesystems | |
| +# | |
| +CONFIG_PROC_FS=y | |
| +CONFIG_PROC_SYSCTL=y | |
| +CONFIG_PROC_PAGE_MONITOR=y | |
| +# CONFIG_PROC_CHILDREN is not set | |
| +CONFIG_KERNFS=y | |
| +CONFIG_SYSFS=y | |
| +CONFIG_TMPFS=y | |
| +CONFIG_TMPFS_POSIX_ACL=y | |
| +CONFIG_TMPFS_XATTR=y | |
| +# CONFIG_HUGETLBFS is not set | |
| +# CONFIG_HUGETLB_PAGE is not set | |
| +CONFIG_CONFIGFS_FS=y | |
| +CONFIG_MISC_FILESYSTEMS=y | |
| +# CONFIG_ADFS_FS is not set | |
| +# CONFIG_AFFS_FS is not set | |
| +# CONFIG_ECRYPT_FS is not set | |
| +# CONFIG_HFS_FS is not set | |
| +# CONFIG_HFSPLUS_FS is not set | |
| +# CONFIG_BEFS_FS is not set | |
| +# CONFIG_BFS_FS is not set | |
| +# CONFIG_EFS_FS is not set | |
| +# CONFIG_JFFS2_FS is not set | |
| +CONFIG_UBIFS_FS=y | |
| +# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set | |
| +CONFIG_UBIFS_FS_LZO=y | |
| +CONFIG_UBIFS_FS_ZLIB=y | |
| +# CONFIG_UBIFS_ATIME_SUPPORT is not set | |
| +# CONFIG_LOGFS is not set | |
| +# CONFIG_CRAMFS is not set | |
| +# CONFIG_SQUASHFS is not set | |
| +# CONFIG_VXFS_FS is not set | |
| +# CONFIG_MINIX_FS is not set | |
| +# CONFIG_OMFS_FS is not set | |
| +# CONFIG_HPFS_FS is not set | |
| +# CONFIG_QNX4FS_FS is not set | |
| +# CONFIG_QNX6FS_FS is not set | |
| +# CONFIG_ROMFS_FS is not set | |
| +# CONFIG_PSTORE is not set | |
| +# CONFIG_SYSV_FS is not set | |
| +# CONFIG_UFS_FS is not set | |
| +CONFIG_NETWORK_FILESYSTEMS=y | |
| +CONFIG_NFS_FS=y | |
| +CONFIG_NFS_V2=y | |
| +CONFIG_NFS_V3=y | |
| +CONFIG_NFS_V3_ACL=y | |
| +CONFIG_NFS_V4=y | |
| +# CONFIG_NFS_SWAP is not set | |
| +# CONFIG_NFS_V4_1 is not set | |
| +# CONFIG_NFS_FSCACHE is not set | |
| +# CONFIG_NFS_USE_LEGACY_DNS is not set | |
| +CONFIG_NFS_USE_KERNEL_DNS=y | |
| +CONFIG_NFSD=y | |
| +CONFIG_NFSD_V2_ACL=y | |
| +CONFIG_NFSD_V3=y | |
| +CONFIG_NFSD_V3_ACL=y | |
| +CONFIG_NFSD_V4=y | |
| +# CONFIG_NFSD_PNFS is not set | |
| +CONFIG_NFSD_V4_SECURITY_LABEL=y | |
| +CONFIG_GRACE_PERIOD=y | |
| +CONFIG_LOCKD=y | |
| +CONFIG_LOCKD_V4=y | |
| +CONFIG_NFS_ACL_SUPPORT=y | |
| +CONFIG_NFS_COMMON=y | |
| +CONFIG_SUNRPC=y | |
| +CONFIG_SUNRPC_GSS=y | |
| +# CONFIG_SUNRPC_DEBUG is not set | |
| +# CONFIG_CEPH_FS is not set | |
| +CONFIG_CIFS=y | |
| +# CONFIG_CIFS_STATS is not set | |
| +CONFIG_CIFS_WEAK_PW_HASH=y | |
| +CONFIG_CIFS_UPCALL=y | |
| +CONFIG_CIFS_XATTR=y | |
| +CONFIG_CIFS_POSIX=y | |
| +CONFIG_CIFS_ACL=y | |
| +CONFIG_CIFS_DEBUG=y | |
| +# CONFIG_CIFS_DEBUG2 is not set | |
| +CONFIG_CIFS_DFS_UPCALL=y | |
| +CONFIG_CIFS_SMB2=y | |
| +# CONFIG_CIFS_SMB311 is not set | |
| +# CONFIG_CIFS_FSCACHE is not set | |
| +# CONFIG_NCP_FS is not set | |
| +# CONFIG_CODA_FS is not set | |
| +# CONFIG_AFS_FS is not set | |
| +CONFIG_NLS=y | |
| +CONFIG_NLS_DEFAULT="iso8859-1" | |
| +CONFIG_NLS_CODEPAGE_437=y | |
| +# CONFIG_NLS_CODEPAGE_737 is not set | |
| +# CONFIG_NLS_CODEPAGE_775 is not set | |
| +CONFIG_NLS_CODEPAGE_850=y | |
| +# CONFIG_NLS_CODEPAGE_852 is not set | |
| +# CONFIG_NLS_CODEPAGE_855 is not set | |
| +# CONFIG_NLS_CODEPAGE_857 is not set | |
| +# CONFIG_NLS_CODEPAGE_860 is not set | |
| +# CONFIG_NLS_CODEPAGE_861 is not set | |
| +# CONFIG_NLS_CODEPAGE_862 is not set | |
| +# CONFIG_NLS_CODEPAGE_863 is not set | |
| +# CONFIG_NLS_CODEPAGE_864 is not set | |
| +# CONFIG_NLS_CODEPAGE_865 is not set | |
| +# CONFIG_NLS_CODEPAGE_866 is not set | |
| +# CONFIG_NLS_CODEPAGE_869 is not set | |
| +# CONFIG_NLS_CODEPAGE_936 is not set | |
| +# CONFIG_NLS_CODEPAGE_950 is not set | |
| +# CONFIG_NLS_CODEPAGE_932 is not set | |
| +# CONFIG_NLS_CODEPAGE_949 is not set | |
| +# CONFIG_NLS_CODEPAGE_874 is not set | |
| +# CONFIG_NLS_ISO8859_8 is not set | |
| +# CONFIG_NLS_CODEPAGE_1250 is not set | |
| +# CONFIG_NLS_CODEPAGE_1251 is not set | |
| +# CONFIG_NLS_ASCII is not set | |
| +CONFIG_NLS_ISO8859_1=y | |
| +CONFIG_NLS_ISO8859_2=y | |
| +# CONFIG_NLS_ISO8859_3 is not set | |
| +# CONFIG_NLS_ISO8859_4 is not set | |
| +# CONFIG_NLS_ISO8859_5 is not set | |
| +# CONFIG_NLS_ISO8859_6 is not set | |
| +# CONFIG_NLS_ISO8859_7 is not set | |
| +# CONFIG_NLS_ISO8859_9 is not set | |
| +# CONFIG_NLS_ISO8859_13 is not set | |
| +# CONFIG_NLS_ISO8859_14 is not set | |
| +# CONFIG_NLS_ISO8859_15 is not set | |
| +# CONFIG_NLS_KOI8_R is not set | |
| +# CONFIG_NLS_KOI8_U is not set | |
| +# CONFIG_NLS_MAC_ROMAN is not set | |
| +# CONFIG_NLS_MAC_CELTIC is not set | |
| +# CONFIG_NLS_MAC_CENTEURO is not set | |
| +# CONFIG_NLS_MAC_CROATIAN is not set | |
| +# CONFIG_NLS_MAC_CYRILLIC is not set | |
| +# CONFIG_NLS_MAC_GAELIC is not set | |
| +# CONFIG_NLS_MAC_GREEK is not set | |
| +# CONFIG_NLS_MAC_ICELAND is not set | |
| +# CONFIG_NLS_MAC_INUIT is not set | |
| +# CONFIG_NLS_MAC_ROMANIAN is not set | |
| +# CONFIG_NLS_MAC_TURKISH is not set | |
| +CONFIG_NLS_UTF8=y | |
| +# CONFIG_DLM is not set | |
| + | |
| +# | |
| +# Kernel hacking | |
| +# | |
| + | |
| +# | |
| +# printk and dmesg options | |
| +# | |
| +CONFIG_PRINTK_TIME=y | |
| +CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 | |
| +# CONFIG_BOOT_PRINTK_DELAY is not set | |
| + | |
| +# | |
| +# Compile-time checks and compiler options | |
| +# | |
| +CONFIG_DEBUG_INFO=y | |
| +CONFIG_DEBUG_INFO_REDUCED=y | |
| +# CONFIG_DEBUG_INFO_SPLIT is not set | |
| +# CONFIG_DEBUG_INFO_DWARF4 is not set | |
| +# CONFIG_GDB_SCRIPTS is not set | |
| +CONFIG_ENABLE_WARN_DEPRECATED=y | |
| +CONFIG_ENABLE_MUST_CHECK=y | |
| +CONFIG_FRAME_WARN=1024 | |
| +# CONFIG_STRIP_ASM_SYMS is not set | |
| +# CONFIG_READABLE_ASM is not set | |
| +# CONFIG_UNUSED_SYMBOLS is not set | |
| +# CONFIG_PAGE_OWNER is not set | |
| +# CONFIG_DEBUG_FS is not set | |
| +# CONFIG_HEADERS_CHECK is not set | |
| +# CONFIG_DEBUG_SECTION_MISMATCH is not set | |
| +CONFIG_SECTION_MISMATCH_WARN_ONLY=y | |
| +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set | |
| +CONFIG_MAGIC_SYSRQ=y | |
| +CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1 | |
| +CONFIG_DEBUG_KERNEL=y | |
| + | |
| +# | |
| +# Memory Debugging | |
| +# | |
| +# CONFIG_PAGE_EXTENSION is not set | |
| +# CONFIG_DEBUG_PAGEALLOC is not set | |
| +# CONFIG_DEBUG_OBJECTS is not set | |
| +# CONFIG_SLUB_DEBUG_ON is not set | |
| +# CONFIG_SLUB_STATS is not set | |
| +CONFIG_HAVE_DEBUG_KMEMLEAK=y | |
| +# CONFIG_DEBUG_KMEMLEAK is not set | |
| +# CONFIG_DEBUG_STACK_USAGE is not set | |
| +# CONFIG_DEBUG_VM is not set | |
| +# CONFIG_DEBUG_MEMORY_INIT is not set | |
| +# CONFIG_DEBUG_PER_CPU_MAPS is not set | |
| +# CONFIG_DEBUG_HIGHMEM is not set | |
| +# CONFIG_DEBUG_SHIRQ is not set | |
| + | |
| +# | |
| +# Debug Lockups and Hangs | |
| +# | |
| +CONFIG_LOCKUP_DETECTOR=y | |
| +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set | |
| +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 | |
| +# CONFIG_DETECT_HUNG_TASK is not set | |
| +CONFIG_PANIC_ON_OOPS=y | |
| +CONFIG_PANIC_ON_OOPS_VALUE=1 | |
| +CONFIG_PANIC_TIMEOUT=0 | |
| +CONFIG_SCHED_DEBUG=y | |
| +CONFIG_SCHED_INFO=y | |
| +# CONFIG_SCHEDSTATS is not set | |
| +# CONFIG_SCHED_STACK_END_CHECK is not set | |
| +# CONFIG_DEBUG_TIMEKEEPING is not set | |
| +# CONFIG_TIMER_STATS is not set | |
| + | |
| +# | |
| +# Lock Debugging (spinlocks, mutexes, etc...) | |
| +# | |
| +# CONFIG_DEBUG_RT_MUTEXES is not set | |
| +# CONFIG_DEBUG_SPINLOCK is not set | |
| +# CONFIG_DEBUG_MUTEXES is not set | |
| +# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set | |
| +# CONFIG_DEBUG_LOCK_ALLOC is not set | |
| +# CONFIG_PROVE_LOCKING is not set | |
| +# CONFIG_LOCK_STAT is not set | |
| +# CONFIG_DEBUG_ATOMIC_SLEEP is not set | |
| +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set | |
| +# CONFIG_LOCK_TORTURE_TEST is not set | |
| +CONFIG_STACKTRACE=y | |
| +# CONFIG_DEBUG_KOBJECT is not set | |
| +CONFIG_DEBUG_BUGVERBOSE=y | |
| +# CONFIG_DEBUG_LIST is not set | |
| +# CONFIG_DEBUG_PI_LIST is not set | |
| +# CONFIG_DEBUG_SG is not set | |
| +# CONFIG_DEBUG_NOTIFIERS is not set | |
| +# CONFIG_DEBUG_CREDENTIALS is not set | |
| + | |
| +# | |
| +# RCU Debugging | |
| +# | |
| +# CONFIG_PROVE_RCU is not set | |
| +# CONFIG_SPARSE_RCU_POINTER is not set | |
| +# CONFIG_TORTURE_TEST is not set | |
| +# CONFIG_RCU_TORTURE_TEST is not set | |
| +CONFIG_RCU_CPU_STALL_TIMEOUT=21 | |
| +# CONFIG_RCU_TRACE is not set | |
| +# CONFIG_RCU_EQS_DEBUG is not set | |
| +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set | |
| +# CONFIG_NOTIFIER_ERROR_INJECTION is not set | |
| +# CONFIG_FAULT_INJECTION is not set | |
| +CONFIG_HAVE_FUNCTION_TRACER=y | |
| +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y | |
| +CONFIG_HAVE_DYNAMIC_FTRACE=y | |
| +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y | |
| +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y | |
| +CONFIG_HAVE_C_RECORDMCOUNT=y | |
| +CONFIG_TRACING_SUPPORT=y | |
| +# CONFIG_FTRACE is not set | |
| + | |
| +# | |
| +# Runtime Testing | |
| +# | |
| +# CONFIG_TEST_LIST_SORT is not set | |
| +# CONFIG_BACKTRACE_SELF_TEST is not set | |
| +# CONFIG_RBTREE_TEST is not set | |
| +# CONFIG_INTERVAL_TREE_TEST is not set | |
| +# CONFIG_PERCPU_TEST is not set | |
| +# CONFIG_ATOMIC64_SELFTEST is not set | |
| +# CONFIG_ASYNC_RAID6_TEST is not set | |
| +# CONFIG_TEST_HEXDUMP is not set | |
| +# CONFIG_TEST_STRING_HELPERS is not set | |
| +# CONFIG_TEST_KSTRTOX is not set | |
| +# CONFIG_TEST_PRINTF is not set | |
| +# CONFIG_TEST_RHASHTABLE is not set | |
| +# CONFIG_DMA_API_DEBUG is not set | |
| +# CONFIG_TEST_LKM is not set | |
| +# CONFIG_TEST_USER_COPY is not set | |
| +# CONFIG_TEST_BPF is not set | |
| +# CONFIG_TEST_FIRMWARE is not set | |
| +# CONFIG_TEST_UDELAY is not set | |
| +# CONFIG_MEMTEST is not set | |
| +# CONFIG_TEST_STATIC_KEYS is not set | |
| +# CONFIG_SAMPLES is not set | |
| +CONFIG_HAVE_ARCH_KGDB=y | |
| +# CONFIG_KGDB is not set | |
| +# CONFIG_ARM_PTDUMP is not set | |
| +# CONFIG_STRICT_DEVMEM is not set | |
| +CONFIG_ARM_UNWIND=y | |
| +CONFIG_DEBUG_USER=y | |
| +# CONFIG_DEBUG_LL is not set | |
| +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" | |
| +# CONFIG_DEBUG_UART_8250 is not set | |
| +CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" | |
| +# CONFIG_PID_IN_CONTEXTIDR is not set | |
| +# CONFIG_DEBUG_SET_MODULE_RONX is not set | |
| +# CONFIG_CORESIGHT is not set | |
| + | |
| +# | |
| +# Security options | |
| +# | |
| +CONFIG_KEYS=y | |
| +# CONFIG_PERSISTENT_KEYRINGS is not set | |
| +# CONFIG_BIG_KEYS is not set | |
| +# CONFIG_ENCRYPTED_KEYS is not set | |
| +# CONFIG_SECURITY_DMESG_RESTRICT is not set | |
| +CONFIG_SECURITY=y | |
| +# CONFIG_SECURITYFS is not set | |
| +# CONFIG_SECURITY_NETWORK is not set | |
| +# CONFIG_SECURITY_PATH is not set | |
| +# CONFIG_SECURITY_SMACK is not set | |
| +# CONFIG_SECURITY_TOMOYO is not set | |
| +# CONFIG_SECURITY_APPARMOR is not set | |
| +# CONFIG_SECURITY_YAMA is not set | |
| +# CONFIG_INTEGRITY is not set | |
| +CONFIG_DEFAULT_SECURITY_DAC=y | |
| +CONFIG_DEFAULT_SECURITY="" | |
| +CONFIG_XOR_BLOCKS=y | |
| +CONFIG_ASYNC_CORE=y | |
| +CONFIG_ASYNC_MEMCPY=y | |
| +CONFIG_ASYNC_XOR=y | |
| +CONFIG_ASYNC_PQ=y | |
| +CONFIG_ASYNC_RAID6_RECOV=y | |
| +CONFIG_CRYPTO=y | |
| + | |
| +# | |
| +# Crypto core or helper | |
| +# | |
| +CONFIG_CRYPTO_ALGAPI=y | |
| +CONFIG_CRYPTO_ALGAPI2=y | |
| +CONFIG_CRYPTO_AEAD=y | |
| +CONFIG_CRYPTO_AEAD2=y | |
| +CONFIG_CRYPTO_BLKCIPHER=y | |
| +CONFIG_CRYPTO_BLKCIPHER2=y | |
| +CONFIG_CRYPTO_HASH=y | |
| +CONFIG_CRYPTO_HASH2=y | |
| +CONFIG_CRYPTO_RNG=y | |
| +CONFIG_CRYPTO_RNG2=y | |
| +CONFIG_CRYPTO_RNG_DEFAULT=y | |
| +CONFIG_CRYPTO_PCOMP2=y | |
| +CONFIG_CRYPTO_AKCIPHER2=y | |
| +# CONFIG_CRYPTO_RSA is not set | |
| +CONFIG_CRYPTO_MANAGER=y | |
| +CONFIG_CRYPTO_MANAGER2=y | |
| +CONFIG_CRYPTO_USER=y | |
| +CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y | |
| +# CONFIG_CRYPTO_GF128MUL is not set | |
| +CONFIG_CRYPTO_NULL=y | |
| +CONFIG_CRYPTO_NULL2=y | |
| +# CONFIG_CRYPTO_PCRYPT is not set | |
| +CONFIG_CRYPTO_WORKQUEUE=y | |
| +# CONFIG_CRYPTO_CRYPTD is not set | |
| +# CONFIG_CRYPTO_MCRYPTD is not set | |
| +CONFIG_CRYPTO_AUTHENC=y | |
| +# CONFIG_CRYPTO_TEST is not set | |
| + | |
| +# | |
| +# Authenticated Encryption with Associated Data | |
| +# | |
| +CONFIG_CRYPTO_CCM=y | |
| +# CONFIG_CRYPTO_GCM is not set | |
| +# CONFIG_CRYPTO_CHACHA20POLY1305 is not set | |
| +CONFIG_CRYPTO_SEQIV=y | |
| +# CONFIG_CRYPTO_ECHAINIV is not set | |
| + | |
| +# | |
| +# Block modes | |
| +# | |
| +CONFIG_CRYPTO_CBC=y | |
| +CONFIG_CRYPTO_CTR=y | |
| +# CONFIG_CRYPTO_CTS is not set | |
| +CONFIG_CRYPTO_ECB=y | |
| +# CONFIG_CRYPTO_LRW is not set | |
| +# CONFIG_CRYPTO_PCBC is not set | |
| +# CONFIG_CRYPTO_XTS is not set | |
| +# CONFIG_CRYPTO_KEYWRAP is not set | |
| + | |
| +# | |
| +# Hash modes | |
| +# | |
| +CONFIG_CRYPTO_CMAC=y | |
| +CONFIG_CRYPTO_HMAC=y | |
| +# CONFIG_CRYPTO_XCBC is not set | |
| +# CONFIG_CRYPTO_VMAC is not set | |
| + | |
| +# | |
| +# Digest | |
| +# | |
| +CONFIG_CRYPTO_CRC32C=y | |
| +# CONFIG_CRYPTO_CRC32 is not set | |
| +CONFIG_CRYPTO_CRCT10DIF=y | |
| +# CONFIG_CRYPTO_GHASH is not set | |
| +# CONFIG_CRYPTO_POLY1305 is not set | |
| +CONFIG_CRYPTO_MD4=y | |
| +CONFIG_CRYPTO_MD5=y | |
| +# CONFIG_CRYPTO_MICHAEL_MIC is not set | |
| +# CONFIG_CRYPTO_RMD128 is not set | |
| +# CONFIG_CRYPTO_RMD160 is not set | |
| +# CONFIG_CRYPTO_RMD256 is not set | |
| +# CONFIG_CRYPTO_RMD320 is not set | |
| +CONFIG_CRYPTO_SHA1=y | |
| +CONFIG_CRYPTO_SHA256=y | |
| +CONFIG_CRYPTO_SHA512=y | |
| +# CONFIG_CRYPTO_TGR192 is not set | |
| +# CONFIG_CRYPTO_WP512 is not set | |
| + | |
| +# | |
| +# Ciphers | |
| +# | |
| +CONFIG_CRYPTO_AES=y | |
| +# CONFIG_CRYPTO_ANUBIS is not set | |
| +CONFIG_CRYPTO_ARC4=y | |
| +CONFIG_CRYPTO_BLOWFISH=y | |
| +CONFIG_CRYPTO_BLOWFISH_COMMON=y | |
| +# CONFIG_CRYPTO_CAMELLIA is not set | |
| +# CONFIG_CRYPTO_CAST5 is not set | |
| +# CONFIG_CRYPTO_CAST6 is not set | |
| +CONFIG_CRYPTO_DES=y | |
| +# CONFIG_CRYPTO_FCRYPT is not set | |
| +# CONFIG_CRYPTO_KHAZAD is not set | |
| +# CONFIG_CRYPTO_SALSA20 is not set | |
| +# CONFIG_CRYPTO_CHACHA20 is not set | |
| +# CONFIG_CRYPTO_SEED is not set | |
| +# CONFIG_CRYPTO_SERPENT is not set | |
| +# CONFIG_CRYPTO_TEA is not set | |
| +# CONFIG_CRYPTO_TWOFISH is not set | |
| + | |
| +# | |
| +# Compression | |
| +# | |
| +CONFIG_CRYPTO_DEFLATE=y | |
| +# CONFIG_CRYPTO_ZLIB is not set | |
| +CONFIG_CRYPTO_LZO=y | |
| +# CONFIG_CRYPTO_842 is not set | |
| +# CONFIG_CRYPTO_LZ4 is not set | |
| +# CONFIG_CRYPTO_LZ4HC is not set | |
| + | |
| +# | |
| +# Random Number Generation | |
| +# | |
| +# CONFIG_CRYPTO_ANSI_CPRNG is not set | |
| +CONFIG_CRYPTO_DRBG_MENU=y | |
| +CONFIG_CRYPTO_DRBG_HMAC=y | |
| +# CONFIG_CRYPTO_DRBG_HASH is not set | |
| +# CONFIG_CRYPTO_DRBG_CTR is not set | |
| +CONFIG_CRYPTO_DRBG=y | |
| +CONFIG_CRYPTO_JITTERENTROPY=y | |
| +CONFIG_CRYPTO_USER_API=y | |
| +CONFIG_CRYPTO_USER_API_HASH=y | |
| +CONFIG_CRYPTO_USER_API_SKCIPHER=y | |
| +# CONFIG_CRYPTO_USER_API_RNG is not set | |
| +# CONFIG_CRYPTO_USER_API_AEAD is not set | |
| +CONFIG_CRYPTO_HW=y | |
| +# CONFIG_CRYPTO_DEV_HIFN_795X is not set | |
| +CONFIG_CRYPTO_DEV_AL_CRYPTO=y | |
| +CONFIG_CRYPTO_DEV_AL_CRYPTO_STATS=y | |
| +CONFIG_CRYPTO_DEV_AL_AHASH_CRC=y | |
| +# CONFIG_ASYMMETRIC_KEY_TYPE is not set | |
| + | |
| +# | |
| +# Certificates for signature checking | |
| +# | |
| +# CONFIG_SYSTEM_TRUSTED_KEYRING is not set | |
| +CONFIG_ARM_CRYPTO=y | |
| +# CONFIG_CRYPTO_SHA1_ARM is not set | |
| +CONFIG_CRYPTO_SHA256_ARM=y | |
| +# CONFIG_CRYPTO_SHA512_ARM is not set | |
| +# CONFIG_CRYPTO_AES_ARM is not set | |
| +# CONFIG_BINARY_PRINTF is not set | |
| + | |
| +# | |
| +# Library routines | |
| +# | |
| +CONFIG_RAID6_PQ=y | |
| +CONFIG_BITREVERSE=y | |
| +CONFIG_HAVE_ARCH_BITREVERSE=y | |
| +CONFIG_RATIONAL=y | |
| +CONFIG_GENERIC_STRNCPY_FROM_USER=y | |
| +CONFIG_GENERIC_STRNLEN_USER=y | |
| +CONFIG_GENERIC_NET_UTILS=y | |
| +CONFIG_GENERIC_PCI_IOMAP=y | |
| +CONFIG_GENERIC_IO=y | |
| +CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y | |
| +# CONFIG_CRC_CCITT is not set | |
| +CONFIG_CRC16=y | |
| +CONFIG_CRC_T10DIF=y | |
| +CONFIG_CRC_ITU_T=y | |
| +CONFIG_CRC32=y | |
| +# CONFIG_CRC32_SELFTEST is not set | |
| +CONFIG_CRC32_SLICEBY8=y | |
| +# CONFIG_CRC32_SLICEBY4 is not set | |
| +# CONFIG_CRC32_SARWATE is not set | |
| +# CONFIG_CRC32_BIT is not set | |
| +# CONFIG_CRC7 is not set | |
| +CONFIG_LIBCRC32C=y | |
| +# CONFIG_CRC8 is not set | |
| +# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set | |
| +# CONFIG_RANDOM32_SELFTEST is not set | |
| +CONFIG_ZLIB_INFLATE=y | |
| +CONFIG_ZLIB_DEFLATE=y | |
| +CONFIG_LZO_COMPRESS=y | |
| +CONFIG_LZO_DECOMPRESS=y | |
| +CONFIG_XZ_DEC=y | |
| +CONFIG_XZ_DEC_X86=y | |
| +CONFIG_XZ_DEC_POWERPC=y | |
| +CONFIG_XZ_DEC_IA64=y | |
| +CONFIG_XZ_DEC_ARM=y | |
| +CONFIG_XZ_DEC_ARMTHUMB=y | |
| +CONFIG_XZ_DEC_SPARC=y | |
| +CONFIG_XZ_DEC_BCJ=y | |
| +# CONFIG_XZ_DEC_TEST is not set | |
| +CONFIG_DECOMPRESS_GZIP=y | |
| +CONFIG_DECOMPRESS_LZMA=y | |
| +CONFIG_DECOMPRESS_XZ=y | |
| +CONFIG_GENERIC_ALLOCATOR=y | |
| +CONFIG_ASSOCIATIVE_ARRAY=y | |
| +CONFIG_HAS_IOMEM=y | |
| +CONFIG_HAS_IOPORT_MAP=y | |
| +CONFIG_HAS_DMA=y | |
| +CONFIG_CPU_RMAP=y | |
| +CONFIG_DQL=y | |
| +CONFIG_GLOB=y | |
| +# CONFIG_GLOB_SELFTEST is not set | |
| +CONFIG_NLATTR=y | |
| +CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y | |
| +# CONFIG_CORDIC is not set | |
| +# CONFIG_DDR is not set | |
| +CONFIG_LIBFDT=y | |
| +CONFIG_OID_REGISTRY=y | |
| +# CONFIG_SG_SPLIT is not set | |
| +CONFIG_ARCH_HAS_SG_CHAIN=y | |
| +# CONFIG_VIRTUALIZATION is not set | |
| diff -x .git -Naur linux-4.4.111/arch/arm/crypto/sha256-core.S linux-4.4.111-alpine/arch/arm/crypto/sha256-core.S | |
| --- linux-4.4.111/arch/arm/crypto/sha256-core.S 1969-12-31 19:00:00.000000000 -0500 | |
| +++ linux-4.4.111-alpine/arch/arm/crypto/sha256-core.S 2018-02-14 21:04:17.000000000 -0500 | |
| @@ -0,0 +1,2808 @@ | |
| + | |
| +@ ==================================================================== | |
| +@ Written by Andy Polyakov <appro@openssl.org> for the OpenSSL | |
| +@ project. The module is, however, dual licensed under OpenSSL and | |
| +@ CRYPTOGAMS licenses depending on where you obtain it. For further | |
| +@ details see http://www.openssl.org/~appro/cryptogams/. | |
| +@ | |
| +@ Permission to use under GPL terms is granted. | |
| +@ ==================================================================== | |
| + | |
| +@ SHA256 block procedure for ARMv4. May 2007. | |
| + | |
| +@ Performance is ~2x better than gcc 3.4 generated code and in "abso- | |
| +@ lute" terms is ~2250 cycles per 64-byte block or ~35 cycles per | |
| +@ byte [on single-issue Xscale PXA250 core]. | |
| + | |
| +@ July 2010. | |
| +@ | |
| +@ Rescheduling for dual-issue pipeline resulted in 22% improvement on | |
| +@ Cortex A8 core and ~20 cycles per processed byte. | |
| + | |
| +@ February 2011. | |
| +@ | |
| +@ Profiler-assisted and platform-specific optimization resulted in 16% | |
| +@ improvement on Cortex A8 core and ~15.4 cycles per processed byte. | |
| + | |
| +@ September 2013. | |
| +@ | |
| +@ Add NEON implementation. On Cortex A8 it was measured to process one | |
| +@ byte in 12.5 cycles or 23% faster than integer-only code. Snapdragon | |
| +@ S4 does it in 12.5 cycles too, but it's 50% faster than integer-only | |
| +@ code (meaning that latter performs sub-optimally, nothing was done | |
| +@ about it). | |
| + | |
| +@ May 2014. | |
| +@ | |
| +@ Add ARMv8 code path performing at 2.0 cpb on Apple A7. | |
| + | |
| +#ifndef __KERNEL__ | |
| +# include "arm_arch.h" | |
| +#else | |
| +# define __ARM_ARCH__ __LINUX_ARM_ARCH__ | |
| +# define __ARM_MAX_ARCH__ 7 | |
| +#endif | |
| + | |
| +.text | |
| +#if __ARM_ARCH__<7 | |
| +.code 32 | |
| +#else | |
| +.syntax unified | |
| +# ifdef __thumb2__ | |
| +# define adrl adr | |
| +.thumb | |
| +# else | |
| +.code 32 | |
| +# endif | |
| +#endif | |
| + | |
| +.type K256,%object | |
| +.align 5 | |
| +K256: | |
| +.word 0x428a2f98,0x71374491,0xb5c0fbcf,0xe9b5dba5 | |
| +.word 0x3956c25b,0x59f111f1,0x923f82a4,0xab1c5ed5 | |
| +.word 0xd807aa98,0x12835b01,0x243185be,0x550c7dc3 | |
| +.word 0x72be5d74,0x80deb1fe,0x9bdc06a7,0xc19bf174 | |
| +.word 0xe49b69c1,0xefbe4786,0x0fc19dc6,0x240ca1cc | |
| +.word 0x2de92c6f,0x4a7484aa,0x5cb0a9dc,0x76f988da | |
| +.word 0x983e5152,0xa831c66d,0xb00327c8,0xbf597fc7 | |
| +.word 0xc6e00bf3,0xd5a79147,0x06ca6351,0x14292967 | |
| +.word 0x27b70a85,0x2e1b2138,0x4d2c6dfc,0x53380d13 | |
| +.word 0x650a7354,0x766a0abb,0x81c2c92e,0x92722c85 | |
| +.word 0xa2bfe8a1,0xa81a664b,0xc24b8b70,0xc76c51a3 | |
| +.word 0xd192e819,0xd6990624,0xf40e3585,0x106aa070 | |
| +.word 0x19a4c116,0x1e376c08,0x2748774c,0x34b0bcb5 | |
| +.word 0x391c0cb3,0x4ed8aa4a,0x5b9cca4f,0x682e6ff3 | |
| +.word 0x748f82ee,0x78a5636f,0x84c87814,0x8cc70208 | |
| +.word 0x90befffa,0xa4506ceb,0xbef9a3f7,0xc67178f2 | |
| +.size K256,.-K256 | |
| +.word 0 @ terminator | |
| +#if __ARM_MAX_ARCH__>=7 && !defined(__KERNEL__) | |
| +.LOPENSSL_armcap: | |
| +.word OPENSSL_armcap_P-sha256_block_data_order | |
| +#endif | |
| +.align 5 | |
| + | |
| +.global sha256_block_data_order | |
| +.type sha256_block_data_order,%function | |
| +sha256_block_data_order: | |
| +#if __ARM_ARCH__<7 | |
| + sub r3,pc,#8 @ sha256_block_data_order | |
| +#else | |
| + adr r3,sha256_block_data_order | |
| +#endif | |
| +#if __ARM_MAX_ARCH__>=7 && !defined(__KERNEL__) | |
| + ldr r12,.LOPENSSL_armcap | |
| + ldr r12,[r3,r12] @ OPENSSL_armcap_P | |
| + tst r12,#ARMV8_SHA256 | |
| + bne .LARMv8 | |
| + tst r12,#ARMV7_NEON | |
| + bne .LNEON | |
| +#endif | |
| + add r2,r1,r2,lsl#6 @ len to point at the end of inp | |
| + stmdb sp!,{r0,r1,r2,r4-r11,lr} | |
| + ldmia r0,{r4,r5,r6,r7,r8,r9,r10,r11} | |
| + sub r14,r3,#256+32 @ K256 | |
| + sub sp,sp,#16*4 @ alloca(X[16]) | |
| +.Loop: | |
| +# if __ARM_ARCH__>=7 | |
| + ldr r2,[r1],#4 | |
| +# else | |
| + ldrb r2,[r1,#3] | |
| +# endif | |
| + eor r3,r5,r6 @ magic | |
| + eor r12,r12,r12 | |
| +#if __ARM_ARCH__>=7 | |
| + @ ldr r2,[r1],#4 @ 0 | |
| +# if 0==15 | |
| + str r1,[sp,#17*4] @ make room for r1 | |
| +# endif | |
| + eor r0,r8,r8,ror#5 | |
| + add r4,r4,r12 @ h+=Maj(a,b,c) from the past | |
| + eor r0,r0,r8,ror#19 @ Sigma1(e) | |
| +# ifndef __ARMEB__ | |
| + rev r2,r2 | |
| +# endif | |
| +#else | |
| + @ ldrb r2,[r1,#3] @ 0 | |
| + add r4,r4,r12 @ h+=Maj(a,b,c) from the past | |
| + ldrb r12,[r1,#2] | |
| + ldrb r0,[r1,#1] | |
| + orr r2,r2,r12,lsl#8 | |
| + ldrb r12,[r1],#4 | |
| + orr r2,r2,r0,lsl#16 | |
| +# if 0==15 | |
| + str r1,[sp,#17*4] @ make room for r1 | |
| +# endif | |
| + eor r0,r8,r8,ror#5 | |
| + orr r2,r2,r12,lsl#24 | |
| + eor r0,r0,r8,ror#19 @ Sigma1(e) | |
| +#endif | |
| + ldr r12,[r14],#4 @ *K256++ | |
| + add r11,r11,r2 @ h+=X[i] | |
| + str r2,[sp,#0*4] | |
| + eor r2,r9,r10 | |
| + add r11,r11,r0,ror#6 @ h+=Sigma1(e) | |
| + and r2,r2,r8 | |
| + add r11,r11,r12 @ h+=K256[i] | |
| + eor r2,r2,r10 @ Ch(e,f,g) | |
| + eor r0,r4,r4,ror#11 | |
| + add r11,r11,r2 @ h+=Ch(e,f,g) | |
| +#if 0==31 | |
| + and r12,r12,#0xff | |
| + cmp r12,#0xf2 @ done? | |
| +#endif | |
| +#if 0<15 | |
| +# if __ARM_ARCH__>=7 | |
| + ldr r2,[r1],#4 @ prefetch | |
| +# else | |
| + ldrb r2,[r1,#3] | |
| +# endif | |
| + eor r12,r4,r5 @ a^b, b^c in next round | |
| +#else | |
| + ldr r2,[sp,#2*4] @ from future BODY_16_xx | |
| + eor r12,r4,r5 @ a^b, b^c in next round | |
| + ldr r1,[sp,#15*4] @ from future BODY_16_xx | |
| +#endif | |
| + eor r0,r0,r4,ror#20 @ Sigma0(a) | |
| + and r3,r3,r12 @ (b^c)&=(a^b) | |
| + add r7,r7,r11 @ d+=h | |
| + eor r3,r3,r5 @ Maj(a,b,c) | |
| + add r11,r11,r0,ror#2 @ h+=Sigma0(a) | |
| + @ add r11,r11,r3 @ h+=Maj(a,b,c) | |
| +#if __ARM_ARCH__>=7 | |
| + @ ldr r2,[r1],#4 @ 1 | |
| +# if 1==15 | |
| + str r1,[sp,#17*4] @ make room for r1 | |
| +# endif | |
| + eor r0,r7,r7,ror#5 | |
| + add r11,r11,r3 @ h+=Maj(a,b,c) from the past | |
| + eor r0,r0,r7,ror#19 @ Sigma1(e) | |
| +# ifndef __ARMEB__ | |
| + rev r2,r2 | |
| +# endif | |
| +#else | |
| + @ ldrb r2,[r1,#3] @ 1 | |
| + add r11,r11,r3 @ h+=Maj(a,b,c) from the past | |
| + ldrb r3,[r1,#2] | |
| + ldrb r0,[r1,#1] | |
| + orr r2,r2,r3,lsl#8 | |
| + ldrb r3,[r1],#4 | |
| + orr r2,r2,r0,lsl#16 | |
| +# if 1==15 | |
| + str r1,[sp,#17*4] @ make room for r1 | |
| +# endif | |
| + eor r0,r7,r7,ror#5 | |
| + orr r2,r2,r3,lsl#24 | |
| + eor r0,r0,r7,ror#19 @ Sigma1(e) | |
| +#endif | |
| + ldr r3,[r14],#4 @ *K256++ | |
| + add r10,r10,r2 @ h+=X[i] | |
| + str r2,[sp,#1*4] | |
| + eor r2,r8,r9 | |
| + add r10,r10,r0,ror#6 @ h+=Sigma1(e) | |
| + and r2,r2,r7 | |
| + add r10,r10,r3 @ h+=K256[i] | |
| + eor r2,r2,r9 @ Ch(e,f,g) | |
| + eor r0,r11,r11,ror#11 | |
| + add r10,r10,r2 @ h+=Ch(e,f,g) | |
| +#if 1==31 | |
| + and r3,r3,#0xff | |
| + cmp r3,#0xf2 @ done? | |
| +#endif | |
| +#if 1<15 | |
| +# if __ARM_ARCH__>=7 | |
| + ldr r2,[r1],#4 @ prefetch | |
| +# else | |
| + ldrb r2,[r1,#3] | |
| +# endif | |
| + eor r3,r11,r4 @ a^b, b^c in next round | |
| +#else | |
| + ldr r2,[sp,#3*4] @ from future BODY_16_xx | |
| + eor r3,r11,r4 @ a^b, b^c in next round | |
| + ldr r1,[sp,#0*4] @ from future BODY_16_xx | |
| +#endif | |
| + eor r0,r0,r11,ror#20 @ Sigma0(a) | |
| + and r12,r12,r3 @ (b^c)&=(a^b) | |
| + add r6,r6,r10 @ d+=h | |
| + eor r12,r12,r4 @ Maj(a,b,c) | |
| + add r10,r10,r0,ror#2 @ h+=Sigma0(a) | |
| + @ add r10,r10,r12 @ h+=Maj(a,b,c) | |
| +#if __ARM_ARCH__>=7 | |
| + @ ldr r2,[r1],#4 @ 2 | |
| +# if 2==15 | |
| + str r1,[sp,#17*4] @ make room for r1 | |
| +# endif | |
| + eor r0,r6,r6,ror#5 | |
| + add r10,r10,r12 @ h+=Maj(a,b,c) from the past | |
| + eor r0,r0,r6,ror#19 @ Sigma1(e) | |
| +# ifndef __ARMEB__ | |
| + rev r2,r2 | |
| +# endif | |
| +#else | |
| + @ ldrb r2,[r1,#3] @ 2 | |
| + add r10,r10,r12 @ h+=Maj(a,b,c) from the past | |
| + ldrb r12,[r1,#2] | |
| + ldrb r0,[r1,#1] | |
| + orr r2,r2,r12,lsl#8 | |
| + ldrb r12,[r1],#4 | |
| + orr r2,r2,r0,lsl#16 | |
| +# if 2==15 | |
| + str r1,[sp,#17*4] @ make room for r1 | |
| +# endif | |
| + eor r0,r6,r6,ror#5 | |
| + orr r2,r2,r12,lsl#24 | |
| + eor r0,r0,r6,ror#19 @ Sigma1(e) | |
| +#endif | |
| + ldr r12,[r14],#4 @ *K256++ | |
| + add r9,r9,r2 @ h+=X[i] | |
| + str r2,[sp,#2*4] | |
| + eor r2,r7,r8 | |
| + add r9,r9,r0,ror#6 @ h+=Sigma1(e) | |
| + and r2,r2,r6 | |
| + add r9,r9,r12 @ h+=K256[i] | |
| + eor r2,r2,r8 @ Ch(e,f,g) | |
| + eor r0,r10,r10,ror#11 | |
| + add r9,r9,r2 @ h+=Ch(e,f,g) | |
| +#if 2==31 | |
| + and r12,r12,#0xff | |
| + cmp r12,#0xf2 @ done? | |
| +#endif | |
| +#if 2<15 | |
| +# if __ARM_ARCH__>=7 | |
| + ldr r2,[r1],#4 @ prefetch | |
| +# else | |
| + ldrb r2,[r1,#3] | |
| +# endif | |
| + eor r12,r10,r11 @ a^b, b^c in next round | |
| +#else | |
| + ldr r2,[sp,#4*4] @ from future BODY_16_xx | |
| + eor r12,r10,r11 @ a^b, b^c in next round | |
| + ldr r1,[sp,#1*4] @ from future BODY_16_xx | |
| +#endif | |
| + eor r0,r0,r10,ror#20 @ Sigma0(a) | |
| + and r3,r3,r12 @ (b^c)&=(a^b) | |
| + add r5,r5,r9 @ d+=h | |
| + eor r3,r3,r11 @ Maj(a,b,c) | |
| + add r9,r9,r0,ror#2 @ h+=Sigma0(a) | |
| + @ add r9,r9,r3 @ h+=Maj(a,b,c) | |
| +#if __ARM_ARCH__>=7 | |
| + @ ldr r2,[r1],#4 @ 3 | |
| +# if 3==15 | |
| + str r1,[sp,#17*4] @ make room for r1 | |
| +# endif | |
| + eor r0,r5,r5,ror#5 | |
| + add r9,r9,r3 @ h+=Maj(a,b,c) from the past | |
| + eor r0,r0,r5,ror#19 @ Sigma1(e) | |
| +# ifndef __ARMEB__ | |
| + rev r2,r2 | |
| +# endif | |
| +#else | |
| + @ ldrb r2,[r1,#3] @ 3 | |
| + add r9,r9,r3 @ h+=Maj(a,b,c) from the past | |
| + ldrb r3,[r1,#2] | |
| + ldrb r0,[r1,#1] | |
| + orr r2,r2,r3,lsl#8 | |
| + ldrb r3,[r1],#4 | |
| + orr r2,r2,r0,lsl#16 | |
| +# if 3==15 | |
| + str r1,[sp,#17*4] @ make room for r1 | |
| +# endif | |
| + eor r0,r5,r5,ror#5 | |
| + orr r2,r2,r3,lsl#24 | |
| + eor r0,r0,r5,ror#19 @ Sigma1(e) | |
| +#endif | |
| + ldr r3,[r14],#4 @ *K256++ | |
| + add r8,r8,r2 @ h+=X[i] | |
| + str r2,[sp,#3*4] | |
| + eor r2,r6,r7 | |
| + add r8,r8,r0,ror#6 @ h+=Sigma1(e) | |
| + and r2,r2,r5 | |
| + add r8,r8,r3 @ h+=K256[i] | |
| + eor r2,r2,r7 @ Ch(e,f,g) | |
| + eor r0,r9,r9,ror#11 | |
| + add r8,r8,r2 @ h+=Ch(e,f,g) | |
| +#if 3==31 | |
| + and r3,r3,#0xff | |
| + cmp r3,#0xf2 @ done? | |
| +#endif | |
| +#if 3<15 | |
| +# if __ARM_ARCH__>=7 | |
| + ldr r2,[r1],#4 @ prefetch | |
| +# else | |
| + ldrb r2,[r1,#3] | |
| +# endif | |
| + eor r3,r9,r10 @ a^b, b^c in next round | |
| +#else | |
| + ldr r2,[sp,#5*4] @ from future BODY_16_xx | |
| + eor r3,r9,r10 @ a^b, b^c in next round | |
| + ldr r1,[sp,#2*4] @ from future BODY_16_xx | |
| +#endif | |
| + eor r0,r0,r9,ror#20 @ Sigma0(a) | |
| + and r12,r12,r3 @ (b^c)&=(a^b) | |
| + add r4,r4,r8 @ d+=h | |
| + eor r12,r12,r10 @ Maj(a,b,c) | |
| + add r8,r8,r0,ror#2 @ h+=Sigma0(a) | |
| + @ add r8,r8,r12 @ h+=Maj(a,b,c) | |
| +#if __ARM_ARCH__>=7 | |
| + @ ldr r2,[r1],#4 @ 4 | |
| +# if 4==15 | |
| + str r1,[sp,#17*4] @ make room for r1 | |
| +# endif | |
| + eor r0,r4,r4,ror#5 | |
| + add r8,r8,r12 @ h+=Maj(a,b,c) from the past | |
| + eor r0,r0,r4,ror#19 @ Sigma1(e) | |
| +# ifndef __ARMEB__ | |
| + rev r2,r2 | |
| +# endif | |
| +#else | |
| + @ ldrb r2,[r1,#3] @ 4 | |
| + add r8,r8,r12 @ h+=Maj(a,b,c) from the past | |
| + ldrb r12,[r1,#2] | |
| + ldrb r0,[r1,#1] | |
| + orr r2,r2,r12,lsl#8 | |
| + ldrb r12,[r1],#4 | |
| + orr r2,r2,r0,lsl#16 | |
| +# if 4==15 | |
| + str r1,[sp,#17*4] @ make room for r1 | |
| +# endif | |
| + eor r0,r4,r4,ror#5 | |
| + orr r2,r2,r12,lsl#24 | |
| + eor r0,r0,r4,ror#19 @ Sigma1(e) | |
| +#endif | |
| + ldr r12,[r14],#4 @ *K256++ | |
| + add r7,r7,r2 @ h+=X[i] | |
| + str r2,[sp,#4*4] | |
| + eor r2,r5,r6 | |
| + add r7,r7,r0,ror#6 @ h+=Sigma1(e) | |
| + and r2,r2,r4 | |
| + add r7,r7,r12 @ h+=K256[i] | |
| + eor r2,r2,r6 @ Ch(e,f,g) | |
| + eor r0,r8,r8,ror#11 | |
| + add r7,r7,r2 @ h+=Ch(e,f,g) | |
| +#if 4==31 | |
| + and r12,r12,#0xff | |
| + cmp r12,#0xf2 @ done? | |
| +#endif | |
| +#if 4<15 | |
| +# if __ARM_ARCH__>=7 | |
| + ldr r2,[r1],#4 @ prefetch | |
| +# else | |
| + ldrb r2,[r1,#3] | |
| +# endif | |
| + eor r12,r8,r9 @ a^b, b^c in next round | |
| +#else | |
| + ldr r2,[sp,#6*4] @ from future BODY_16_xx | |
| + eor r12,r8,r9 @ a^b, b^c in next round | |
| + ldr r1,[sp,#3*4] @ from future BODY_16_xx | |
| +#endif | |
| + eor r0,r0,r8,ror#20 @ Sigma0(a) | |
| + and r3,r3,r12 @ (b^c)&=(a^b) | |
| + add r11,r11,r7 @ d+=h | |
| + eor r3,r3,r9 @ Maj(a,b,c) | |
| + add r7,r7,r0,ror#2 @ h+=Sigma0(a) | |
| + @ add r7,r7,r3 @ h+=Maj(a,b,c) | |
| +#if __ARM_ARCH__>=7 | |
| + @ ldr r2,[r1],#4 @ 5 | |
| +# if 5==15 | |
| + str r1,[sp,#17*4] @ make room for r1 | |
| +# endif | |
| + eor r0,r11,r11,ror#5 | |
| + add r7,r7,r3 @ h+=Maj(a,b,c) from the past | |
| + eor r0,r0,r11,ror#19 @ Sigma1(e) | |
| +# ifndef __ARMEB__ | |
| + rev r2,r2 | |
| +# endif | |
| +#else | |
| + @ ldrb r2,[r1,#3] @ 5 | |
| + add r7,r7,r3 @ h+=Maj(a,b,c) from the past | |
| + ldrb r3,[r1,#2] | |
| + ldrb r0,[r1,#1] | |
| + orr r2,r2,r3,lsl#8 | |
| + ldrb r3,[r1],#4 | |
| + orr r2,r2,r0,lsl#16 | |
| +# if 5==15 | |
| + str r1,[sp,#17*4] @ make room for r1 | |
| +# endif | |
| + eor r0,r11,r11,ror#5 | |
| + orr r2,r2,r3,lsl#24 | |
| + eor r0,r0,r11,ror#19 @ Sigma1(e) | |
| +#endif | |
| + ldr r3,[r14],#4 @ *K256++ | |
| + add r6,r6,r2 @ h+=X[i] | |
| + str r2,[sp,#5*4] | |
| + eor r2,r4,r5 | |
| + add r6,r6,r0,ror#6 @ h+=Sigma1(e) | |
| + and r2,r2,r11 | |
| + add r6,r6,r3 @ h+=K256[i] | |
| + eor r2,r2,r5 @ Ch(e,f,g) | |
| + eor r0,r7,r7,ror#11 | |
| + add r6,r6,r2 @ h+=Ch(e,f,g) | |
| +#if 5==31 | |
| + and r3,r3,#0xff | |
| + cmp r3,#0xf2 @ done? | |
| +#endif | |
| +#if 5<15 | |
| +# if __ARM_ARCH__>=7 | |
| + ldr r2,[r1],#4 @ prefetch | |
| +# else | |
| + ldrb r2,[r1,#3] | |
| +# endif | |
| + eor r3,r7,r8 @ a^b, b^c in next round | |
| +#else | |
| + ldr r2,[sp,#7*4] @ from future BODY_16_xx | |
| + eor r3,r7,r8 @ a^b, b^c in next round | |
| + ldr r1,[sp,#4*4] @ from future BODY_16_xx | |
| +#endif | |
| + eor r0,r0,r7,ror#20 @ Sigma0(a) | |
| + and r12,r12,r3 @ (b^c)&=(a^b) | |
| + add r10,r10,r6 @ d+=h | |
| + eor r12,r12,r8 @ Maj(a,b,c) | |
| + add r6,r6,r0,ror#2 @ h+=Sigma0(a) | |
| + @ add r6,r6,r12 @ h+=Maj(a,b,c) | |
| +#if __ARM_ARCH__>=7 | |
| + @ ldr r2,[r1],#4 @ 6 | |
| +# if 6==15 | |
| + str r1,[sp,#17*4] @ make room for r1 | |
| +# endif | |
| + eor r0,r10,r10,ror#5 | |
| + add r6,r6,r12 @ h+=Maj(a,b,c) from the past | |
| + eor r0,r0,r10,ror#19 @ Sigma1(e) | |
| +# ifndef __ARMEB__ | |
| + rev r2,r2 | |
| +# endif | |
| +#else | |
| + @ ldrb r2,[r1,#3] @ 6 | |
| + add r6,r6,r12 @ h+=Maj(a,b,c) from the past | |
| + ldrb r12,[r1,#2] | |
| + ldrb r0,[r1,#1] | |
| + orr r2,r2,r12,lsl#8 | |
| + ldrb r12,[r1],#4 | |
| + orr r2,r2,r0,lsl#16 | |
| +# if 6==15 | |
| + str r1,[sp,#17*4] @ make room for r1 | |
| +# endif | |
| + eor r0,r10,r10,ror#5 | |
| + orr r2,r2,r12,lsl#24 | |
| + eor r0,r0,r10,ror#19 @ Sigma1(e) | |
| +#endif | |
| + ldr r12,[r14],#4 @ *K256++ | |
| + add r5,r5,r2 @ h+=X[i] | |
| + str r2,[sp,#6*4] | |
| + eor r2,r11,r4 | |
| + add r5,r5,r0,ror#6 @ h+=Sigma1(e) | |
| + and r2,r2,r10 | |
| + add r5,r5,r12 @ h+=K256[i] | |
| + eor r2,r2,r4 @ Ch(e,f,g) | |
| + eor r0,r6,r6,ror#11 | |
| + add r5,r5,r2 @ h+=Ch(e,f,g) | |
| +#if 6==31 | |
| + and r12,r12,#0xff | |
| + cmp r12,#0xf2 @ done? | |
| +#endif | |
| +#if 6<15 | |
| +# if __ARM_ARCH__>=7 | |
| + ldr r2,[r1],#4 @ prefetch | |
| +# else | |
| + ldrb r2,[r1,#3] | |
| +# endif | |
| + eor r12,r6,r7 @ a^b, b^c in next round | |
| +#else | |
| + ldr r2,[sp,#8*4] @ from future BODY_16_xx | |
| + eor r12,r6,r7 @ a^b, b^c in next round | |
| + ldr r1,[sp,#5*4] @ from future BODY_16_xx | |
| +#endif | |
| + eor r0,r0,r6,ror#20 @ Sigma0(a) | |
| + and r3,r3,r12 @ (b^c)&=(a^b) | |
| + add r9,r9,r5 @ d+=h | |
| + eor r3,r3,r7 @ Maj(a,b,c) | |
| + add r5,r5,r0,ror#2 @ h+=Sigma0(a) | |
| + @ add r5,r5,r3 @ h+=Maj(a,b,c) | |
| +#if __ARM_ARCH__>=7 | |
| + @ ldr r2,[r1],#4 @ 7 | |
| +# if 7==15 | |
| + str r1,[sp,#17*4] @ make room for r1 | |
| +# endif | |
| + eor r0,r9,r9,ror#5 | |
| + add r5,r5,r3 @ h+=Maj(a,b,c) from the past | |
| + eor r0,r0,r9,ror#19 @ Sigma1(e) | |
| +# ifndef __ARMEB__ | |
| + rev r2,r2 | |
| +# endif | |
| +#else | |
| + @ ldrb r2,[r1,#3] @ 7 | |
| + add r5,r5,r3 @ h+=Maj(a,b,c) from the past | |
| + ldrb r3,[r1,#2] | |
| + ldrb r0,[r1,#1] | |
| + orr r2,r2,r3,lsl#8 | |
| + ldrb r3,[r1],#4 | |
| + orr r2,r2,r0,lsl#16 | |
| +# if 7==15 | |
| + str r1,[sp,#17*4] @ make room for r1 | |
| +# endif | |
| + eor r0,r9,r9,ror#5 | |
| + orr r2,r2,r3,lsl#24 | |
| + eor r0,r0,r9,ror#19 @ Sigma1(e) | |
| +#endif | |
| + ldr r3,[r14],#4 @ *K256++ | |
| + add r4,r4,r2 @ h+=X[i] | |
| + str r2,[sp,#7*4] | |
| + eor r2,r10,r11 | |
| + add r4,r4,r0,ror#6 @ h+=Sigma1(e) | |
| + and r2,r2,r9 | |
| + add r4,r4,r3 @ h+=K256[i] | |
| + eor r2,r2,r11 @ Ch(e,f,g) | |
| + eor r0,r5,r5,ror#11 | |
| + add r4,r4,r2 @ h+=Ch(e,f,g) | |
| +#if 7==31 | |
| + and r3,r3,#0xff | |
| + cmp r3,#0xf2 @ done? | |
| +#endif | |
| +#if 7<15 | |
| +# if __ARM_ARCH__>=7 | |
| + ldr r2,[r1],#4 @ prefetch | |
| +# else | |
| + ldrb r2,[r1,#3] | |
| +# endif | |
| + eor r3,r5,r6 @ a^b, b^c in next round | |
| +#else | |
| + ldr r2,[sp,#9*4] @ from future BODY_16_xx | |
| + eor r3,r5,r6 @ a^b, b^c in next round | |
| + ldr r1,[sp,#6*4] @ from future BODY_16_xx | |
| +#endif | |
| + eor r0,r0,r5,ror#20 @ Sigma0(a) | |
| + and r12,r12,r3 @ (b^c)&=(a^b) | |
| + add r8,r8,r4 @ d+=h | |
| + eor r12,r12,r6 @ Maj(a,b,c) | |
| + add r4,r4,r0,ror#2 @ h+=Sigma0(a) | |
| + @ add r4,r4,r12 @ h+=Maj(a,b,c) | |
| +#if __ARM_ARCH__>=7 | |
| + @ ldr r2,[r1],#4 @ 8 | |
| +# if 8==15 | |
| + str r1,[sp,#17*4] @ make room for r1 | |
| +# endif | |
| + eor r0,r8,r8,ror#5 | |
| + add r4,r4,r12 @ h+=Maj(a,b,c) from the past | |
| + eor r0,r0,r8,ror#19 @ Sigma1(e) | |
| +# ifndef __ARMEB__ | |
| + rev r2,r2 | |
| +# endif | |
| +#else | |
| + @ ldrb r2,[r1,#3] @ 8 | |
| + add r4,r4,r12 @ h+=Maj(a,b,c) from the past | |
| + ldrb r12,[r1,#2] | |
| + ldrb r0,[r1,#1] | |
| + orr r2,r2,r12,lsl#8 | |
| + ldrb r12,[r1],#4 | |
| + orr r2,r2,r0,lsl#16 | |
| +# if 8==15 | |
| + str r1,[sp,#17*4] @ make room for r1 | |
| +# endif | |
| + eor r0,r8,r8,ror#5 | |
| + orr r2,r2,r12,lsl#24 | |
| + eor r0,r0,r8,ror#19 @ Sigma1(e) | |
| +#endif | |
| + ldr r12,[r14],#4 @ *K256++ | |
| + add r11,r11,r2 @ h+=X[i] | |
| + str r2,[sp,#8*4] | |
| + eor r2,r9,r10 | |
| + add r11,r11,r0,ror#6 @ h+=Sigma1(e) | |
| + and r2,r2,r8 | |
| + add r11,r11,r12 @ h+=K256[i] | |
| + eor r2,r2,r10 @ Ch(e,f,g) | |
| + eor r0,r4,r4,ror#11 | |
| + add r11,r11,r2 @ h+=Ch(e,f,g) | |
| +#if 8==31 | |
| + and r12,r12,#0xff | |
| + cmp r12,#0xf2 @ done? | |
| +#endif | |
| +#if 8<15 | |
| +# if __ARM_ARCH__>=7 | |
| + ldr r2,[r1],#4 @ prefetch | |
| +# else | |
| + ldrb r2,[r1,#3] | |
| +# endif | |
| + eor r12,r4,r5 @ a^b, b^c in next round | |
| +#else | |
| + ldr r2,[sp,#10*4] @ from future BODY_16_xx | |
| + eor r12,r4,r5 @ a^b, b^c in next round | |
| + ldr r1,[sp,#7*4] @ from future BODY_16_xx | |
| +#endif | |
| + eor r0,r0,r4,ror#20 @ Sigma0(a) | |
| + and r3,r3,r12 @ (b^c)&=(a^b) | |
| + add r7,r7,r11 @ d+=h | |
| + eor r3,r3,r5 @ Maj(a,b,c) | |
| + add r11,r11,r0,ror#2 @ h+=Sigma0(a) | |
| + @ add r11,r11,r3 @ h+=Maj(a,b,c) | |
| +#if __ARM_ARCH__>=7 | |
| + @ ldr r2,[r1],#4 @ 9 | |
| +# if 9==15 | |
| + str r1,[sp,#17*4] @ make room for r1 | |
| +# endif | |
| + eor r0,r7,r7,ror#5 | |
| + add r11,r11,r3 @ h+=Maj(a,b,c) from the past | |
| + eor r0,r0,r7,ror#19 @ Sigma1(e) | |
| +# ifndef __ARMEB__ | |
| + rev r2,r2 | |
| +# endif | |
| +#else | |
| + @ ldrb r2,[r1,#3] @ 9 | |
| + add r11,r11,r3 @ h+=Maj(a,b,c) from the past | |
| + ldrb r3,[r1,#2] | |
| + ldrb r0,[r1,#1] | |
| + orr r2,r2,r3,lsl#8 | |
| + ldrb r3,[r1],#4 | |
| + orr r2,r2,r0,lsl#16 | |
| +# if 9==15 | |
| + str r1,[sp,#17*4] @ make room for r1 | |
| +# endif | |
| + eor r0,r7,r7,ror#5 | |
| + orr r2,r2,r3,lsl#24 | |
| + eor r0,r0,r7,ror#19 @ Sigma1(e) | |
| +#endif | |
| + ldr r3,[r14],#4 @ *K256++ | |
| + add r10,r10,r2 @ h+=X[i] | |
| + str r2,[sp,#9*4] | |
| + eor r2,r8,r9 | |
| + add r10,r10,r0,ror#6 @ h+=Sigma1(e) | |
| + and r2,r2,r7 | |
| + add r10,r10,r3 @ h+=K256[i] | |
| + eor r2,r2,r9 @ Ch(e,f,g) | |
| + eor r0,r11,r11,ror#11 | |
| + add r10,r10,r2 @ h+=Ch(e,f,g) | |
| +#if 9==31 | |
| + and r3,r3,#0xff | |
| + cmp r3,#0xf2 @ done? | |
| +#endif | |
| +#if 9<15 | |
| +# if __ARM_ARCH__>=7 | |
| + ldr r2,[r1],#4 @ prefetch | |
| +# else | |
| + ldrb r2,[r1,#3] | |
| +# endif | |
| + eor r3,r11,r4 @ a^b, b^c in next round | |
| +#else | |
| + ldr r2,[sp,#11*4] @ from future BODY_16_xx | |
| + eor r3,r11,r4 @ a^b, b^c in next round | |
| + ldr r1,[sp,#8*4] @ from future BODY_16_xx | |
| +#endif | |
| + eor r0,r0,r11,ror#20 @ Sigma0(a) | |
| + and r12,r12,r3 @ (b^c)&=(a^b) | |
| + add r6,r6,r10 @ d+=h | |
| + eor r12,r12,r4 @ Maj(a,b,c) | |
| + add r10,r10,r0,ror#2 @ h+=Sigma0(a) | |
| + @ add r10,r10,r12 @ h+=Maj(a,b,c) | |
| +#if __ARM_ARCH__>=7 | |
| + @ ldr r2,[r1],#4 @ 10 | |
| +# if 10==15 | |
| + str r1,[sp,#17*4] @ make room for r1 | |
| +# endif | |
| + eor r0,r6,r6,ror#5 | |
| + add r10,r10,r12 @ h+=Maj(a,b,c) from the past | |
| + eor r0,r0,r6,ror#19 @ Sigma1(e) | |
| +# ifndef __ARMEB__ | |
| + rev r2,r2 | |
| +# endif | |
| +#else | |
| + @ ldrb r2,[r1,#3] @ 10 | |
| + add r10,r10,r12 @ h+=Maj(a,b,c) from the past | |
| + ldrb r12,[r1,#2] | |
| + ldrb r0,[r1,#1] | |
| + orr r2,r2,r12,lsl#8 | |
| + ldrb r12,[r1],#4 | |
| + orr r2,r2,r0,lsl#16 | |
| +# if 10==15 | |
| + str r1,[sp,#17*4] @ make room for r1 | |
| +# endif | |
| + eor r0,r6,r6,ror#5 | |
| + orr r2,r2,r12,lsl#24 | |
| + eor r0,r0,r6,ror#19 @ Sigma1(e) | |
| +#endif | |
| + ldr r12,[r14],#4 @ *K256++ | |
| + add r9,r9,r2 @ h+=X[i] | |
| + str r2,[sp,#10*4] | |
| + eor r2,r7,r8 | |
| + add r9,r9,r0,ror#6 @ h+=Sigma1(e) | |
| + and r2,r2,r6 | |
| + add r9,r9,r12 @ h+=K256[i] | |
| + eor r2,r2,r8 @ Ch(e,f,g) | |
| + eor r0,r10,r10,ror#11 | |
| + add r9,r9,r2 @ h+=Ch(e,f,g) | |
| +#if 10==31 | |
| + and r12,r12,#0xff | |
| + cmp r12,#0xf2 @ done? | |
| +#endif | |
| +#if 10<15 | |
| +# if __ARM_ARCH__>=7 | |
| + ldr r2,[r1],#4 @ prefetch | |
| +# else | |
| + ldrb r2,[r1,#3] | |
| +# endif | |
| + eor r12,r10,r11 @ a^b, b^c in next round | |
| +#else | |
| + ldr r2,[sp,#12*4] @ from future BODY_16_xx | |
| + eor r12,r10,r11 @ a^b, b^c in next round | |
| + ldr r1,[sp,#9*4] @ from future BODY_16_xx | |
| +#endif | |
| + eor r0,r0,r10,ror#20 @ Sigma0(a) | |
| + and r3,r3,r12 @ (b^c)&=(a^b) | |
| + add r5,r5,r9 @ d+=h | |
| + eor r3,r3,r11 @ Maj(a,b,c) | |
| + add r9,r9,r0,ror#2 @ h+=Sigma0(a) | |
| + @ add r9,r9,r3 @ h+=Maj(a,b,c) | |
| +#if __ARM_ARCH__>=7 | |
| + @ ldr r2,[r1],#4 @ 11 | |
| +# if 11==15 | |
| + str r1,[sp,#17*4] @ make room for r1 | |
| +# endif | |
| + eor r0,r5,r5,ror#5 | |
| + add r9,r9,r3 @ h+=Maj(a,b,c) from the past | |
| + eor r0,r0,r5,ror#19 @ Sigma1(e) | |
| +# ifndef __ARMEB__ | |
| + rev r2,r2 | |
| +# endif | |
| +#else | |
| + @ ldrb r2,[r1,#3] @ 11 | |
| + add r9,r9,r3 @ h+=Maj(a,b,c) from the past | |
| + ldrb r3,[r1,#2] | |
| + ldrb r0,[r1,#1] | |
| + orr r2,r2,r3,lsl#8 | |
| + ldrb r3,[r1],#4 | |
| + orr r2,r2,r0,lsl#16 | |
| +# if 11==15 | |
| + str r1,[sp,#17*4] @ make room for r1 | |
| +# endif | |
| + eor r0,r5,r5,ror#5 | |
| + orr r2,r2,r3,lsl#24 | |
| + eor r0,r0,r5,ror#19 @ Sigma1(e) | |
| +#endif | |
| + ldr r3,[r14],#4 @ *K256++ | |
| + add r8,r8,r2 @ h+=X[i] | |
| + str r2,[sp,#11*4] | |
| + eor r2,r6,r7 | |
| + add r8,r8,r0,ror#6 @ h+=Sigma1(e) | |
| + and r2,r2,r5 | |
| + add r8,r8,r3 @ h+=K256[i] | |
| + eor r2,r2,r7 @ Ch(e,f,g) | |
| + eor r0,r9,r9,ror#11 | |
| + add r8,r8,r2 @ h+=Ch(e,f,g) | |
| +#if 11==31 | |
| + and r3,r3,#0xff | |
| + cmp r3,#0xf2 @ done? | |
| +#endif | |
| +#if 11<15 | |
| +# if __ARM_ARCH__>=7 | |
| + ldr r2,[r1],#4 @ prefetch | |
| +# else | |
| + ldrb r2,[r1,#3] | |
| +# endif | |
| + eor r3,r9,r10 @ a^b, b^c in next round | |
| +#else | |
| + ldr r2,[sp,#13*4] @ from future BODY_16_xx | |
| + eor r3,r9,r10 @ a^b, b^c in next round | |
| + ldr r1,[sp,#10*4] @ from future BODY_16_xx | |
| +#endif | |
| + eor r0,r0,r9,ror#20 @ Sigma0(a) | |
| + and r12,r12,r3 @ (b^c)&=(a^b) | |
| + add r4,r4,r8 @ d+=h | |
| + eor r12,r12,r10 @ Maj(a,b,c) | |
| + add r8,r8,r0,ror#2 @ h+=Sigma0(a) | |
| + @ add r8,r8,r12 @ h+=Maj(a,b,c) | |
| +#if __ARM_ARCH__>=7 | |
| + @ ldr r2,[r1],#4 @ 12 | |
| +# if 12==15 | |
| + str r1,[sp,#17*4] @ make room for r1 | |
| +# endif | |
| + eor r0,r4,r4,ror#5 | |
| + add r8,r8,r12 @ h+=Maj(a,b,c) from the past | |
| + eor r0,r0,r4,ror#19 @ Sigma1(e) | |
| +# ifndef __ARMEB__ | |
| + rev r2,r2 | |
| +# endif | |
| +#else | |
| + @ ldrb r2,[r1,#3] @ 12 | |
| + add r8,r8,r12 @ h+=Maj(a,b,c) from the past | |
| + ldrb r12,[r1,#2] | |
| + ldrb r0,[r1,#1] | |
| + orr r2,r2,r12,lsl#8 | |
| + ldrb r12,[r1],#4 | |
| + orr r2,r2,r0,lsl#16 | |
| +# if 12==15 | |
| + str r1,[sp,#17*4] @ make room for r1 | |
| +# endif | |
| + eor r0,r4,r4,ror#5 | |
| + orr r2,r2,r12,lsl#24 | |
| + eor r0,r0,r4,ror#19 @ Sigma1(e) | |
| +#endif | |
| + ldr r12,[r14],#4 @ *K256++ | |
| + add r7,r7,r2 @ h+=X[i] | |
| + str r2,[sp,#12*4] | |
| + eor r2,r5,r6 | |
| + add r7,r7,r0,ror#6 @ h+=Sigma1(e) | |
| + and r2,r2,r4 | |
| + add r7,r7,r12 @ h+=K256[i] | |
| + eor r2,r2,r6 @ Ch(e,f,g) | |
| + eor r0,r8,r8,ror#11 | |
| + add r7,r7,r2 @ h+=Ch(e,f,g) | |
| +#if 12==31 | |
| + and r12,r12,#0xff | |
| + cmp r12,#0xf2 @ done? | |
| +#endif | |
| +#if 12<15 | |
| +# if __ARM_ARCH__>=7 | |
| + ldr r2,[r1],#4 @ prefetch | |
| +# else | |
| + ldrb r2,[r1,#3] | |
| +# endif | |
| + eor r12,r8,r9 @ a^b, b^c in next round | |
| +#else | |
| + ldr r2,[sp,#14*4] @ from future BODY_16_xx | |
| + eor r12,r8,r9 @ a^b, b^c in next round | |
| + ldr r1,[sp,#11*4] @ from future BODY_16_xx | |
| +#endif | |
| + eor r0,r0,r8,ror#20 @ Sigma0(a) | |
| + and r3,r3,r12 @ (b^c)&=(a^b) | |
| + add r11,r11,r7 @ d+=h | |
| + eor r3,r3,r9 @ Maj(a,b,c) | |
| + add r7,r7,r0,ror#2 @ h+=Sigma0(a) | |
| + @ add r7,r7,r3 @ h+=Maj(a,b,c) | |
| +#if __ARM_ARCH__>=7 | |
| + @ ldr r2,[r1],#4 @ 13 | |
| +# if 13==15 | |
| + str r1,[sp,#17*4] @ make room for r1 | |
| +# endif | |
| + eor r0,r11,r11,ror#5 | |
| + add r7,r7,r3 @ h+=Maj(a,b,c) from the past | |
| + eor r0,r0,r11,ror#19 @ Sigma1(e) | |
| +# ifndef __ARMEB__ | |
| + rev r2,r2 | |
| +# endif | |
| +#else | |
| + @ ldrb r2,[r1,#3] @ 13 | |
| + add r7,r7,r3 @ h+=Maj(a,b,c) from the past | |
| + ldrb r3,[r1,#2] | |
| + ldrb r0,[r1,#1] | |
| + orr r2,r2,r3,lsl#8 | |
| + ldrb r3,[r1],#4 | |
| + orr r2,r2,r0,lsl#16 | |
| +# if 13==15 | |
| + str r1,[sp,#17*4] @ make room for r1 | |
| +# endif | |
| + eor r0,r11,r11,ror#5 | |
| + orr r2,r2,r3,lsl#24 | |
| + eor r0,r0,r11,ror#19 @ Sigma1(e) | |
| +#endif | |
| + ldr r3,[r14],#4 @ *K256++ | |
| + add r6,r6,r2 @ h+=X[i] | |
| + str r2,[sp,#13*4] | |
| + eor r2,r4,r5 | |
| + add r6,r6,r0,ror#6 @ h+=Sigma1(e) | |
| + and r2,r2,r11 | |
| + add r6,r6,r3 @ h+=K256[i] | |
| + eor r2,r2,r5 @ Ch(e,f,g) | |
| + eor r0,r7,r7,ror#11 | |
| + add r6,r6,r2 @ h+=Ch(e,f,g) | |
| +#if 13==31 | |
| + and r3,r3,#0xff | |
| + cmp r3,#0xf2 @ done? | |
| +#endif | |
| +#if 13<15 | |
| +# if __ARM_ARCH__>=7 | |
| + ldr r2,[r1],#4 @ prefetch | |
| +# else | |
| + ldrb r2,[r1,#3] | |
| +# endif | |
| + eor r3,r7,r8 @ a^b, b^c in next round | |
| +#else | |
| + ldr r2,[sp,#15*4] @ from future BODY_16_xx | |
| + eor r3,r7,r8 @ a^b, b^c in next round | |
| + ldr r1,[sp,#12*4] @ from future BODY_16_xx | |
| +#endif | |
| + eor r0,r0,r7,ror#20 @ Sigma0(a) | |
| + and r12,r12,r3 @ (b^c)&=(a^b) | |
| + add r10,r10,r6 @ d+=h | |
| + eor r12,r12,r8 @ Maj(a,b,c) | |
| + add r6,r6,r0,ror#2 @ h+=Sigma0(a) | |
| + @ add r6,r6,r12 @ h+=Maj(a,b,c) | |
| +#if __ARM_ARCH__>=7 | |
| + @ ldr r2,[r1],#4 @ 14 | |
| +# if 14==15 | |
| + str r1,[sp,#17*4] @ make room for r1 | |
| +# endif | |
| + eor r0,r10,r10,ror#5 | |
| + add r6,r6,r12 @ h+=Maj(a,b,c) from the past | |
| + eor r0,r0,r10,ror#19 @ Sigma1(e) | |
| +# ifndef __ARMEB__ | |
| + rev r2,r2 | |
| +# endif | |
| +#else | |
| + @ ldrb r2,[r1,#3] @ 14 | |
| + add r6,r6,r12 @ h+=Maj(a,b,c) from the past | |
| + ldrb r12,[r1,#2] | |
| + ldrb r0,[r1,#1] | |
| + orr r2,r2,r12,lsl#8 | |
| + ldrb r12,[r1],#4 | |
| + orr r2,r2,r0,lsl#16 | |
| +# if 14==15 | |
| + str r1,[sp,#17*4] @ make room for r1 | |
| +# endif | |
| + eor r0,r10,r10,ror#5 | |
| + orr r2,r2,r12,lsl#24 | |
| + eor r0,r0,r10,ror#19 @ Sigma1(e) | |
| +#endif | |
| + ldr r12,[r14],#4 @ *K256++ | |
| + add r5,r5,r2 @ h+=X[i] | |
| + str r2,[sp,#14*4] | |
| + eor r2,r11,r4 | |
| + add r5,r5,r0,ror#6 @ h+=Sigma1(e) | |
| + and r2,r2,r10 | |
| + add r5,r5,r12 @ h+=K256[i] | |
| + eor r2,r2,r4 @ Ch(e,f,g) | |
| + eor r0,r6,r6,ror#11 | |
| + add r5,r5,r2 @ h+=Ch(e,f,g) | |
| +#if 14==31 | |
| + and r12,r12,#0xff | |
| + cmp r12,#0xf2 @ done? | |
| +#endif | |
| +#if 14<15 | |
| +# if __ARM_ARCH__>=7 | |
| + ldr r2,[r1],#4 @ prefetch | |
| +# else | |
| + ldrb r2,[r1,#3] | |
| +# endif | |
| + eor r12,r6,r7 @ a^b, b^c in next round | |
| +#else | |
| + ldr r2,[sp,#0*4] @ from future BODY_16_xx | |
| + eor r12,r6,r7 @ a^b, b^c in next round | |
| + ldr r1,[sp,#13*4] @ from future BODY_16_xx | |
| +#endif | |
| + eor r0,r0,r6,ror#20 @ Sigma0(a) | |
| + and r3,r3,r12 @ (b^c)&=(a^b) | |
| + add r9,r9,r5 @ d+=h | |
| + eor r3,r3,r7 @ Maj(a,b,c) | |
| + add r5,r5,r0,ror#2 @ h+=Sigma0(a) | |
| + @ add r5,r5,r3 @ h+=Maj(a,b,c) | |
| +#if __ARM_ARCH__>=7 | |
| + @ ldr r2,[r1],#4 @ 15 | |
| +# if 15==15 | |
| + str r1,[sp,#17*4] @ make room for r1 | |
| +# endif | |
| + eor r0,r9,r9,ror#5 | |
| + add r5,r5,r3 @ h+=Maj(a,b,c) from the past | |
| + eor r0,r0,r9,ror#19 @ Sigma1(e) | |
| +# ifndef __ARMEB__ | |
| + rev r2,r2 | |
| +# endif | |
| +#else | |
| + @ ldrb r2,[r1,#3] @ 15 | |
| + add r5,r5,r3 @ h+=Maj(a,b,c) from the past | |
| + ldrb r3,[r1,#2] | |
| + ldrb r0,[r1,#1] | |
| + orr r2,r2,r3,lsl#8 | |
| + ldrb r3,[r1],#4 | |
| + orr r2,r2,r0,lsl#16 | |
| +# if 15==15 | |
| + str r1,[sp,#17*4] @ make room for r1 | |
| +# endif | |
| + eor r0,r9,r9,ror#5 | |
| + orr r2,r2,r3,lsl#24 | |
| + eor r0,r0,r9,ror#19 @ Sigma1(e) | |
| +#endif | |
| + ldr r3,[r14],#4 @ *K256++ | |
| + add r4,r4,r2 @ h+=X[i] | |
| + str r2,[sp,#15*4] | |
| + eor r2,r10,r11 | |
| + add r4,r4,r0,ror#6 @ h+=Sigma1(e) | |
| + and r2,r2,r9 | |
| + add r4,r4,r3 @ h+=K256[i] | |
| + eor r2,r2,r11 @ Ch(e,f,g) | |
| + eor r0,r5,r5,ror#11 | |
| + add r4,r4,r2 @ h+=Ch(e,f,g) | |
| +#if 15==31 | |
| + and r3,r3,#0xff | |
| + cmp r3,#0xf2 @ done? | |
| +#endif | |
| +#if 15<15 | |
| +# if __ARM_ARCH__>=7 | |
| + ldr r2,[r1],#4 @ prefetch | |
| +# else | |
| + ldrb r2,[r1,#3] | |
| +# endif | |
| + eor r3,r5,r6 @ a^b, b^c in next round | |
| +#else | |
| + ldr r2,[sp,#1*4] @ from future BODY_16_xx | |
| + eor r3,r5,r6 @ a^b, b^c in next round | |
| + ldr r1,[sp,#14*4] @ from future BODY_16_xx | |
| +#endif | |
| + eor r0,r0,r5,ror#20 @ Sigma0(a) | |
| + and r12,r12,r3 @ (b^c)&=(a^b) | |
| + add r8,r8,r4 @ d+=h | |
| + eor r12,r12,r6 @ Maj(a,b,c) | |
| + add r4,r4,r0,ror#2 @ h+=Sigma0(a) | |
| + @ add r4,r4,r12 @ h+=Maj(a,b,c) | |
| +.Lrounds_16_xx: | |
| + @ ldr r2,[sp,#1*4] @ 16 | |
| + @ ldr r1,[sp,#14*4] | |
| + mov r0,r2,ror#7 | |
| + add r4,r4,r12 @ h+=Maj(a,b,c) from the past | |
| + mov r12,r1,ror#17 | |
| + eor r0,r0,r2,ror#18 | |
| + eor r12,r12,r1,ror#19 | |
| + eor r0,r0,r2,lsr#3 @ sigma0(X[i+1]) | |
| + ldr r2,[sp,#0*4] | |
| + eor r12,r12,r1,lsr#10 @ sigma1(X[i+14]) | |
| + ldr r1,[sp,#9*4] | |
| + | |
| + add r12,r12,r0 | |
| + eor r0,r8,r8,ror#5 @ from BODY_00_15 | |
| + add r2,r2,r12 | |
| + eor r0,r0,r8,ror#19 @ Sigma1(e) | |
| + add r2,r2,r1 @ X[i] | |
| + ldr r12,[r14],#4 @ *K256++ | |
| + add r11,r11,r2 @ h+=X[i] | |
| + str r2,[sp,#0*4] | |
| + eor r2,r9,r10 | |
| + add r11,r11,r0,ror#6 @ h+=Sigma1(e) | |
| + and r2,r2,r8 | |
| + add r11,r11,r12 @ h+=K256[i] | |
| + eor r2,r2,r10 @ Ch(e,f,g) | |
| + eor r0,r4,r4,ror#11 | |
| + add r11,r11,r2 @ h+=Ch(e,f,g) | |
| +#if 16==31 | |
| + and r12,r12,#0xff | |
| + cmp r12,#0xf2 @ done? | |
| +#endif | |
| +#if 16<15 | |
| +# if __ARM_ARCH__>=7 | |
| + ldr r2,[r1],#4 @ prefetch | |
| +# else | |
| + ldrb r2,[r1,#3] | |
| +# endif | |
| + eor r12,r4,r5 @ a^b, b^c in next round | |
| +#else | |
| + ldr r2,[sp,#2*4] @ from future BODY_16_xx | |
| + eor r12,r4,r5 @ a^b, b^c in next round | |
| + ldr r1,[sp,#15*4] @ from future BODY_16_xx | |
| +#endif | |
| + eor r0,r0,r4,ror#20 @ Sigma0(a) | |
| + and r3,r3,r12 @ (b^c)&=(a^b) | |
| + add r7,r7,r11 @ d+=h | |
| + eor r3,r3,r5 @ Maj(a,b,c) | |
| + add r11,r11,r0,ror#2 @ h+=Sigma0(a) | |
| + @ add r11,r11,r3 @ h+=Maj(a,b,c) | |
| + @ ldr r2,[sp,#2*4] @ 17 | |
| + @ ldr r1,[sp,#15*4] | |
| + mov r0,r2,ror#7 | |
| + add r11,r11,r3 @ h+=Maj(a,b,c) from the past | |
| + mov r3,r1,ror#17 | |
| + eor r0,r0,r2,ror#18 | |
| + eor r3,r3,r1,ror#19 | |
| + eor r0,r0,r2,lsr#3 @ sigma0(X[i+1]) | |
| + ldr r2,[sp,#1*4] | |
| + eor r3,r3,r1,lsr#10 @ sigma1(X[i+14]) | |
| + ldr r1,[sp,#10*4] | |
| + | |
| + add r3,r3,r0 | |
| + eor r0,r7,r7,ror#5 @ from BODY_00_15 | |
| + add r2,r2,r3 | |
| + eor r0,r0,r7,ror#19 @ Sigma1(e) | |
| + add r2,r2,r1 @ X[i] | |
| + ldr r3,[r14],#4 @ *K256++ | |
| + add r10,r10,r2 @ h+=X[i] | |
| + str r2,[sp,#1*4] | |
| + eor r2,r8,r9 | |
| + add r10,r10,r0,ror#6 @ h+=Sigma1(e) | |
| + and r2,r2,r7 | |
| + add r10,r10,r3 @ h+=K256[i] | |
| + eor r2,r2,r9 @ Ch(e,f,g) | |
| + eor r0,r11,r11,ror#11 | |
| + add r10,r10,r2 @ h+=Ch(e,f,g) | |
| +#if 17==31 | |
| + and r3,r3,#0xff | |
| + cmp r3,#0xf2 @ done? | |
| +#endif | |
| +#if 17<15 | |
| +# if __ARM_ARCH__>=7 | |
| + ldr r2,[r1],#4 @ prefetch | |
| +# else | |
| + ldrb r2,[r1,#3] | |
| +# endif | |
| + eor r3,r11,r4 @ a^b, b^c in next round | |
| +#else | |
| + ldr r2,[sp,#3*4] @ from future BODY_16_xx | |
| + eor r3,r11,r4 @ a^b, b^c in next round | |
| + ldr r1,[sp,#0*4] @ from future BODY_16_xx | |
| +#endif | |
| + eor r0,r0,r11,ror#20 @ Sigma0(a) | |
| + and r12,r12,r3 @ (b^c)&=(a^b) | |
| + add r6,r6,r10 @ d+=h | |
| + eor r12,r12,r4 @ Maj(a,b,c) | |
| + add r10,r10,r0,ror#2 @ h+=Sigma0(a) | |
| + @ add r10,r10,r12 @ h+=Maj(a,b,c) | |
| + @ ldr r2,[sp,#3*4] @ 18 | |
| + @ ldr r1,[sp,#0*4] | |
| + mov r0,r2,ror#7 | |
| + add r10,r10,r12 @ h+=Maj(a,b,c) from the past | |
| + mov r12,r1,ror#17 | |
| + eor r0,r0,r2,ror#18 | |
| + eor r12,r12,r1,ror#19 | |
| + eor r0,r0,r2,lsr#3 @ sigma0(X[i+1]) | |
| + ldr r2,[sp,#2*4] | |
| + eor r12,r12,r1,lsr#10 @ sigma1(X[i+14]) | |
| + ldr r1,[sp,#11*4] | |
| + | |
| + add r12,r12,r0 | |
| + eor r0,r6,r6,ror#5 @ from BODY_00_15 | |
| + add r2,r2,r12 | |
| + eor r0,r0,r6,ror#19 @ Sigma1(e) | |
| + add r2,r2,r1 @ X[i] | |
| + ldr r12,[r14],#4 @ *K256++ | |
| + add r9,r9,r2 @ h+=X[i] | |
| + str r2,[sp,#2*4] | |
| + eor r2,r7,r8 | |
| + add r9,r9,r0,ror#6 @ h+=Sigma1(e) | |
| + and r2,r2,r6 | |
| + add r9,r9,r12 @ h+=K256[i] | |
| + eor r2,r2,r8 @ Ch(e,f,g) | |
| + eor r0,r10,r10,ror#11 | |
| + add r9,r9,r2 @ h+=Ch(e,f,g) | |
| +#if 18==31 | |
| + and r12,r12,#0xff | |
| + cmp r12,#0xf2 @ done? | |
| +#endif | |
| +#if 18<15 | |
| +# if __ARM_ARCH__>=7 | |
| + ldr r2,[r1],#4 @ prefetch | |
| +# else | |
| + ldrb r2,[r1,#3] | |
| +# endif | |
| + eor r12,r10,r11 @ a^b, b^c in next round | |
| +#else | |
| + ldr r2,[sp,#4*4] @ from future BODY_16_xx | |
| + eor r12,r10,r11 @ a^b, b^c in next round | |
| + ldr r1,[sp,#1*4] @ from future BODY_16_xx | |
| +#endif | |
| + eor r0,r0,r10,ror#20 @ Sigma0(a) | |
| + and r3,r3,r12 @ (b^c)&=(a^b) | |
| + add r5,r5,r9 @ d+=h | |
| + eor r3,r3,r11 @ Maj(a,b,c) | |
| + add r9,r9,r0,ror#2 @ h+=Sigma0(a) | |
| + @ add r9,r9,r3 @ h+=Maj(a,b,c) | |
| + @ ldr r2,[sp,#4*4] @ 19 | |
| + @ ldr r1,[sp,#1*4] | |
| + mov r0,r2,ror#7 | |
| + add r9,r9,r3 @ h+=Maj(a,b,c) from the past | |
| + mov r3,r1,ror#17 | |
| + eor r0,r0,r2,ror#18 | |
| + eor r3,r3,r1,ror#19 | |
| + eor r0,r0,r2,lsr#3 @ sigma0(X[i+1]) | |
| + ldr r2,[sp,#3*4] | |
| + eor r3,r3,r1,lsr#10 @ sigma1(X[i+14]) | |
| + ldr r1,[sp,#12*4] | |
| + | |
| + add r3,r3,r0 | |
| + eor r0,r5,r5,ror#5 @ from BODY_00_15 | |
| + add r2,r2,r3 | |
| + eor r0,r0,r5,ror#19 @ Sigma1(e) | |
| + add r2,r2,r1 @ X[i] | |
| + ldr r3,[r14],#4 @ *K256++ | |
| + add r8,r8,r2 @ h+=X[i] | |
| + str r2,[sp,#3*4] | |
| + eor r2,r6,r7 | |
| + add r8,r8,r0,ror#6 @ h+=Sigma1(e) | |
| + and r2,r2,r5 | |
| + add r8,r8,r3 @ h+=K256[i] | |
| + eor r2,r2,r7 @ Ch(e,f,g) | |
| + eor r0,r9,r9,ror#11 | |
| + add r8,r8,r2 @ h+=Ch(e,f,g) | |
| +#if 19==31 | |
| + and r3,r3,#0xff | |
| + cmp r3,#0xf2 @ done? | |
| +#endif | |
| +#if 19<15 | |
| +# if __ARM_ARCH__>=7 | |
| + ldr r2,[r1],#4 @ prefetch | |
| +# else | |
| + ldrb r2,[r1,#3] | |
| +# endif | |
| + eor r3,r9,r10 @ a^b, b^c in next round | |
| +#else | |
| + ldr r2,[sp,#5*4] @ from future BODY_16_xx | |
| + eor r3,r9,r10 @ a^b, b^c in next round | |
| + ldr r1,[sp,#2*4] @ from future BODY_16_xx | |
| +#endif | |
| + eor r0,r0,r9,ror#20 @ Sigma0(a) | |
| + and r12,r12,r3 @ (b^c)&=(a^b) | |
| + add r4,r4,r8 @ d+=h | |
| + eor r12,r12,r10 @ Maj(a,b,c) | |
| + add r8,r8,r0,ror#2 @ h+=Sigma0(a) | |
| + @ add r8,r8,r12 @ h+=Maj(a,b,c) | |
| + @ ldr r2,[sp,#5*4] @ 20 | |
| + @ ldr r1,[sp,#2*4] | |
| + mov r0,r2,ror#7 | |
| + add r8,r8,r12 @ h+=Maj(a,b,c) from the past | |
| + mov r12,r1,ror#17 | |
| + eor r0,r0,r2,ror#18 | |
| + eor r12,r12,r1,ror#19 | |
| + eor r0,r0,r2,lsr#3 @ sigma0(X[i+1]) | |
| + ldr r2,[sp,#4*4] | |
| + eor r12,r12,r1,lsr#10 @ sigma1(X[i+14]) | |
| + ldr r1,[sp,#13*4] | |
| + | |
| + add r12,r12,r0 | |
| + eor r0,r4,r4,ror#5 @ from BODY_00_15 | |
| + add r2,r2,r12 | |
| + eor r0,r0,r4,ror#19 @ Sigma1(e) | |
| + add r2,r2,r1 @ X[i] | |
| + ldr r12,[r14],#4 @ *K256++ | |
| + add r7,r7,r2 @ h+=X[i] | |
| + str r2,[sp,#4*4] | |
| + eor r2,r5,r6 | |
| + add r7,r7,r0,ror#6 @ h+=Sigma1(e) | |
| + and r2,r2,r4 | |
| + add r7,r7,r12 @ h+=K256[i] | |
| + eor r2,r2,r6 @ Ch(e,f,g) | |
| + eor r0,r8,r8,ror#11 | |
| + add r7,r7,r2 @ h+=Ch(e,f,g) | |
| +#if 20==31 | |
| + and r12,r12,#0xff | |
| + cmp r12,#0xf2 @ done? | |
| +#endif | |
| +#if 20<15 | |
| +# if __ARM_ARCH__>=7 | |
| + ldr r2,[r1],#4 @ prefetch | |
| +# else | |
| + ldrb r2,[r1,#3] | |
| +# endif | |
| + eor r12,r8,r9 @ a^b, b^c in next round | |
| +#else | |
| + ldr r2,[sp,#6*4] @ from future BODY_16_xx | |
| + eor r12,r8,r9 @ a^b, b^c in next round | |
| + ldr r1,[sp,#3*4] @ from future BODY_16_xx | |
| +#endif | |
| + eor r0,r0,r8,ror#20 @ Sigma0(a) | |
| + and r3,r3,r12 @ (b^c)&=(a^b) | |
| + add r11,r11,r7 @ d+=h | |
| + eor r3,r3,r9 @ Maj(a,b,c) | |
| + add r7,r7,r0,ror#2 @ h+=Sigma0(a) | |
| + @ add r7,r7,r3 @ h+=Maj(a,b,c) | |
| + @ ldr r2,[sp,#6*4] @ 21 | |
| + @ ldr r1,[sp,#3*4] | |
| + mov r0,r2,ror#7 | |
| + add r7,r7,r3 @ h+=Maj(a,b,c) from the past | |
| + mov r3,r1,ror#17 | |
| + eor r0,r0,r2,ror#18 | |
| + eor r3,r3,r1,ror#19 | |
| + eor r0,r0,r2,lsr#3 @ sigma0(X[i+1]) | |
| + ldr r2,[sp,#5*4] | |
| + eor r3,r3,r1,lsr#10 @ sigma1(X[i+14]) | |
| + ldr r1,[sp,#14*4] | |
| + | |
| + add r3,r3,r0 | |
| + eor r0,r11,r11,ror#5 @ from BODY_00_15 | |
| + add r2,r2,r3 | |
| + eor r0,r0,r11,ror#19 @ Sigma1(e) | |
| + add r2,r2,r1 @ X[i] | |
| + ldr r3,[r14],#4 @ *K256++ | |
| + add r6,r6,r2 @ h+=X[i] | |
| + str r2,[sp,#5*4] | |
| + eor r2,r4,r5 | |
| + add r6,r6,r0,ror#6 @ h+=Sigma1(e) | |
| + and r2,r2,r11 | |
| + add r6,r6,r3 @ h+=K256[i] | |
| + eor r2,r2,r5 @ Ch(e,f,g) | |
| + eor r0,r7,r7,ror#11 | |
| + add r6,r6,r2 @ h+=Ch(e,f,g) | |
| +#if 21==31 | |
| + and r3,r3,#0xff | |
| + cmp r3,#0xf2 @ done? | |
| +#endif | |
| +#if 21<15 | |
| +# if __ARM_ARCH__>=7 | |
| + ldr r2,[r1],#4 @ prefetch | |
| +# else | |
| + ldrb r2,[r1,#3] | |
| +# endif | |
| + eor r3,r7,r8 @ a^b, b^c in next round | |
| +#else | |
| + ldr r2,[sp,#7*4] @ from future BODY_16_xx | |
| + eor r3,r7,r8 @ a^b, b^c in next round | |
| + ldr r1,[sp,#4*4] @ from future BODY_16_xx | |
| +#endif | |
| + eor r0,r0,r7,ror#20 @ Sigma0(a) | |
| + and r12,r12,r3 @ (b^c)&=(a^b) | |
| + add r10,r10,r6 @ d+=h | |
| + eor r12,r12,r8 @ Maj(a,b,c) | |
| + add r6,r6,r0,ror#2 @ h+=Sigma0(a) | |
| + @ add r6,r6,r12 @ h+=Maj(a,b,c) | |
| + @ ldr r2,[sp,#7*4] @ 22 | |
| + @ ldr r1,[sp,#4*4] | |
| + mov r0,r2,ror#7 | |
| + add r6,r6,r12 @ h+=Maj(a,b,c) from the past | |
| + mov r12,r1,ror#17 | |
| + eor r0,r0,r2,ror#18 | |
| + eor r12,r12,r1,ror#19 | |
| + eor r0,r0,r2,lsr#3 @ sigma0(X[i+1]) | |
| + ldr r2,[sp,#6*4] | |
| + eor r12,r12,r1,lsr#10 @ sigma1(X[i+14]) | |
| + ldr r1,[sp,#15*4] | |
| + | |
| + add r12,r12,r0 | |
| + eor r0,r10,r10,ror#5 @ from BODY_00_15 | |
| + add r2,r2,r12 | |
| + eor r0,r0,r10,ror#19 @ Sigma1(e) | |
| + add r2,r2,r1 @ X[i] | |
| + ldr r12,[r14],#4 @ *K256++ | |
| + add r5,r5,r2 @ h+=X[i] | |
| + str r2,[sp,#6*4] | |
| + eor r2,r11,r4 | |
| + add r5,r5,r0,ror#6 @ h+=Sigma1(e) | |
| + and r2,r2,r10 | |
| + add r5,r5,r12 @ h+=K256[i] | |
| + eor r2,r2,r4 @ Ch(e,f,g) | |
| + eor r0,r6,r6,ror#11 | |
| + add r5,r5,r2 @ h+=Ch(e,f,g) | |
| +#if 22==31 | |
| + and r12,r12,#0xff | |
| + cmp r12,#0xf2 @ done? | |
| +#endif | |
| +#if 22<15 | |
| +# if __ARM_ARCH__>=7 | |
| + ldr r2,[r1],#4 @ prefetch | |
| +# else | |
| + ldrb r2,[r1,#3] | |
| +# endif | |
| + eor r12,r6,r7 @ a^b, b^c in next round | |
| +#else | |
| + ldr r2,[sp,#8*4] @ from future BODY_16_xx | |
| + eor r12,r6,r7 @ a^b, b^c in next round | |
| + ldr r1,[sp,#5*4] @ from future BODY_16_xx | |
| +#endif | |
| + eor r0,r0,r6,ror#20 @ Sigma0(a) | |
| + and r3,r3,r12 @ (b^c)&=(a^b) | |
| + add r9,r9,r5 @ d+=h | |
| + eor r3,r3,r7 @ Maj(a,b,c) | |
| + add r5,r5,r0,ror#2 @ h+=Sigma0(a) | |
| + @ add r5,r5,r3 @ h+=Maj(a,b,c) | |
| + @ ldr r2,[sp,#8*4] @ 23 | |
| + @ ldr r1,[sp,#5*4] | |
| + mov r0,r2,ror#7 | |
| + add r5,r5,r3 @ h+=Maj(a,b,c) from the past | |
| + mov r3,r1,ror#17 | |
| + eor r0,r0,r2,ror#18 | |
| + eor r3,r3,r1,ror#19 | |
| + eor r0,r0,r2,lsr#3 @ sigma0(X[i+1]) | |
| + ldr r2,[sp,#7*4] | |
| + eor r3,r3,r1,lsr#10 @ sigma1(X[i+14]) | |
| + ldr r1,[sp,#0*4] | |
| + | |
| + add r3,r3,r0 | |
| + eor r0,r9,r9,ror#5 @ from BODY_00_15 | |
| + add r2,r2,r3 | |
| + eor r0,r0,r9,ror#19 @ Sigma1(e) | |
| + add r2,r2,r1 @ X[i] | |
| + ldr r3,[r14],#4 @ *K256++ | |
| + add r4,r4,r2 @ h+=X[i] | |
| + str r2,[sp,#7*4] | |
| + eor r2,r10,r11 | |
| + add r4,r4,r0,ror#6 @ h+=Sigma1(e) | |
| + and r2,r2,r9 | |
| + add r4,r4,r3 @ h+=K256[i] | |
| + eor r2,r2,r11 @ Ch(e,f,g) | |
| + eor r0,r5,r5,ror#11 | |
| + add r4,r4,r2 @ h+=Ch(e,f,g) | |
| +#if 23==31 | |
| + and r3,r3,#0xff | |
| + cmp r3,#0xf2 @ done? | |
| +#endif | |
| +#if 23<15 | |
| +# if __ARM_ARCH__>=7 | |
| + ldr r2,[r1],#4 @ prefetch | |
| +# else | |
| + ldrb r2,[r1,#3] | |
| +# endif | |
| + eor r3,r5,r6 @ a^b, b^c in next round | |
| +#else | |
| + ldr r2,[sp,#9*4] @ from future BODY_16_xx | |
| + eor r3,r5,r6 @ a^b, b^c in next round | |
| + ldr r1,[sp,#6*4] @ from future BODY_16_xx | |
| +#endif | |
| + eor r0,r0,r5,ror#20 @ Sigma0(a) | |
| + and r12,r12,r3 @ (b^c)&=(a^b) | |
| + add r8,r8,r4 @ d+=h | |
| + eor r12,r12,r6 @ Maj(a,b,c) | |
| + add r4,r4,r0,ror#2 @ h+=Sigma0(a) | |
| + @ add r4,r4,r12 @ h+=Maj(a,b,c) | |
| + @ ldr r2,[sp,#9*4] @ 24 | |
| + @ ldr r1,[sp,#6*4] | |
| + mov r0,r2,ror#7 | |
| + add r4,r4,r12 @ h+=Maj(a,b,c) from the past | |
| + mov r12,r1,ror#17 | |
| + eor r0,r0,r2,ror#18 | |
| + eor r12,r12,r1,ror#19 | |
| + eor r0,r0,r2,lsr#3 @ sigma0(X[i+1]) | |
| + ldr r2,[sp,#8*4] | |
| + eor r12,r12,r1,lsr#10 @ sigma1(X[i+14]) | |
| + ldr r1,[sp,#1*4] | |
| + | |
| + add r12,r12,r0 | |
| + eor r0,r8,r8,ror#5 @ from BODY_00_15 | |
| + add r2,r2,r12 | |
| + eor r0,r0,r8,ror#19 @ Sigma1(e) | |
| + add r2,r2,r1 @ X[i] | |
| + ldr r12,[r14],#4 @ *K256++ | |
| + add r11,r11,r2 @ h+=X[i] | |
| + str r2,[sp,#8*4] | |
| + eor r2,r9,r10 | |
| + add r11,r11,r0,ror#6 @ h+=Sigma1(e) | |
| + and r2,r2,r8 | |
| + add r11,r11,r12 @ h+=K256[i] | |
| + eor r2,r2,r10 @ Ch(e,f,g) | |
| + eor r0,r4,r4,ror#11 | |
| + add r11,r11,r2 @ h+=Ch(e,f,g) | |
| +#if 24==31 | |
| + and r12,r12,#0xff | |
| + cmp r12,#0xf2 @ done? | |
| +#endif | |
| +#if 24<15 | |
| +# if __ARM_ARCH__>=7 | |
| + ldr r2,[r1],#4 @ prefetch | |
| +# else | |
| + ldrb r2,[r1,#3] | |
| +# endif | |
| + eor r12,r4,r5 @ a^b, b^c in next round | |
| +#else | |
| + ldr r2,[sp,#10*4] @ from future BODY_16_xx | |
| + eor r12,r4,r5 @ a^b, b^c in next round | |
| + ldr r1,[sp,#7*4] @ from future BODY_16_xx | |
| +#endif | |
| + eor r0,r0,r4,ror#20 @ Sigma0(a) | |
| + and r3,r3,r12 @ (b^c)&=(a^b) | |
| + add r7,r7,r11 @ d+=h | |
| + eor r3,r3,r5 @ Maj(a,b,c) | |
| + add r11,r11,r0,ror#2 @ h+=Sigma0(a) | |
| + @ add r11,r11,r3 @ h+=Maj(a,b,c) | |
| + @ ldr r2,[sp,#10*4] @ 25 | |
| + @ ldr r1,[sp,#7*4] | |
| + mov r0,r2,ror#7 | |
| + add r11,r11,r3 @ h+=Maj(a,b,c) from the past | |
| + mov r3,r1,ror#17 | |
| + eor r0,r0,r2,ror#18 | |
| + eor r3,r3,r1,ror#19 | |
| + eor r0,r0,r2,lsr#3 @ sigma0(X[i+1]) | |
| + ldr r2,[sp,#9*4] | |
| + eor r3,r3,r1,lsr#10 @ sigma1(X[i+14]) | |
| + ldr r1,[sp,#2*4] | |
| + | |
| + add r3,r3,r0 | |
| + eor r0,r7,r7,ror#5 @ from BODY_00_15 | |
| + add r2,r2,r3 | |
| + eor r0,r0,r7,ror#19 @ Sigma1(e) | |
| + add r2,r2,r1 @ X[i] | |
| + ldr r3,[r14],#4 @ *K256++ | |
| + add r10,r10,r2 @ h+=X[i] | |
| + str r2,[sp,#9*4] | |
| + eor r2,r8,r9 | |
| + add r10,r10,r0,ror#6 @ h+=Sigma1(e) | |
| + and r2,r2,r7 | |
| + add r10,r10,r3 @ h+=K256[i] | |
| + eor r2,r2,r9 @ Ch(e,f,g) | |
| + eor r0,r11,r11,ror#11 | |
| + add r10,r10,r2 @ h+=Ch(e,f,g) | |
| +#if 25==31 | |
| + and r3,r3,#0xff | |
| + cmp r3,#0xf2 @ done? | |
| +#endif | |
| +#if 25<15 | |
| +# if __ARM_ARCH__>=7 | |
| + ldr r2,[r1],#4 @ prefetch | |
| +# else | |
| + ldrb r2,[r1,#3] | |
| +# endif | |
| + eor r3,r11,r4 @ a^b, b^c in next round | |
| +#else | |
| + ldr r2,[sp,#11*4] @ from future BODY_16_xx | |
| + eor r3,r11,r4 @ a^b, b^c in next round | |
| + ldr r1,[sp,#8*4] @ from future BODY_16_xx | |
| +#endif | |
| + eor r0,r0,r11,ror#20 @ Sigma0(a) | |
| + and r12,r12,r3 @ (b^c)&=(a^b) | |
| + add r6,r6,r10 @ d+=h | |
| + eor r12,r12,r4 @ Maj(a,b,c) | |
| + add r10,r10,r0,ror#2 @ h+=Sigma0(a) | |
| + @ add r10,r10,r12 @ h+=Maj(a,b,c) | |
| + @ ldr r2,[sp,#11*4] @ 26 | |
| + @ ldr r1,[sp,#8*4] | |
| + mov r0,r2,ror#7 | |
| + add r10,r10,r12 @ h+=Maj(a,b,c) from the past | |
| + mov r12,r1,ror#17 | |
| + eor r0,r0,r2,ror#18 | |
| + eor r12,r12,r1,ror#19 | |
| + eor r0,r0,r2,lsr#3 @ sigma0(X[i+1]) | |
| + ldr r2,[sp,#10*4] | |
| + eor r12,r12,r1,lsr#10 @ sigma1(X[i+14]) | |
| + ldr r1,[sp,#3*4] | |
| + | |
| + add r12,r12,r0 | |
| + eor r0,r6,r6,ror#5 @ from BODY_00_15 | |
| + add r2,r2,r12 | |
| + eor r0,r0,r6,ror#19 @ Sigma1(e) | |
| + add r2,r2,r1 @ X[i] | |
| + ldr r12,[r14],#4 @ *K256++ | |
| + add r9,r9,r2 @ h+=X[i] | |
| + str r2,[sp,#10*4] | |
| + eor r2,r7,r8 | |
| + add r9,r9,r0,ror#6 @ h+=Sigma1(e) | |
| + and r2,r2,r6 | |
| + add r9,r9,r12 @ h+=K256[i] | |
| + eor r2,r2,r8 @ Ch(e,f,g) | |
| + eor r0,r10,r10,ror#11 | |
| + add r9,r9,r2 @ h+=Ch(e,f,g) | |
| +#if 26==31 | |
| + and r12,r12,#0xff | |
| + cmp r12,#0xf2 @ done? | |
| +#endif | |
| +#if 26<15 | |
| +# if __ARM_ARCH__>=7 | |
| + ldr r2,[r1],#4 @ prefetch | |
| +# else | |
| + ldrb r2,[r1,#3] | |
| +# endif | |
| + eor r12,r10,r11 @ a^b, b^c in next round | |
| +#else | |
| + ldr r2,[sp,#12*4] @ from future BODY_16_xx | |
| + eor r12,r10,r11 @ a^b, b^c in next round | |
| + ldr r1,[sp,#9*4] @ from future BODY_16_xx | |
| +#endif | |
| + eor r0,r0,r10,ror#20 @ Sigma0(a) | |
| + and r3,r3,r12 @ (b^c)&=(a^b) | |
| + add r5,r5,r9 @ d+=h | |
| + eor r3,r3,r11 @ Maj(a,b,c) | |
| + add r9,r9,r0,ror#2 @ h+=Sigma0(a) | |
| + @ add r9,r9,r3 @ h+=Maj(a,b,c) | |
| + @ ldr r2,[sp,#12*4] @ 27 | |
| + @ ldr r1,[sp,#9*4] | |
| + mov r0,r2,ror#7 | |
| + add r9,r9,r3 @ h+=Maj(a,b,c) from the past | |
| + mov r3,r1,ror#17 | |
| + eor r0,r0,r2,ror#18 | |
| + eor r3,r3,r1,ror#19 | |
| + eor r0,r0,r2,lsr#3 @ sigma0(X[i+1]) | |
| + ldr r2,[sp,#11*4] | |
| + eor r3,r3,r1,lsr#10 @ sigma1(X[i+14]) | |
| + ldr r1,[sp,#4*4] | |
| + | |
| + add r3,r3,r0 | |
| + eor r0,r5,r5,ror#5 @ from BODY_00_15 | |
| + add r2,r2,r3 | |
| + eor r0,r0,r5,ror#19 @ Sigma1(e) | |
| + add r2,r2,r1 @ X[i] | |
| + ldr r3,[r14],#4 @ *K256++ | |
| + add r8,r8,r2 @ h+=X[i] | |
| + str r2,[sp,#11*4] | |
| + eor r2,r6,r7 | |
| + add r8,r8,r0,ror#6 @ h+=Sigma1(e) | |
| + and r2,r2,r5 | |
| + add r8,r8,r3 @ h+=K256[i] | |
| + eor r2,r2,r7 @ Ch(e,f,g) | |
| + eor r0,r9,r9,ror#11 | |
| + add r8,r8,r2 @ h+=Ch(e,f,g) | |
| +#if 27==31 | |
| + and r3,r3,#0xff | |
| + cmp r3,#0xf2 @ done? | |
| +#endif | |
| +#if 27<15 | |
| +# if __ARM_ARCH__>=7 | |
| + ldr r2,[r1],#4 @ prefetch | |
| +# else | |
| + ldrb r2,[r1,#3] | |
| +# endif | |
| + eor r3,r9,r10 @ a^b, b^c in next round | |
| +#else | |
| + ldr r2,[sp,#13*4] @ from future BODY_16_xx | |
| + eor r3,r9,r10 @ a^b, b^c in next round | |
| + ldr r1,[sp,#10*4] @ from future BODY_16_xx | |
| +#endif | |
| + eor r0,r0,r9,ror#20 @ Sigma0(a) | |
| + and r12,r12,r3 @ (b^c)&=(a^b) | |
| + add r4,r4,r8 @ d+=h | |
| + eor r12,r12,r10 @ Maj(a,b,c) | |
| + add r8,r8,r0,ror#2 @ h+=Sigma0(a) | |
| + @ add r8,r8,r12 @ h+=Maj(a,b,c) | |
| + @ ldr r2,[sp,#13*4] @ 28 | |
| + @ ldr r1,[sp,#10*4] | |
| + mov r0,r2,ror#7 | |
| + add r8,r8,r12 @ h+=Maj(a,b,c) from the past | |
| + mov r12,r1,ror#17 | |
| + eor r0,r0,r2,ror#18 | |
| + eor r12,r12,r1,ror#19 | |
| + eor r0,r0,r2,lsr#3 @ sigma0(X[i+1]) | |
| + ldr r2,[sp,#12*4] | |
| + eor r12,r12,r1,lsr#10 @ sigma1(X[i+14]) | |
| + ldr r1,[sp,#5*4] | |
| + | |
| + add r12,r12,r0 | |
| + eor r0,r4,r4,ror#5 @ from BODY_00_15 | |
| + add r2,r2,r12 | |
| + eor r0,r0,r4,ror#19 @ Sigma1(e) | |
| + add r2,r2,r1 @ X[i] | |
| + ldr r12,[r14],#4 @ *K256++ | |
| + add r7,r7,r2 @ h+=X[i] | |
| + str r2,[sp,#12*4] | |
| + eor r2,r5,r6 | |
| + add r7,r7,r0,ror#6 @ h+=Sigma1(e) | |
| + and r2,r2,r4 | |
| + add r7,r7,r12 @ h+=K256[i] | |
| + eor r2,r2,r6 @ Ch(e,f,g) | |
| + eor r0,r8,r8,ror#11 | |
| + add r7,r7,r2 @ h+=Ch(e,f,g) | |
| +#if 28==31 | |
| + and r12,r12,#0xff | |
| + cmp r12,#0xf2 @ done? | |
| +#endif | |
| +#if 28<15 | |
| +# if __ARM_ARCH__>=7 | |
| + ldr r2,[r1],#4 @ prefetch | |
| +# else | |
| + ldrb r2,[r1,#3] | |
| +# endif | |
| + eor r12,r8,r9 @ a^b, b^c in next round | |
| +#else | |
| + ldr r2,[sp,#14*4] @ from future BODY_16_xx | |
| + eor r12,r8,r9 @ a^b, b^c in next round | |
| + ldr r1,[sp,#11*4] @ from future BODY_16_xx | |
| +#endif | |
| + eor r0,r0,r8,ror#20 @ Sigma0(a) | |
| + and r3,r3,r12 @ (b^c)&=(a^b) | |
| + add r11,r11,r7 @ d+=h | |
| + eor r3,r3,r9 @ Maj(a,b,c) | |
| + add r7,r7,r0,ror#2 @ h+=Sigma0(a) | |
| + @ add r7,r7,r3 @ h+=Maj(a,b,c) | |
| + @ ldr r2,[sp,#14*4] @ 29 | |
| + @ ldr r1,[sp,#11*4] | |
| + mov r0,r2,ror#7 | |
| + add r7,r7,r3 @ h+=Maj(a,b,c) from the past | |
| + mov r3,r1,ror#17 | |
| + eor r0,r0,r2,ror#18 | |
| + eor r3,r3,r1,ror#19 | |
| + eor r0,r0,r2,lsr#3 @ sigma0(X[i+1]) | |
| + ldr r2,[sp,#13*4] | |
| + eor r3,r3,r1,lsr#10 @ sigma1(X[i+14]) | |
| + ldr r1,[sp,#6*4] | |
| + | |
| + add r3,r3,r0 | |
| + eor r0,r11,r11,ror#5 @ from BODY_00_15 | |
| + add r2,r2,r3 | |
| + eor r0,r0,r11,ror#19 @ Sigma1(e) | |
| + add r2,r2,r1 @ X[i] | |
| + ldr r3,[r14],#4 @ *K256++ | |
| + add r6,r6,r2 @ h+=X[i] | |
| + str r2,[sp,#13*4] | |
| + eor r2,r4,r5 | |
| + add r6,r6,r0,ror#6 @ h+=Sigma1(e) | |
| + and r2,r2,r11 | |
| + add r6,r6,r3 @ h+=K256[i] | |
| + eor r2,r2,r5 @ Ch(e,f,g) | |
| + eor r0,r7,r7,ror#11 | |
| + add r6,r6,r2 @ h+=Ch(e,f,g) | |
| +#if 29==31 | |
| + and r3,r3,#0xff | |
| + cmp r3,#0xf2 @ done? | |
| +#endif | |
| +#if 29<15 | |
| +# if __ARM_ARCH__>=7 | |
| + ldr r2,[r1],#4 @ prefetch | |
| +# else | |
| + ldrb r2,[r1,#3] | |
| +# endif | |
| + eor r3,r7,r8 @ a^b, b^c in next round | |
| +#else | |
| + ldr r2,[sp,#15*4] @ from future BODY_16_xx | |
| + eor r3,r7,r8 @ a^b, b^c in next round | |
| + ldr r1,[sp,#12*4] @ from future BODY_16_xx | |
| +#endif | |
| + eor r0,r0,r7,ror#20 @ Sigma0(a) | |
| + and r12,r12,r3 @ (b^c)&=(a^b) | |
| + add r10,r10,r6 @ d+=h | |
| + eor r12,r12,r8 @ Maj(a,b,c) | |
| + add r6,r6,r0,ror#2 @ h+=Sigma0(a) | |
| + @ add r6,r6,r12 @ h+=Maj(a,b,c) | |
| + @ ldr r2,[sp,#15*4] @ 30 | |
| + @ ldr r1,[sp,#12*4] | |
| + mov r0,r2,ror#7 | |
| + add r6,r6,r12 @ h+=Maj(a,b,c) from the past | |
| + mov r12,r1,ror#17 | |
| + eor r0,r0,r2,ror#18 | |
| + eor r12,r12,r1,ror#19 | |
| + eor r0,r0,r2,lsr#3 @ sigma0(X[i+1]) | |
| + ldr r2,[sp,#14*4] | |
| + eor r12,r12,r1,lsr#10 @ sigma1(X[i+14]) | |
| + ldr r1,[sp,#7*4] | |
| + | |
| + add r12,r12,r0 | |
| + eor r0,r10,r10,ror#5 @ from BODY_00_15 | |
| + add r2,r2,r12 | |
| + eor r0,r0,r10,ror#19 @ Sigma1(e) | |
| + add r2,r2,r1 @ X[i] | |
| + ldr r12,[r14],#4 @ *K256++ | |
| + add r5,r5,r2 @ h+=X[i] | |
| + str r2,[sp,#14*4] | |
| + eor r2,r11,r4 | |
| + add r5,r5,r0,ror#6 @ h+=Sigma1(e) | |
| + and r2,r2,r10 | |
| + add r5,r5,r12 @ h+=K256[i] | |
| + eor r2,r2,r4 @ Ch(e,f,g) | |
| + eor r0,r6,r6,ror#11 | |
| + add r5,r5,r2 @ h+=Ch(e,f,g) | |
| +#if 30==31 | |
| + and r12,r12,#0xff | |
| + cmp r12,#0xf2 @ done? | |
| +#endif | |
| +#if 30<15 | |
| +# if __ARM_ARCH__>=7 | |
| + ldr r2,[r1],#4 @ prefetch | |
| +# else | |
| + ldrb r2,[r1,#3] | |
| +# endif | |
| + eor r12,r6,r7 @ a^b, b^c in next round | |
| +#else | |
| + ldr r2,[sp,#0*4] @ from future BODY_16_xx | |
| + eor r12,r6,r7 @ a^b, b^c in next round | |
| + ldr r1,[sp,#13*4] @ from future BODY_16_xx | |
| +#endif | |
| + eor r0,r0,r6,ror#20 @ Sigma0(a) | |
| + and r3,r3,r12 @ (b^c)&=(a^b) | |
| + add r9,r9,r5 @ d+=h | |
| + eor r3,r3,r7 @ Maj(a,b,c) | |
| + add r5,r5,r0,ror#2 @ h+=Sigma0(a) | |
| + @ add r5,r5,r3 @ h+=Maj(a,b,c) | |
| + @ ldr r2,[sp,#0*4] @ 31 | |
| + @ ldr r1,[sp,#13*4] | |
| + mov r0,r2,ror#7 | |
| + add r5,r5,r3 @ h+=Maj(a,b,c) from the past | |
| + mov r3,r1,ror#17 | |
| + eor r0,r0,r2,ror#18 | |
| + eor r3,r3,r1,ror#19 | |
| + eor r0,r0,r2,lsr#3 @ sigma0(X[i+1]) | |
| + ldr r2,[sp,#15*4] | |
| + eor r3,r3,r1,lsr#10 @ sigma1(X[i+14]) | |
| + ldr r1,[sp,#8*4] | |
| + | |
| + add r3,r3,r0 | |
| + eor r0,r9,r9,ror#5 @ from BODY_00_15 | |
| + add r2,r2,r3 | |
| + eor r0,r0,r9,ror#19 @ Sigma1(e) | |
| + add r2,r2,r1 @ X[i] | |
| + ldr r3,[r14],#4 @ *K256++ | |
| + add r4,r4,r2 @ h+=X[i] | |
| + str r2,[sp,#15*4] | |
| + eor r2,r10,r11 | |
| + add r4,r4,r0,ror#6 @ h+=Sigma1(e) | |
| + and r2,r2,r9 | |
| + add r4,r4,r3 @ h+=K256[i] | |
| + eor r2,r2,r11 @ Ch(e,f,g) | |
| + eor r0,r5,r5,ror#11 | |
| + add r4,r4,r2 @ h+=Ch(e,f,g) | |
| +#if 31==31 | |
| + and r3,r3,#0xff | |
| + cmp r3,#0xf2 @ done? | |
| +#endif | |
| +#if 31<15 | |
| +# if __ARM_ARCH__>=7 | |
| + ldr r2,[r1],#4 @ prefetch | |
| +# else | |
| + ldrb r2,[r1,#3] | |
| +# endif | |
| + eor r3,r5,r6 @ a^b, b^c in next round | |
| +#else | |
| + ldr r2,[sp,#1*4] @ from future BODY_16_xx | |
| + eor r3,r5,r6 @ a^b, b^c in next round | |
| + ldr r1,[sp,#14*4] @ from future BODY_16_xx | |
| +#endif | |
| + eor r0,r0,r5,ror#20 @ Sigma0(a) | |
| + and r12,r12,r3 @ (b^c)&=(a^b) | |
| + add r8,r8,r4 @ d+=h | |
| + eor r12,r12,r6 @ Maj(a,b,c) | |
| + add r4,r4,r0,ror#2 @ h+=Sigma0(a) | |
| + @ add r4,r4,r12 @ h+=Maj(a,b,c) | |
| +#if __ARM_ARCH__>=7 | |
| + ite eq @ Thumb2 thing, sanity check in ARM | |
| +#endif | |
| + ldreq r3,[sp,#16*4] @ pull ctx | |
| + bne .Lrounds_16_xx | |
| + | |
| + add r4,r4,r12 @ h+=Maj(a,b,c) from the past | |
| + ldr r0,[r3,#0] | |
| + ldr r2,[r3,#4] | |
| + ldr r12,[r3,#8] | |
| + add r4,r4,r0 | |
| + ldr r0,[r3,#12] | |
| + add r5,r5,r2 | |
| + ldr r2,[r3,#16] | |
| + add r6,r6,r12 | |
| + ldr r12,[r3,#20] | |
| + add r7,r7,r0 | |
| + ldr r0,[r3,#24] | |
| + add r8,r8,r2 | |
| + ldr r2,[r3,#28] | |
| + add r9,r9,r12 | |
| + ldr r1,[sp,#17*4] @ pull inp | |
| + ldr r12,[sp,#18*4] @ pull inp+len | |
| + add r10,r10,r0 | |
| + add r11,r11,r2 | |
| + stmia r3,{r4,r5,r6,r7,r8,r9,r10,r11} | |
| + cmp r1,r12 | |
| + sub r14,r14,#256 @ rewind Ktbl | |
| + bne .Loop | |
| + | |
| + add sp,sp,#19*4 @ destroy frame | |
| +#if __ARM_ARCH__>=5 | |
| + ldmia sp!,{r4-r11,pc} | |
| +#else | |
| + ldmia sp!,{r4-r11,lr} | |
| + tst lr,#1 | |
| + moveq pc,lr @ be binary compatible with V4, yet | |
| + .word 0xe12fff1e @ interoperable with Thumb ISA:-) | |
| +#endif | |
| +.size sha256_block_data_order,.-sha256_block_data_order | |
| +#if __ARM_MAX_ARCH__>=7 | |
| +.arch armv7-a | |
| +.fpu neon | |
| + | |
| +.global sha256_block_data_order_neon | |
| +.type sha256_block_data_order_neon,%function | |
| +.align 4 | |
| +sha256_block_data_order_neon: | |
| +.LNEON: | |
| + stmdb sp!,{r4-r12,lr} | |
| + | |
| + sub r11,sp,#16*4+16 | |
| + adrl r14,K256 | |
| + bic r11,r11,#15 @ align for 128-bit stores | |
| + mov r12,sp | |
| + mov sp,r11 @ alloca | |
| + add r2,r1,r2,lsl#6 @ len to point at the end of inp | |
| + | |
| + vld1.8 {q0},[r1]! | |
| + vld1.8 {q1},[r1]! | |
| + vld1.8 {q2},[r1]! | |
| + vld1.8 {q3},[r1]! | |
| + vld1.32 {q8},[r14,:128]! | |
| + vld1.32 {q9},[r14,:128]! | |
| + vld1.32 {q10},[r14,:128]! | |
| + vld1.32 {q11},[r14,:128]! | |
| + vrev32.8 q0,q0 @ yes, even on | |
| + str r0,[sp,#64] | |
| + vrev32.8 q1,q1 @ big-endian | |
| + str r1,[sp,#68] | |
| + mov r1,sp | |
| + vrev32.8 q2,q2 | |
| + str r2,[sp,#72] | |
| + vrev32.8 q3,q3 | |
| + str r12,[sp,#76] @ save original sp | |
| + vadd.i32 q8,q8,q0 | |
| + vadd.i32 q9,q9,q1 | |
| + vst1.32 {q8},[r1,:128]! | |
| + vadd.i32 q10,q10,q2 | |
| + vst1.32 {q9},[r1,:128]! | |
| + vadd.i32 q11,q11,q3 | |
| + vst1.32 {q10},[r1,:128]! | |
| + vst1.32 {q11},[r1,:128]! | |
| + | |
| + ldmia r0,{r4-r11} | |
| + sub r1,r1,#64 | |
| + ldr r2,[sp,#0] | |
| + eor r12,r12,r12 | |
| + eor r3,r5,r6 | |
| + b .L_00_48 | |
| + | |
| +.align 4 | |
| +.L_00_48: | |
| + vext.8 q8,q0,q1,#4 | |
| + add r11,r11,r2 | |
| + eor r2,r9,r10 | |
| + eor r0,r8,r8,ror#5 | |
| + vext.8 q9,q2,q3,#4 | |
| + add r4,r4,r12 | |
| + and r2,r2,r8 | |
| + eor r12,r0,r8,ror#19 | |
| + vshr.u32 q10,q8,#7 | |
| + eor r0,r4,r4,ror#11 | |
| + eor r2,r2,r10 | |
| + vadd.i32 q0,q0,q9 | |
| + add r11,r11,r12,ror#6 | |
| + eor r12,r4,r5 | |
| + vshr.u32 q9,q8,#3 | |
| + eor r0,r0,r4,ror#20 | |
| + add r11,r11,r2 | |
| + vsli.32 q10,q8,#25 | |
| + ldr r2,[sp,#4] | |
| + and r3,r3,r12 | |
| + vshr.u32 q11,q8,#18 | |
| + add r7,r7,r11 | |
| + add r11,r11,r0,ror#2 | |
| + eor r3,r3,r5 | |
| + veor q9,q9,q10 | |
| + add r10,r10,r2 | |
| + vsli.32 q11,q8,#14 | |
| + eor r2,r8,r9 | |
| + eor r0,r7,r7,ror#5 | |
| + vshr.u32 d24,d7,#17 | |
| + add r11,r11,r3 | |
| + and r2,r2,r7 | |
| + veor q9,q9,q11 | |
| + eor r3,r0,r7,ror#19 | |
| + eor r0,r11,r11,ror#11 | |
| + vsli.32 d24,d7,#15 | |
| + eor r2,r2,r9 | |
| + add r10,r10,r3,ror#6 | |
| + vshr.u32 d25,d7,#10 | |
| + eor r3,r11,r4 | |
| + eor r0,r0,r11,ror#20 | |
| + vadd.i32 q0,q0,q9 | |
| + add r10,r10,r2 | |
| + ldr r2,[sp,#8] | |
| + veor d25,d25,d24 | |
| + and r12,r12,r3 | |
| + add r6,r6,r10 | |
| + vshr.u32 d24,d7,#19 | |
| + add r10,r10,r0,ror#2 | |
| + eor r12,r12,r4 | |
| + vsli.32 d24,d7,#13 | |
| + add r9,r9,r2 | |
| + eor r2,r7,r8 | |
| + veor d25,d25,d24 | |
| + eor r0,r6,r6,ror#5 | |
| + add r10,r10,r12 | |
| + vadd.i32 d0,d0,d25 | |
| + and r2,r2,r6 | |
| + eor r12,r0,r6,ror#19 | |
| + vshr.u32 d24,d0,#17 | |
| + eor r0,r10,r10,ror#11 | |
| + eor r2,r2,r8 | |
| + vsli.32 d24,d0,#15 | |
| + add r9,r9,r12,ror#6 | |
| + eor r12,r10,r11 | |
| + vshr.u32 d25,d0,#10 | |
| + eor r0,r0,r10,ror#20 | |
| + add r9,r9,r2 | |
| + veor d25,d25,d24 | |
| + ldr r2,[sp,#12] | |
| + and r3,r3,r12 | |
| + vshr.u32 d24,d0,#19 | |
| + add r5,r5,r9 | |
| + add r9,r9,r0,ror#2 | |
| + eor r3,r3,r11 | |
| + vld1.32 {q8},[r14,:128]! | |
| + add r8,r8,r2 | |
| + vsli.32 d24,d0,#13 | |
| + eor r2,r6,r7 | |
| + eor r0,r5,r5,ror#5 | |
| + veor d25,d25,d24 | |
| + add r9,r9,r3 | |
| + and r2,r2,r5 | |
| + vadd.i32 d1,d1,d25 | |
| + eor r3,r0,r5,ror#19 | |
| + eor r0,r9,r9,ror#11 | |
| + vadd.i32 q8,q8,q0 | |
| + eor r2,r2,r7 | |
| + add r8,r8,r3,ror#6 | |
| + eor r3,r9,r10 | |
| + eor r0,r0,r9,ror#20 | |
| + add r8,r8,r2 | |
| + ldr r2,[sp,#16] | |
| + and r12,r12,r3 | |
| + add r4,r4,r8 | |
| + vst1.32 {q8},[r1,:128]! | |
| + add r8,r8,r0,ror#2 | |
| + eor r12,r12,r10 | |
| + vext.8 q8,q1,q2,#4 | |
| + add r7,r7,r2 | |
| + eor r2,r5,r6 | |
| + eor r0,r4,r4,ror#5 | |
| + vext.8 q9,q3,q0,#4 | |
| + add r8,r8,r12 | |
| + and r2,r2,r4 | |
| + eor r12,r0,r4,ror#19 | |
| + vshr.u32 q10,q8,#7 | |
| + eor r0,r8,r8,ror#11 | |
| + eor r2,r2,r6 | |
| + vadd.i32 q1,q1,q9 | |
| + add r7,r7,r12,ror#6 | |
| + eor r12,r8,r9 | |
| + vshr.u32 q9,q8,#3 | |
| + eor r0,r0,r8,ror#20 | |
| + add r7,r7,r2 | |
| + vsli.32 q10,q8,#25 | |
| + ldr r2,[sp,#20] | |
| + and r3,r3,r12 | |
| + vshr.u32 q11,q8,#18 | |
| + add r11,r11,r7 | |
| + add r7,r7,r0,ror#2 | |
| + eor r3,r3,r9 | |
| + veor q9,q9,q10 | |
| + add r6,r6,r2 | |
| + vsli.32 q11,q8,#14 | |
| + eor r2,r4,r5 | |
| + eor r0,r11,r11,ror#5 | |
| + vshr.u32 d24,d1,#17 | |
| + add r7,r7,r3 | |
| + and r2,r2,r11 | |
| + veor q9,q9,q11 | |
| + eor r3,r0,r11,ror#19 | |
| + eor r0,r7,r7,ror#11 | |
| + vsli.32 d24,d1,#15 | |
| + eor r2,r2,r5 | |
| + add r6,r6,r3,ror#6 | |
| + vshr.u32 d25,d1,#10 | |
| + eor r3,r7,r8 | |
| + eor r0,r0,r7,ror#20 | |
| + vadd.i32 q1,q1,q9 | |
| + add r6,r6,r2 | |
| + ldr r2,[sp,#24] | |
| + veor d25,d25,d24 | |
| + and r12,r12,r3 | |
| + add r10,r10,r6 | |
| + vshr.u32 d24,d1,#19 | |
| + add r6,r6,r0,ror#2 | |
| + eor r12,r12,r8 | |
| + vsli.32 d24,d1,#13 | |
| + add r5,r5,r2 | |
| + eor r2,r11,r4 | |
| + veor d25,d25,d24 | |
| + eor r0,r10,r10,ror#5 | |
| + add r6,r6,r12 | |
| + vadd.i32 d2,d2,d25 | |
| + and r2,r2,r10 | |
| + eor r12,r0,r10,ror#19 | |
| + vshr.u32 d24,d2,#17 | |
| + eor r0,r6,r6,ror#11 | |
| + eor r2,r2,r4 | |
| + vsli.32 d24,d2,#15 | |
| + add r5,r5,r12,ror#6 | |
| + eor r12,r6,r7 | |
| + vshr.u32 d25,d2,#10 | |
| + eor r0,r0,r6,ror#20 | |
| + add r5,r5,r2 | |
| + veor d25,d25,d24 | |
| + ldr r2,[sp,#28] | |
| + and r3,r3,r12 | |
| + vshr.u32 d24,d2,#19 | |
| + add r9,r9,r5 | |
| + add r5,r5,r0,ror#2 | |
| + eor r3,r3,r7 | |
| + vld1.32 {q8},[r14,:128]! | |
| + add r4,r4,r2 | |
| + vsli.32 d24,d2,#13 | |
| + eor r2,r10,r11 | |
| + eor r0,r9,r9,ror#5 | |
| + veor d25,d25,d24 | |
| + add r5,r5,r3 | |
| + and r2,r2,r9 | |
| + vadd.i32 d3,d3,d25 | |
| + eor r3,r0,r9,ror#19 | |
| + eor r0,r5,r5,ror#11 | |
| + vadd.i32 q8,q8,q1 | |
| + eor r2,r2,r11 | |
| + add r4,r4,r3,ror#6 | |
| + eor r3,r5,r6 | |
| + eor r0,r0,r5,ror#20 | |
| + add r4,r4,r2 | |
| + ldr r2,[sp,#32] | |
| + and r12,r12,r3 | |
| + add r8,r8,r4 | |
| + vst1.32 {q8},[r1,:128]! | |
| + add r4,r4,r0,ror#2 | |
| + eor r12,r12,r6 | |
| + vext.8 q8,q2,q3,#4 | |
| + add r11,r11,r2 | |
| + eor r2,r9,r10 | |
| + eor r0,r8,r8,ror#5 | |
| + vext.8 q9,q0,q1,#4 | |
| + add r4,r4,r12 | |
| + and r2,r2,r8 | |
| + eor r12,r0,r8,ror#19 | |
| + vshr.u32 q10,q8,#7 | |
| + eor r0,r4,r4,ror#11 | |
| + eor r2,r2,r10 | |
| + vadd.i32 q2,q2,q9 | |
| + add r11,r11,r12,ror#6 | |
| + eor r12,r4,r5 | |
| + vshr.u32 q9,q8,#3 | |
| + eor r0,r0,r4,ror#20 | |
| + add r11,r11,r2 | |
| + vsli.32 q10,q8,#25 | |
| + ldr r2,[sp,#36] | |
| + and r3,r3,r12 | |
| + vshr.u32 q11,q8,#18 | |
| + add r7,r7,r11 | |
| + add r11,r11,r0,ror#2 | |
| + eor r3,r3,r5 | |
| + veor q9,q9,q10 | |
| + add r10,r10,r2 | |
| + vsli.32 q11,q8,#14 | |
| + eor r2,r8,r9 | |
| + eor r0,r7,r7,ror#5 | |
| + vshr.u32 d24,d3,#17 | |
| + add r11,r11,r3 | |
| + and r2,r2,r7 | |
| + veor q9,q9,q11 | |
| + eor r3,r0,r7,ror#19 | |
| + eor r0,r11,r11,ror#11 | |
| + vsli.32 d24,d3,#15 | |
| + eor r2,r2,r9 | |
| + add r10,r10,r3,ror#6 | |
| + vshr.u32 d25,d3,#10 | |
| + eor r3,r11,r4 | |
| + eor r0,r0,r11,ror#20 | |
| + vadd.i32 q2,q2,q9 | |
| + add r10,r10,r2 | |
| + ldr r2,[sp,#40] | |
| + veor d25,d25,d24 | |
| + and r12,r12,r3 | |
| + add r6,r6,r10 | |
| + vshr.u32 d24,d3,#19 | |
| + add r10,r10,r0,ror#2 | |
| + eor r12,r12,r4 | |
| + vsli.32 d24,d3,#13 | |
| + add r9,r9,r2 | |
| + eor r2,r7,r8 | |
| + veor d25,d25,d24 | |
| + eor r0,r6,r6,ror#5 | |
| + add r10,r10,r12 | |
| + vadd.i32 d4,d4,d25 | |
| + and r2,r2,r6 | |
| + eor r12,r0,r6,ror#19 | |
| + vshr.u32 d24,d4,#17 | |
| + eor r0,r10,r10,ror#11 | |
| + eor r2,r2,r8 | |
| + vsli.32 d24,d4,#15 | |
| + add r9,r9,r12,ror#6 | |
| + eor r12,r10,r11 | |
| + vshr.u32 d25,d4,#10 | |
| + eor r0,r0,r10,ror#20 | |
| + add r9,r9,r2 | |
| + veor d25,d25,d24 | |
| + ldr r2,[sp,#44] | |
| + and r3,r3,r12 | |
| + vshr.u32 d24,d4,#19 | |
| + add r5,r5,r9 | |
| + add r9,r9,r0,ror#2 | |
| + eor r3,r3,r11 | |
| + vld1.32 {q8},[r14,:128]! | |
| + add r8,r8,r2 | |
| + vsli.32 d24,d4,#13 | |
| + eor r2,r6,r7 | |
| + eor r0,r5,r5,ror#5 | |
| + veor d25,d25,d24 | |
| + add r9,r9,r3 | |
| + and r2,r2,r5 | |
| + vadd.i32 d5,d5,d25 | |
| + eor r3,r0,r5,ror#19 | |
| + eor r0,r9,r9,ror#11 | |
| + vadd.i32 q8,q8,q2 | |
| + eor r2,r2,r7 | |
| + add r8,r8,r3,ror#6 | |
| + eor r3,r9,r10 | |
| + eor r0,r0,r9,ror#20 | |
| + add r8,r8,r2 | |
| + ldr r2,[sp,#48] | |
| + and r12,r12,r3 | |
| + add r4,r4,r8 | |
| + vst1.32 {q8},[r1,:128]! | |
| + add r8,r8,r0,ror#2 | |
| + eor r12,r12,r10 | |
| + vext.8 q8,q3,q0,#4 | |
| + add r7,r7,r2 | |
| + eor r2,r5,r6 | |
| + eor r0,r4,r4,ror#5 | |
| + vext.8 q9,q1,q2,#4 | |
| + add r8,r8,r12 | |
| + and r2,r2,r4 | |
| + eor r12,r0,r4,ror#19 | |
| + vshr.u32 q10,q8,#7 | |
| + eor r0,r8,r8,ror#11 | |
| + eor r2,r2,r6 | |
| + vadd.i32 q3,q3,q9 | |
| + add r7,r7,r12,ror#6 | |
| + eor r12,r8,r9 | |
| + vshr.u32 q9,q8,#3 | |
| + eor r0,r0,r8,ror#20 | |
| + add r7,r7,r2 | |
| + vsli.32 q10,q8,#25 | |
| + ldr r2,[sp,#52] | |
| + and r3,r3,r12 | |
| + vshr.u32 q11,q8,#18 | |
| + add r11,r11,r7 | |
| + add r7,r7,r0,ror#2 | |
| + eor r3,r3,r9 | |
| + veor q9,q9,q10 | |
| + add r6,r6,r2 | |
| + vsli.32 q11,q8,#14 | |
| + eor r2,r4,r5 | |
| + eor r0,r11,r11,ror#5 | |
| + vshr.u32 d24,d5,#17 | |
| + add r7,r7,r3 | |
| + and r2,r2,r11 | |
| + veor q9,q9,q11 | |
| + eor r3,r0,r11,ror#19 | |
| + eor r0,r7,r7,ror#11 | |
| + vsli.32 d24,d5,#15 | |
| + eor r2,r2,r5 | |
| + add r6,r6,r3,ror#6 | |
| + vshr.u32 d25,d5,#10 | |
| + eor r3,r7,r8 | |
| + eor r0,r0,r7,ror#20 | |
| + vadd.i32 q3,q3,q9 | |
| + add r6,r6,r2 | |
| + ldr r2,[sp,#56] | |
| + veor d25,d25,d24 | |
| + and r12,r12,r3 | |
| + add r10,r10,r6 | |
| + vshr.u32 d24,d5,#19 | |
| + add r6,r6,r0,ror#2 | |
| + eor r12,r12,r8 | |
| + vsli.32 d24,d5,#13 | |
| + add r5,r5,r2 | |
| + eor r2,r11,r4 | |
| + veor d25,d25,d24 | |
| + eor r0,r10,r10,ror#5 | |
| + add r6,r6,r12 | |
| + vadd.i32 d6,d6,d25 | |
| + and r2,r2,r10 | |
| + eor r12,r0,r10,ror#19 | |
| + vshr.u32 d24,d6,#17 | |
| + eor r0,r6,r6,ror#11 | |
| + eor r2,r2,r4 | |
| + vsli.32 d24,d6,#15 | |
| + add r5,r5,r12,ror#6 | |
| + eor r12,r6,r7 | |
| + vshr.u32 d25,d6,#10 | |
| + eor r0,r0,r6,ror#20 | |
| + add r5,r5,r2 | |
| + veor d25,d25,d24 | |
| + ldr r2,[sp,#60] | |
| + and r3,r3,r12 | |
| + vshr.u32 d24,d6,#19 | |
| + add r9,r9,r5 | |
| + add r5,r5,r0,ror#2 | |
| + eor r3,r3,r7 | |
| + vld1.32 {q8},[r14,:128]! | |
| + add r4,r4,r2 | |
| + vsli.32 d24,d6,#13 | |
| + eor r2,r10,r11 | |
| + eor r0,r9,r9,ror#5 | |
| + veor d25,d25,d24 | |
| + add r5,r5,r3 | |
| + and r2,r2,r9 | |
| + vadd.i32 d7,d7,d25 | |
| + eor r3,r0,r9,ror#19 | |
| + eor r0,r5,r5,ror#11 | |
| + vadd.i32 q8,q8,q3 | |
| + eor r2,r2,r11 | |
| + add r4,r4,r3,ror#6 | |
| + eor r3,r5,r6 | |
| + eor r0,r0,r5,ror#20 | |
| + add r4,r4,r2 | |
| + ldr r2,[r14] | |
| + and r12,r12,r3 | |
| + add r8,r8,r4 | |
| + vst1.32 {q8},[r1,:128]! | |
| + add r4,r4,r0,ror#2 | |
| + eor r12,r12,r6 | |
| + teq r2,#0 @ check for K256 terminator | |
| + ldr r2,[sp,#0] | |
| + sub r1,r1,#64 | |
| + bne .L_00_48 | |
| + | |
| + ldr r1,[sp,#68] | |
| + ldr r0,[sp,#72] | |
| + sub r14,r14,#256 @ rewind r14 | |
| + teq r1,r0 | |
| + it eq | |
| + subeq r1,r1,#64 @ avoid SEGV | |
| + vld1.8 {q0},[r1]! @ load next input block | |
| + vld1.8 {q1},[r1]! | |
| + vld1.8 {q2},[r1]! | |
| + vld1.8 {q3},[r1]! | |
| + it ne | |
| + strne r1,[sp,#68] | |
| + mov r1,sp | |
| + add r11,r11,r2 | |
| + eor r2,r9,r10 | |
| + eor r0,r8,r8,ror#5 | |
| + add r4,r4,r12 | |
| + vld1.32 {q8},[r14,:128]! | |
| + and r2,r2,r8 | |
| + eor r12,r0,r8,ror#19 | |
| + eor r0,r4,r4,ror#11 | |
| + eor r2,r2,r10 | |
| + vrev32.8 q0,q0 | |
| + add r11,r11,r12,ror#6 | |
| + eor r12,r4,r5 | |
| + eor r0,r0,r4,ror#20 | |
| + add r11,r11,r2 | |
| + vadd.i32 q8,q8,q0 | |
| + ldr r2,[sp,#4] | |
| + and r3,r3,r12 | |
| + add r7,r7,r11 | |
| + add r11,r11,r0,ror#2 | |
| + eor r3,r3,r5 | |
| + add r10,r10,r2 | |
| + eor r2,r8,r9 | |
| + eor r0,r7,r7,ror#5 | |
| + add r11,r11,r3 | |
| + and r2,r2,r7 | |
| + eor r3,r0,r7,ror#19 | |
| + eor r0,r11,r11,ror#11 | |
| + eor r2,r2,r9 | |
| + add r10,r10,r3,ror#6 | |
| + eor r3,r11,r4 | |
| + eor r0,r0,r11,ror#20 | |
| + add r10,r10,r2 | |
| + ldr r2,[sp,#8] | |
| + and r12,r12,r3 | |
| + add r6,r6,r10 | |
| + add r10,r10,r0,ror#2 | |
| + eor r12,r12,r4 | |
| + add r9,r9,r2 | |
| + eor r2,r7,r8 | |
| + eor r0,r6,r6,ror#5 | |
| + add r10,r10,r12 | |
| + and r2,r2,r6 | |
| + eor r12,r0,r6,ror#19 | |
| + eor r0,r10,r10,ror#11 | |
| + eor r2,r2,r8 | |
| + add r9,r9,r12,ror#6 | |
| + eor r12,r10,r11 | |
| + eor r0,r0,r10,ror#20 | |
| + add r9,r9,r2 | |
| + ldr r2,[sp,#12] | |
| + and r3,r3,r12 | |
| + add r5,r5,r9 | |
| + add r9,r9,r0,ror#2 | |
| + eor r3,r3,r11 | |
| + add r8,r8,r2 | |
| + eor r2,r6,r7 | |
| + eor r0,r5,r5,ror#5 | |
| + add r9,r9,r3 | |
| + and r2,r2,r5 | |
| + eor r3,r0,r5,ror#19 | |
| + eor r0,r9,r9,ror#11 | |
| + eor r2,r2,r7 | |
| + add r8,r8,r3,ror#6 | |
| + eor r3,r9,r10 | |
| + eor r0,r0,r9,ror#20 | |
| + add r8,r8,r2 | |
| + ldr r2,[sp,#16] | |
| + and r12,r12,r3 | |
| + add r4,r4,r8 | |
| + add r8,r8,r0,ror#2 | |
| + eor r12,r12,r10 | |
| + vst1.32 {q8},[r1,:128]! | |
| + add r7,r7,r2 | |
| + eor r2,r5,r6 | |
| + eor r0,r4,r4,ror#5 | |
| + add r8,r8,r12 | |
| + vld1.32 {q8},[r14,:128]! | |
| + and r2,r2,r4 | |
| + eor r12,r0,r4,ror#19 | |
| + eor r0,r8,r8,ror#11 | |
| + eor r2,r2,r6 | |
| + vrev32.8 q1,q1 | |
| + add r7,r7,r12,ror#6 | |
| + eor r12,r8,r9 | |
| + eor r0,r0,r8,ror#20 | |
| + add r7,r7,r2 | |
| + vadd.i32 q8,q8,q1 | |
| + ldr r2,[sp,#20] | |
| + and r3,r3,r12 | |
| + add r11,r11,r7 | |
| + add r7,r7,r0,ror#2 | |
| + eor r3,r3,r9 | |
| + add r6,r6,r2 | |
| + eor r2,r4,r5 | |
| + eor r0,r11,r11,ror#5 | |
| + add r7,r7,r3 | |
| + and r2,r2,r11 | |
| + eor r3,r0,r11,ror#19 | |
| + eor r0,r7,r7,ror#11 | |
| + eor r2,r2,r5 | |
| + add r6,r6,r3,ror#6 | |
| + eor r3,r7,r8 | |
| + eor r0,r0,r7,ror#20 | |
| + add r6,r6,r2 | |
| + ldr r2,[sp,#24] | |
| + and r12,r12,r3 | |
| + add r10,r10,r6 | |
| + add r6,r6,r0,ror#2 | |
| + eor r12,r12,r8 | |
| + add r5,r5,r2 | |
| + eor r2,r11,r4 | |
| + eor r0,r10,r10,ror#5 | |
| + add r6,r6,r12 | |
| + and r2,r2,r10 | |
| + eor r12,r0,r10,ror#19 | |
| + eor r0,r6,r6,ror#11 | |
| + eor r2,r2,r4 | |
| + add r5,r5,r12,ror#6 | |
| + eor r12,r6,r7 | |
| + eor r0,r0,r6,ror#20 | |
| + add r5,r5,r2 | |
| + ldr r2,[sp,#28] | |
| + and r3,r3,r12 | |
| + add r9,r9,r5 | |
| + add r5,r5,r0,ror#2 | |
| + eor r3,r3,r7 | |
| + add r4,r4,r2 | |
| + eor r2,r10,r11 | |
| + eor r0,r9,r9,ror#5 | |
| + add r5,r5,r3 | |
| + and r2,r2,r9 | |
| + eor r3,r0,r9,ror#19 | |
| + eor r0,r5,r5,ror#11 | |
| + eor r2,r2,r11 | |
| + add r4,r4,r3,ror#6 | |
| + eor r3,r5,r6 | |
| + eor r0,r0,r5,ror#20 | |
| + add r4,r4,r2 | |
| + ldr r2,[sp,#32] | |
| + and r12,r12,r3 | |
| + add r8,r8,r4 | |
| + add r4,r4,r0,ror#2 | |
| + eor r12,r12,r6 | |
| + vst1.32 {q8},[r1,:128]! | |
| + add r11,r11,r2 | |
| + eor r2,r9,r10 | |
| + eor r0,r8,r8,ror#5 | |
| + add r4,r4,r12 | |
| + vld1.32 {q8},[r14,:128]! | |
| + and r2,r2,r8 | |
| + eor r12,r0,r8,ror#19 | |
| + eor r0,r4,r4,ror#11 | |
| + eor r2,r2,r10 | |
| + vrev32.8 q2,q2 | |
| + add r11,r11,r12,ror#6 | |
| + eor r12,r4,r5 | |
| + eor r0,r0,r4,ror#20 | |
| + add r11,r11,r2 | |
| + vadd.i32 q8,q8,q2 | |
| + ldr r2,[sp,#36] | |
| + and r3,r3,r12 | |
| + add r7,r7,r11 | |
| + add r11,r11,r0,ror#2 | |
| + eor r3,r3,r5 | |
| + add r10,r10,r2 | |
| + eor r2,r8,r9 | |
| + eor r0,r7,r7,ror#5 | |
| + add r11,r11,r3 | |
| + and r2,r2,r7 | |
| + eor r3,r0,r7,ror#19 | |
| + eor r0,r11,r11,ror#11 | |
| + eor r2,r2,r9 | |
| + add r10,r10,r3,ror#6 | |
| + eor r3,r11,r4 | |
| + eor r0,r0,r11,ror#20 | |
| + add r10,r10,r2 | |
| + ldr r2,[sp,#40] | |
| + and r12,r12,r3 | |
| + add r6,r6,r10 | |
| + add r10,r10,r0,ror#2 | |
| + eor r12,r12,r4 | |
| + add r9,r9,r2 | |
| + eor r2,r7,r8 | |
| + eor r0,r6,r6,ror#5 | |
| + add r10,r10,r12 | |
| + and r2,r2,r6 | |
| + eor r12,r0,r6,ror#19 | |
| + eor r0,r10,r10,ror#11 | |
| + eor r2,r2,r8 | |
| + add r9,r9,r12,ror#6 | |
| + eor r12,r10,r11 | |
| + eor r0,r0,r10,ror#20 | |
| + add r9,r9,r2 | |
| + ldr r2,[sp,#44] | |
| + and r3,r3,r12 | |
| + add r5,r5,r9 | |
| + add r9,r9,r0,ror#2 | |
| + eor r3,r3,r11 | |
| + add r8,r8,r2 | |
| + eor r2,r6,r7 | |
| + eor r0,r5,r5,ror#5 | |
| + add r9,r9,r3 | |
| + and r2,r2,r5 | |
| + eor r3,r0,r5,ror#19 | |
| + eor r0,r9,r9,ror#11 | |
| + eor r2,r2,r7 | |
| + add r8,r8,r3,ror#6 | |
| + eor r3,r9,r10 | |
| + eor r0,r0,r9,ror#20 | |
| + add r8,r8,r2 | |
| + ldr r2,[sp,#48] | |
| + and r12,r12,r3 | |
| + add r4,r4,r8 | |
| + add r8,r8,r0,ror#2 | |
| + eor r12,r12,r10 | |
| + vst1.32 {q8},[r1,:128]! | |
| + add r7,r7,r2 | |
| + eor r2,r5,r6 | |
| + eor r0,r4,r4,ror#5 | |
| + add r8,r8,r12 | |
| + vld1.32 {q8},[r14,:128]! | |
| + and r2,r2,r4 | |
| + eor r12,r0,r4,ror#19 | |
| + eor r0,r8,r8,ror#11 | |
| + eor r2,r2,r6 | |
| + vrev32.8 q3,q3 | |
| + add r7,r7,r12,ror#6 | |
| + eor r12,r8,r9 | |
| + eor r0,r0,r8,ror#20 | |
| + add r7,r7,r2 | |
| + vadd.i32 q8,q8,q3 | |
| + ldr r2,[sp,#52] | |
| + and r3,r3,r12 | |
| + add r11,r11,r7 | |
| + add r7,r7,r0,ror#2 | |
| + eor r3,r3,r9 | |
| + add r6,r6,r2 | |
| + eor r2,r4,r5 | |
| + eor r0,r11,r11,ror#5 | |
| + add r7,r7,r3 | |
| + and r2,r2,r11 | |
| + eor r3,r0,r11,ror#19 | |
| + eor r0,r7,r7,ror#11 | |
| + eor r2,r2,r5 | |
| + add r6,r6,r3,ror#6 | |
| + eor r3,r7,r8 | |
| + eor r0,r0,r7,ror#20 | |
| + add r6,r6,r2 | |
| + ldr r2,[sp,#56] | |
| + and r12,r12,r3 | |
| + add r10,r10,r6 | |
| + add r6,r6,r0,ror#2 | |
| + eor r12,r12,r8 | |
| + add r5,r5,r2 | |
| + eor r2,r11,r4 | |
| + eor r0,r10,r10,ror#5 | |
| + add r6,r6,r12 | |
| + and r2,r2,r10 | |
| + eor r12,r0,r10,ror#19 | |
| + eor r0,r6,r6,ror#11 | |
| + eor r2,r2,r4 | |
| + add r5,r5,r12,ror#6 | |
| + eor r12,r6,r7 | |
| + eor r0,r0,r6,ror#20 | |
| + add r5,r5,r2 | |
| + ldr r2,[sp,#60] | |
| + and r3,r3,r12 | |
| + add r9,r9,r5 | |
| + add r5,r5,r0,ror#2 | |
| + eor r3,r3,r7 | |
| + add r4,r4,r2 | |
| + eor r2,r10,r11 | |
| + eor r0,r9,r9,ror#5 | |
| + add r5,r5,r3 | |
| + and r2,r2,r9 | |
| + eor r3,r0,r9,ror#19 | |
| + eor r0,r5,r5,ror#11 | |
| + eor r2,r2,r11 | |
| + add r4,r4,r3,ror#6 | |
| + eor r3,r5,r6 | |
| + eor r0,r0,r5,ror#20 | |
| + add r4,r4,r2 | |
| + ldr r2,[sp,#64] | |
| + and r12,r12,r3 | |
| + add r8,r8,r4 | |
| + add r4,r4,r0,ror#2 | |
| + eor r12,r12,r6 | |
| + vst1.32 {q8},[r1,:128]! | |
| + ldr r0,[r2,#0] | |
| + add r4,r4,r12 @ h+=Maj(a,b,c) from the past | |
| + ldr r12,[r2,#4] | |
| + ldr r3,[r2,#8] | |
| + ldr r1,[r2,#12] | |
| + add r4,r4,r0 @ accumulate | |
| + ldr r0,[r2,#16] | |
| + add r5,r5,r12 | |
| + ldr r12,[r2,#20] | |
| + add r6,r6,r3 | |
| + ldr r3,[r2,#24] | |
| + add r7,r7,r1 | |
| + ldr r1,[r2,#28] | |
| + add r8,r8,r0 | |
| + str r4,[r2],#4 | |
| + add r9,r9,r12 | |
| + str r5,[r2],#4 | |
| + add r10,r10,r3 | |
| + str r6,[r2],#4 | |
| + add r11,r11,r1 | |
| + str r7,[r2],#4 | |
| + stmia r2,{r8-r11} | |
| + | |
| + ittte ne | |
| + movne r1,sp | |
| + ldrne r2,[sp,#0] | |
| + eorne r12,r12,r12 | |
| + ldreq sp,[sp,#76] @ restore original sp | |
| + itt ne | |
| + eorne r3,r5,r6 | |
| + bne .L_00_48 | |
| + | |
| + ldmia sp!,{r4-r12,pc} | |
| +.size sha256_block_data_order_neon,.-sha256_block_data_order_neon | |
| +#endif | |
| +#if __ARM_MAX_ARCH__>=7 && !defined(__KERNEL__) | |
| + | |
| +# ifdef __thumb2__ | |
| +# define INST(a,b,c,d) .byte c,d|0xc,a,b | |
| +# else | |
| +# define INST(a,b,c,d) .byte a,b,c,d | |
| +# endif | |
| + | |
| +.type sha256_block_data_order_armv8,%function | |
| +.align 5 | |
| +sha256_block_data_order_armv8: | |
| +.LARMv8: | |
| + vld1.32 {q0,q1},[r0] | |
| +# ifdef __thumb2__ | |
| + adr r3,.LARMv8 | |
| + sub r3,r3,#.LARMv8-K256 | |
| +# else | |
| + adrl r3,K256 | |
| +# endif | |
| + add r2,r1,r2,lsl#6 @ len to point at the end of inp | |
| + | |
| +.Loop_v8: | |
| + vld1.8 {q8-q9},[r1]! | |
| + vld1.8 {q10-q11},[r1]! | |
| + vld1.32 {q12},[r3]! | |
| + vrev32.8 q8,q8 | |
| + vrev32.8 q9,q9 | |
| + vrev32.8 q10,q10 | |
| + vrev32.8 q11,q11 | |
| + vmov q14,q0 @ offload | |
| + vmov q15,q1 | |
| + teq r1,r2 | |
| + vld1.32 {q13},[r3]! | |
| + vadd.i32 q12,q12,q8 | |
| + INST(0xe2,0x03,0xfa,0xf3) @ sha256su0 q8,q9 | |
| + vmov q2,q0 | |
| + INST(0x68,0x0c,0x02,0xf3) @ sha256h q0,q1,q12 | |
| + INST(0x68,0x2c,0x14,0xf3) @ sha256h2 q1,q2,q12 | |
| + INST(0xe6,0x0c,0x64,0xf3) @ sha256su1 q8,q10,q11 | |
| + vld1.32 {q12},[r3]! | |
| + vadd.i32 q13,q13,q9 | |
| + INST(0xe4,0x23,0xfa,0xf3) @ sha256su0 q9,q10 | |
| + vmov q2,q0 | |
| + INST(0x6a,0x0c,0x02,0xf3) @ sha256h q0,q1,q13 | |
| + INST(0x6a,0x2c,0x14,0xf3) @ sha256h2 q1,q2,q13 | |
| + INST(0xe0,0x2c,0x66,0xf3) @ sha256su1 q9,q11,q8 | |
| + vld1.32 {q13},[r3]! | |
| + vadd.i32 q12,q12,q10 | |
| + INST(0xe6,0x43,0xfa,0xf3) @ sha256su0 q10,q11 | |
| + vmov q2,q0 | |
| + INST(0x68,0x0c,0x02,0xf3) @ sha256h q0,q1,q12 | |
| + INST(0x68,0x2c,0x14,0xf3) @ sha256h2 q1,q2,q12 | |
| + INST(0xe2,0x4c,0x60,0xf3) @ sha256su1 q10,q8,q9 | |
| + vld1.32 {q12},[r3]! | |
| + vadd.i32 q13,q13,q11 | |
| + INST(0xe0,0x63,0xfa,0xf3) @ sha256su0 q11,q8 | |
| + vmov q2,q0 | |
| + INST(0x6a,0x0c,0x02,0xf3) @ sha256h q0,q1,q13 | |
| + INST(0x6a,0x2c,0x14,0xf3) @ sha256h2 q1,q2,q13 | |
| + INST(0xe4,0x6c,0x62,0xf3) @ sha256su1 q11,q9,q10 | |
| + vld1.32 {q13},[r3]! | |
| + vadd.i32 q12,q12,q8 | |
| + INST(0xe2,0x03,0xfa,0xf3) @ sha256su0 q8,q9 | |
| + vmov q2,q0 | |
| + INST(0x68,0x0c,0x02,0xf3) @ sha256h q0,q1,q12 | |
| + INST(0x68,0x2c,0x14,0xf3) @ sha256h2 q1,q2,q12 | |
| + INST(0xe6,0x0c,0x64,0xf3) @ sha256su1 q8,q10,q11 | |
| + vld1.32 {q12},[r3]! | |
| + vadd.i32 q13,q13,q9 | |
| + INST(0xe4,0x23,0xfa,0xf3) @ sha256su0 q9,q10 | |
| + vmov q2,q0 | |
| + INST(0x6a,0x0c,0x02,0xf3) @ sha256h q0,q1,q13 | |
| + INST(0x6a,0x2c,0x14,0xf3) @ sha256h2 q1,q2,q13 | |
| + INST(0xe0,0x2c,0x66,0xf3) @ sha256su1 q9,q11,q8 | |
| + vld1.32 {q13},[r3]! | |
| + vadd.i32 q12,q12,q10 | |
| + INST(0xe6,0x43,0xfa,0xf3) @ sha256su0 q10,q11 | |
| + vmov q2,q0 | |
| + INST(0x68,0x0c,0x02,0xf3) @ sha256h q0,q1,q12 | |
| + INST(0x68,0x2c,0x14,0xf3) @ sha256h2 q1,q2,q12 | |
| + INST(0xe2,0x4c,0x60,0xf3) @ sha256su1 q10,q8,q9 | |
| + vld1.32 {q12},[r3]! | |
| + vadd.i32 q13,q13,q11 | |
| + INST(0xe0,0x63,0xfa,0xf3) @ sha256su0 q11,q8 | |
| + vmov q2,q0 | |
| + INST(0x6a,0x0c,0x02,0xf3) @ sha256h q0,q1,q13 | |
| + INST(0x6a,0x2c,0x14,0xf3) @ sha256h2 q1,q2,q13 | |
| + INST(0xe4,0x6c,0x62,0xf3) @ sha256su1 q11,q9,q10 | |
| + vld1.32 {q13},[r3]! | |
| + vadd.i32 q12,q12,q8 | |
| + INST(0xe2,0x03,0xfa,0xf3) @ sha256su0 q8,q9 | |
| + vmov q2,q0 | |
| + INST(0x68,0x0c,0x02,0xf3) @ sha256h q0,q1,q12 | |
| + INST(0x68,0x2c,0x14,0xf3) @ sha256h2 q1,q2,q12 | |
| + INST(0xe6,0x0c,0x64,0xf3) @ sha256su1 q8,q10,q11 | |
| + vld1.32 {q12},[r3]! | |
| + vadd.i32 q13,q13,q9 | |
| + INST(0xe4,0x23,0xfa,0xf3) @ sha256su0 q9,q10 | |
| + vmov q2,q0 | |
| + INST(0x6a,0x0c,0x02,0xf3) @ sha256h q0,q1,q13 | |
| + INST(0x6a,0x2c,0x14,0xf3) @ sha256h2 q1,q2,q13 | |
| + INST(0xe0,0x2c,0x66,0xf3) @ sha256su1 q9,q11,q8 | |
| + vld1.32 {q13},[r3]! | |
| + vadd.i32 q12,q12,q10 | |
| + INST(0xe6,0x43,0xfa,0xf3) @ sha256su0 q10,q11 | |
| + vmov q2,q0 | |
| + INST(0x68,0x0c,0x02,0xf3) @ sha256h q0,q1,q12 | |
| + INST(0x68,0x2c,0x14,0xf3) @ sha256h2 q1,q2,q12 | |
| + INST(0xe2,0x4c,0x60,0xf3) @ sha256su1 q10,q8,q9 | |
| + vld1.32 {q12},[r3]! | |
| + vadd.i32 q13,q13,q11 | |
| + INST(0xe0,0x63,0xfa,0xf3) @ sha256su0 q11,q8 | |
| + vmov q2,q0 | |
| + INST(0x6a,0x0c,0x02,0xf3) @ sha256h q0,q1,q13 | |
| + INST(0x6a,0x2c,0x14,0xf3) @ sha256h2 q1,q2,q13 | |
| + INST(0xe4,0x6c,0x62,0xf3) @ sha256su1 q11,q9,q10 | |
| + vld1.32 {q13},[r3]! | |
| + vadd.i32 q12,q12,q8 | |
| + vmov q2,q0 | |
| + INST(0x68,0x0c,0x02,0xf3) @ sha256h q0,q1,q12 | |
| + INST(0x68,0x2c,0x14,0xf3) @ sha256h2 q1,q2,q12 | |
| + | |
| + vld1.32 {q12},[r3]! | |
| + vadd.i32 q13,q13,q9 | |
| + vmov q2,q0 | |
| + INST(0x6a,0x0c,0x02,0xf3) @ sha256h q0,q1,q13 | |
| + INST(0x6a,0x2c,0x14,0xf3) @ sha256h2 q1,q2,q13 | |
| + | |
| + vld1.32 {q13},[r3] | |
| + vadd.i32 q12,q12,q10 | |
| + sub r3,r3,#256-16 @ rewind | |
| + vmov q2,q0 | |
| + INST(0x68,0x0c,0x02,0xf3) @ sha256h q0,q1,q12 | |
| + INST(0x68,0x2c,0x14,0xf3) @ sha256h2 q1,q2,q12 | |
| + | |
| + vadd.i32 q13,q13,q11 | |
| + vmov q2,q0 | |
| + INST(0x6a,0x0c,0x02,0xf3) @ sha256h q0,q1,q13 | |
| + INST(0x6a,0x2c,0x14,0xf3) @ sha256h2 q1,q2,q13 | |
| + | |
| + vadd.i32 q0,q0,q14 | |
| + vadd.i32 q1,q1,q15 | |
| + it ne | |
| + bne .Loop_v8 | |
| + | |
| + vst1.32 {q0,q1},[r0] | |
| + | |
| + bx lr @ bx lr | |
| +.size sha256_block_data_order_armv8,.-sha256_block_data_order_armv8 | |
| +#endif | |
| +.asciz "SHA256 block transform for ARMv4/NEON/ARMv8, CRYPTOGAMS by <appro@openssl.org>" | |
| +.align 2 | |
| +#if __ARM_MAX_ARCH__>=7 && !defined(__KERNEL__) | |
| +.comm OPENSSL_armcap_P,4,4 | |
| +#endif | |
| diff -x .git -Naur linux-4.4.111/arch/arm/crypto/sha512-core.S linux-4.4.111-alpine/arch/arm/crypto/sha512-core.S | |
| --- linux-4.4.111/arch/arm/crypto/sha512-core.S 1969-12-31 19:00:00.000000000 -0500 | |
| +++ linux-4.4.111-alpine/arch/arm/crypto/sha512-core.S 2018-02-17 11:19:04.000000000 -0500 | |
| @@ -0,0 +1,1861 @@ | |
| + | |
| +@ ==================================================================== | |
| +@ Written by Andy Polyakov <appro@openssl.org> for the OpenSSL | |
| +@ project. The module is, however, dual licensed under OpenSSL and | |
| +@ CRYPTOGAMS licenses depending on where you obtain it. For further | |
| +@ details see http://www.openssl.org/~appro/cryptogams/. | |
| +@ | |
| +@ Permission to use under GPL terms is granted. | |
| +@ ==================================================================== | |
| + | |
| +@ SHA512 block procedure for ARMv4. September 2007. | |
| + | |
| +@ This code is ~4.5 (four and a half) times faster than code generated | |
| +@ by gcc 3.4 and it spends ~72 clock cycles per byte [on single-issue | |
| +@ Xscale PXA250 core]. | |
| +@ | |
| +@ July 2010. | |
| +@ | |
| +@ Rescheduling for dual-issue pipeline resulted in 6% improvement on | |
| +@ Cortex A8 core and ~40 cycles per processed byte. | |
| + | |
| +@ February 2011. | |
| +@ | |
| +@ Profiler-assisted and platform-specific optimization resulted in 7% | |
| +@ improvement on Coxtex A8 core and ~38 cycles per byte. | |
| + | |
| +@ March 2011. | |
| +@ | |
| +@ Add NEON implementation. On Cortex A8 it was measured to process | |
| +@ one byte in 23.3 cycles or ~60% faster than integer-only code. | |
| + | |
| +@ August 2012. | |
| +@ | |
| +@ Improve NEON performance by 12% on Snapdragon S4. In absolute | |
| +@ terms it's 22.6 cycles per byte, which is disappointing result. | |
| +@ Technical writers asserted that 3-way S4 pipeline can sustain | |
| +@ multiple NEON instructions per cycle, but dual NEON issue could | |
| +@ not be observed, see http://www.openssl.org/~appro/Snapdragon-S4.html | |
| +@ for further details. On side note Cortex-A15 processes one byte in | |
| +@ 16 cycles. | |
| + | |
| +@ Byte order [in]dependence. ========================================= | |
| +@ | |
| +@ Originally caller was expected to maintain specific *dword* order in | |
| +@ h[0-7], namely with most significant dword at *lower* address, which | |
| +@ was reflected in below two parameters as 0 and 4. Now caller is | |
| +@ expected to maintain native byte order for whole 64-bit values. | |
| +#ifndef __KERNEL__ | |
| +# include "arm_arch.h" | |
| +# define VFP_ABI_PUSH vstmdb sp!,{d8-d15} | |
| +# define VFP_ABI_POP vldmia sp!,{d8-d15} | |
| +#else | |
| +# define __ARM_ARCH__ __LINUX_ARM_ARCH__ | |
| +# define __ARM_MAX_ARCH__ 7 | |
| +# define VFP_ABI_PUSH | |
| +# define VFP_ABI_POP | |
| +#endif | |
| + | |
| +#ifdef __ARMEL__ | |
| +# define LO 0 | |
| +# define HI 4 | |
| +# define WORD64(hi0,lo0,hi1,lo1) .word lo0,hi0, lo1,hi1 | |
| +#else | |
| +# define HI 0 | |
| +# define LO 4 | |
| +# define WORD64(hi0,lo0,hi1,lo1) .word hi0,lo0, hi1,lo1 | |
| +#endif | |
| + | |
| +.text | |
| +#if __ARM_ARCH__<7 | |
| +.code 32 | |
| +#else | |
| +.syntax unified | |
| +# ifdef __thumb2__ | |
| +# define adrl adr | |
| +.thumb | |
| +# else | |
| +.code 32 | |
| +# endif | |
| +#endif | |
| + | |
| +.type K512,%object | |
| +.align 5 | |
| +K512: | |
| +WORD64(0x428a2f98,0xd728ae22, 0x71374491,0x23ef65cd) | |
| +WORD64(0xb5c0fbcf,0xec4d3b2f, 0xe9b5dba5,0x8189dbbc) | |
| +WORD64(0x3956c25b,0xf348b538, 0x59f111f1,0xb605d019) | |
| +WORD64(0x923f82a4,0xaf194f9b, 0xab1c5ed5,0xda6d8118) | |
| +WORD64(0xd807aa98,0xa3030242, 0x12835b01,0x45706fbe) | |
| +WORD64(0x243185be,0x4ee4b28c, 0x550c7dc3,0xd5ffb4e2) | |
| +WORD64(0x72be5d74,0xf27b896f, 0x80deb1fe,0x3b1696b1) | |
| +WORD64(0x9bdc06a7,0x25c71235, 0xc19bf174,0xcf692694) | |
| +WORD64(0xe49b69c1,0x9ef14ad2, 0xefbe4786,0x384f25e3) | |
| +WORD64(0x0fc19dc6,0x8b8cd5b5, 0x240ca1cc,0x77ac9c65) | |
| +WORD64(0x2de92c6f,0x592b0275, 0x4a7484aa,0x6ea6e483) | |
| +WORD64(0x5cb0a9dc,0xbd41fbd4, 0x76f988da,0x831153b5) | |
| +WORD64(0x983e5152,0xee66dfab, 0xa831c66d,0x2db43210) | |
| +WORD64(0xb00327c8,0x98fb213f, 0xbf597fc7,0xbeef0ee4) | |
| +WORD64(0xc6e00bf3,0x3da88fc2, 0xd5a79147,0x930aa725) | |
| +WORD64(0x06ca6351,0xe003826f, 0x14292967,0x0a0e6e70) | |
| +WORD64(0x27b70a85,0x46d22ffc, 0x2e1b2138,0x5c26c926) | |
| +WORD64(0x4d2c6dfc,0x5ac42aed, 0x53380d13,0x9d95b3df) | |
| +WORD64(0x650a7354,0x8baf63de, 0x766a0abb,0x3c77b2a8) | |
| +WORD64(0x81c2c92e,0x47edaee6, 0x92722c85,0x1482353b) | |
| +WORD64(0xa2bfe8a1,0x4cf10364, 0xa81a664b,0xbc423001) | |
| +WORD64(0xc24b8b70,0xd0f89791, 0xc76c51a3,0x0654be30) | |
| +WORD64(0xd192e819,0xd6ef5218, 0xd6990624,0x5565a910) | |
| +WORD64(0xf40e3585,0x5771202a, 0x106aa070,0x32bbd1b8) | |
| +WORD64(0x19a4c116,0xb8d2d0c8, 0x1e376c08,0x5141ab53) | |
| +WORD64(0x2748774c,0xdf8eeb99, 0x34b0bcb5,0xe19b48a8) | |
| +WORD64(0x391c0cb3,0xc5c95a63, 0x4ed8aa4a,0xe3418acb) | |
| +WORD64(0x5b9cca4f,0x7763e373, 0x682e6ff3,0xd6b2b8a3) | |
| +WORD64(0x748f82ee,0x5defb2fc, 0x78a5636f,0x43172f60) | |
| +WORD64(0x84c87814,0xa1f0ab72, 0x8cc70208,0x1a6439ec) | |
| +WORD64(0x90befffa,0x23631e28, 0xa4506ceb,0xde82bde9) | |
| +WORD64(0xbef9a3f7,0xb2c67915, 0xc67178f2,0xe372532b) | |
| +WORD64(0xca273ece,0xea26619c, 0xd186b8c7,0x21c0c207) | |
| +WORD64(0xeada7dd6,0xcde0eb1e, 0xf57d4f7f,0xee6ed178) | |
| +WORD64(0x06f067aa,0x72176fba, 0x0a637dc5,0xa2c898a6) | |
| +WORD64(0x113f9804,0xbef90dae, 0x1b710b35,0x131c471b) | |
| +WORD64(0x28db77f5,0x23047d84, 0x32caab7b,0x40c72493) | |
| +WORD64(0x3c9ebe0a,0x15c9bebc, 0x431d67c4,0x9c100d4c) | |
| +WORD64(0x4cc5d4be,0xcb3e42b6, 0x597f299c,0xfc657e2a) | |
| +WORD64(0x5fcb6fab,0x3ad6faec, 0x6c44198c,0x4a475817) | |
| +.size K512,.-K512 | |
| +#if __ARM_MAX_ARCH__>=7 && !defined(__KERNEL__) | |
| +.LOPENSSL_armcap: | |
| +.word OPENSSL_armcap_P-sha512_block_data_order | |
| +.skip 32-4 | |
| +#else | |
| +.skip 32 | |
| +#endif | |
| + | |
| +.global sha512_block_data_order | |
| +.type sha512_block_data_order,%function | |
| +sha512_block_data_order: | |
| +#if __ARM_ARCH__<7 | |
| + sub r3,pc,#8 @ sha512_block_data_order | |
| +#else | |
| + adr r3,sha512_block_data_order | |
| +#endif | |
| +#if __ARM_MAX_ARCH__>=7 && !defined(__KERNEL__) | |
| + ldr r12,.LOPENSSL_armcap | |
| + ldr r12,[r3,r12] @ OPENSSL_armcap_P | |
| + tst r12,#1 | |
| + bne .LNEON | |
| +#endif | |
| + add r2,r1,r2,lsl#7 @ len to point at the end of inp | |
| + stmdb sp!,{r4-r12,lr} | |
| + sub r14,r3,#672 @ K512 | |
| + sub sp,sp,#9*8 | |
| + | |
| + ldr r7,[r0,#32+LO] | |
| + ldr r8,[r0,#32+HI] | |
| + ldr r9, [r0,#48+LO] | |
| + ldr r10, [r0,#48+HI] | |
| + ldr r11, [r0,#56+LO] | |
| + ldr r12, [r0,#56+HI] | |
| +.Loop: | |
| + str r9, [sp,#48+0] | |
| + str r10, [sp,#48+4] | |
| + str r11, [sp,#56+0] | |
| + str r12, [sp,#56+4] | |
| + ldr r5,[r0,#0+LO] | |
| + ldr r6,[r0,#0+HI] | |
| + ldr r3,[r0,#8+LO] | |
| + ldr r4,[r0,#8+HI] | |
| + ldr r9, [r0,#16+LO] | |
| + ldr r10, [r0,#16+HI] | |
| + ldr r11, [r0,#24+LO] | |
| + ldr r12, [r0,#24+HI] | |
| + str r3,[sp,#8+0] | |
| + str r4,[sp,#8+4] | |
| + str r9, [sp,#16+0] | |
| + str r10, [sp,#16+4] | |
| + str r11, [sp,#24+0] | |
| + str r12, [sp,#24+4] | |
| + ldr r3,[r0,#40+LO] | |
| + ldr r4,[r0,#40+HI] | |
| + str r3,[sp,#40+0] | |
| + str r4,[sp,#40+4] | |
| + | |
| +.L00_15: | |
| +#if __ARM_ARCH__<7 | |
| + ldrb r3,[r1,#7] | |
| + ldrb r9, [r1,#6] | |
| + ldrb r10, [r1,#5] | |
| + ldrb r11, [r1,#4] | |
| + ldrb r4,[r1,#3] | |
| + ldrb r12, [r1,#2] | |
| + orr r3,r3,r9,lsl#8 | |
| + ldrb r9, [r1,#1] | |
| + orr r3,r3,r10,lsl#16 | |
| + ldrb r10, [r1],#8 | |
| + orr r3,r3,r11,lsl#24 | |
| + orr r4,r4,r12,lsl#8 | |
| + orr r4,r4,r9,lsl#16 | |
| + orr r4,r4,r10,lsl#24 | |
| +#else | |
| + ldr r3,[r1,#4] | |
| + ldr r4,[r1],#8 | |
| +#ifdef __ARMEL__ | |
| + rev r3,r3 | |
| + rev r4,r4 | |
| +#endif | |
| +#endif | |
| + @ Sigma1(x) (ROTR((x),14) ^ ROTR((x),18) ^ ROTR((x),41)) | |
| + @ LO lo>>14^hi<<18 ^ lo>>18^hi<<14 ^ hi>>9^lo<<23 | |
| + @ HI hi>>14^lo<<18 ^ hi>>18^lo<<14 ^ lo>>9^hi<<23 | |
| + mov r9,r7,lsr#14 | |
| + str r3,[sp,#64+0] | |
| + mov r10,r8,lsr#14 | |
| + str r4,[sp,#64+4] | |
| + eor r9,r9,r8,lsl#18 | |
| + ldr r11,[sp,#56+0] @ h.lo | |
| + eor r10,r10,r7,lsl#18 | |
| + ldr r12,[sp,#56+4] @ h.hi | |
| + eor r9,r9,r7,lsr#18 | |
| + eor r10,r10,r8,lsr#18 | |
| + eor r9,r9,r8,lsl#14 | |
| + eor r10,r10,r7,lsl#14 | |
| + eor r9,r9,r8,lsr#9 | |
| + eor r10,r10,r7,lsr#9 | |
| + eor r9,r9,r7,lsl#23 | |
| + eor r10,r10,r8,lsl#23 @ Sigma1(e) | |
| + adds r3,r3,r9 | |
| + ldr r9,[sp,#40+0] @ f.lo | |
| + adc r4,r4,r10 @ T += Sigma1(e) | |
| + ldr r10,[sp,#40+4] @ f.hi | |
| + adds r3,r3,r11 | |
| + ldr r11,[sp,#48+0] @ g.lo | |
| + adc r4,r4,r12 @ T += h | |
| + ldr r12,[sp,#48+4] @ g.hi | |
| + | |
| + eor r9,r9,r11 | |
| + str r7,[sp,#32+0] | |
| + eor r10,r10,r12 | |
| + str r8,[sp,#32+4] | |
| + and r9,r9,r7 | |
| + str r5,[sp,#0+0] | |
| + and r10,r10,r8 | |
| + str r6,[sp,#0+4] | |
| + eor r9,r9,r11 | |
| + ldr r11,[r14,#LO] @ K[i].lo | |
| + eor r10,r10,r12 @ Ch(e,f,g) | |
| + ldr r12,[r14,#HI] @ K[i].hi | |
| + | |
| + adds r3,r3,r9 | |
| + ldr r7,[sp,#24+0] @ d.lo | |
| + adc r4,r4,r10 @ T += Ch(e,f,g) | |
| + ldr r8,[sp,#24+4] @ d.hi | |
| + adds r3,r3,r11 | |
| + and r9,r11,#0xff | |
| + adc r4,r4,r12 @ T += K[i] | |
| + adds r7,r7,r3 | |
| + ldr r11,[sp,#8+0] @ b.lo | |
| + adc r8,r8,r4 @ d += T | |
| + teq r9,#148 | |
| + | |
| + ldr r12,[sp,#16+0] @ c.lo | |
| +#if __ARM_ARCH__>=7 | |
| + it eq @ Thumb2 thing, sanity check in ARM | |
| +#endif | |
| + orreq r14,r14,#1 | |
| + @ Sigma0(x) (ROTR((x),28) ^ ROTR((x),34) ^ ROTR((x),39)) | |
| + @ LO lo>>28^hi<<4 ^ hi>>2^lo<<30 ^ hi>>7^lo<<25 | |
| + @ HI hi>>28^lo<<4 ^ lo>>2^hi<<30 ^ lo>>7^hi<<25 | |
| + mov r9,r5,lsr#28 | |
| + mov r10,r6,lsr#28 | |
| + eor r9,r9,r6,lsl#4 | |
| + eor r10,r10,r5,lsl#4 | |
| + eor r9,r9,r6,lsr#2 | |
| + eor r10,r10,r5,lsr#2 | |
| + eor r9,r9,r5,lsl#30 | |
| + eor r10,r10,r6,lsl#30 | |
| + eor r9,r9,r6,lsr#7 | |
| + eor r10,r10,r5,lsr#7 | |
| + eor r9,r9,r5,lsl#25 | |
| + eor r10,r10,r6,lsl#25 @ Sigma0(a) | |
| + adds r3,r3,r9 | |
| + and r9,r5,r11 | |
| + adc r4,r4,r10 @ T += Sigma0(a) | |
| + | |
| + ldr r10,[sp,#8+4] @ b.hi | |
| + orr r5,r5,r11 | |
| + ldr r11,[sp,#16+4] @ c.hi | |
| + and r5,r5,r12 | |
| + and r12,r6,r10 | |
| + orr r6,r6,r10 | |
| + orr r5,r5,r9 @ Maj(a,b,c).lo | |
| + and r6,r6,r11 | |
| + adds r5,r5,r3 | |
| + orr r6,r6,r12 @ Maj(a,b,c).hi | |
| + sub sp,sp,#8 | |
| + adc r6,r6,r4 @ h += T | |
| + tst r14,#1 | |
| + add r14,r14,#8 | |
| + tst r14,#1 | |
| + beq .L00_15 | |
| + ldr r9,[sp,#184+0] | |
| + ldr r10,[sp,#184+4] | |
| + bic r14,r14,#1 | |
| +.L16_79: | |
| + @ sigma0(x) (ROTR((x),1) ^ ROTR((x),8) ^ ((x)>>7)) | |
| + @ LO lo>>1^hi<<31 ^ lo>>8^hi<<24 ^ lo>>7^hi<<25 | |
| + @ HI hi>>1^lo<<31 ^ hi>>8^lo<<24 ^ hi>>7 | |
| + mov r3,r9,lsr#1 | |
| + ldr r11,[sp,#80+0] | |
| + mov r4,r10,lsr#1 | |
| + ldr r12,[sp,#80+4] | |
| + eor r3,r3,r10,lsl#31 | |
| + eor r4,r4,r9,lsl#31 | |
| + eor r3,r3,r9,lsr#8 | |
| + eor r4,r4,r10,lsr#8 | |
| + eor r3,r3,r10,lsl#24 | |
| + eor r4,r4,r9,lsl#24 | |
| + eor r3,r3,r9,lsr#7 | |
| + eor r4,r4,r10,lsr#7 | |
| + eor r3,r3,r10,lsl#25 | |
| + | |
| + @ sigma1(x) (ROTR((x),19) ^ ROTR((x),61) ^ ((x)>>6)) | |
| + @ LO lo>>19^hi<<13 ^ hi>>29^lo<<3 ^ lo>>6^hi<<26 | |
| + @ HI hi>>19^lo<<13 ^ lo>>29^hi<<3 ^ hi>>6 | |
| + mov r9,r11,lsr#19 | |
| + mov r10,r12,lsr#19 | |
| + eor r9,r9,r12,lsl#13 | |
| + eor r10,r10,r11,lsl#13 | |
| + eor r9,r9,r12,lsr#29 | |
| + eor r10,r10,r11,lsr#29 | |
| + eor r9,r9,r11,lsl#3 | |
| + eor r10,r10,r12,lsl#3 | |
| + eor r9,r9,r11,lsr#6 | |
| + eor r10,r10,r12,lsr#6 | |
| + ldr r11,[sp,#120+0] | |
| + eor r9,r9,r12,lsl#26 | |
| + | |
| + ldr r12,[sp,#120+4] | |
| + adds r3,r3,r9 | |
| + ldr r9,[sp,#192+0] | |
| + adc r4,r4,r10 | |
| + | |
| + ldr r10,[sp,#192+4] | |
| + adds r3,r3,r11 | |
| + adc r4,r4,r12 | |
| + adds r3,r3,r9 | |
| + adc r4,r4,r10 | |
| + @ Sigma1(x) (ROTR((x),14) ^ ROTR((x),18) ^ ROTR((x),41)) | |
| + @ LO lo>>14^hi<<18 ^ lo>>18^hi<<14 ^ hi>>9^lo<<23 | |
| + @ HI hi>>14^lo<<18 ^ hi>>18^lo<<14 ^ lo>>9^hi<<23 | |
| + mov r9,r7,lsr#14 | |
| + str r3,[sp,#64+0] | |
| + mov r10,r8,lsr#14 | |
| + str r4,[sp,#64+4] | |
| + eor r9,r9,r8,lsl#18 | |
| + ldr r11,[sp,#56+0] @ h.lo | |
| + eor r10,r10,r7,lsl#18 | |
| + ldr r12,[sp,#56+4] @ h.hi | |
| + eor r9,r9,r7,lsr#18 | |
| + eor r10,r10,r8,lsr#18 | |
| + eor r9,r9,r8,lsl#14 | |
| + eor r10,r10,r7,lsl#14 | |
| + eor r9,r9,r8,lsr#9 | |
| + eor r10,r10,r7,lsr#9 | |
| + eor r9,r9,r7,lsl#23 | |
| + eor r10,r10,r8,lsl#23 @ Sigma1(e) | |
| + adds r3,r3,r9 | |
| + ldr r9,[sp,#40+0] @ f.lo | |
| + adc r4,r4,r10 @ T += Sigma1(e) | |
| + ldr r10,[sp,#40+4] @ f.hi | |
| + adds r3,r3,r11 | |
| + ldr r11,[sp,#48+0] @ g.lo | |
| + adc r4,r4,r12 @ T += h | |
| + ldr r12,[sp,#48+4] @ g.hi | |
| + | |
| + eor r9,r9,r11 | |
| + str r7,[sp,#32+0] | |
| + eor r10,r10,r12 | |
| + str r8,[sp,#32+4] | |
| + and r9,r9,r7 | |
| + str r5,[sp,#0+0] | |
| + and r10,r10,r8 | |
| + str r6,[sp,#0+4] | |
| + eor r9,r9,r11 | |
| + ldr r11,[r14,#LO] @ K[i].lo | |
| + eor r10,r10,r12 @ Ch(e,f,g) | |
| + ldr r12,[r14,#HI] @ K[i].hi | |
| + | |
| + adds r3,r3,r9 | |
| + ldr r7,[sp,#24+0] @ d.lo | |
| + adc r4,r4,r10 @ T += Ch(e,f,g) | |
| + ldr r8,[sp,#24+4] @ d.hi | |
| + adds r3,r3,r11 | |
| + and r9,r11,#0xff | |
| + adc r4,r4,r12 @ T += K[i] | |
| + adds r7,r7,r3 | |
| + ldr r11,[sp,#8+0] @ b.lo | |
| + adc r8,r8,r4 @ d += T | |
| + teq r9,#23 | |
| + | |
| + ldr r12,[sp,#16+0] @ c.lo | |
| +#if __ARM_ARCH__>=7 | |
| + it eq @ Thumb2 thing, sanity check in ARM | |
| +#endif | |
| + orreq r14,r14,#1 | |
| + @ Sigma0(x) (ROTR((x),28) ^ ROTR((x),34) ^ ROTR((x),39)) | |
| + @ LO lo>>28^hi<<4 ^ hi>>2^lo<<30 ^ hi>>7^lo<<25 | |
| + @ HI hi>>28^lo<<4 ^ lo>>2^hi<<30 ^ lo>>7^hi<<25 | |
| + mov r9,r5,lsr#28 | |
| + mov r10,r6,lsr#28 | |
| + eor r9,r9,r6,lsl#4 | |
| + eor r10,r10,r5,lsl#4 | |
| + eor r9,r9,r6,lsr#2 | |
| + eor r10,r10,r5,lsr#2 | |
| + eor r9,r9,r5,lsl#30 | |
| + eor r10,r10,r6,lsl#30 | |
| + eor r9,r9,r6,lsr#7 | |
| + eor r10,r10,r5,lsr#7 | |
| + eor r9,r9,r5,lsl#25 | |
| + eor r10,r10,r6,lsl#25 @ Sigma0(a) | |
| + adds r3,r3,r9 | |
| + and r9,r5,r11 | |
| + adc r4,r4,r10 @ T += Sigma0(a) | |
| + | |
| + ldr r10,[sp,#8+4] @ b.hi | |
| + orr r5,r5,r11 | |
| + ldr r11,[sp,#16+4] @ c.hi | |
| + and r5,r5,r12 | |
| + and r12,r6,r10 | |
| + orr r6,r6,r10 | |
| + orr r5,r5,r9 @ Maj(a,b,c).lo | |
| + and r6,r6,r11 | |
| + adds r5,r5,r3 | |
| + orr r6,r6,r12 @ Maj(a,b,c).hi | |
| + sub sp,sp,#8 | |
| + adc r6,r6,r4 @ h += T | |
| + tst r14,#1 | |
| + add r14,r14,#8 | |
| +#if __ARM_ARCH__>=7 | |
| + ittt eq @ Thumb2 thing, sanity check in ARM | |
| +#endif | |
| + ldreq r9,[sp,#184+0] | |
| + ldreq r10,[sp,#184+4] | |
| + beq .L16_79 | |
| + bic r14,r14,#1 | |
| + | |
| + ldr r3,[sp,#8+0] | |
| + ldr r4,[sp,#8+4] | |
| + ldr r9, [r0,#0+LO] | |
| + ldr r10, [r0,#0+HI] | |
| + ldr r11, [r0,#8+LO] | |
| + ldr r12, [r0,#8+HI] | |
| + adds r9,r5,r9 | |
| + str r9, [r0,#0+LO] | |
| + adc r10,r6,r10 | |
| + str r10, [r0,#0+HI] | |
| + adds r11,r3,r11 | |
| + str r11, [r0,#8+LO] | |
| + adc r12,r4,r12 | |
| + str r12, [r0,#8+HI] | |
| + | |
| + ldr r5,[sp,#16+0] | |
| + ldr r6,[sp,#16+4] | |
| + ldr r3,[sp,#24+0] | |
| + ldr r4,[sp,#24+4] | |
| + ldr r9, [r0,#16+LO] | |
| + ldr r10, [r0,#16+HI] | |
| + ldr r11, [r0,#24+LO] | |
| + ldr r12, [r0,#24+HI] | |
| + adds r9,r5,r9 | |
| + str r9, [r0,#16+LO] | |
| + adc r10,r6,r10 | |
| + str r10, [r0,#16+HI] | |
| + adds r11,r3,r11 | |
| + str r11, [r0,#24+LO] | |
| + adc r12,r4,r12 | |
| + str r12, [r0,#24+HI] | |
| + | |
| + ldr r3,[sp,#40+0] | |
| + ldr r4,[sp,#40+4] | |
| + ldr r9, [r0,#32+LO] | |
| + ldr r10, [r0,#32+HI] | |
| + ldr r11, [r0,#40+LO] | |
| + ldr r12, [r0,#40+HI] | |
| + adds r7,r7,r9 | |
| + str r7,[r0,#32+LO] | |
| + adc r8,r8,r10 | |
| + str r8,[r0,#32+HI] | |
| + adds r11,r3,r11 | |
| + str r11, [r0,#40+LO] | |
| + adc r12,r4,r12 | |
| + str r12, [r0,#40+HI] | |
| + | |
| + ldr r5,[sp,#48+0] | |
| + ldr r6,[sp,#48+4] | |
| + ldr r3,[sp,#56+0] | |
| + ldr r4,[sp,#56+4] | |
| + ldr r9, [r0,#48+LO] | |
| + ldr r10, [r0,#48+HI] | |
| + ldr r11, [r0,#56+LO] | |
| + ldr r12, [r0,#56+HI] | |
| + adds r9,r5,r9 | |
| + str r9, [r0,#48+LO] | |
| + adc r10,r6,r10 | |
| + str r10, [r0,#48+HI] | |
| + adds r11,r3,r11 | |
| + str r11, [r0,#56+LO] | |
| + adc r12,r4,r12 | |
| + str r12, [r0,#56+HI] | |
| + | |
| + add sp,sp,#640 | |
| + sub r14,r14,#640 | |
| + | |
| + teq r1,r2 | |
| + bne .Loop | |
| + | |
| + add sp,sp,#8*9 @ destroy frame | |
| +#if __ARM_ARCH__>=5 | |
| + ldmia sp!,{r4-r12,pc} | |
| +#else | |
| + ldmia sp!,{r4-r12,lr} | |
| + tst lr,#1 | |
| + moveq pc,lr @ be binary compatible with V4, yet | |
| + .word 0xe12fff1e @ interoperable with Thumb ISA:-) | |
| +#endif | |
| +.size sha512_block_data_order,.-sha512_block_data_order | |
| +#if __ARM_MAX_ARCH__>=7 | |
| +.arch armv7-a | |
| +.fpu neon | |
| + | |
| +.global sha512_block_data_order_neon | |
| +.type sha512_block_data_order_neon,%function | |
| +.align 4 | |
| +sha512_block_data_order_neon: | |
| +.LNEON: | |
| + dmb @ errata #451034 on early Cortex A8 | |
| + add r2,r1,r2,lsl#7 @ len to point at the end of inp | |
| + VFP_ABI_PUSH | |
| + adrl r3,K512 | |
| + vldmia r0,{d16-d23} @ load context | |
| +.Loop_neon: | |
| + vshr.u64 d24,d20,#14 @ 0 | |
| +#if 0<16 | |
| + vld1.64 {d0},[r1]! @ handles unaligned | |
| +#endif | |
| + vshr.u64 d25,d20,#18 | |
| +#if 0>0 | |
| + vadd.i64 d16,d30 @ h+=Maj from the past | |
| +#endif | |
| + vshr.u64 d26,d20,#41 | |
| + vld1.64 {d28},[r3,:64]! @ K[i++] | |
| + vsli.64 d24,d20,#50 | |
| + vsli.64 d25,d20,#46 | |
| + vmov d29,d20 | |
| + vsli.64 d26,d20,#23 | |
| +#if 0<16 && defined(__ARMEL__) | |
| + vrev64.8 d0,d0 | |
| +#endif | |
| + veor d25,d24 | |
| + vbsl d29,d21,d22 @ Ch(e,f,g) | |
| + vshr.u64 d24,d16,#28 | |
| + veor d26,d25 @ Sigma1(e) | |
| + vadd.i64 d27,d29,d23 | |
| + vshr.u64 d25,d16,#34 | |
| + vsli.64 d24,d16,#36 | |
| + vadd.i64 d27,d26 | |
| + vshr.u64 d26,d16,#39 | |
| + vadd.i64 d28,d0 | |
| + vsli.64 d25,d16,#30 | |
| + veor d30,d16,d17 | |
| + vsli.64 d26,d16,#25 | |
| + veor d23,d24,d25 | |
| + vadd.i64 d27,d28 | |
| + vbsl d30,d18,d17 @ Maj(a,b,c) | |
| + veor d23,d26 @ Sigma0(a) | |
| + vadd.i64 d19,d27 | |
| + vadd.i64 d30,d27 | |
| + @ vadd.i64 d23,d30 | |
| + vshr.u64 d24,d19,#14 @ 1 | |
| +#if 1<16 | |
| + vld1.64 {d1},[r1]! @ handles unaligned | |
| +#endif | |
| + vshr.u64 d25,d19,#18 | |
| +#if 1>0 | |
| + vadd.i64 d23,d30 @ h+=Maj from the past | |
| +#endif | |
| + vshr.u64 d26,d19,#41 | |
| + vld1.64 {d28},[r3,:64]! @ K[i++] | |
| + vsli.64 d24,d19,#50 | |
| + vsli.64 d25,d19,#46 | |
| + vmov d29,d19 | |
| + vsli.64 d26,d19,#23 | |
| +#if 1<16 && defined(__ARMEL__) | |
| + vrev64.8 d1,d1 | |
| +#endif | |
| + veor d25,d24 | |
| + vbsl d29,d20,d21 @ Ch(e,f,g) | |
| + vshr.u64 d24,d23,#28 | |
| + veor d26,d25 @ Sigma1(e) | |
| + vadd.i64 d27,d29,d22 | |
| + vshr.u64 d25,d23,#34 | |
| + vsli.64 d24,d23,#36 | |
| + vadd.i64 d27,d26 | |
| + vshr.u64 d26,d23,#39 | |
| + vadd.i64 d28,d1 | |
| + vsli.64 d25,d23,#30 | |
| + veor d30,d23,d16 | |
| + vsli.64 d26,d23,#25 | |
| + veor d22,d24,d25 | |
| + vadd.i64 d27,d28 | |
| + vbsl d30,d17,d16 @ Maj(a,b,c) | |
| + veor d22,d26 @ Sigma0(a) | |
| + vadd.i64 d18,d27 | |
| + vadd.i64 d30,d27 | |
| + @ vadd.i64 d22,d30 | |
| + vshr.u64 d24,d18,#14 @ 2 | |
| +#if 2<16 | |
| + vld1.64 {d2},[r1]! @ handles unaligned | |
| +#endif | |
| + vshr.u64 d25,d18,#18 | |
| +#if 2>0 | |
| + vadd.i64 d22,d30 @ h+=Maj from the past | |
| +#endif | |
| + vshr.u64 d26,d18,#41 | |
| + vld1.64 {d28},[r3,:64]! @ K[i++] | |
| + vsli.64 d24,d18,#50 | |
| + vsli.64 d25,d18,#46 | |
| + vmov d29,d18 | |
| + vsli.64 d26,d18,#23 | |
| +#if 2<16 && defined(__ARMEL__) | |
| + vrev64.8 d2,d2 | |
| +#endif | |
| + veor d25,d24 | |
| + vbsl d29,d19,d20 @ Ch(e,f,g) | |
| + vshr.u64 d24,d22,#28 | |
| + veor d26,d25 @ Sigma1(e) | |
| + vadd.i64 d27,d29,d21 | |
| + vshr.u64 d25,d22,#34 | |
| + vsli.64 d24,d22,#36 | |
| + vadd.i64 d27,d26 | |
| + vshr.u64 d26,d22,#39 | |
| + vadd.i64 d28,d2 | |
| + vsli.64 d25,d22,#30 | |
| + veor d30,d22,d23 | |
| + vsli.64 d26,d22,#25 | |
| + veor d21,d24,d25 | |
| + vadd.i64 d27,d28 | |
| + vbsl d30,d16,d23 @ Maj(a,b,c) | |
| + veor d21,d26 @ Sigma0(a) | |
| + vadd.i64 d17,d27 | |
| + vadd.i64 d30,d27 | |
| + @ vadd.i64 d21,d30 | |
| + vshr.u64 d24,d17,#14 @ 3 | |
| +#if 3<16 | |
| + vld1.64 {d3},[r1]! @ handles unaligned | |
| +#endif | |
| + vshr.u64 d25,d17,#18 | |
| +#if 3>0 | |
| + vadd.i64 d21,d30 @ h+=Maj from the past | |
| +#endif | |
| + vshr.u64 d26,d17,#41 | |
| + vld1.64 {d28},[r3,:64]! @ K[i++] | |
| + vsli.64 d24,d17,#50 | |
| + vsli.64 d25,d17,#46 | |
| + vmov d29,d17 | |
| + vsli.64 d26,d17,#23 | |
| +#if 3<16 && defined(__ARMEL__) | |
| + vrev64.8 d3,d3 | |
| +#endif | |
| + veor d25,d24 | |
| + vbsl d29,d18,d19 @ Ch(e,f,g) | |
| + vshr.u64 d24,d21,#28 | |
| + veor d26,d25 @ Sigma1(e) | |
| + vadd.i64 d27,d29,d20 | |
| + vshr.u64 d25,d21,#34 | |
| + vsli.64 d24,d21,#36 | |
| + vadd.i64 d27,d26 | |
| + vshr.u64 d26,d21,#39 | |
| + vadd.i64 d28,d3 | |
| + vsli.64 d25,d21,#30 | |
| + veor d30,d21,d22 | |
| + vsli.64 d26,d21,#25 | |
| + veor d20,d24,d25 | |
| + vadd.i64 d27,d28 | |
| + vbsl d30,d23,d22 @ Maj(a,b,c) | |
| + veor d20,d26 @ Sigma0(a) | |
| + vadd.i64 d16,d27 | |
| + vadd.i64 d30,d27 | |
| + @ vadd.i64 d20,d30 | |
| + vshr.u64 d24,d16,#14 @ 4 | |
| +#if 4<16 | |
| + vld1.64 {d4},[r1]! @ handles unaligned | |
| +#endif | |
| + vshr.u64 d25,d16,#18 | |
| +#if 4>0 | |
| + vadd.i64 d20,d30 @ h+=Maj from the past | |
| +#endif | |
| + vshr.u64 d26,d16,#41 | |
| + vld1.64 {d28},[r3,:64]! @ K[i++] | |
| + vsli.64 d24,d16,#50 | |
| + vsli.64 d25,d16,#46 | |
| + vmov d29,d16 | |
| + vsli.64 d26,d16,#23 | |
| +#if 4<16 && defined(__ARMEL__) | |
| + vrev64.8 d4,d4 | |
| +#endif | |
| + veor d25,d24 | |
| + vbsl d29,d17,d18 @ Ch(e,f,g) | |
| + vshr.u64 d24,d20,#28 | |
| + veor d26,d25 @ Sigma1(e) | |
| + vadd.i64 d27,d29,d19 | |
| + vshr.u64 d25,d20,#34 | |
| + vsli.64 d24,d20,#36 | |
| + vadd.i64 d27,d26 | |
| + vshr.u64 d26,d20,#39 | |
| + vadd.i64 d28,d4 | |
| + vsli.64 d25,d20,#30 | |
| + veor d30,d20,d21 | |
| + vsli.64 d26,d20,#25 | |
| + veor d19,d24,d25 | |
| + vadd.i64 d27,d28 | |
| + vbsl d30,d22,d21 @ Maj(a,b,c) | |
| + veor d19,d26 @ Sigma0(a) | |
| + vadd.i64 d23,d27 | |
| + vadd.i64 d30,d27 | |
| + @ vadd.i64 d19,d30 | |
| + vshr.u64 d24,d23,#14 @ 5 | |
| +#if 5<16 | |
| + vld1.64 {d5},[r1]! @ handles unaligned | |
| +#endif | |
| + vshr.u64 d25,d23,#18 | |
| +#if 5>0 | |
| + vadd.i64 d19,d30 @ h+=Maj from the past | |
| +#endif | |
| + vshr.u64 d26,d23,#41 | |
| + vld1.64 {d28},[r3,:64]! @ K[i++] | |
| + vsli.64 d24,d23,#50 | |
| + vsli.64 d25,d23,#46 | |
| + vmov d29,d23 | |
| + vsli.64 d26,d23,#23 | |
| +#if 5<16 && defined(__ARMEL__) | |
| + vrev64.8 d5,d5 | |
| +#endif | |
| + veor d25,d24 | |
| + vbsl d29,d16,d17 @ Ch(e,f,g) | |
| + vshr.u64 d24,d19,#28 | |
| + veor d26,d25 @ Sigma1(e) | |
| + vadd.i64 d27,d29,d18 | |
| + vshr.u64 d25,d19,#34 | |
| + vsli.64 d24,d19,#36 | |
| + vadd.i64 d27,d26 | |
| + vshr.u64 d26,d19,#39 | |
| + vadd.i64 d28,d5 | |
| + vsli.64 d25,d19,#30 | |
| + veor d30,d19,d20 | |
| + vsli.64 d26,d19,#25 | |
| + veor d18,d24,d25 | |
| + vadd.i64 d27,d28 | |
| + vbsl d30,d21,d20 @ Maj(a,b,c) | |
| + veor d18,d26 @ Sigma0(a) | |
| + vadd.i64 d22,d27 | |
| + vadd.i64 d30,d27 | |
| + @ vadd.i64 d18,d30 | |
| + vshr.u64 d24,d22,#14 @ 6 | |
| +#if 6<16 | |
| + vld1.64 {d6},[r1]! @ handles unaligned | |
| +#endif | |
| + vshr.u64 d25,d22,#18 | |
| +#if 6>0 | |
| + vadd.i64 d18,d30 @ h+=Maj from the past | |
| +#endif | |
| + vshr.u64 d26,d22,#41 | |
| + vld1.64 {d28},[r3,:64]! @ K[i++] | |
| + vsli.64 d24,d22,#50 | |
| + vsli.64 d25,d22,#46 | |
| + vmov d29,d22 | |
| + vsli.64 d26,d22,#23 | |
| +#if 6<16 && defined(__ARMEL__) | |
| + vrev64.8 d6,d6 | |
| +#endif | |
| + veor d25,d24 | |
| + vbsl d29,d23,d16 @ Ch(e,f,g) | |
| + vshr.u64 d24,d18,#28 | |
| + veor d26,d25 @ Sigma1(e) | |
| + vadd.i64 d27,d29,d17 | |
| + vshr.u64 d25,d18,#34 | |
| + vsli.64 d24,d18,#36 | |
| + vadd.i64 d27,d26 | |
| + vshr.u64 d26,d18,#39 | |
| + vadd.i64 d28,d6 | |
| + vsli.64 d25,d18,#30 | |
| + veor d30,d18,d19 | |
| + vsli.64 d26,d18,#25 | |
| + veor d17,d24,d25 | |
| + vadd.i64 d27,d28 | |
| + vbsl d30,d20,d19 @ Maj(a,b,c) | |
| + veor d17,d26 @ Sigma0(a) | |
| + vadd.i64 d21,d27 | |
| + vadd.i64 d30,d27 | |
| + @ vadd.i64 d17,d30 | |
| + vshr.u64 d24,d21,#14 @ 7 | |
| +#if 7<16 | |
| + vld1.64 {d7},[r1]! @ handles unaligned | |
| +#endif | |
| + vshr.u64 d25,d21,#18 | |
| +#if 7>0 | |
| + vadd.i64 d17,d30 @ h+=Maj from the past | |
| +#endif | |
| + vshr.u64 d26,d21,#41 | |
| + vld1.64 {d28},[r3,:64]! @ K[i++] | |
| + vsli.64 d24,d21,#50 | |
| + vsli.64 d25,d21,#46 | |
| + vmov d29,d21 | |
| + vsli.64 d26,d21,#23 | |
| +#if 7<16 && defined(__ARMEL__) | |
| + vrev64.8 d7,d7 | |
| +#endif | |
| + veor d25,d24 | |
| + vbsl d29,d22,d23 @ Ch(e,f,g) | |
| + vshr.u64 d24,d17,#28 | |
| + veor d26,d25 @ Sigma1(e) | |
| + vadd.i64 d27,d29,d16 | |
| + vshr.u64 d25,d17,#34 | |
| + vsli.64 d24,d17,#36 | |
| + vadd.i64 d27,d26 | |
| + vshr.u64 d26,d17,#39 | |
| + vadd.i64 d28,d7 | |
| + vsli.64 d25,d17,#30 | |
| + veor d30,d17,d18 | |
| + vsli.64 d26,d17,#25 | |
| + veor d16,d24,d25 | |
| + vadd.i64 d27,d28 | |
| + vbsl d30,d19,d18 @ Maj(a,b,c) | |
| + veor d16,d26 @ Sigma0(a) | |
| + vadd.i64 d20,d27 | |
| + vadd.i64 d30,d27 | |
| + @ vadd.i64 d16,d30 | |
| + vshr.u64 d24,d20,#14 @ 8 | |
| +#if 8<16 | |
| + vld1.64 {d8},[r1]! @ handles unaligned | |
| +#endif | |
| + vshr.u64 d25,d20,#18 | |
| +#if 8>0 | |
| + vadd.i64 d16,d30 @ h+=Maj from the past | |
| +#endif | |
| + vshr.u64 d26,d20,#41 | |
| + vld1.64 {d28},[r3,:64]! @ K[i++] | |
| + vsli.64 d24,d20,#50 | |
| + vsli.64 d25,d20,#46 | |
| + vmov d29,d20 | |
| + vsli.64 d26,d20,#23 | |
| +#if 8<16 && defined(__ARMEL__) | |
| + vrev64.8 d8,d8 | |
| +#endif | |
| + veor d25,d24 | |
| + vbsl d29,d21,d22 @ Ch(e,f,g) | |
| + vshr.u64 d24,d16,#28 | |
| + veor d26,d25 @ Sigma1(e) | |
| + vadd.i64 d27,d29,d23 | |
| + vshr.u64 d25,d16,#34 | |
| + vsli.64 d24,d16,#36 | |
| + vadd.i64 d27,d26 | |
| + vshr.u64 d26,d16,#39 | |
| + vadd.i64 d28,d8 | |
| + vsli.64 d25,d16,#30 | |
| + veor d30,d16,d17 | |
| + vsli.64 d26,d16,#25 | |
| + veor d23,d24,d25 | |
| + vadd.i64 d27,d28 | |
| + vbsl d30,d18,d17 @ Maj(a,b,c) | |
| + veor d23,d26 @ Sigma0(a) | |
| + vadd.i64 d19,d27 | |
| + vadd.i64 d30,d27 | |
| + @ vadd.i64 d23,d30 | |
| + vshr.u64 d24,d19,#14 @ 9 | |
| +#if 9<16 | |
| + vld1.64 {d9},[r1]! @ handles unaligned | |
| +#endif | |
| + vshr.u64 d25,d19,#18 | |
| +#if 9>0 | |
| + vadd.i64 d23,d30 @ h+=Maj from the past | |
| +#endif | |
| + vshr.u64 d26,d19,#41 | |
| + vld1.64 {d28},[r3,:64]! @ K[i++] | |
| + vsli.64 d24,d19,#50 | |
| + vsli.64 d25,d19,#46 | |
| + vmov d29,d19 | |
| + vsli.64 d26,d19,#23 | |
| +#if 9<16 && defined(__ARMEL__) | |
| + vrev64.8 d9,d9 | |
| +#endif | |
| + veor d25,d24 | |
| + vbsl d29,d20,d21 @ Ch(e,f,g) | |
| + vshr.u64 d24,d23,#28 | |
| + veor d26,d25 @ Sigma1(e) | |
| + vadd.i64 d27,d29,d22 | |
| + vshr.u64 d25,d23,#34 | |
| + vsli.64 d24,d23,#36 | |
| + vadd.i64 d27,d26 | |
| + vshr.u64 d26,d23,#39 | |
| + vadd.i64 d28,d9 | |
| + vsli.64 d25,d23,#30 | |
| + veor d30,d23,d16 | |
| + vsli.64 d26,d23,#25 | |
| + veor d22,d24,d25 | |
| + vadd.i64 d27,d28 | |
| + vbsl d30,d17,d16 @ Maj(a,b,c) | |
| + veor d22,d26 @ Sigma0(a) | |
| + vadd.i64 d18,d27 | |
| + vadd.i64 d30,d27 | |
| + @ vadd.i64 d22,d30 | |
| + vshr.u64 d24,d18,#14 @ 10 | |
| +#if 10<16 | |
| + vld1.64 {d10},[r1]! @ handles unaligned | |
| +#endif | |
| + vshr.u64 d25,d18,#18 | |
| +#if 10>0 | |
| + vadd.i64 d22,d30 @ h+=Maj from the past | |
| +#endif | |
| + vshr.u64 d26,d18,#41 | |
| + vld1.64 {d28},[r3,:64]! @ K[i++] | |
| + vsli.64 d24,d18,#50 | |
| + vsli.64 d25,d18,#46 | |
| + vmov d29,d18 | |
| + vsli.64 d26,d18,#23 | |
| +#if 10<16 && defined(__ARMEL__) | |
| + vrev64.8 d10,d10 | |
| +#endif | |
| + veor d25,d24 | |
| + vbsl d29,d19,d20 @ Ch(e,f,g) | |
| + vshr.u64 d24,d22,#28 | |
| + veor d26,d25 @ Sigma1(e) | |
| + vadd.i64 d27,d29,d21 | |
| + vshr.u64 d25,d22,#34 | |
| + vsli.64 d24,d22,#36 | |
| + vadd.i64 d27,d26 | |
| + vshr.u64 d26,d22,#39 | |
| + vadd.i64 d28,d10 | |
| + vsli.64 d25,d22,#30 | |
| + veor d30,d22,d23 | |
| + vsli.64 d26,d22,#25 | |
| + veor d21,d24,d25 | |
| + vadd.i64 d27,d28 | |
| + vbsl d30,d16,d23 @ Maj(a,b,c) | |
| + veor d21,d26 @ Sigma0(a) | |
| + vadd.i64 d17,d27 | |
| + vadd.i64 d30,d27 | |
| + @ vadd.i64 d21,d30 | |
| + vshr.u64 d24,d17,#14 @ 11 | |
| +#if 11<16 | |
| + vld1.64 {d11},[r1]! @ handles unaligned | |
| +#endif | |
| + vshr.u64 d25,d17,#18 | |
| +#if 11>0 | |
| + vadd.i64 d21,d30 @ h+=Maj from the past | |
| +#endif | |
| + vshr.u64 d26,d17,#41 | |
| + vld1.64 {d28},[r3,:64]! @ K[i++] | |
| + vsli.64 d24,d17,#50 | |
| + vsli.64 d25,d17,#46 | |
| + vmov d29,d17 | |
| + vsli.64 d26,d17,#23 | |
| +#if 11<16 && defined(__ARMEL__) | |
| + vrev64.8 d11,d11 | |
| +#endif | |
| + veor d25,d24 | |
| + vbsl d29,d18,d19 @ Ch(e,f,g) | |
| + vshr.u64 d24,d21,#28 | |
| + veor d26,d25 @ Sigma1(e) | |
| + vadd.i64 d27,d29,d20 | |
| + vshr.u64 d25,d21,#34 | |
| + vsli.64 d24,d21,#36 | |
| + vadd.i64 d27,d26 | |
| + vshr.u64 d26,d21,#39 | |
| + vadd.i64 d28,d11 | |
| + vsli.64 d25,d21,#30 | |
| + veor d30,d21,d22 | |
| + vsli.64 d26,d21,#25 | |
| + veor d20,d24,d25 | |
| + vadd.i64 d27,d28 | |
| + vbsl d30,d23,d22 @ Maj(a,b,c) | |
| + veor d20,d26 @ Sigma0(a) | |
| + vadd.i64 d16,d27 | |
| + vadd.i64 d30,d27 | |
| + @ vadd.i64 d20,d30 | |
| + vshr.u64 d24,d16,#14 @ 12 | |
| +#if 12<16 | |
| + vld1.64 {d12},[r1]! @ handles unaligned | |
| +#endif | |
| + vshr.u64 d25,d16,#18 | |
| +#if 12>0 | |
| + vadd.i64 d20,d30 @ h+=Maj from the past | |
| +#endif | |
| + vshr.u64 d26,d16,#41 | |
| + vld1.64 {d28},[r3,:64]! @ K[i++] | |
| + vsli.64 d24,d16,#50 | |
| + vsli.64 d25,d16,#46 | |
| + vmov d29,d16 | |
| + vsli.64 d26,d16,#23 | |
| +#if 12<16 && defined(__ARMEL__) | |
| + vrev64.8 d12,d12 | |
| +#endif | |
| + veor d25,d24 | |
| + vbsl d29,d17,d18 @ Ch(e,f,g) | |
| + vshr.u64 d24,d20,#28 | |
| + veor d26,d25 @ Sigma1(e) | |
| + vadd.i64 d27,d29,d19 | |
| + vshr.u64 d25,d20,#34 | |
| + vsli.64 d24,d20,#36 | |
| + vadd.i64 d27,d26 | |
| + vshr.u64 d26,d20,#39 | |
| + vadd.i64 d28,d12 | |
| + vsli.64 d25,d20,#30 | |
| + veor d30,d20,d21 | |
| + vsli.64 d26,d20,#25 | |
| + veor d19,d24,d25 | |
| + vadd.i64 d27,d28 | |
| + vbsl d30,d22,d21 @ Maj(a,b,c) | |
| + veor d19,d26 @ Sigma0(a) | |
| + vadd.i64 d23,d27 | |
| + vadd.i64 d30,d27 | |
| + @ vadd.i64 d19,d30 | |
| + vshr.u64 d24,d23,#14 @ 13 | |
| +#if 13<16 | |
| + vld1.64 {d13},[r1]! @ handles unaligned | |
| +#endif | |
| + vshr.u64 d25,d23,#18 | |
| +#if 13>0 | |
| + vadd.i64 d19,d30 @ h+=Maj from the past | |
| +#endif | |
| + vshr.u64 d26,d23,#41 | |
| + vld1.64 {d28},[r3,:64]! @ K[i++] | |
| + vsli.64 d24,d23,#50 | |
| + vsli.64 d25,d23,#46 | |
| + vmov d29,d23 | |
| + vsli.64 d26,d23,#23 | |
| +#if 13<16 && defined(__ARMEL__) | |
| + vrev64.8 d13,d13 | |
| +#endif | |
| + veor d25,d24 | |
| + vbsl d29,d16,d17 @ Ch(e,f,g) | |
| + vshr.u64 d24,d19,#28 | |
| + veor d26,d25 @ Sigma1(e) | |
| + vadd.i64 d27,d29,d18 | |
| + vshr.u64 d25,d19,#34 | |
| + vsli.64 d24,d19,#36 | |
| + vadd.i64 d27,d26 | |
| + vshr.u64 d26,d19,#39 | |
| + vadd.i64 d28,d13 | |
| + vsli.64 d25,d19,#30 | |
| + veor d30,d19,d20 | |
| + vsli.64 d26,d19,#25 | |
| + veor d18,d24,d25 | |
| + vadd.i64 d27,d28 | |
| + vbsl d30,d21,d20 @ Maj(a,b,c) | |
| + veor d18,d26 @ Sigma0(a) | |
| + vadd.i64 d22,d27 | |
| + vadd.i64 d30,d27 | |
| + @ vadd.i64 d18,d30 | |
| + vshr.u64 d24,d22,#14 @ 14 | |
| +#if 14<16 | |
| + vld1.64 {d14},[r1]! @ handles unaligned | |
| +#endif | |
| + vshr.u64 d25,d22,#18 | |
| +#if 14>0 | |
| + vadd.i64 d18,d30 @ h+=Maj from the past | |
| +#endif | |
| + vshr.u64 d26,d22,#41 | |
| + vld1.64 {d28},[r3,:64]! @ K[i++] | |
| + vsli.64 d24,d22,#50 | |
| + vsli.64 d25,d22,#46 | |
| + vmov d29,d22 | |
| + vsli.64 d26,d22,#23 | |
| +#if 14<16 && defined(__ARMEL__) | |
| + vrev64.8 d14,d14 | |
| +#endif | |
| + veor d25,d24 | |
| + vbsl d29,d23,d16 @ Ch(e,f,g) | |
| + vshr.u64 d24,d18,#28 | |
| + veor d26,d25 @ Sigma1(e) | |
| + vadd.i64 d27,d29,d17 | |
| + vshr.u64 d25,d18,#34 | |
| + vsli.64 d24,d18,#36 | |
| + vadd.i64 d27,d26 | |
| + vshr.u64 d26,d18,#39 | |
| + vadd.i64 d28,d14 | |
| + vsli.64 d25,d18,#30 | |
| + veor d30,d18,d19 | |
| + vsli.64 d26,d18,#25 | |
| + veor d17,d24,d25 | |
| + vadd.i64 d27,d28 | |
| + vbsl d30,d20,d19 @ Maj(a,b,c) | |
| + veor d17,d26 @ Sigma0(a) | |
| + vadd.i64 d21,d27 | |
| + vadd.i64 d30,d27 | |
| + @ vadd.i64 d17,d30 | |
| + vshr.u64 d24,d21,#14 @ 15 | |
| +#if 15<16 | |
| + vld1.64 {d15},[r1]! @ handles unaligned | |
| +#endif | |
| + vshr.u64 d25,d21,#18 | |
| +#if 15>0 | |
| + vadd.i64 d17,d30 @ h+=Maj from the past | |
| +#endif | |
| + vshr.u64 d26,d21,#41 | |
| + vld1.64 {d28},[r3,:64]! @ K[i++] | |
| + vsli.64 d24,d21,#50 | |
| + vsli.64 d25,d21,#46 | |
| + vmov d29,d21 | |
| + vsli.64 d26,d21,#23 | |
| +#if 15<16 && defined(__ARMEL__) | |
| + vrev64.8 d15,d15 | |
| +#endif | |
| + veor d25,d24 | |
| + vbsl d29,d22,d23 @ Ch(e,f,g) | |
| + vshr.u64 d24,d17,#28 | |
| + veor d26,d25 @ Sigma1(e) | |
| + vadd.i64 d27,d29,d16 | |
| + vshr.u64 d25,d17,#34 | |
| + vsli.64 d24,d17,#36 | |
| + vadd.i64 d27,d26 | |
| + vshr.u64 d26,d17,#39 | |
| + vadd.i64 d28,d15 | |
| + vsli.64 d25,d17,#30 | |
| + veor d30,d17,d18 | |
| + vsli.64 d26,d17,#25 | |
| + veor d16,d24,d25 | |
| + vadd.i64 d27,d28 | |
| + vbsl d30,d19,d18 @ Maj(a,b,c) | |
| + veor d16,d26 @ Sigma0(a) | |
| + vadd.i64 d20,d27 | |
| + vadd.i64 d30,d27 | |
| + @ vadd.i64 d16,d30 | |
| + mov r12,#4 | |
| +.L16_79_neon: | |
| + subs r12,#1 | |
| + vshr.u64 q12,q7,#19 | |
| + vshr.u64 q13,q7,#61 | |
| + vadd.i64 d16,d30 @ h+=Maj from the past | |
| + vshr.u64 q15,q7,#6 | |
| + vsli.64 q12,q7,#45 | |
| + vext.8 q14,q0,q1,#8 @ X[i+1] | |
| + vsli.64 q13,q7,#3 | |
| + veor q15,q12 | |
| + vshr.u64 q12,q14,#1 | |
| + veor q15,q13 @ sigma1(X[i+14]) | |
| + vshr.u64 q13,q14,#8 | |
| + vadd.i64 q0,q15 | |
| + vshr.u64 q15,q14,#7 | |
| + vsli.64 q12,q14,#63 | |
| + vsli.64 q13,q14,#56 | |
| + vext.8 q14,q4,q5,#8 @ X[i+9] | |
| + veor q15,q12 | |
| + vshr.u64 d24,d20,#14 @ from NEON_00_15 | |
| + vadd.i64 q0,q14 | |
| + vshr.u64 d25,d20,#18 @ from NEON_00_15 | |
| + veor q15,q13 @ sigma0(X[i+1]) | |
| + vshr.u64 d26,d20,#41 @ from NEON_00_15 | |
| + vadd.i64 q0,q15 | |
| + vld1.64 {d28},[r3,:64]! @ K[i++] | |
| + vsli.64 d24,d20,#50 | |
| + vsli.64 d25,d20,#46 | |
| + vmov d29,d20 | |
| + vsli.64 d26,d20,#23 | |
| +#if 16<16 && defined(__ARMEL__) | |
| + vrev64.8 , | |
| +#endif | |
| + veor d25,d24 | |
| + vbsl d29,d21,d22 @ Ch(e,f,g) | |
| + vshr.u64 d24,d16,#28 | |
| + veor d26,d25 @ Sigma1(e) | |
| + vadd.i64 d27,d29,d23 | |
| + vshr.u64 d25,d16,#34 | |
| + vsli.64 d24,d16,#36 | |
| + vadd.i64 d27,d26 | |
| + vshr.u64 d26,d16,#39 | |
| + vadd.i64 d28,d0 | |
| + vsli.64 d25,d16,#30 | |
| + veor d30,d16,d17 | |
| + vsli.64 d26,d16,#25 | |
| + veor d23,d24,d25 | |
| + vadd.i64 d27,d28 | |
| + vbsl d30,d18,d17 @ Maj(a,b,c) | |
| + veor d23,d26 @ Sigma0(a) | |
| + vadd.i64 d19,d27 | |
| + vadd.i64 d30,d27 | |
| + @ vadd.i64 d23,d30 | |
| + vshr.u64 d24,d19,#14 @ 17 | |
| +#if 17<16 | |
| + vld1.64 {d1},[r1]! @ handles unaligned | |
| +#endif | |
| + vshr.u64 d25,d19,#18 | |
| +#if 17>0 | |
| + vadd.i64 d23,d30 @ h+=Maj from the past | |
| +#endif | |
| + vshr.u64 d26,d19,#41 | |
| + vld1.64 {d28},[r3,:64]! @ K[i++] | |
| + vsli.64 d24,d19,#50 | |
| + vsli.64 d25,d19,#46 | |
| + vmov d29,d19 | |
| + vsli.64 d26,d19,#23 | |
| +#if 17<16 && defined(__ARMEL__) | |
| + vrev64.8 , | |
| +#endif | |
| + veor d25,d24 | |
| + vbsl d29,d20,d21 @ Ch(e,f,g) | |
| + vshr.u64 d24,d23,#28 | |
| + veor d26,d25 @ Sigma1(e) | |
| + vadd.i64 d27,d29,d22 | |
| + vshr.u64 d25,d23,#34 | |
| + vsli.64 d24,d23,#36 | |
| + vadd.i64 d27,d26 | |
| + vshr.u64 d26,d23,#39 | |
| + vadd.i64 d28,d1 | |
| + vsli.64 d25,d23,#30 | |
| + veor d30,d23,d16 | |
| + vsli.64 d26,d23,#25 | |
| + veor d22,d24,d25 | |
| + vadd.i64 d27,d28 | |
| + vbsl d30,d17,d16 @ Maj(a,b,c) | |
| + veor d22,d26 @ Sigma0(a) | |
| + vadd.i64 d18,d27 | |
| + vadd.i64 d30,d27 | |
| + @ vadd.i64 d22,d30 | |
| + vshr.u64 q12,q0,#19 | |
| + vshr.u64 q13,q0,#61 | |
| + vadd.i64 d22,d30 @ h+=Maj from the past | |
| + vshr.u64 q15,q0,#6 | |
| + vsli.64 q12,q0,#45 | |
| + vext.8 q14,q1,q2,#8 @ X[i+1] | |
| + vsli.64 q13,q0,#3 | |
| + veor q15,q12 | |
| + vshr.u64 q12,q14,#1 | |
| + veor q15,q13 @ sigma1(X[i+14]) | |
| + vshr.u64 q13,q14,#8 | |
| + vadd.i64 q1,q15 | |
| + vshr.u64 q15,q14,#7 | |
| + vsli.64 q12,q14,#63 | |
| + vsli.64 q13,q14,#56 | |
| + vext.8 q14,q5,q6,#8 @ X[i+9] | |
| + veor q15,q12 | |
| + vshr.u64 d24,d18,#14 @ from NEON_00_15 | |
| + vadd.i64 q1,q14 | |
| + vshr.u64 d25,d18,#18 @ from NEON_00_15 | |
| + veor q15,q13 @ sigma0(X[i+1]) | |
| + vshr.u64 d26,d18,#41 @ from NEON_00_15 | |
| + vadd.i64 q1,q15 | |
| + vld1.64 {d28},[r3,:64]! @ K[i++] | |
| + vsli.64 d24,d18,#50 | |
| + vsli.64 d25,d18,#46 | |
| + vmov d29,d18 | |
| + vsli.64 d26,d18,#23 | |
| +#if 18<16 && defined(__ARMEL__) | |
| + vrev64.8 , | |
| +#endif | |
| + veor d25,d24 | |
| + vbsl d29,d19,d20 @ Ch(e,f,g) | |
| + vshr.u64 d24,d22,#28 | |
| + veor d26,d25 @ Sigma1(e) | |
| + vadd.i64 d27,d29,d21 | |
| + vshr.u64 d25,d22,#34 | |
| + vsli.64 d24,d22,#36 | |
| + vadd.i64 d27,d26 | |
| + vshr.u64 d26,d22,#39 | |
| + vadd.i64 d28,d2 | |
| + vsli.64 d25,d22,#30 | |
| + veor d30,d22,d23 | |
| + vsli.64 d26,d22,#25 | |
| + veor d21,d24,d25 | |
| + vadd.i64 d27,d28 | |
| + vbsl d30,d16,d23 @ Maj(a,b,c) | |
| + veor d21,d26 @ Sigma0(a) | |
| + vadd.i64 d17,d27 | |
| + vadd.i64 d30,d27 | |
| + @ vadd.i64 d21,d30 | |
| + vshr.u64 d24,d17,#14 @ 19 | |
| +#if 19<16 | |
| + vld1.64 {d3},[r1]! @ handles unaligned | |
| +#endif | |
| + vshr.u64 d25,d17,#18 | |
| +#if 19>0 | |
| + vadd.i64 d21,d30 @ h+=Maj from the past | |
| +#endif | |
| + vshr.u64 d26,d17,#41 | |
| + vld1.64 {d28},[r3,:64]! @ K[i++] | |
| + vsli.64 d24,d17,#50 | |
| + vsli.64 d25,d17,#46 | |
| + vmov d29,d17 | |
| + vsli.64 d26,d17,#23 | |
| +#if 19<16 && defined(__ARMEL__) | |
| + vrev64.8 , | |
| +#endif | |
| + veor d25,d24 | |
| + vbsl d29,d18,d19 @ Ch(e,f,g) | |
| + vshr.u64 d24,d21,#28 | |
| + veor d26,d25 @ Sigma1(e) | |
| + vadd.i64 d27,d29,d20 | |
| + vshr.u64 d25,d21,#34 | |
| + vsli.64 d24,d21,#36 | |
| + vadd.i64 d27,d26 | |
| + vshr.u64 d26,d21,#39 | |
| + vadd.i64 d28,d3 | |
| + vsli.64 d25,d21,#30 | |
| + veor d30,d21,d22 | |
| + vsli.64 d26,d21,#25 | |
| + veor d20,d24,d25 | |
| + vadd.i64 d27,d28 | |
| + vbsl d30,d23,d22 @ Maj(a,b,c) | |
| + veor d20,d26 @ Sigma0(a) | |
| + vadd.i64 d16,d27 | |
| + vadd.i64 d30,d27 | |
| + @ vadd.i64 d20,d30 | |
| + vshr.u64 q12,q1,#19 | |
| + vshr.u64 q13,q1,#61 | |
| + vadd.i64 d20,d30 @ h+=Maj from the past | |
| + vshr.u64 q15,q1,#6 | |
| + vsli.64 q12,q1,#45 | |
| + vext.8 q14,q2,q3,#8 @ X[i+1] | |
| + vsli.64 q13,q1,#3 | |
| + veor q15,q12 | |
| + vshr.u64 q12,q14,#1 | |
| + veor q15,q13 @ sigma1(X[i+14]) | |
| + vshr.u64 q13,q14,#8 | |
| + vadd.i64 q2,q15 | |
| + vshr.u64 q15,q14,#7 | |
| + vsli.64 q12,q14,#63 | |
| + vsli.64 q13,q14,#56 | |
| + vext.8 q14,q6,q7,#8 @ X[i+9] | |
| + veor q15,q12 | |
| + vshr.u64 d24,d16,#14 @ from NEON_00_15 | |
| + vadd.i64 q2,q14 | |
| + vshr.u64 d25,d16,#18 @ from NEON_00_15 | |
| + veor q15,q13 @ sigma0(X[i+1]) | |
| + vshr.u64 d26,d16,#41 @ from NEON_00_15 | |
| + vadd.i64 q2,q15 | |
| + vld1.64 {d28},[r3,:64]! @ K[i++] | |
| + vsli.64 d24,d16,#50 | |
| + vsli.64 d25,d16,#46 | |
| + vmov d29,d16 | |
| + vsli.64 d26,d16,#23 | |
| +#if 20<16 && defined(__ARMEL__) | |
| + vrev64.8 , | |
| +#endif | |
| + veor d25,d24 | |
| + vbsl d29,d17,d18 @ Ch(e,f,g) | |
| + vshr.u64 d24,d20,#28 | |
| + veor d26,d25 @ Sigma1(e) | |
| + vadd.i64 d27,d29,d19 | |
| + vshr.u64 d25,d20,#34 | |
| + vsli.64 d24,d20,#36 | |
| + vadd.i64 d27,d26 | |
| + vshr.u64 d26,d20,#39 | |
| + vadd.i64 d28,d4 | |
| + vsli.64 d25,d20,#30 | |
| + veor d30,d20,d21 | |
| + vsli.64 d26,d20,#25 | |
| + veor d19,d24,d25 | |
| + vadd.i64 d27,d28 | |
| + vbsl d30,d22,d21 @ Maj(a,b,c) | |
| + veor d19,d26 @ Sigma0(a) | |
| + vadd.i64 d23,d27 | |
| + vadd.i64 d30,d27 | |
| + @ vadd.i64 d19,d30 | |
| + vshr.u64 d24,d23,#14 @ 21 | |
| +#if 21<16 | |
| + vld1.64 {d5},[r1]! @ handles unaligned | |
| +#endif | |
| + vshr.u64 d25,d23,#18 | |
| +#if 21>0 | |
| + vadd.i64 d19,d30 @ h+=Maj from the past | |
| +#endif | |
| + vshr.u64 d26,d23,#41 | |
| + vld1.64 {d28},[r3,:64]! @ K[i++] | |
| + vsli.64 d24,d23,#50 | |
| + vsli.64 d25,d23,#46 | |
| + vmov d29,d23 | |
| + vsli.64 d26,d23,#23 | |
| +#if 21<16 && defined(__ARMEL__) | |
| + vrev64.8 , | |
| +#endif | |
| + veor d25,d24 | |
| + vbsl d29,d16,d17 @ Ch(e,f,g) | |
| + vshr.u64 d24,d19,#28 | |
| + veor d26,d25 @ Sigma1(e) | |
| + vadd.i64 d27,d29,d18 | |
| + vshr.u64 d25,d19,#34 | |
| + vsli.64 d24,d19,#36 | |
| + vadd.i64 d27,d26 | |
| + vshr.u64 d26,d19,#39 | |
| + vadd.i64 d28,d5 | |
| + vsli.64 d25,d19,#30 | |
| + veor d30,d19,d20 | |
| + vsli.64 d26,d19,#25 | |
| + veor d18,d24,d25 | |
| + vadd.i64 d27,d28 | |
| + vbsl d30,d21,d20 @ Maj(a,b,c) | |
| + veor d18,d26 @ Sigma0(a) | |
| + vadd.i64 d22,d27 | |
| + vadd.i64 d30,d27 | |
| + @ vadd.i64 d18,d30 | |
| + vshr.u64 q12,q2,#19 | |
| + vshr.u64 q13,q2,#61 | |
| + vadd.i64 d18,d30 @ h+=Maj from the past | |
| + vshr.u64 q15,q2,#6 | |
| + vsli.64 q12,q2,#45 | |
| + vext.8 q14,q3,q4,#8 @ X[i+1] | |
| + vsli.64 q13,q2,#3 | |
| + veor q15,q12 | |
| + vshr.u64 q12,q14,#1 | |
| + veor q15,q13 @ sigma1(X[i+14]) | |
| + vshr.u64 q13,q14,#8 | |
| + vadd.i64 q3,q15 | |
| + vshr.u64 q15,q14,#7 | |
| + vsli.64 q12,q14,#63 | |
| + vsli.64 q13,q14,#56 | |
| + vext.8 q14,q7,q0,#8 @ X[i+9] | |
| + veor q15,q12 | |
| + vshr.u64 d24,d22,#14 @ from NEON_00_15 | |
| + vadd.i64 q3,q14 | |
| + vshr.u64 d25,d22,#18 @ from NEON_00_15 | |
| + veor q15,q13 @ sigma0(X[i+1]) | |
| + vshr.u64 d26,d22,#41 @ from NEON_00_15 | |
| + vadd.i64 q3,q15 | |
| + vld1.64 {d28},[r3,:64]! @ K[i++] | |
| + vsli.64 d24,d22,#50 | |
| + vsli.64 d25,d22,#46 | |
| + vmov d29,d22 | |
| + vsli.64 d26,d22,#23 | |
| +#if 22<16 && defined(__ARMEL__) | |
| + vrev64.8 , | |
| +#endif | |
| + veor d25,d24 | |
| + vbsl d29,d23,d16 @ Ch(e,f,g) | |
| + vshr.u64 d24,d18,#28 | |
| + veor d26,d25 @ Sigma1(e) | |
| + vadd.i64 d27,d29,d17 | |
| + vshr.u64 d25,d18,#34 | |
| + vsli.64 d24,d18,#36 | |
| + vadd.i64 d27,d26 | |
| + vshr.u64 d26,d18,#39 | |
| + vadd.i64 d28,d6 | |
| + vsli.64 d25,d18,#30 | |
| + veor d30,d18,d19 | |
| + vsli.64 d26,d18,#25 | |
| + veor d17,d24,d25 | |
| + vadd.i64 d27,d28 | |
| + vbsl d30,d20,d19 @ Maj(a,b,c) | |
| + veor d17,d26 @ Sigma0(a) | |
| + vadd.i64 d21,d27 | |
| + vadd.i64 d30,d27 | |
| + @ vadd.i64 d17,d30 | |
| + vshr.u64 d24,d21,#14 @ 23 | |
| +#if 23<16 | |
| + vld1.64 {d7},[r1]! @ handles unaligned | |
| +#endif | |
| + vshr.u64 d25,d21,#18 | |
| +#if 23>0 | |
| + vadd.i64 d17,d30 @ h+=Maj from the past | |
| +#endif | |
| + vshr.u64 d26,d21,#41 | |
| + vld1.64 {d28},[r3,:64]! @ K[i++] | |
| + vsli.64 d24,d21,#50 | |
| + vsli.64 d25,d21,#46 | |
| + vmov d29,d21 | |
| + vsli.64 d26,d21,#23 | |
| +#if 23<16 && defined(__ARMEL__) | |
| + vrev64.8 , | |
| +#endif | |
| + veor d25,d24 | |
| + vbsl d29,d22,d23 @ Ch(e,f,g) | |
| + vshr.u64 d24,d17,#28 | |
| + veor d26,d25 @ Sigma1(e) | |
| + vadd.i64 d27,d29,d16 | |
| + vshr.u64 d25,d17,#34 | |
| + vsli.64 d24,d17,#36 | |
| + vadd.i64 d27,d26 | |
| + vshr.u64 d26,d17,#39 | |
| + vadd.i64 d28,d7 | |
| + vsli.64 d25,d17,#30 | |
| + veor d30,d17,d18 | |
| + vsli.64 d26,d17,#25 | |
| + veor d16,d24,d25 | |
| + vadd.i64 d27,d28 | |
| + vbsl d30,d19,d18 @ Maj(a,b,c) | |
| + veor d16,d26 @ Sigma0(a) | |
| + vadd.i64 d20,d27 | |
| + vadd.i64 d30,d27 | |
| + @ vadd.i64 d16,d30 | |
| + vshr.u64 q12,q3,#19 | |
| + vshr.u64 q13,q3,#61 | |
| + vadd.i64 d16,d30 @ h+=Maj from the past | |
| + vshr.u64 q15,q3,#6 | |
| + vsli.64 q12,q3,#45 | |
| + vext.8 q14,q4,q5,#8 @ X[i+1] | |
| + vsli.64 q13,q3,#3 | |
| + veor q15,q12 | |
| + vshr.u64 q12,q14,#1 | |
| + veor q15,q13 @ sigma1(X[i+14]) | |
| + vshr.u64 q13,q14,#8 | |
| + vadd.i64 q4,q15 | |
| + vshr.u64 q15,q14,#7 | |
| + vsli.64 q12,q14,#63 | |
| + vsli.64 q13,q14,#56 | |
| + vext.8 q14,q0,q1,#8 @ X[i+9] | |
| + veor q15,q12 | |
| + vshr.u64 d24,d20,#14 @ from NEON_00_15 | |
| + vadd.i64 q4,q14 | |
| + vshr.u64 d25,d20,#18 @ from NEON_00_15 | |
| + veor q15,q13 @ sigma0(X[i+1]) | |
| + vshr.u64 d26,d20,#41 @ from NEON_00_15 | |
| + vadd.i64 q4,q15 | |
| + vld1.64 {d28},[r3,:64]! @ K[i++] | |
| + vsli.64 d24,d20,#50 | |
| + vsli.64 d25,d20,#46 | |
| + vmov d29,d20 | |
| + vsli.64 d26,d20,#23 | |
| +#if 24<16 && defined(__ARMEL__) | |
| + vrev64.8 , | |
| +#endif | |
| + veor d25,d24 | |
| + vbsl d29,d21,d22 @ Ch(e,f,g) | |
| + vshr.u64 d24,d16,#28 | |
| + veor d26,d25 @ Sigma1(e) | |
| + vadd.i64 d27,d29,d23 | |
| + vshr.u64 d25,d16,#34 | |
| + vsli.64 d24,d16,#36 | |
| + vadd.i64 d27,d26 | |
| + vshr.u64 d26,d16,#39 | |
| + vadd.i64 d28,d8 | |
| + vsli.64 d25,d16,#30 | |
| + veor d30,d16,d17 | |
| + vsli.64 d26,d16,#25 | |
| + veor d23,d24,d25 | |
| + vadd.i64 d27,d28 | |
| + vbsl d30,d18,d17 @ Maj(a,b,c) | |
| + veor d23,d26 @ Sigma0(a) | |
| + vadd.i64 d19,d27 | |
| + vadd.i64 d30,d27 | |
| + @ vadd.i64 d23,d30 | |
| + vshr.u64 d24,d19,#14 @ 25 | |
| +#if 25<16 | |
| + vld1.64 {d9},[r1]! @ handles unaligned | |
| +#endif | |
| + vshr.u64 d25,d19,#18 | |
| +#if 25>0 | |
| + vadd.i64 d23,d30 @ h+=Maj from the past | |
| +#endif | |
| + vshr.u64 d26,d19,#41 | |
| + vld1.64 {d28},[r3,:64]! @ K[i++] | |
| + vsli.64 d24,d19,#50 | |
| + vsli.64 d25,d19,#46 | |
| + vmov d29,d19 | |
| + vsli.64 d26,d19,#23 | |
| +#if 25<16 && defined(__ARMEL__) | |
| + vrev64.8 , | |
| +#endif | |
| + veor d25,d24 | |
| + vbsl d29,d20,d21 @ Ch(e,f,g) | |
| + vshr.u64 d24,d23,#28 | |
| + veor d26,d25 @ Sigma1(e) | |
| + vadd.i64 d27,d29,d22 | |
| + vshr.u64 d25,d23,#34 | |
| + vsli.64 d24,d23,#36 | |
| + vadd.i64 d27,d26 | |
| + vshr.u64 d26,d23,#39 | |
| + vadd.i64 d28,d9 | |
| + vsli.64 d25,d23,#30 | |
| + veor d30,d23,d16 | |
| + vsli.64 d26,d23,#25 | |
| + veor d22,d24,d25 | |
| + vadd.i64 d27,d28 | |
| + vbsl d30,d17,d16 @ Maj(a,b,c) | |
| + veor d22,d26 @ Sigma0(a) | |
| + vadd.i64 d18,d27 | |
| + vadd.i64 d30,d27 | |
| + @ vadd.i64 d22,d30 | |
| + vshr.u64 q12,q4,#19 | |
| + vshr.u64 q13,q4,#61 | |
| + vadd.i64 d22,d30 @ h+=Maj from the past | |
| + vshr.u64 q15,q4,#6 | |
| + vsli.64 q12,q4,#45 | |
| + vext.8 q14,q5,q6,#8 @ X[i+1] | |
| + vsli.64 q13,q4,#3 | |
| + veor q15,q12 | |
| + vshr.u64 q12,q14,#1 | |
| + veor q15,q13 @ sigma1(X[i+14]) | |
| + vshr.u64 q13,q14,#8 | |
| + vadd.i64 q5,q15 | |
| + vshr.u64 q15,q14,#7 | |
| + vsli.64 q12,q14,#63 | |
| + vsli.64 q13,q14,#56 | |
| + vext.8 q14,q1,q2,#8 @ X[i+9] | |
| + veor q15,q12 | |
| + vshr.u64 d24,d18,#14 @ from NEON_00_15 | |
| + vadd.i64 q5,q14 | |
| + vshr.u64 d25,d18,#18 @ from NEON_00_15 | |
| + veor q15,q13 @ sigma0(X[i+1]) | |
| + vshr.u64 d26,d18,#41 @ from NEON_00_15 | |
| + vadd.i64 q5,q15 | |
| + vld1.64 {d28},[r3,:64]! @ K[i++] | |
| + vsli.64 d24,d18,#50 | |
| + vsli.64 d25,d18,#46 | |
| + vmov d29,d18 | |
| + vsli.64 d26,d18,#23 | |
| +#if 26<16 && defined(__ARMEL__) | |
| + vrev64.8 , | |
| +#endif | |
| + veor d25,d24 | |
| + vbsl d29,d19,d20 @ Ch(e,f,g) | |
| + vshr.u64 d24,d22,#28 | |
| + veor d26,d25 @ Sigma1(e) | |
| + vadd.i64 d27,d29,d21 | |
| + vshr.u64 d25,d22,#34 | |
| + vsli.64 d24,d22,#36 | |
| + vadd.i64 d27,d26 | |
| + vshr.u64 d26,d22,#39 | |
| + vadd.i64 d28,d10 | |
| + vsli.64 d25,d22,#30 | |
| + veor d30,d22,d23 | |
| + vsli.64 d26,d22,#25 | |
| + veor d21,d24,d25 | |
| + vadd.i64 d27,d28 | |
| + vbsl d30,d16,d23 @ Maj(a,b,c) | |
| + veor d21,d26 @ Sigma0(a) | |
| + vadd.i64 d17,d27 | |
| + vadd.i64 d30,d27 | |
| + @ vadd.i64 d21,d30 | |
| + vshr.u64 d24,d17,#14 @ 27 | |
| +#if 27<16 | |
| + vld1.64 {d11},[r1]! @ handles unaligned | |
| +#endif | |
| + vshr.u64 d25,d17,#18 | |
| +#if 27>0 | |
| + vadd.i64 d21,d30 @ h+=Maj from the past | |
| +#endif | |
| + vshr.u64 d26,d17,#41 | |
| + vld1.64 {d28},[r3,:64]! @ K[i++] | |
| + vsli.64 d24,d17,#50 | |
| + vsli.64 d25,d17,#46 | |
| + vmov d29,d17 | |
| + vsli.64 d26,d17,#23 | |
| +#if 27<16 && defined(__ARMEL__) | |
| + vrev64.8 , | |
| +#endif | |
| + veor d25,d24 | |
| + vbsl d29,d18,d19 @ Ch(e,f,g) | |
| + vshr.u64 d24,d21,#28 | |
| + veor d26,d25 @ Sigma1(e) | |
| + vadd.i64 d27,d29,d20 | |
| + vshr.u64 d25,d21,#34 | |
| + vsli.64 d24,d21,#36 | |
| + vadd.i64 d27,d26 | |
| + vshr.u64 d26,d21,#39 | |
| + vadd.i64 d28,d11 | |
| + vsli.64 d25,d21,#30 | |
| + veor d30,d21,d22 | |
| + vsli.64 d26,d21,#25 | |
| + veor d20,d24,d25 | |
| + vadd.i64 d27,d28 | |
| + vbsl d30,d23,d22 @ Maj(a,b,c) | |
| + veor d20,d26 @ Sigma0(a) | |
| + vadd.i64 d16,d27 | |
| + vadd.i64 d30,d27 | |
| + @ vadd.i64 d20,d30 | |
| + vshr.u64 q12,q5,#19 | |
| + vshr.u64 q13,q5,#61 | |
| + vadd.i64 d20,d30 @ h+=Maj from the past | |
| + vshr.u64 q15,q5,#6 | |
| + vsli.64 q12,q5,#45 | |
| + vext.8 q14,q6,q7,#8 @ X[i+1] | |
| + vsli.64 q13,q5,#3 | |
| + veor q15,q12 | |
| + vshr.u64 q12,q14,#1 | |
| + veor q15,q13 @ sigma1(X[i+14]) | |
| + vshr.u64 q13,q14,#8 | |
| + vadd.i64 q6,q15 | |
| + vshr.u64 q15,q14,#7 | |
| + vsli.64 q12,q14,#63 | |
| + vsli.64 q13,q14,#56 | |
| + vext.8 q14,q2,q3,#8 @ X[i+9] | |
| + veor q15,q12 | |
| + vshr.u64 d24,d16,#14 @ from NEON_00_15 | |
| + vadd.i64 q6,q14 | |
| + vshr.u64 d25,d16,#18 @ from NEON_00_15 | |
| + veor q15,q13 @ sigma0(X[i+1]) | |
| + vshr.u64 d26,d16,#41 @ from NEON_00_15 | |
| + vadd.i64 q6,q15 | |
| + vld1.64 {d28},[r3,:64]! @ K[i++] | |
| + vsli.64 d24,d16,#50 | |
| + vsli.64 d25,d16,#46 | |
| + vmov d29,d16 | |
| + vsli.64 d26,d16,#23 | |
| +#if 28<16 && defined(__ARMEL__) | |
| + vrev64.8 , | |
| +#endif | |
| + veor d25,d24 | |
| + vbsl d29,d17,d18 @ Ch(e,f,g) | |
| + vshr.u64 d24,d20,#28 | |
| + veor d26,d25 @ Sigma1(e) | |
| + vadd.i64 d27,d29,d19 | |
| + vshr.u64 d25,d20,#34 | |
| + vsli.64 d24,d20,#36 | |
| + vadd.i64 d27,d26 | |
| + vshr.u64 d26,d20,#39 | |
| + vadd.i64 d28,d12 | |
| + vsli.64 d25,d20,#30 | |
| + veor d30,d20,d21 | |
| + vsli.64 d26,d20,#25 | |
| + veor d19,d24,d25 | |
| + vadd.i64 d27,d28 | |
| + vbsl d30,d22,d21 @ Maj(a,b,c) | |
| + veor d19,d26 @ Sigma0(a) | |
| + vadd.i64 d23,d27 | |
| + vadd.i64 d30,d27 | |
| + @ vadd.i64 d19,d30 | |
| + vshr.u64 d24,d23,#14 @ 29 | |
| +#if 29<16 | |
| + vld1.64 {d13},[r1]! @ handles unaligned | |
| +#endif | |
| + vshr.u64 d25,d23,#18 | |
| +#if 29>0 | |
| + vadd.i64 d19,d30 @ h+=Maj from the past | |
| +#endif | |
| + vshr.u64 d26,d23,#41 | |
| + vld1.64 {d28},[r3,:64]! @ K[i++] | |
| + vsli.64 d24,d23,#50 | |
| + vsli.64 d25,d23,#46 | |
| + vmov d29,d23 | |
| + vsli.64 d26,d23,#23 | |
| +#if 29<16 && defined(__ARMEL__) | |
| + vrev64.8 , | |
| +#endif | |
| + veor d25,d24 | |
| + vbsl d29,d16,d17 @ Ch(e,f,g) | |
| + vshr.u64 d24,d19,#28 | |
| + veor d26,d25 @ Sigma1(e) | |
| + vadd.i64 d27,d29,d18 | |
| + vshr.u64 d25,d19,#34 | |
| + vsli.64 d24,d19,#36 | |
| + vadd.i64 d27,d26 | |
| + vshr.u64 d26,d19,#39 | |
| + vadd.i64 d28,d13 | |
| + vsli.64 d25,d19,#30 | |
| + veor d30,d19,d20 | |
| + vsli.64 d26,d19,#25 | |
| + veor d18,d24,d25 | |
| + vadd.i64 d27,d28 | |
| + vbsl d30,d21,d20 @ Maj(a,b,c) | |
| + veor d18,d26 @ Sigma0(a) | |
| + vadd.i64 d22,d27 | |
| + vadd.i64 d30,d27 | |
| + @ vadd.i64 d18,d30 | |
| + vshr.u64 q12,q6,#19 | |
| + vshr.u64 q13,q6,#61 | |
| + vadd.i64 d18,d30 @ h+=Maj from the past | |
| + vshr.u64 q15,q6,#6 | |
| + vsli.64 q12,q6,#45 | |
| + vext.8 q14,q7,q0,#8 @ X[i+1] | |
| + vsli.64 q13,q6,#3 | |
| + veor q15,q12 | |
| + vshr.u64 q12,q14,#1 | |
| + veor q15,q13 @ sigma1(X[i+14]) | |
| + vshr.u64 q13,q14,#8 | |
| + vadd.i64 q7,q15 | |
| + vshr.u64 q15,q14,#7 | |
| + vsli.64 q12,q14,#63 | |
| + vsli.64 q13,q14,#56 | |
| + vext.8 q14,q3,q4,#8 @ X[i+9] | |
| + veor q15,q12 | |
| + vshr.u64 d24,d22,#14 @ from NEON_00_15 | |
| + vadd.i64 q7,q14 | |
| + vshr.u64 d25,d22,#18 @ from NEON_00_15 | |
| + veor q15,q13 @ sigma0(X[i+1]) | |
| + vshr.u64 d26,d22,#41 @ from NEON_00_15 | |
| + vadd.i64 q7,q15 | |
| + vld1.64 {d28},[r3,:64]! @ K[i++] | |
| + vsli.64 d24,d22,#50 | |
| + vsli.64 d25,d22,#46 | |
| + vmov d29,d22 | |
| + vsli.64 d26,d22,#23 | |
| +#if 30<16 && defined(__ARMEL__) | |
| + vrev64.8 , | |
| +#endif | |
| + veor d25,d24 | |
| + vbsl d29,d23,d16 @ Ch(e,f,g) | |
| + vshr.u64 d24,d18,#28 | |
| + veor d26,d25 @ Sigma1(e) | |
| + vadd.i64 d27,d29,d17 | |
| + vshr.u64 d25,d18,#34 | |
| + vsli.64 d24,d18,#36 | |
| + vadd.i64 d27,d26 | |
| + vshr.u64 d26,d18,#39 | |
| + vadd.i64 d28,d14 | |
| + vsli.64 d25,d18,#30 | |
| + veor d30,d18,d19 | |
| + vsli.64 d26,d18,#25 | |
| + veor d17,d24,d25 | |
| + vadd.i64 d27,d28 | |
| + vbsl d30,d20,d19 @ Maj(a,b,c) | |
| + veor d17,d26 @ Sigma0(a) | |
| + vadd.i64 d21,d27 | |
| + vadd.i64 d30,d27 | |
| + @ vadd.i64 d17,d30 | |
| + vshr.u64 d24,d21,#14 @ 31 | |
| +#if 31<16 | |
| + vld1.64 {d15},[r1]! @ handles unaligned | |
| +#endif | |
| + vshr.u64 d25,d21,#18 | |
| +#if 31>0 | |
| + vadd.i64 d17,d30 @ h+=Maj from the past | |
| +#endif | |
| + vshr.u64 d26,d21,#41 | |
| + vld1.64 {d28},[r3,:64]! @ K[i++] | |
| + vsli.64 d24,d21,#50 | |
| + vsli.64 d25,d21,#46 | |
| + vmov d29,d21 | |
| + vsli.64 d26,d21,#23 | |
| +#if 31<16 && defined(__ARMEL__) | |
| + vrev64.8 , | |
| +#endif | |
| + veor d25,d24 | |
| + vbsl d29,d22,d23 @ Ch(e,f,g) | |
| + vshr.u64 d24,d17,#28 | |
| + veor d26,d25 @ Sigma1(e) | |
| + vadd.i64 d27,d29,d16 | |
| + vshr.u64 d25,d17,#34 | |
| + vsli.64 d24,d17,#36 | |
| + vadd.i64 d27,d26 | |
| + vshr.u64 d26,d17,#39 | |
| + vadd.i64 d28,d15 | |
| + vsli.64 d25,d17,#30 | |
| + veor d30,d17,d18 | |
| + vsli.64 d26,d17,#25 | |
| + veor d16,d24,d25 | |
| + vadd.i64 d27,d28 | |
| + vbsl d30,d19,d18 @ Maj(a,b,c) | |
| + veor d16,d26 @ Sigma0(a) | |
| + vadd.i64 d20,d27 | |
| + vadd.i64 d30,d27 | |
| + @ vadd.i64 d16,d30 | |
| + bne .L16_79_neon | |
| + | |
| + vadd.i64 d16,d30 @ h+=Maj from the past | |
| + vldmia r0,{d24-d31} @ load context to temp | |
| + vadd.i64 q8,q12 @ vectorized accumulate | |
| + vadd.i64 q9,q13 | |
| + vadd.i64 q10,q14 | |
| + vadd.i64 q11,q15 | |
| + vstmia r0,{d16-d23} @ save context | |
| + teq r1,r2 | |
| + sub r3,#640 @ rewind K512 | |
| + bne .Loop_neon | |
| + | |
| + VFP_ABI_POP | |
| + bx lr @ .word 0xe12fff1e | |
| +.size sha512_block_data_order_neon,.-sha512_block_data_order_neon | |
| +#endif | |
| +.asciz "SHA512 block transform for ARMv4/NEON, CRYPTOGAMS by <appro@openssl.org>" | |
| +.align 2 | |
| +#if __ARM_MAX_ARCH__>=7 && !defined(__KERNEL__) | |
| +.comm OPENSSL_armcap_P,4,4 | |
| +#endif | |
| diff -x .git -Naur linux-4.4.111/arch/arm/include/asm/msi.h linux-4.4.111-alpine/arch/arm/include/asm/msi.h | |
| --- linux-4.4.111/arch/arm/include/asm/msi.h 1969-12-31 19:00:00.000000000 -0500 | |
| +++ linux-4.4.111-alpine/arch/arm/include/asm/msi.h 2018-02-14 21:04:17.000000000 -0500 | |
| @@ -0,0 +1,2 @@ | |
| +#include <asm-generic/msi.h> | |
| + | |
| diff -x .git -Naur linux-4.4.111/arch/arm/include/uapi/asm/setup.h linux-4.4.111-alpine/arch/arm/include/uapi/asm/setup.h | |
| --- linux-4.4.111/arch/arm/include/uapi/asm/setup.h 2018-02-20 12:32:32.868050867 -0500 | |
| +++ linux-4.4.111-alpine/arch/arm/include/uapi/asm/setup.h 2018-02-14 21:04:17.000000000 -0500 | |
| @@ -143,6 +143,19 @@ | |
| __u32 fmemclk; | |
| }; | |
| +/* Marvell uboot parameters */ | |
| +#define ATAG_MV_UBOOT 0x41000403 | |
| + | |
| +struct tag_mv_uboot { | |
| + __u32 uboot_version; | |
| + __u32 tclk; | |
| + __u32 sysclk; | |
| + __u32 isusbhost; | |
| + __u8 macaddr[4][6]; | |
| + __u16 mtu[4]; | |
| + __u32 nand_ecc; | |
| +}; | |
| + | |
| struct tag { | |
| struct tag_header hdr; | |
| union { | |
| @@ -165,6 +178,11 @@ | |
| * DC21285 specific | |
| */ | |
| struct tag_memclk memclk; | |
| + | |
| + /* | |
| + * Marvell specific | |
| + */ | |
| + struct tag_mv_uboot mv_uboot; | |
| } u; | |
| }; | |
| diff -x .git -Naur linux-4.4.111/arch/arm/kernel/bios32.c linux-4.4.111-alpine/arch/arm/kernel/bios32.c | |
| --- linux-4.4.111/arch/arm/kernel/bios32.c 2018-02-20 12:32:32.878050906 -0500 | |
| +++ linux-4.4.111-alpine/arch/arm/kernel/bios32.c 2018-02-14 21:04:17.000000000 -0500 | |
| @@ -557,6 +557,7 @@ | |
| return str; | |
| } | |
| +#ifndef CONFIG_PCI_EXTERNAL_ALPINE | |
| /* | |
| * From arch/i386/kernel/pci-i386.c: | |
| * | |
| @@ -592,6 +593,17 @@ | |
| return start; | |
| } | |
| +#else | |
| +/** | |
| + * Since External PCIe Alpine driver does not use arm structures (pcie_sys_data | |
| + * specifically), we can't use the default "pcibios_align_resource" resources | |
| + */ | |
| +resource_size_t pcibios_align_resource(void *data, const struct resource *res, | |
| + resource_size_t size, resource_size_t align) | |
| +{ | |
| + return res->start; | |
| +} | |
| +#endif | |
| /** | |
| * pcibios_enable_device - Enable I/O and memory. | |
| diff -x .git -Naur linux-4.4.111/arch/arm/mach-alpine/Kconfig linux-4.4.111-alpine/arch/arm/mach-alpine/Kconfig | |
| --- linux-4.4.111/arch/arm/mach-alpine/Kconfig 2018-02-20 12:32:32.918051063 -0500 | |
| +++ linux-4.4.111-alpine/arch/arm/mach-alpine/Kconfig 2018-02-14 21:04:17.000000000 -0500 | |
| @@ -3,10 +3,15 @@ | |
| select ARM_AMBA | |
| select ARM_GIC | |
| select GENERIC_IRQ_CHIP | |
| + select GENERIC_MSI_IRQ_DOMAIN | |
| select HAVE_ARM_ARCH_TIMER | |
| select HAVE_SMP | |
| + select IRQ_DOMAIN_HIERARCHY | |
| select MFD_SYSCON | |
| select PCI | |
| - select PCI_HOST_GENERIC | |
| + select PCI_DOMAINS | |
| + select PCI_MSI | |
| + select PCI_MSI_IRQ_DOMAIN | |
| + select POWER_RESET_ALPINE | |
| help | |
| This enables support for the Annapurna Labs Alpine V1 boards. | |
| diff -x .git -Naur linux-4.4.111/arch/arm/mm/mm.h linux-4.4.111-alpine/arch/arm/mm/mm.h | |
| --- linux-4.4.111/arch/arm/mm/mm.h 2018-02-20 12:32:33.508053371 -0500 | |
| +++ linux-4.4.111-alpine/arch/arm/mm/mm.h 2018-02-14 21:04:17.000000000 -0500 | |
| @@ -86,8 +86,8 @@ | |
| extern phys_addr_t arm_dma_limit; | |
| extern unsigned long arm_dma_pfn_limit; | |
| #else | |
| -#define arm_dma_limit ((phys_addr_t)~0) | |
| -#define arm_dma_pfn_limit (~0ul >> PAGE_SHIFT) | |
| +#define arm_dma_limit (PHYS_MASK) | |
| +#define arm_dma_pfn_limit (PHYS_MASK >> PAGE_SHIFT) | |
| #endif | |
| extern phys_addr_t arm_lowmem_limit; | |
| diff -x .git -Naur linux-4.4.111/arch/arm64/configs/alpine_defconfig linux-4.4.111-alpine/arch/arm64/configs/alpine_defconfig | |
| --- linux-4.4.111/arch/arm64/configs/alpine_defconfig 1969-12-31 19:00:00.000000000 -0500 | |
| +++ linux-4.4.111-alpine/arch/arm64/configs/alpine_defconfig 2018-02-14 21:04:17.000000000 -0500 | |
| @@ -0,0 +1,141 @@ | |
| +# CONFIG_LOCALVERSION_AUTO is not set | |
| +CONFIG_SYSVIPC=y | |
| +CONFIG_FHANDLE=y | |
| +CONFIG_NO_HZ=y | |
| +CONFIG_HIGH_RES_TIMERS=y | |
| +CONFIG_IKCONFIG=y | |
| +CONFIG_IKCONFIG_PROC=y | |
| +CONFIG_CGROUPS=y | |
| +CONFIG_USER_NS=y | |
| +CONFIG_BLK_DEV_INITRD=y | |
| +CONFIG_SLAB=y | |
| +CONFIG_PROFILING=y | |
| +CONFIG_MODULES=y | |
| +CONFIG_MODULE_UNLOAD=y | |
| +CONFIG_BLK_DEV_INTEGRITY=y | |
| +CONFIG_PARTITION_ADVANCED=y | |
| +# CONFIG_EFI_PARTITION is not set | |
| +CONFIG_ARCH_VEXPRESS=y | |
| +CONFIG_ARCH_ALPINE=y | |
| +CONFIG_PCI_IOV=y | |
| +CONFIG_PCI_INTERNAL_ALPINE=y | |
| +CONFIG_PCI_EXTERNAL_ALPINE=y | |
| +CONFIG_SMP=y | |
| +CONFIG_NR_CPUS=4 | |
| +CONFIG_TRANSPARENT_HUGEPAGE=y | |
| +# CONFIG_SUSPEND is not set | |
| +CONFIG_NET=y | |
| +CONFIG_PACKET=y | |
| +CONFIG_UNIX=y | |
| +CONFIG_XFRM_USER=y | |
| +CONFIG_NET_KEY=y | |
| +CONFIG_INET=y | |
| +CONFIG_IP_MULTICAST=y | |
| +CONFIG_IP_PNP=y | |
| +CONFIG_IP_PNP_BOOTP=y | |
| +CONFIG_INET_AH=y | |
| +CONFIG_INET_ESP=y | |
| +# CONFIG_INET_DIAG is not set | |
| +# CONFIG_IPV6 is not set | |
| +CONFIG_DEVTMPFS=y | |
| +CONFIG_DEVTMPFS_MOUNT=y | |
| +CONFIG_MTD=y | |
| +CONFIG_MTD_NAND=y | |
| +CONFIG_MTD_NAND_AL=y | |
| +CONFIG_MTD_UBI=y | |
| +CONFIG_BLK_DEV_NVME=y | |
| +CONFIG_RAID_ATTRS=y | |
| +CONFIG_BLK_DEV_SD=y | |
| +CONFIG_SCSI_SAS_ATTRS=y | |
| +CONFIG_SCSI_MPT2SAS=m | |
| +CONFIG_ATA=y | |
| +# CONFIG_SATA_PMP is not set | |
| +CONFIG_SATA_AHCI=y | |
| +CONFIG_SATA_AHCI_PLATFORM=y | |
| +CONFIG_SATA_SIL24=m | |
| +CONFIG_MD=y | |
| +CONFIG_BLK_DEV_MD=y | |
| +CONFIG_MD_RAID0=y | |
| +CONFIG_MD_RAID1=y | |
| +CONFIG_MD_RAID10=y | |
| +CONFIG_MD_RAID456=y | |
| +CONFIG_BLK_DEV_DM=y | |
| +CONFIG_DM_CRYPT=y | |
| +CONFIG_TARGET_CORE=m | |
| +CONFIG_ISCSI_TARGET=m | |
| +CONFIG_NETDEVICES=y | |
| +CONFIG_BONDING=m | |
| +CONFIG_NET_TEAM=m | |
| +CONFIG_NET_TEAM_MODE_BROADCAST=m | |
| +CONFIG_NET_TEAM_MODE_ROUNDROBIN=m | |
| +CONFIG_NET_TEAM_MODE_RANDOM=m | |
| +CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m | |
| +CONFIG_NET_TEAM_MODE_LOADBALANCE=m | |
| +CONFIG_NET_AL_ETH=y | |
| +CONFIG_E100=m | |
| +CONFIG_E1000=m | |
| +CONFIG_E1000E=m | |
| +CONFIG_IGB=m | |
| +CONFIG_IGBVF=m | |
| +CONFIG_IXGBE=m | |
| +CONFIG_IXGBEVF=m | |
| +CONFIG_AT803X_PHY=y | |
| +CONFIG_INPUT_EVDEV=y | |
| +# CONFIG_SERIO_SERPORT is not set | |
| +CONFIG_SERIO_AMBAKMI=y | |
| +CONFIG_LEGACY_PTY_COUNT=16 | |
| +CONFIG_SERIAL_8250=y | |
| +CONFIG_SERIAL_8250_CONSOLE=y | |
| +CONFIG_SERIAL_8250_EXTENDED=y | |
| +CONFIG_SERIAL_8250_MANY_PORTS=y | |
| +CONFIG_SERIAL_8250_SHARE_IRQ=y | |
| +CONFIG_SERIAL_8250_RSA=y | |
| +CONFIG_SERIAL_8250_DW=y | |
| +CONFIG_SERIAL_OF_PLATFORM=y | |
| +CONFIG_HW_RANDOM=y | |
| +CONFIG_I2C=y | |
| +CONFIG_I2C_CHARDEV=y | |
| +CONFIG_I2C_MUX=y | |
| +CONFIG_I2C_MUX_PCA954x=y | |
| +CONFIG_I2C_DESIGNWARE_PLATFORM=y | |
| +# CONFIG_HWMON is not set | |
| +# CONFIG_HID is not set | |
| +# CONFIG_USB_SUPPORT is not set | |
| +CONFIG_DMADEVICES=y | |
| +CONFIG_DMADEVICES_DEBUG=y | |
| +CONFIG_DMADEVICES_VDEBUG=y | |
| +CONFIG_ASYNC_TX_DMA=y | |
| +CONFIG_DMATEST=y | |
| +CONFIG_AL_DMA=y | |
| +CONFIG_AL_DMA_STATS=y | |
| +CONFIG_AL_DMA_PCI_IOV=y | |
| +CONFIG_UIO=y | |
| +# CONFIG_IOMMU_SUPPORT is not set | |
| +CONFIG_EXT2_FS=y | |
| +CONFIG_EXT3_FS=y | |
| +CONFIG_EXT4_FS=y | |
| +CONFIG_VFAT_FS=y | |
| +CONFIG_TMPFS=y | |
| +CONFIG_TMPFS_POSIX_ACL=y | |
| +CONFIG_HUGETLBFS=y | |
| +CONFIG_CONFIGFS_FS=y | |
| +CONFIG_ECRYPT_FS=y | |
| +CONFIG_UBIFS_FS=y | |
| +# CONFIG_NETWORK_FILESYSTEMS is not set | |
| +CONFIG_NLS_CODEPAGE_850=y | |
| +CONFIG_NLS_ISO8859_1=y | |
| +CONFIG_PRINTK_TIME=y | |
| +CONFIG_MESSAGE_LOGLEVEL_DEFAULT=7 | |
| +CONFIG_DEBUG_INFO=y | |
| +CONFIG_MAGIC_SYSRQ=y | |
| +CONFIG_DEBUG_KERNEL=y | |
| +CONFIG_ENABLE_DEFAULT_TRACERS=y | |
| +CONFIG_KEYS=y | |
| +CONFIG_ENCRYPTED_KEYS=y | |
| +# CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set | |
| +CONFIG_CRYPTO_CMAC=y | |
| +CONFIG_CRYPTO_MD4=y | |
| +CONFIG_CRYPTO_ARC4=y | |
| +CONFIG_CRYPTO_DEV_AL_CRYPTO=y | |
| +CONFIG_CRYPTO_DEV_AL_CRYPTO_STATS=y | |
| +CONFIG_LIBCRC32C=y | |
| diff -x .git -Naur linux-4.4.111/arch/arm64/include/asm/io.h linux-4.4.111-alpine/arch/arm64/include/asm/io.h | |
| --- linux-4.4.111/arch/arm64/include/asm/io.h 2018-02-20 12:32:33.598053723 -0500 | |
| +++ linux-4.4.111-alpine/arch/arm64/include/asm/io.h 2018-02-14 21:04:17.000000000 -0500 | |
| @@ -166,6 +166,7 @@ | |
| extern void __iomem *__ioremap(phys_addr_t phys_addr, size_t size, pgprot_t prot); | |
| extern void __iounmap(volatile void __iomem *addr); | |
| extern void __iomem *ioremap_cache(phys_addr_t phys_addr, size_t size); | |
| +extern int pci_ioremap_io(unsigned int offset, phys_addr_t phys_addr); | |
| #define ioremap(addr, size) __ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRE)) | |
| #define ioremap_nocache(addr, size) __ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRE)) | |
| diff -x .git -Naur linux-4.4.111/arch/arm64/include/asm/msi.h linux-4.4.111-alpine/arch/arm64/include/asm/msi.h | |
| --- linux-4.4.111/arch/arm64/include/asm/msi.h 1969-12-31 19:00:00.000000000 -0500 | |
| +++ linux-4.4.111-alpine/arch/arm64/include/asm/msi.h 2018-02-14 21:04:17.000000000 -0500 | |
| @@ -0,0 +1,2 @@ | |
| +#include <asm-generic/msi.h> | |
| + | |
| diff -x .git -Naur linux-4.4.111/arch/arm64/Kconfig.platforms linux-4.4.111-alpine/arch/arm64/Kconfig.platforms | |
| --- linux-4.4.111/arch/arm64/Kconfig.platforms 2018-02-20 12:32:33.548053528 -0500 | |
| +++ linux-4.4.111-alpine/arch/arm64/Kconfig.platforms 2018-02-14 21:04:17.000000000 -0500 | |
| @@ -1,5 +1,15 @@ | |
| menu "Platform selection" | |
| +config ARCH_ALPINE | |
| + bool "Annapurna-Labs Alpine Family" | |
| + select PCI | |
| + select PCI_MSI | |
| + select PCI_DOMAINS | |
| + select GENERIC_IRQ_CHIP | |
| + select POWER_RESET_ALPINE | |
| + help | |
| + This enables support for Alpine SOC Family | |
| + | |
| config ARCH_BCM_IPROC | |
| bool "Broadcom iProc SoC Family" | |
| help | |
| diff -x .git -Naur linux-4.4.111/arch/arm64/mm/ioremap.c linux-4.4.111-alpine/arch/arm64/mm/ioremap.c | |
| --- linux-4.4.111/arch/arm64/mm/ioremap.c 2018-02-20 12:32:33.658053958 -0500 | |
| +++ linux-4.4.111-alpine/arch/arm64/mm/ioremap.c 2018-02-14 21:04:17.000000000 -0500 | |
| @@ -104,6 +104,18 @@ | |
| } | |
| EXPORT_SYMBOL(ioremap_cache); | |
| +#ifdef CONFIG_PCI | |
| +int pci_ioremap_io(unsigned int offset, phys_addr_t phys_addr) | |
| +{ | |
| + BUG_ON(offset + SZ_64K > IO_SPACE_LIMIT); | |
| + return ioremap_page_range(PCI_IOBASE + offset, | |
| + PCI_IOBASE + offset + SZ_64K, | |
| + phys_addr, | |
| + __pgprot(PROT_DEVICE_nGnRE)); | |
| +} | |
| +EXPORT_SYMBOL_GPL(pci_ioremap_io); | |
| +#endif | |
| + | |
| /* | |
| * Must be called after early_fixmap_init | |
| */ | |
| diff -x .git -Naur linux-4.4.111/arch/x86/include/asm/pgtable.h linux-4.4.111-alpine/arch/x86/include/asm/pgtable.h | |
| --- linux-4.4.111/arch/x86/include/asm/pgtable.h 2018-02-20 12:32:39.558077045 -0500 | |
| +++ linux-4.4.111-alpine/arch/x86/include/asm/pgtable.h 2018-02-14 21:04:17.000000000 -0500 | |
| @@ -6,6 +6,7 @@ | |
| #include <asm/pgtable_types.h> | |
| +#define PHYS_MASK 0xffffffffull | |
| /* | |
| * Macro to mark a page protection value as UC- | |
| */ | |
| diff -x .git -Naur linux-4.4.111/arch/x86/Kconfig linux-4.4.111-alpine/arch/x86/Kconfig | |
| --- linux-4.4.111/arch/x86/Kconfig 2018-02-20 12:32:39.408076458 -0500 | |
| +++ linux-4.4.111-alpine/arch/x86/Kconfig 2018-02-14 21:04:17.000000000 -0500 | |
| @@ -74,7 +74,7 @@ | |
| select GENERIC_TIME_VSYSCALL | |
| select HAVE_ACPI_APEI if ACPI | |
| select HAVE_ACPI_APEI_NMI if ACPI | |
| - select HAVE_ALIGNED_STRUCT_PAGE if SLUB | |
| + select HAVE_ALIGNED_STRUCT_PAGE if SLUB && !LFS_ON_32CPU | |
| select HAVE_AOUT if X86_32 | |
| select HAVE_ARCH_AUDITSYSCALL | |
| select HAVE_ARCH_HUGE_VMAP if X86_64 || X86_PAE | |
| diff -x .git -Naur linux-4.4.111/arch/x86/mm/kaiser.c linux-4.4.111-alpine/arch/x86/mm/kaiser.c | |
| --- linux-4.4.111/arch/x86/mm/kaiser.c 2018-02-20 12:32:40.138079314 -0500 | |
| +++ linux-4.4.111-alpine/arch/x86/mm/kaiser.c 2018-02-14 21:04:17.000000000 -0500 | |
| @@ -10,6 +10,7 @@ | |
| #include <linux/mm.h> | |
| #include <linux/uaccess.h> | |
| #include <linux/ftrace.h> | |
| +#include <linux/dmi.h> | |
| #undef pr_fmt | |
| #define pr_fmt(fmt) "Kernel/User page tables isolation: " fmt | |
| @@ -302,6 +303,18 @@ | |
| if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) | |
| goto disable; | |
| + { | |
| + const char *p = dmi_get_system_info(DMI_PRODUCT_NAME); | |
| + | |
| + if (!memcmp(p, "ReadyNAS 312", 12) || | |
| + !memcmp(p, "RN312", 5) || | |
| + !memcmp(p, "ReadyNAS 314", 12) || | |
| + !memcmp(p, "RN314", 5) || | |
| + !memcmp(p, "ReadyNAS 316", 12) || | |
| + !memcmp(p, "RN316", 5)) | |
| + goto disable; | |
| + } | |
| + | |
| enable: | |
| if (enable) | |
| setup_force_cpu_cap(X86_FEATURE_KAISER); | |
| diff -x .git -Naur linux-4.4.111/block/badblocks.c linux-4.4.111-alpine/block/badblocks.c | |
| --- linux-4.4.111/block/badblocks.c 1969-12-31 19:00:00.000000000 -0500 | |
| +++ linux-4.4.111-alpine/block/badblocks.c 2018-02-14 21:04:16.000000000 -0500 | |
| @@ -0,0 +1,586 @@ | |
| +/* | |
| + * Bad block management | |
| + * | |
| + * - Heavily based on MD badblocks code from Neil Brown | |
| + * | |
| + * Copyright (c) 2015, Intel Corporation. | |
| + * | |
| + * This program is free software; you can redistribute it and/or modify it | |
| + * under the terms and conditions of the GNU General Public License, | |
| + * version 2, as published by the Free Software Foundation. | |
| + * | |
| + * This program is distributed in the hope it will be useful, but WITHOUT | |
| + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
| + * more details. | |
| + */ | |
| + | |
| +#include <linux/badblocks.h> | |
| +#include <linux/seqlock.h> | |
| +#include <linux/device.h> | |
| +#include <linux/kernel.h> | |
| +#include <linux/module.h> | |
| +#include <linux/stddef.h> | |
| +#include <linux/types.h> | |
| +#include <linux/slab.h> | |
| + | |
| +/** | |
| + * badblocks_check() - check a given range for bad sectors | |
| + * @bb: the badblocks structure that holds all badblock information | |
| + * @s: sector (start) at which to check for badblocks | |
| + * @sectors: number of sectors to check for badblocks | |
| + * @first_bad: pointer to store location of the first badblock | |
| + * @bad_sectors: pointer to store number of badblocks after @first_bad | |
| + * | |
| + * We can record which blocks on each device are 'bad' and so just | |
| + * fail those blocks, or that stripe, rather than the whole device. | |
| + * Entries in the bad-block table are 64bits wide. This comprises: | |
| + * Length of bad-range, in sectors: 0-511 for lengths 1-512 | |
| + * Start of bad-range, sector offset, 54 bits (allows 8 exbibytes) | |
| + * A 'shift' can be set so that larger blocks are tracked and | |
| + * consequently larger devices can be covered. | |
| + * 'Acknowledged' flag - 1 bit. - the most significant bit. | |
| + * | |
| + * Locking of the bad-block table uses a seqlock so badblocks_check | |
| + * might need to retry if it is very unlucky. | |
| + * We will sometimes want to check for bad blocks in a bi_end_io function, | |
| + * so we use the write_seqlock_irq variant. | |
| + * | |
| + * When looking for a bad block we specify a range and want to | |
| + * know if any block in the range is bad. So we binary-search | |
| + * to the last range that starts at-or-before the given endpoint, | |
| + * (or "before the sector after the target range") | |
| + * then see if it ends after the given start. | |
| + * | |
| + * Return: | |
| + * 0: there are no known bad blocks in the range | |
| + * 1: there are known bad block which are all acknowledged | |
| + * -1: there are bad blocks which have not yet been acknowledged in metadata. | |
| + * plus the start/length of the first bad section we overlap. | |
| + */ | |
| +int badblocks_check(struct badblocks *bb, sector_t s, int sectors, | |
| + sector_t *first_bad, int *bad_sectors) | |
| +{ | |
| + int hi; | |
| + int lo; | |
| + u64 *p = bb->page; | |
| + int rv; | |
| + sector_t target = s + sectors; | |
| + unsigned seq; | |
| + | |
| + if (bb->shift > 0) { | |
| + /* round the start down, and the end up */ | |
| + s >>= bb->shift; | |
| + target += (1<<bb->shift) - 1; | |
| + target >>= bb->shift; | |
| + sectors = target - s; | |
| + } | |
| + /* 'target' is now the first block after the bad range */ | |
| + | |
| +retry: | |
| + seq = read_seqbegin(&bb->lock); | |
| + lo = 0; | |
| + rv = 0; | |
| + hi = bb->count; | |
| + | |
| + /* Binary search between lo and hi for 'target' | |
| + * i.e. for the last range that starts before 'target' | |
| + */ | |
| + /* INVARIANT: ranges before 'lo' and at-or-after 'hi' | |
| + * are known not to be the last range before target. | |
| + * VARIANT: hi-lo is the number of possible | |
| + * ranges, and decreases until it reaches 1 | |
| + */ | |
| + while (hi - lo > 1) { | |
| + int mid = (lo + hi) / 2; | |
| + sector_t a = BB_OFFSET(p[mid]); | |
| + | |
| + if (a < target) | |
| + /* This could still be the one, earlier ranges | |
| + * could not. | |
| + */ | |
| + lo = mid; | |
| + else | |
| + /* This and later ranges are definitely out. */ | |
| + hi = mid; | |
| + } | |
| + /* 'lo' might be the last that started before target, but 'hi' isn't */ | |
| + if (hi > lo) { | |
| + /* need to check all range that end after 's' to see if | |
| + * any are unacknowledged. | |
| + */ | |
| + while (lo >= 0 && | |
| + BB_OFFSET(p[lo]) + BB_LEN(p[lo]) > s) { | |
| + if (BB_OFFSET(p[lo]) < target) { | |
| + /* starts before the end, and finishes after | |
| + * the start, so they must overlap | |
| + */ | |
| + if (rv != -1 && BB_ACK(p[lo])) | |
| + rv = 1; | |
| + else | |
| + rv = -1; | |
| + *first_bad = BB_OFFSET(p[lo]); | |
| + *bad_sectors = BB_LEN(p[lo]); | |
| + } | |
| + lo--; | |
| + } | |
| + } | |
| + | |
| + if (read_seqretry(&bb->lock, seq)) | |
| + goto retry; | |
| + | |
| + return rv; | |
| +} | |
| +EXPORT_SYMBOL_GPL(badblocks_check); | |
| + | |
| +/** | |
| + * badblocks_set() - Add a range of bad blocks to the table. | |
| + * @bb: the badblocks structure that holds all badblock information | |
| + * @s: first sector to mark as bad | |
| + * @sectors: number of sectors to mark as bad | |
| + * @acknowledged: weather to mark the bad sectors as acknowledged | |
| + * | |
| + * This might extend the table, or might contract it if two adjacent ranges | |
| + * can be merged. We binary-search to find the 'insertion' point, then | |
| + * decide how best to handle it. | |
| + * | |
| + * Return: | |
| + * 0: success | |
| + * 1: failed to set badblocks (out of space) | |
| + * -1: failed to set badblocks (badblocks are disabled) | |
| + */ | |
| +int badblocks_set(struct badblocks *bb, sector_t s, int sectors, | |
| + int acknowledged) | |
| +{ | |
| + u64 *p; | |
| + int lo, hi; | |
| + int rv = 0; | |
| + unsigned long flags; | |
| + | |
| + if (bb->shift < 0) | |
| + /* badblocks are disabled */ | |
| + return -1; | |
| + | |
| + if (bb->shift) { | |
| + /* round the start down, and the end up */ | |
| + sector_t next = s + sectors; | |
| + | |
| + s >>= bb->shift; | |
| + next += (1<<bb->shift) - 1; | |
| + next >>= bb->shift; | |
| + sectors = next - s; | |
| + } | |
| + | |
| + write_seqlock_irqsave(&bb->lock, flags); | |
| + | |
| + p = bb->page; | |
| + lo = 0; | |
| + hi = bb->count; | |
| + /* Find the last range that starts at-or-before 's' */ | |
| + while (hi - lo > 1) { | |
| + int mid = (lo + hi) / 2; | |
| + sector_t a = BB_OFFSET(p[mid]); | |
| + | |
| + if (a <= s) | |
| + lo = mid; | |
| + else | |
| + hi = mid; | |
| + } | |
| + if (hi > lo && BB_OFFSET(p[lo]) > s) | |
| + hi = lo; | |
| + | |
| + if (hi > lo) { | |
| + /* we found a range that might merge with the start | |
| + * of our new range | |
| + */ | |
| + sector_t a = BB_OFFSET(p[lo]); | |
| + sector_t e = a + BB_LEN(p[lo]); | |
| + int ack = BB_ACK(p[lo]); | |
| + | |
| + if (e >= s) { | |
| + /* Yes, we can merge with a previous range */ | |
| + if (s == a && s + sectors >= e) | |
| + /* new range covers old */ | |
| + ack = acknowledged; | |
| + else | |
| + ack = ack && acknowledged; | |
| + | |
| + if (e < s + sectors) | |
| + e = s + sectors; | |
| + if (e - a <= BB_MAX_LEN) { | |
| + p[lo] = BB_MAKE(a, e-a, ack); | |
| + s = e; | |
| + } else { | |
| + /* does not all fit in one range, | |
| + * make p[lo] maximal | |
| + */ | |
| + if (BB_LEN(p[lo]) != BB_MAX_LEN) | |
| + p[lo] = BB_MAKE(a, BB_MAX_LEN, ack); | |
| + s = a + BB_MAX_LEN; | |
| + } | |
| + sectors = e - s; | |
| + } | |
| + } | |
| + if (sectors && hi < bb->count) { | |
| + /* 'hi' points to the first range that starts after 's'. | |
| + * Maybe we can merge with the start of that range | |
| + */ | |
| + sector_t a = BB_OFFSET(p[hi]); | |
| + sector_t e = a + BB_LEN(p[hi]); | |
| + int ack = BB_ACK(p[hi]); | |
| + | |
| + if (a <= s + sectors) { | |
| + /* merging is possible */ | |
| + if (e <= s + sectors) { | |
| + /* full overlap */ | |
| + e = s + sectors; | |
| + ack = acknowledged; | |
| + } else | |
| + ack = ack && acknowledged; | |
| + | |
| + a = s; | |
| + if (e - a <= BB_MAX_LEN) { | |
| + p[hi] = BB_MAKE(a, e-a, ack); | |
| + s = e; | |
| + } else { | |
| + p[hi] = BB_MAKE(a, BB_MAX_LEN, ack); | |
| + s = a + BB_MAX_LEN; | |
| + } | |
| + sectors = e - s; | |
| + lo = hi; | |
| + hi++; | |
| + } | |
| + } | |
| + if (sectors == 0 && hi < bb->count) { | |
| + /* we might be able to combine lo and hi */ | |
| + /* Note: 's' is at the end of 'lo' */ | |
| + sector_t a = BB_OFFSET(p[hi]); | |
| + int lolen = BB_LEN(p[lo]); | |
| + int hilen = BB_LEN(p[hi]); | |
| + int newlen = lolen + hilen - (s - a); | |
| + | |
| + if (s >= a && newlen < BB_MAX_LEN) { | |
| + /* yes, we can combine them */ | |
| + int ack = BB_ACK(p[lo]) && BB_ACK(p[hi]); | |
| + | |
| + p[lo] = BB_MAKE(BB_OFFSET(p[lo]), newlen, ack); | |
| + memmove(p + hi, p + hi + 1, | |
| + (bb->count - hi - 1) * 8); | |
| + bb->count--; | |
| + } | |
| + } | |
| + while (sectors) { | |
| + /* didn't merge (it all). | |
| + * Need to add a range just before 'hi' | |
| + */ | |
| + if (bb->count >= MAX_BADBLOCKS) { | |
| + /* No room for more */ | |
| + rv = 1; | |
| + break; | |
| + } else { | |
| + int this_sectors = sectors; | |
| + | |
| + memmove(p + hi + 1, p + hi, | |
| + (bb->count - hi) * 8); | |
| + bb->count++; | |
| + | |
| + if (this_sectors > BB_MAX_LEN) | |
| + this_sectors = BB_MAX_LEN; | |
| + p[hi] = BB_MAKE(s, this_sectors, acknowledged); | |
| + sectors -= this_sectors; | |
| + s += this_sectors; | |
| + } | |
| + } | |
| + | |
| + bb->changed = 1; | |
| + if (!acknowledged) | |
| + bb->unacked_exist = 1; | |
| + write_sequnlock_irqrestore(&bb->lock, flags); | |
| + | |
| + return rv; | |
| +} | |
| +EXPORT_SYMBOL_GPL(badblocks_set); | |
| + | |
| +/** | |
| + * badblocks_clear() - Remove a range of bad blocks to the table. | |
| + * @bb: the badblocks structure that holds all badblock information | |
| + * @s: first sector to mark as bad | |
| + * @sectors: number of sectors to mark as bad | |
| + * | |
| + * This may involve extending the table if we spilt a region, | |
| + * but it must not fail. So if the table becomes full, we just | |
| + * drop the remove request. | |
| + * | |
| + * Return: | |
| + * 0: success | |
| + * 1: failed to clear badblocks | |
| + */ | |
| +int badblocks_clear(struct badblocks *bb, sector_t s, int sectors) | |
| +{ | |
| + u64 *p; | |
| + int lo, hi; | |
| + sector_t target = s + sectors; | |
| + int rv = 0; | |
| + | |
| + if (bb->shift > 0) { | |
| + /* When clearing we round the start up and the end down. | |
| + * This should not matter as the shift should align with | |
| + * the block size and no rounding should ever be needed. | |
| + * However it is better the think a block is bad when it | |
| + * isn't than to think a block is not bad when it is. | |
| + */ | |
| + s += (1<<bb->shift) - 1; | |
| + s >>= bb->shift; | |
| + target >>= bb->shift; | |
| + sectors = target - s; | |
| + } | |
| + | |
| + write_seqlock_irq(&bb->lock); | |
| + | |
| + p = bb->page; | |
| + lo = 0; | |
| + hi = bb->count; | |
| + /* Find the last range that starts before 'target' */ | |
| + while (hi - lo > 1) { | |
| + int mid = (lo + hi) / 2; | |
| + sector_t a = BB_OFFSET(p[mid]); | |
| + | |
| + if (a < target) | |
| + lo = mid; | |
| + else | |
| + hi = mid; | |
| + } | |
| + if (hi > lo) { | |
| + /* p[lo] is the last range that could overlap the | |
| + * current range. Earlier ranges could also overlap, | |
| + * but only this one can overlap the end of the range. | |
| + */ | |
| + if (BB_OFFSET(p[lo]) + BB_LEN(p[lo]) > target) { | |
| + /* Partial overlap, leave the tail of this range */ | |
| + int ack = BB_ACK(p[lo]); | |
| + sector_t a = BB_OFFSET(p[lo]); | |
| + sector_t end = a + BB_LEN(p[lo]); | |
| + | |
| + if (a < s) { | |
| + /* we need to split this range */ | |
| + if (bb->count >= MAX_BADBLOCKS) { | |
| + rv = -ENOSPC; | |
| + goto out; | |
| + } | |
| + memmove(p+lo+1, p+lo, (bb->count - lo) * 8); | |
| + bb->count++; | |
| + p[lo] = BB_MAKE(a, s-a, ack); | |
| + lo++; | |
| + } | |
| + p[lo] = BB_MAKE(target, end - target, ack); | |
| + /* there is no longer an overlap */ | |
| + hi = lo; | |
| + lo--; | |
| + } | |
| + while (lo >= 0 && | |
| + BB_OFFSET(p[lo]) + BB_LEN(p[lo]) > s) { | |
| + /* This range does overlap */ | |
| + if (BB_OFFSET(p[lo]) < s) { | |
| + /* Keep the early parts of this range. */ | |
| + int ack = BB_ACK(p[lo]); | |
| + sector_t start = BB_OFFSET(p[lo]); | |
| + | |
| + p[lo] = BB_MAKE(start, s - start, ack); | |
| + /* now low doesn't overlap, so.. */ | |
| + break; | |
| + } | |
| + lo--; | |
| + } | |
| + /* 'lo' is strictly before, 'hi' is strictly after, | |
| + * anything between needs to be discarded | |
| + */ | |
| + if (hi - lo > 1) { | |
| + memmove(p+lo+1, p+hi, (bb->count - hi) * 8); | |
| + bb->count -= (hi - lo - 1); | |
| + } | |
| + } | |
| + | |
| + bb->changed = 1; | |
| +out: | |
| + write_sequnlock_irq(&bb->lock); | |
| + return rv; | |
| +} | |
| +EXPORT_SYMBOL_GPL(badblocks_clear); | |
| + | |
| +/** | |
| + * ack_all_badblocks() - Acknowledge all bad blocks in a list. | |
| + * @bb: the badblocks structure that holds all badblock information | |
| + * | |
| + * This only succeeds if ->changed is clear. It is used by | |
| + * in-kernel metadata updates | |
| + */ | |
| +void ack_all_badblocks(struct badblocks *bb) | |
| +{ | |
| + if (bb->page == NULL || bb->changed) | |
| + /* no point even trying */ | |
| + return; | |
| + write_seqlock_irq(&bb->lock); | |
| + | |
| + if (bb->changed == 0 && bb->unacked_exist) { | |
| + u64 *p = bb->page; | |
| + int i; | |
| + | |
| + for (i = 0; i < bb->count ; i++) { | |
| + if (!BB_ACK(p[i])) { | |
| + sector_t start = BB_OFFSET(p[i]); | |
| + int len = BB_LEN(p[i]); | |
| + | |
| + p[i] = BB_MAKE(start, len, 1); | |
| + } | |
| + } | |
| + bb->unacked_exist = 0; | |
| + } | |
| + write_sequnlock_irq(&bb->lock); | |
| +} | |
| +EXPORT_SYMBOL_GPL(ack_all_badblocks); | |
| + | |
| +/** | |
| + * badblocks_show() - sysfs access to bad-blocks list | |
| + * @bb: the badblocks structure that holds all badblock information | |
| + * @page: buffer received from sysfs | |
| + * @unack: weather to show unacknowledged badblocks | |
| + * | |
| + * Return: | |
| + * Length of returned data | |
| + */ | |
| +ssize_t badblocks_show(struct badblocks *bb, char *page, int unack) | |
| +{ | |
| + size_t len; | |
| + int i; | |
| + u64 *p = bb->page; | |
| + unsigned seq; | |
| + | |
| + if (bb->shift < 0) | |
| + return 0; | |
| + | |
| +retry: | |
| + seq = read_seqbegin(&bb->lock); | |
| + | |
| + len = 0; | |
| + i = 0; | |
| + | |
| + while (len < PAGE_SIZE && i < bb->count) { | |
| + sector_t s = BB_OFFSET(p[i]); | |
| + unsigned int length = BB_LEN(p[i]); | |
| + int ack = BB_ACK(p[i]); | |
| + | |
| + i++; | |
| + | |
| + if (unack && ack) | |
| + continue; | |
| + | |
| + len += snprintf(page+len, PAGE_SIZE-len, "%llu %u\n", | |
| + (unsigned long long)s << bb->shift, | |
| + length << bb->shift); | |
| + } | |
| + if (unack && len == 0) | |
| + bb->unacked_exist = 0; | |
| + | |
| + if (read_seqretry(&bb->lock, seq)) | |
| + goto retry; | |
| + | |
| + return len; | |
| +} | |
| +EXPORT_SYMBOL_GPL(badblocks_show); | |
| + | |
| +/** | |
| + * badblocks_store() - sysfs access to bad-blocks list | |
| + * @bb: the badblocks structure that holds all badblock information | |
| + * @page: buffer received from sysfs | |
| + * @len: length of data received from sysfs | |
| + * @unack: weather to show unacknowledged badblocks | |
| + * | |
| + * Return: | |
| + * Length of the buffer processed or -ve error. | |
| + */ | |
| +ssize_t badblocks_store(struct badblocks *bb, const char *page, size_t len, | |
| + int unack) | |
| +{ | |
| + unsigned long long sector; | |
| + int length; | |
| + char newline; | |
| + | |
| + switch (sscanf(page, "%llu %d%c", §or, &length, &newline)) { | |
| + case 3: | |
| + if (newline != '\n') | |
| + return -EINVAL; | |
| + case 2: | |
| + if (length <= 0) | |
| + return -EINVAL; | |
| + break; | |
| + default: | |
| + return -EINVAL; | |
| + } | |
| + | |
| + if (badblocks_set(bb, sector, length, !unack)) | |
| + return -ENOSPC; | |
| + else | |
| + return len; | |
| +} | |
| +EXPORT_SYMBOL_GPL(badblocks_store); | |
| + | |
| +static int __badblocks_init(struct device *dev, struct badblocks *bb, | |
| + int enable) | |
| +{ | |
| + bb->dev = dev; | |
| + bb->count = 0; | |
| + if (enable) | |
| + bb->shift = 0; | |
| + else | |
| + bb->shift = -1; | |
| + if (dev) | |
| + bb->page = devm_kzalloc(dev, PAGE_SIZE, GFP_KERNEL); | |
| + else | |
| + bb->page = kzalloc(PAGE_SIZE, GFP_KERNEL); | |
| + if (!bb->page) { | |
| + bb->shift = -1; | |
| + return -ENOMEM; | |
| + } | |
| + seqlock_init(&bb->lock); | |
| + | |
| + return 0; | |
| +} | |
| + | |
| +/** | |
| + * badblocks_init() - initialize the badblocks structure | |
| + * @bb: the badblocks structure that holds all badblock information | |
| + * @enable: weather to enable badblocks accounting | |
| + * | |
| + * Return: | |
| + * 0: success | |
| + * -ve errno: on error | |
| + */ | |
| +int badblocks_init(struct badblocks *bb, int enable) | |
| +{ | |
| + return __badblocks_init(NULL, bb, enable); | |
| +} | |
| +EXPORT_SYMBOL_GPL(badblocks_init); | |
| + | |
| +int devm_init_badblocks(struct device *dev, struct badblocks *bb) | |
| +{ | |
| + if (!bb) | |
| + return -EINVAL; | |
| + return __badblocks_init(dev, bb, 1); | |
| +} | |
| +EXPORT_SYMBOL_GPL(devm_init_badblocks); | |
| + | |
| +/** | |
| + * badblocks_exit() - free the badblocks structure | |
| + * @bb: the badblocks structure that holds all badblock information | |
| + */ | |
| +void badblocks_exit(struct badblocks *bb) | |
| +{ | |
| + if (!bb) | |
| + return; | |
| + if (bb->dev) | |
| + devm_kfree(bb->dev, bb->page); | |
| + else | |
| + kfree(bb->page); | |
| + bb->page = NULL; | |
| +} | |
| +EXPORT_SYMBOL_GPL(badblocks_exit); | |
| diff -x .git -Naur linux-4.4.111/block/bfq-cgroup.c linux-4.4.111-alpine/block/bfq-cgroup.c | |
| --- linux-4.4.111/block/bfq-cgroup.c 1969-12-31 19:00:00.000000000 -0500 | |
| +++ linux-4.4.111-alpine/block/bfq-cgroup.c 2018-02-14 21:04:16.000000000 -0500 | |
| @@ -0,0 +1,1186 @@ | |
| +/* | |
| + * BFQ: CGROUPS support. | |
| + * | |
| + * Based on ideas and code from CFQ: | |
| + * Copyright (C) 2003 Jens Axboe <axboe@kernel.dk> | |
| + * | |
| + * Copyright (C) 2008 Fabio Checconi <fabio@gandalf.sssup.it> | |
| + * Paolo Valente <paolo.valente@unimore.it> | |
| + * | |
| + * Copyright (C) 2010 Paolo Valente <paolo.valente@unimore.it> | |
| + * | |
| + * Licensed under the GPL-2 as detailed in the accompanying COPYING.BFQ | |
| + * file. | |
| + */ | |
| + | |
| +#ifdef CONFIG_BFQ_GROUP_IOSCHED | |
| + | |
| +/* bfqg stats flags */ | |
| +enum bfqg_stats_flags { | |
| + BFQG_stats_waiting = 0, | |
| + BFQG_stats_idling, | |
| + BFQG_stats_empty, | |
| +}; | |
| + | |
| +#define BFQG_FLAG_FNS(name) \ | |
| +static void bfqg_stats_mark_##name(struct bfqg_stats *stats) \ | |
| +{ \ | |
| + stats->flags |= (1 << BFQG_stats_##name); \ | |
| +} \ | |
| +static void bfqg_stats_clear_##name(struct bfqg_stats *stats) \ | |
| +{ \ | |
| + stats->flags &= ~(1 << BFQG_stats_##name); \ | |
| +} \ | |
| +static int bfqg_stats_##name(struct bfqg_stats *stats) \ | |
| +{ \ | |
| + return (stats->flags & (1 << BFQG_stats_##name)) != 0; \ | |
| +} \ | |
| + | |
| +BFQG_FLAG_FNS(waiting) | |
| +BFQG_FLAG_FNS(idling) | |
| +BFQG_FLAG_FNS(empty) | |
| +#undef BFQG_FLAG_FNS | |
| + | |
| +/* This should be called with the queue_lock held. */ | |
| +static void bfqg_stats_update_group_wait_time(struct bfqg_stats *stats) | |
| +{ | |
| + unsigned long long now; | |
| + | |
| + if (!bfqg_stats_waiting(stats)) | |
| + return; | |
| + | |
| + now = sched_clock(); | |
| + if (time_after64(now, stats->start_group_wait_time)) | |
| + blkg_stat_add(&stats->group_wait_time, | |
| + now - stats->start_group_wait_time); | |
| + bfqg_stats_clear_waiting(stats); | |
| +} | |
| + | |
| +/* This should be called with the queue_lock held. */ | |
| +static void bfqg_stats_set_start_group_wait_time(struct bfq_group *bfqg, | |
| + struct bfq_group *curr_bfqg) | |
| +{ | |
| + struct bfqg_stats *stats = &bfqg->stats; | |
| + | |
| + if (bfqg_stats_waiting(stats)) | |
| + return; | |
| + if (bfqg == curr_bfqg) | |
| + return; | |
| + stats->start_group_wait_time = sched_clock(); | |
| + bfqg_stats_mark_waiting(stats); | |
| +} | |
| + | |
| +/* This should be called with the queue_lock held. */ | |
| +static void bfqg_stats_end_empty_time(struct bfqg_stats *stats) | |
| +{ | |
| + unsigned long long now; | |
| + | |
| + if (!bfqg_stats_empty(stats)) | |
| + return; | |
| + | |
| + now = sched_clock(); | |
| + if (time_after64(now, stats->start_empty_time)) | |
| + blkg_stat_add(&stats->empty_time, | |
| + now - stats->start_empty_time); | |
| + bfqg_stats_clear_empty(stats); | |
| +} | |
| + | |
| +static void bfqg_stats_update_dequeue(struct bfq_group *bfqg) | |
| +{ | |
| + blkg_stat_add(&bfqg->stats.dequeue, 1); | |
| +} | |
| + | |
| +static void bfqg_stats_set_start_empty_time(struct bfq_group *bfqg) | |
| +{ | |
| + struct bfqg_stats *stats = &bfqg->stats; | |
| + | |
| + if (blkg_rwstat_total(&stats->queued)) | |
| + return; | |
| + | |
| + /* | |
| + * group is already marked empty. This can happen if bfqq got new | |
| + * request in parent group and moved to this group while being added | |
| + * to service tree. Just ignore the event and move on. | |
| + */ | |
| + if (bfqg_stats_empty(stats)) | |
| + return; | |
| + | |
| + stats->start_empty_time = sched_clock(); | |
| + bfqg_stats_mark_empty(stats); | |
| +} | |
| + | |
| +static void bfqg_stats_update_idle_time(struct bfq_group *bfqg) | |
| +{ | |
| + struct bfqg_stats *stats = &bfqg->stats; | |
| + | |
| + if (bfqg_stats_idling(stats)) { | |
| + unsigned long long now = sched_clock(); | |
| + | |
| + if (time_after64(now, stats->start_idle_time)) | |
| + blkg_stat_add(&stats->idle_time, | |
| + now - stats->start_idle_time); | |
| + bfqg_stats_clear_idling(stats); | |
| + } | |
| +} | |
| + | |
| +static void bfqg_stats_set_start_idle_time(struct bfq_group *bfqg) | |
| +{ | |
| + struct bfqg_stats *stats = &bfqg->stats; | |
| + | |
| + stats->start_idle_time = sched_clock(); | |
| + bfqg_stats_mark_idling(stats); | |
| +} | |
| + | |
| +static void bfqg_stats_update_avg_queue_size(struct bfq_group *bfqg) | |
| +{ | |
| + struct bfqg_stats *stats = &bfqg->stats; | |
| + | |
| + blkg_stat_add(&stats->avg_queue_size_sum, | |
| + blkg_rwstat_total(&stats->queued)); | |
| + blkg_stat_add(&stats->avg_queue_size_samples, 1); | |
| + bfqg_stats_update_group_wait_time(stats); | |
| +} | |
| + | |
| +static struct blkcg_policy blkcg_policy_bfq; | |
| + | |
| +/* | |
| + * blk-cgroup policy-related handlers | |
| + * The following functions help in converting between blk-cgroup | |
| + * internal structures and BFQ-specific structures. | |
| + */ | |
| + | |
| +static struct bfq_group *pd_to_bfqg(struct blkg_policy_data *pd) | |
| +{ | |
| + return pd ? container_of(pd, struct bfq_group, pd) : NULL; | |
| +} | |
| + | |
| +static struct blkcg_gq *bfqg_to_blkg(struct bfq_group *bfqg) | |
| +{ | |
| + return pd_to_blkg(&bfqg->pd); | |
| +} | |
| + | |
| +static struct bfq_group *blkg_to_bfqg(struct blkcg_gq *blkg) | |
| +{ | |
| + struct blkg_policy_data *pd = blkg_to_pd(blkg, &blkcg_policy_bfq); | |
| + BUG_ON(!pd); | |
| + return pd_to_bfqg(pd); | |
| +} | |
| + | |
| +/* | |
| + * bfq_group handlers | |
| + * The following functions help in navigating the bfq_group hierarchy | |
| + * by allowing to find the parent of a bfq_group or the bfq_group | |
| + * associated to a bfq_queue. | |
| + */ | |
| + | |
| +static struct bfq_group *bfqg_parent(struct bfq_group *bfqg) | |
| +{ | |
| + struct blkcg_gq *pblkg = bfqg_to_blkg(bfqg)->parent; | |
| + | |
| + return pblkg ? blkg_to_bfqg(pblkg) : NULL; | |
| +} | |
| + | |
| +static struct bfq_group *bfqq_group(struct bfq_queue *bfqq) | |
| +{ | |
| + struct bfq_entity *group_entity = bfqq->entity.parent; | |
| + | |
| + return group_entity ? container_of(group_entity, struct bfq_group, | |
| + entity) : | |
| + bfqq->bfqd->root_group; | |
| +} | |
| + | |
| +/* | |
| + * The following two functions handle get and put of a bfq_group by | |
| + * wrapping the related blk-cgroup hooks. | |
| + */ | |
| + | |
| +static void bfqg_get(struct bfq_group *bfqg) | |
| +{ | |
| + return blkg_get(bfqg_to_blkg(bfqg)); | |
| +} | |
| + | |
| +static void bfqg_put(struct bfq_group *bfqg) | |
| +{ | |
| + return blkg_put(bfqg_to_blkg(bfqg)); | |
| +} | |
| + | |
| +static void bfqg_stats_update_io_add(struct bfq_group *bfqg, | |
| + struct bfq_queue *bfqq, | |
| + int rw) | |
| +{ | |
| + blkg_rwstat_add(&bfqg->stats.queued, rw, 1); | |
| + bfqg_stats_end_empty_time(&bfqg->stats); | |
| + if (!(bfqq == ((struct bfq_data *)bfqg->bfqd)->in_service_queue)) | |
| + bfqg_stats_set_start_group_wait_time(bfqg, bfqq_group(bfqq)); | |
| +} | |
| + | |
| +static void bfqg_stats_update_io_remove(struct bfq_group *bfqg, int rw) | |
| +{ | |
| + blkg_rwstat_add(&bfqg->stats.queued, rw, -1); | |
| +} | |
| + | |
| +static void bfqg_stats_update_io_merged(struct bfq_group *bfqg, int rw) | |
| +{ | |
| + blkg_rwstat_add(&bfqg->stats.merged, rw, 1); | |
| +} | |
| + | |
| +static void bfqg_stats_update_dispatch(struct bfq_group *bfqg, | |
| + uint64_t bytes, int rw) | |
| +{ | |
| + blkg_stat_add(&bfqg->stats.sectors, bytes >> 9); | |
| + blkg_rwstat_add(&bfqg->stats.serviced, rw, 1); | |
| + blkg_rwstat_add(&bfqg->stats.service_bytes, rw, bytes); | |
| +} | |
| + | |
| +static void bfqg_stats_update_completion(struct bfq_group *bfqg, | |
| + uint64_t start_time, uint64_t io_start_time, int rw) | |
| +{ | |
| + struct bfqg_stats *stats = &bfqg->stats; | |
| + unsigned long long now = sched_clock(); | |
| + | |
| + if (time_after64(now, io_start_time)) | |
| + blkg_rwstat_add(&stats->service_time, rw, now - io_start_time); | |
| + if (time_after64(io_start_time, start_time)) | |
| + blkg_rwstat_add(&stats->wait_time, rw, | |
| + io_start_time - start_time); | |
| +} | |
| + | |
| +/* @stats = 0 */ | |
| +static void bfqg_stats_reset(struct bfqg_stats *stats) | |
| +{ | |
| + if (!stats) | |
| + return; | |
| + | |
| + /* queued stats shouldn't be cleared */ | |
| + blkg_rwstat_reset(&stats->service_bytes); | |
| + blkg_rwstat_reset(&stats->serviced); | |
| + blkg_rwstat_reset(&stats->merged); | |
| + blkg_rwstat_reset(&stats->service_time); | |
| + blkg_rwstat_reset(&stats->wait_time); | |
| + blkg_stat_reset(&stats->time); | |
| + blkg_stat_reset(&stats->unaccounted_time); | |
| + blkg_stat_reset(&stats->avg_queue_size_sum); | |
| + blkg_stat_reset(&stats->avg_queue_size_samples); | |
| + blkg_stat_reset(&stats->dequeue); | |
| + blkg_stat_reset(&stats->group_wait_time); | |
| + blkg_stat_reset(&stats->idle_time); | |
| + blkg_stat_reset(&stats->empty_time); | |
| +} | |
| + | |
| +/* @to += @from */ | |
| +static void bfqg_stats_merge(struct bfqg_stats *to, struct bfqg_stats *from) | |
| +{ | |
| + if (!to || !from) | |
| + return; | |
| + | |
| + /* queued stats shouldn't be cleared */ | |
| + blkg_rwstat_add_aux(&to->service_bytes, &from->service_bytes); | |
| + blkg_rwstat_add_aux(&to->serviced, &from->serviced); | |
| + blkg_rwstat_add_aux(&to->merged, &from->merged); | |
| + blkg_rwstat_add_aux(&to->service_time, &from->service_time); | |
| + blkg_rwstat_add_aux(&to->wait_time, &from->wait_time); | |
| + blkg_stat_add_aux(&from->time, &from->time); | |
| + blkg_stat_add_aux(&to->unaccounted_time, &from->unaccounted_time); | |
| + blkg_stat_add_aux(&to->avg_queue_size_sum, &from->avg_queue_size_sum); | |
| + blkg_stat_add_aux(&to->avg_queue_size_samples, &from->avg_queue_size_samples); | |
| + blkg_stat_add_aux(&to->dequeue, &from->dequeue); | |
| + blkg_stat_add_aux(&to->group_wait_time, &from->group_wait_time); | |
| + blkg_stat_add_aux(&to->idle_time, &from->idle_time); | |
| + blkg_stat_add_aux(&to->empty_time, &from->empty_time); | |
| +} | |
| + | |
| +/* | |
| + * Transfer @bfqg's stats to its parent's dead_stats so that the ancestors' | |
| + * recursive stats can still account for the amount used by this bfqg after | |
| + * it's gone. | |
| + */ | |
| +static void bfqg_stats_xfer_dead(struct bfq_group *bfqg) | |
| +{ | |
| + struct bfq_group *parent; | |
| + | |
| + if (!bfqg) /* root_group */ | |
| + return; | |
| + | |
| + parent = bfqg_parent(bfqg); | |
| + | |
| + lockdep_assert_held(bfqg_to_blkg(bfqg)->q->queue_lock); | |
| + | |
| + if (unlikely(!parent)) | |
| + return; | |
| + | |
| + bfqg_stats_merge(&parent->dead_stats, &bfqg->stats); | |
| + bfqg_stats_merge(&parent->dead_stats, &bfqg->dead_stats); | |
| + bfqg_stats_reset(&bfqg->stats); | |
| + bfqg_stats_reset(&bfqg->dead_stats); | |
| +} | |
| + | |
| +static void bfq_init_entity(struct bfq_entity *entity, | |
| + struct bfq_group *bfqg) | |
| +{ | |
| + struct bfq_queue *bfqq = bfq_entity_to_bfqq(entity); | |
| + | |
| + entity->weight = entity->new_weight; | |
| + entity->orig_weight = entity->new_weight; | |
| + if (bfqq) { | |
| + bfqq->ioprio = bfqq->new_ioprio; | |
| + bfqq->ioprio_class = bfqq->new_ioprio_class; | |
| + bfqg_get(bfqg); | |
| + } | |
| + entity->parent = bfqg->my_entity; | |
| + entity->sched_data = &bfqg->sched_data; | |
| +} | |
| + | |
| +static void bfqg_stats_exit(struct bfqg_stats *stats) | |
| +{ | |
| + blkg_rwstat_exit(&stats->service_bytes); | |
| + blkg_rwstat_exit(&stats->serviced); | |
| + blkg_rwstat_exit(&stats->merged); | |
| + blkg_rwstat_exit(&stats->service_time); | |
| + blkg_rwstat_exit(&stats->wait_time); | |
| + blkg_rwstat_exit(&stats->queued); | |
| + blkg_stat_exit(&stats->sectors); | |
| + blkg_stat_exit(&stats->time); | |
| + blkg_stat_exit(&stats->unaccounted_time); | |
| + blkg_stat_exit(&stats->avg_queue_size_sum); | |
| + blkg_stat_exit(&stats->avg_queue_size_samples); | |
| + blkg_stat_exit(&stats->dequeue); | |
| + blkg_stat_exit(&stats->group_wait_time); | |
| + blkg_stat_exit(&stats->idle_time); | |
| + blkg_stat_exit(&stats->empty_time); | |
| +} | |
| + | |
| +static int bfqg_stats_init(struct bfqg_stats *stats, gfp_t gfp) | |
| +{ | |
| + if (blkg_rwstat_init(&stats->service_bytes, gfp) || | |
| + blkg_rwstat_init(&stats->serviced, gfp) || | |
| + blkg_rwstat_init(&stats->merged, gfp) || | |
| + blkg_rwstat_init(&stats->service_time, gfp) || | |
| + blkg_rwstat_init(&stats->wait_time, gfp) || | |
| + blkg_rwstat_init(&stats->queued, gfp) || | |
| + blkg_stat_init(&stats->sectors, gfp) || | |
| + blkg_stat_init(&stats->time, gfp) || | |
| + blkg_stat_init(&stats->unaccounted_time, gfp) || | |
| + blkg_stat_init(&stats->avg_queue_size_sum, gfp) || | |
| + blkg_stat_init(&stats->avg_queue_size_samples, gfp) || | |
| + blkg_stat_init(&stats->dequeue, gfp) || | |
| + blkg_stat_init(&stats->group_wait_time, gfp) || | |
| + blkg_stat_init(&stats->idle_time, gfp) || | |
| + blkg_stat_init(&stats->empty_time, gfp)) { | |
| + bfqg_stats_exit(stats); | |
| + return -ENOMEM; | |
| + } | |
| + | |
| + return 0; | |
| +} | |
| + | |
| +static struct bfq_group_data *cpd_to_bfqgd(struct blkcg_policy_data *cpd) | |
| + { | |
| + return cpd ? container_of(cpd, struct bfq_group_data, pd) : NULL; | |
| + } | |
| + | |
| +static struct bfq_group_data *blkcg_to_bfqgd(struct blkcg *blkcg) | |
| +{ | |
| + return cpd_to_bfqgd(blkcg_to_cpd(blkcg, &blkcg_policy_bfq)); | |
| +} | |
| + | |
| +static void bfq_cpd_init(struct blkcg_policy_data *cpd) | |
| +{ | |
| + struct bfq_group_data *d = cpd_to_bfqgd(cpd); | |
| + | |
| + d->weight = BFQ_DEFAULT_GRP_WEIGHT; | |
| +} | |
| + | |
| +static struct blkg_policy_data *bfq_pd_alloc(gfp_t gfp, int node) | |
| +{ | |
| + struct bfq_group *bfqg; | |
| + | |
| + bfqg = kzalloc_node(sizeof(*bfqg), gfp, node); | |
| + if (!bfqg) | |
| + return NULL; | |
| + | |
| + if (bfqg_stats_init(&bfqg->stats, gfp) || | |
| + bfqg_stats_init(&bfqg->dead_stats, gfp)) { | |
| + kfree(bfqg); | |
| + return NULL; | |
| + } | |
| + | |
| + return &bfqg->pd; | |
| +} | |
| + | |
| +static void bfq_group_set_parent(struct bfq_group *bfqg, | |
| + struct bfq_group *parent) | |
| +{ | |
| + struct bfq_entity *entity; | |
| + | |
| + BUG_ON(!parent); | |
| + BUG_ON(!bfqg); | |
| + BUG_ON(bfqg == parent); | |
| + | |
| + entity = &bfqg->entity; | |
| + entity->parent = parent->my_entity; | |
| + entity->sched_data = &parent->sched_data; | |
| +} | |
| + | |
| +static void bfq_pd_init(struct blkg_policy_data *pd) | |
| +{ | |
| + struct blkcg_gq *blkg = pd_to_blkg(pd); | |
| + struct bfq_group *bfqg = blkg_to_bfqg(blkg); | |
| + struct bfq_data *bfqd = blkg->q->elevator->elevator_data; | |
| + struct bfq_entity *entity = &bfqg->entity; | |
| + struct bfq_group_data *d = blkcg_to_bfqgd(blkg->blkcg); | |
| + | |
| + entity->orig_weight = entity->weight = entity->new_weight = d->weight; | |
| + entity->my_sched_data = &bfqg->sched_data; | |
| + bfqg->my_entity = entity; /* | |
| + * the root_group's will be set to NULL | |
| + * in bfq_init_queue() | |
| + */ | |
| + bfqg->bfqd = bfqd; | |
| + bfqg->active_entities = 0; | |
| + bfqg->rq_pos_tree = RB_ROOT; | |
| +} | |
| + | |
| +static void bfq_pd_free(struct blkg_policy_data *pd) | |
| +{ | |
| + struct bfq_group *bfqg = pd_to_bfqg(pd); | |
| + | |
| + bfqg_stats_exit(&bfqg->stats); | |
| + bfqg_stats_exit(&bfqg->dead_stats); | |
| + | |
| + return kfree(bfqg); | |
| +} | |
| + | |
| +/* offset delta from bfqg->stats to bfqg->dead_stats */ | |
| +static const int dead_stats_off_delta = offsetof(struct bfq_group, dead_stats) - | |
| + offsetof(struct bfq_group, stats); | |
| + | |
| +/* to be used by recursive prfill, sums live and dead stats recursively */ | |
| +static u64 bfqg_stat_pd_recursive_sum(struct blkg_policy_data *pd, int off) | |
| +{ | |
| + u64 sum = 0; | |
| + | |
| + sum += blkg_stat_recursive_sum(pd_to_blkg(pd), &blkcg_policy_bfq, off); | |
| + sum += blkg_stat_recursive_sum(pd_to_blkg(pd), &blkcg_policy_bfq, | |
| + off + dead_stats_off_delta); | |
| + return sum; | |
| +} | |
| + | |
| +/* to be used by recursive prfill, sums live and dead rwstats recursively */ | |
| +static struct blkg_rwstat bfqg_rwstat_pd_recursive_sum(struct blkg_policy_data *pd, | |
| + int off) | |
| +{ | |
| + struct blkg_rwstat a, b; | |
| + | |
| + a = blkg_rwstat_recursive_sum(pd_to_blkg(pd), &blkcg_policy_bfq, off); | |
| + b = blkg_rwstat_recursive_sum(pd_to_blkg(pd), &blkcg_policy_bfq, | |
| + off + dead_stats_off_delta); | |
| + blkg_rwstat_add_aux(&a, &b); | |
| + return a; | |
| +} | |
| + | |
| +static void bfq_pd_reset_stats(struct blkg_policy_data *pd) | |
| +{ | |
| + struct bfq_group *bfqg = pd_to_bfqg(pd); | |
| + | |
| + bfqg_stats_reset(&bfqg->stats); | |
| + bfqg_stats_reset(&bfqg->dead_stats); | |
| +} | |
| + | |
| +static struct bfq_group *bfq_find_alloc_group(struct bfq_data *bfqd, | |
| + struct blkcg *blkcg) | |
| +{ | |
| + struct request_queue *q = bfqd->queue; | |
| + struct bfq_group *bfqg = NULL, *parent; | |
| + struct bfq_entity *entity = NULL; | |
| + | |
| + assert_spin_locked(bfqd->queue->queue_lock); | |
| + | |
| + /* avoid lookup for the common case where there's no blkcg */ | |
| + if (blkcg == &blkcg_root) { | |
| + bfqg = bfqd->root_group; | |
| + } else { | |
| + struct blkcg_gq *blkg; | |
| + | |
| + blkg = blkg_lookup_create(blkcg, q); | |
| + if (!IS_ERR(blkg)) | |
| + bfqg = blkg_to_bfqg(blkg); | |
| + else /* fallback to root_group */ | |
| + bfqg = bfqd->root_group; | |
| + } | |
| + | |
| + BUG_ON(!bfqg); | |
| + | |
| + /* | |
| + * Update chain of bfq_groups as we might be handling a leaf group | |
| + * which, along with some of its relatives, has not been hooked yet | |
| + * to the private hierarchy of BFQ. | |
| + */ | |
| + entity = &bfqg->entity; | |
| + for_each_entity(entity) { | |
| + bfqg = container_of(entity, struct bfq_group, entity); | |
| + BUG_ON(!bfqg); | |
| + if (bfqg != bfqd->root_group) { | |
| + parent = bfqg_parent(bfqg); | |
| + if (!parent) | |
| + parent = bfqd->root_group; | |
| + BUG_ON(!parent); | |
| + bfq_group_set_parent(bfqg, parent); | |
| + } | |
| + } | |
| + | |
| + return bfqg; | |
| +} | |
| + | |
| +static void bfq_pos_tree_add_move(struct bfq_data *bfqd, struct bfq_queue *bfqq); | |
| + | |
| +/** | |
| + * bfq_bfqq_move - migrate @bfqq to @bfqg. | |
| + * @bfqd: queue descriptor. | |
| + * @bfqq: the queue to move. | |
| + * @entity: @bfqq's entity. | |
| + * @bfqg: the group to move to. | |
| + * | |
| + * Move @bfqq to @bfqg, deactivating it from its old group and reactivating | |
| + * it on the new one. Avoid putting the entity on the old group idle tree. | |
| + * | |
| + * Must be called under the queue lock; the cgroup owning @bfqg must | |
| + * not disappear (by now this just means that we are called under | |
| + * rcu_read_lock()). | |
| + */ | |
| +static void bfq_bfqq_move(struct bfq_data *bfqd, struct bfq_queue *bfqq, | |
| + struct bfq_entity *entity, struct bfq_group *bfqg) | |
| +{ | |
| + int busy, resume; | |
| + | |
| + busy = bfq_bfqq_busy(bfqq); | |
| + resume = !RB_EMPTY_ROOT(&bfqq->sort_list); | |
| + | |
| + BUG_ON(resume && !entity->on_st); | |
| + BUG_ON(busy && !resume && entity->on_st && | |
| + bfqq != bfqd->in_service_queue); | |
| + | |
| + if (busy) { | |
| + BUG_ON(atomic_read(&bfqq->ref) < 2); | |
| + | |
| + if (!resume) | |
| + bfq_del_bfqq_busy(bfqd, bfqq, 0); | |
| + else | |
| + bfq_deactivate_bfqq(bfqd, bfqq, 0); | |
| + } else if (entity->on_st) | |
| + bfq_put_idle_entity(bfq_entity_service_tree(entity), entity); | |
| + bfqg_put(bfqq_group(bfqq)); | |
| + | |
| + /* | |
| + * Here we use a reference to bfqg. We don't need a refcounter | |
| + * as the cgroup reference will not be dropped, so that its | |
| + * destroy() callback will not be invoked. | |
| + */ | |
| + entity->parent = bfqg->my_entity; | |
| + entity->sched_data = &bfqg->sched_data; | |
| + bfqg_get(bfqg); | |
| + | |
| + if (busy) { | |
| + bfq_pos_tree_add_move(bfqd, bfqq); | |
| + if (resume) | |
| + bfq_activate_bfqq(bfqd, bfqq); | |
| + } | |
| + | |
| + if (!bfqd->in_service_queue && !bfqd->rq_in_driver) | |
| + bfq_schedule_dispatch(bfqd); | |
| +} | |
| + | |
| +/** | |
| + * __bfq_bic_change_cgroup - move @bic to @cgroup. | |
| + * @bfqd: the queue descriptor. | |
| + * @bic: the bic to move. | |
| + * @blkcg: the blk-cgroup to move to. | |
| + * | |
| + * Move bic to blkcg, assuming that bfqd->queue is locked; the caller | |
| + * has to make sure that the reference to cgroup is valid across the call. | |
| + * | |
| + * NOTE: an alternative approach might have been to store the current | |
| + * cgroup in bfqq and getting a reference to it, reducing the lookup | |
| + * time here, at the price of slightly more complex code. | |
| + */ | |
| +static struct bfq_group *__bfq_bic_change_cgroup(struct bfq_data *bfqd, | |
| + struct bfq_io_cq *bic, | |
| + struct blkcg *blkcg) | |
| +{ | |
| + struct bfq_queue *async_bfqq = bic_to_bfqq(bic, 0); | |
| + struct bfq_queue *sync_bfqq = bic_to_bfqq(bic, 1); | |
| + struct bfq_group *bfqg; | |
| + struct bfq_entity *entity; | |
| + | |
| + lockdep_assert_held(bfqd->queue->queue_lock); | |
| + | |
| + bfqg = bfq_find_alloc_group(bfqd, blkcg); | |
| + if (async_bfqq) { | |
| + entity = &async_bfqq->entity; | |
| + | |
| + if (entity->sched_data != &bfqg->sched_data) { | |
| + bic_set_bfqq(bic, NULL, 0); | |
| + bfq_log_bfqq(bfqd, async_bfqq, | |
| + "bic_change_group: %p %d", | |
| + async_bfqq, atomic_read(&async_bfqq->ref)); | |
| + bfq_put_queue(async_bfqq); | |
| + } | |
| + } | |
| + | |
| + if (sync_bfqq) { | |
| + entity = &sync_bfqq->entity; | |
| + if (entity->sched_data != &bfqg->sched_data) | |
| + bfq_bfqq_move(bfqd, sync_bfqq, entity, bfqg); | |
| + } | |
| + | |
| + return bfqg; | |
| +} | |
| + | |
| +static void bfq_bic_update_cgroup(struct bfq_io_cq *bic, struct bio *bio) | |
| +{ | |
| + struct bfq_data *bfqd = bic_to_bfqd(bic); | |
| + struct blkcg *blkcg; | |
| + struct bfq_group *bfqg = NULL; | |
| + uint64_t id; | |
| + | |
| + rcu_read_lock(); | |
| + blkcg = bio_blkcg(bio); | |
| + id = blkcg->css.serial_nr; | |
| + rcu_read_unlock(); | |
| + | |
| + /* | |
| + * Check whether blkcg has changed. The condition may trigger | |
| + * spuriously on a newly created cic but there's no harm. | |
| + */ | |
| + if (unlikely(!bfqd) || likely(bic->blkcg_id == id)) | |
| + return; | |
| + | |
| + bfqg = __bfq_bic_change_cgroup(bfqd, bic, blkcg); | |
| + BUG_ON(!bfqg); | |
| + bic->blkcg_id = id; | |
| +} | |
| + | |
| +/** | |
| + * bfq_flush_idle_tree - deactivate any entity on the idle tree of @st. | |
| + * @st: the service tree being flushed. | |
| + */ | |
| +static void bfq_flush_idle_tree(struct bfq_service_tree *st) | |
| +{ | |
| + struct bfq_entity *entity = st->first_idle; | |
| + | |
| + for (; entity ; entity = st->first_idle) | |
| + __bfq_deactivate_entity(entity, 0); | |
| +} | |
| + | |
| +/** | |
| + * bfq_reparent_leaf_entity - move leaf entity to the root_group. | |
| + * @bfqd: the device data structure with the root group. | |
| + * @entity: the entity to move. | |
| + */ | |
| +static void bfq_reparent_leaf_entity(struct bfq_data *bfqd, | |
| + struct bfq_entity *entity) | |
| +{ | |
| + struct bfq_queue *bfqq = bfq_entity_to_bfqq(entity); | |
| + | |
| + BUG_ON(!bfqq); | |
| + bfq_bfqq_move(bfqd, bfqq, entity, bfqd->root_group); | |
| + return; | |
| +} | |
| + | |
| +/** | |
| + * bfq_reparent_active_entities - move to the root group all active | |
| + * entities. | |
| + * @bfqd: the device data structure with the root group. | |
| + * @bfqg: the group to move from. | |
| + * @st: the service tree with the entities. | |
| + * | |
| + * Needs queue_lock to be taken and reference to be valid over the call. | |
| + */ | |
| +static void bfq_reparent_active_entities(struct bfq_data *bfqd, | |
| + struct bfq_group *bfqg, | |
| + struct bfq_service_tree *st) | |
| +{ | |
| + struct rb_root *active = &st->active; | |
| + struct bfq_entity *entity = NULL; | |
| + | |
| + if (!RB_EMPTY_ROOT(&st->active)) | |
| + entity = bfq_entity_of(rb_first(active)); | |
| + | |
| + for (; entity ; entity = bfq_entity_of(rb_first(active))) | |
| + bfq_reparent_leaf_entity(bfqd, entity); | |
| + | |
| + if (bfqg->sched_data.in_service_entity) | |
| + bfq_reparent_leaf_entity(bfqd, | |
| + bfqg->sched_data.in_service_entity); | |
| + | |
| + return; | |
| +} | |
| + | |
| +/** | |
| + * bfq_destroy_group - destroy @bfqg. | |
| + * @bfqg: the group being destroyed. | |
| + * | |
| + * Destroy @bfqg, making sure that it is not referenced from its parent. | |
| + * blkio already grabs the queue_lock for us, so no need to use RCU-based magic | |
| + */ | |
| +static void bfq_pd_offline(struct blkg_policy_data *pd) | |
| +{ | |
| + struct bfq_service_tree *st; | |
| + struct bfq_group *bfqg; | |
| + struct bfq_data *bfqd; | |
| + struct bfq_entity *entity; | |
| + int i; | |
| + | |
| + BUG_ON(!pd); | |
| + bfqg = pd_to_bfqg(pd); | |
| + BUG_ON(!bfqg); | |
| + bfqd = bfqg->bfqd; | |
| + BUG_ON(bfqd && !bfqd->root_group); | |
| + | |
| + entity = bfqg->my_entity; | |
| + | |
| + if (!entity) /* root group */ | |
| + return; | |
| + | |
| + /* | |
| + * Empty all service_trees belonging to this group before | |
| + * deactivating the group itself. | |
| + */ | |
| + for (i = 0; i < BFQ_IOPRIO_CLASSES; i++) { | |
| + BUG_ON(!bfqg->sched_data.service_tree); | |
| + st = bfqg->sched_data.service_tree + i; | |
| + /* | |
| + * The idle tree may still contain bfq_queues belonging | |
| + * to exited task because they never migrated to a different | |
| + * cgroup from the one being destroyed now. No one else | |
| + * can access them so it's safe to act without any lock. | |
| + */ | |
| + bfq_flush_idle_tree(st); | |
| + | |
| + /* | |
| + * It may happen that some queues are still active | |
| + * (busy) upon group destruction (if the corresponding | |
| + * processes have been forced to terminate). We move | |
| + * all the leaf entities corresponding to these queues | |
| + * to the root_group. | |
| + * Also, it may happen that the group has an entity | |
| + * in service, which is disconnected from the active | |
| + * tree: it must be moved, too. | |
| + * There is no need to put the sync queues, as the | |
| + * scheduler has taken no reference. | |
| + */ | |
| + bfq_reparent_active_entities(bfqd, bfqg, st); | |
| + BUG_ON(!RB_EMPTY_ROOT(&st->active)); | |
| + BUG_ON(!RB_EMPTY_ROOT(&st->idle)); | |
| + } | |
| + BUG_ON(bfqg->sched_data.next_in_service); | |
| + BUG_ON(bfqg->sched_data.in_service_entity); | |
| + | |
| + __bfq_deactivate_entity(entity, 0); | |
| + bfq_put_async_queues(bfqd, bfqg); | |
| + BUG_ON(entity->tree); | |
| + | |
| + bfqg_stats_xfer_dead(bfqg); | |
| +} | |
| + | |
| +static void bfq_end_wr_async(struct bfq_data *bfqd) | |
| +{ | |
| + struct blkcg_gq *blkg; | |
| + | |
| + list_for_each_entry(blkg, &bfqd->queue->blkg_list, q_node) { | |
| + struct bfq_group *bfqg = blkg_to_bfqg(blkg); | |
| + | |
| + bfq_end_wr_async_queues(bfqd, bfqg); | |
| + } | |
| + bfq_end_wr_async_queues(bfqd, bfqd->root_group); | |
| +} | |
| + | |
| +static u64 bfqio_cgroup_weight_read(struct cgroup_subsys_state *css, | |
| + struct cftype *cftype) | |
| +{ | |
| + struct blkcg *blkcg = css_to_blkcg(css); | |
| + struct bfq_group_data *bfqgd = blkcg_to_bfqgd(blkcg); | |
| + int ret = -EINVAL; | |
| + | |
| + spin_lock_irq(&blkcg->lock); | |
| + ret = bfqgd->weight; | |
| + spin_unlock_irq(&blkcg->lock); | |
| + | |
| + return ret; | |
| +} | |
| + | |
| +static int bfqio_cgroup_weight_read_dfl(struct seq_file *sf, void *v) | |
| +{ | |
| + struct blkcg *blkcg = css_to_blkcg(seq_css(sf)); | |
| + struct bfq_group_data *bfqgd = blkcg_to_bfqgd(blkcg); | |
| + | |
| + spin_lock_irq(&blkcg->lock); | |
| + seq_printf(sf, "%u\n", bfqgd->weight); | |
| + spin_unlock_irq(&blkcg->lock); | |
| + | |
| + return 0; | |
| +} | |
| + | |
| +static int bfqio_cgroup_weight_write(struct cgroup_subsys_state *css, | |
| + struct cftype *cftype, | |
| + u64 val) | |
| +{ | |
| + struct blkcg *blkcg = css_to_blkcg(css); | |
| + struct bfq_group_data *bfqgd = blkcg_to_bfqgd(blkcg); | |
| + struct blkcg_gq *blkg; | |
| + int ret = -EINVAL; | |
| + | |
| + if (val < BFQ_MIN_WEIGHT || val > BFQ_MAX_WEIGHT) | |
| + return ret; | |
| + | |
| + ret = 0; | |
| + spin_lock_irq(&blkcg->lock); | |
| + bfqgd->weight = (unsigned short)val; | |
| + hlist_for_each_entry(blkg, &blkcg->blkg_list, blkcg_node) { | |
| + struct bfq_group *bfqg = blkg_to_bfqg(blkg); | |
| + if (!bfqg) | |
| + continue; | |
| + /* | |
| + * Setting the prio_changed flag of the entity | |
| + * to 1 with new_weight == weight would re-set | |
| + * the value of the weight to its ioprio mapping. | |
| + * Set the flag only if necessary. | |
| + */ | |
| + if ((unsigned short)val != bfqg->entity.new_weight) { | |
| + bfqg->entity.new_weight = (unsigned short)val; | |
| + /* | |
| + * Make sure that the above new value has been | |
| + * stored in bfqg->entity.new_weight before | |
| + * setting the prio_changed flag. In fact, | |
| + * this flag may be read asynchronously (in | |
| + * critical sections protected by a different | |
| + * lock than that held here), and finding this | |
| + * flag set may cause the execution of the code | |
| + * for updating parameters whose value may | |
| + * depend also on bfqg->entity.new_weight (in | |
| + * __bfq_entity_update_weight_prio). | |
| + * This barrier makes sure that the new value | |
| + * of bfqg->entity.new_weight is correctly | |
| + * seen in that code. | |
| + */ | |
| + smp_wmb(); | |
| + bfqg->entity.prio_changed = 1; | |
| + } | |
| + } | |
| + spin_unlock_irq(&blkcg->lock); | |
| + | |
| + return ret; | |
| +} | |
| + | |
| +static ssize_t bfqio_cgroup_weight_write_dfl(struct kernfs_open_file *of, | |
| + char *buf, size_t nbytes, | |
| + loff_t off) | |
| +{ | |
| + /* First unsigned long found in the file is used */ | |
| + return bfqio_cgroup_weight_write(of_css(of), NULL, | |
| + simple_strtoull(strim(buf), NULL, 0)); | |
| +} | |
| + | |
| +static int bfqg_print_stat(struct seq_file *sf, void *v) | |
| +{ | |
| + blkcg_print_blkgs(sf, css_to_blkcg(seq_css(sf)), blkg_prfill_stat, | |
| + &blkcg_policy_bfq, seq_cft(sf)->private, false); | |
| + return 0; | |
| +} | |
| + | |
| +static int bfqg_print_rwstat(struct seq_file *sf, void *v) | |
| +{ | |
| + blkcg_print_blkgs(sf, css_to_blkcg(seq_css(sf)), blkg_prfill_rwstat, | |
| + &blkcg_policy_bfq, seq_cft(sf)->private, true); | |
| + return 0; | |
| +} | |
| + | |
| +static u64 bfqg_prfill_stat_recursive(struct seq_file *sf, | |
| + struct blkg_policy_data *pd, int off) | |
| +{ | |
| + u64 sum = bfqg_stat_pd_recursive_sum(pd, off); | |
| + | |
| + return __blkg_prfill_u64(sf, pd, sum); | |
| +} | |
| + | |
| +static u64 bfqg_prfill_rwstat_recursive(struct seq_file *sf, | |
| + struct blkg_policy_data *pd, int off) | |
| +{ | |
| + struct blkg_rwstat sum = bfqg_rwstat_pd_recursive_sum(pd, off); | |
| + | |
| + return __blkg_prfill_rwstat(sf, pd, &sum); | |
| +} | |
| + | |
| +static int bfqg_print_stat_recursive(struct seq_file *sf, void *v) | |
| +{ | |
| + blkcg_print_blkgs(sf, css_to_blkcg(seq_css(sf)), | |
| + bfqg_prfill_stat_recursive, &blkcg_policy_bfq, | |
| + seq_cft(sf)->private, false); | |
| + return 0; | |
| +} | |
| + | |
| +static int bfqg_print_rwstat_recursive(struct seq_file *sf, void *v) | |
| +{ | |
| + blkcg_print_blkgs(sf, css_to_blkcg(seq_css(sf)), | |
| + bfqg_prfill_rwstat_recursive, &blkcg_policy_bfq, | |
| + seq_cft(sf)->private, true); | |
| + return 0; | |
| +} | |
| + | |
| +static u64 bfqg_prfill_avg_queue_size(struct seq_file *sf, | |
| + struct blkg_policy_data *pd, int off) | |
| +{ | |
| + struct bfq_group *bfqg = pd_to_bfqg(pd); | |
| + u64 samples = blkg_stat_read(&bfqg->stats.avg_queue_size_samples); | |
| + u64 v = 0; | |
| + | |
| + if (samples) { | |
| + v = blkg_stat_read(&bfqg->stats.avg_queue_size_sum); | |
| + v = div64_u64(v, samples); | |
| + } | |
| + __blkg_prfill_u64(sf, pd, v); | |
| + return 0; | |
| +} | |
| + | |
| +/* print avg_queue_size */ | |
| +static int bfqg_print_avg_queue_size(struct seq_file *sf, void *v) | |
| +{ | |
| + blkcg_print_blkgs(sf, css_to_blkcg(seq_css(sf)), | |
| + bfqg_prfill_avg_queue_size, &blkcg_policy_bfq, | |
| + 0, false); | |
| + return 0; | |
| +} | |
| + | |
| +static struct bfq_group *bfq_create_group_hierarchy(struct bfq_data *bfqd, int node) | |
| +{ | |
| + int ret; | |
| + | |
| + ret = blkcg_activate_policy(bfqd->queue, &blkcg_policy_bfq); | |
| + if (ret) | |
| + return NULL; | |
| + | |
| + return blkg_to_bfqg(bfqd->queue->root_blkg); | |
| +} | |
| + | |
| +static struct blkcg_policy_data *bfq_cpd_alloc(gfp_t gfp) | |
| +{ | |
| + struct bfq_group_data *bgd; | |
| + | |
| + bgd = kzalloc(sizeof(*bgd), GFP_KERNEL); | |
| + if (!bgd) | |
| + return NULL; | |
| + return &bgd->pd; | |
| +} | |
| + | |
| +static void bfq_cpd_free(struct blkcg_policy_data *cpd) | |
| +{ | |
| + kfree(cpd_to_bfqgd(cpd)); | |
| +} | |
| + | |
| +static struct cftype bfqio_files_dfl[] = { | |
| + { | |
| + .name = "weight", | |
| + .flags = CFTYPE_NOT_ON_ROOT, | |
| + .seq_show = bfqio_cgroup_weight_read_dfl, | |
| + .write = bfqio_cgroup_weight_write_dfl, | |
| + }, | |
| + {} /* terminate */ | |
| +}; | |
| + | |
| +static struct cftype bfqio_files[] = { | |
| + { | |
| + .name = "bfq.weight", | |
| + .read_u64 = bfqio_cgroup_weight_read, | |
| + .write_u64 = bfqio_cgroup_weight_write, | |
| + }, | |
| + /* statistics, cover only the tasks in the bfqg */ | |
| + { | |
| + .name = "bfq.time", | |
| + .private = offsetof(struct bfq_group, stats.time), | |
| + .seq_show = bfqg_print_stat, | |
| + }, | |
| + { | |
| + .name = "bfq.sectors", | |
| + .private = offsetof(struct bfq_group, stats.sectors), | |
| + .seq_show = bfqg_print_stat, | |
| + }, | |
| + { | |
| + .name = "bfq.io_service_bytes", | |
| + .private = offsetof(struct bfq_group, stats.service_bytes), | |
| + .seq_show = bfqg_print_rwstat, | |
| + }, | |
| + { | |
| + .name = "bfq.io_serviced", | |
| + .private = offsetof(struct bfq_group, stats.serviced), | |
| + .seq_show = bfqg_print_rwstat, | |
| + }, | |
| + { | |
| + .name = "bfq.io_service_time", | |
| + .private = offsetof(struct bfq_group, stats.service_time), | |
| + .seq_show = bfqg_print_rwstat, | |
| + }, | |
| + { | |
| + .name = "bfq.io_wait_time", | |
| + .private = offsetof(struct bfq_group, stats.wait_time), | |
| + .seq_show = bfqg_print_rwstat, | |
| + }, | |
| + { | |
| + .name = "bfq.io_merged", | |
| + .private = offsetof(struct bfq_group, stats.merged), | |
| + .seq_show = bfqg_print_rwstat, | |
| + }, | |
| + { | |
| + .name = "bfq.io_queued", | |
| + .private = offsetof(struct bfq_group, stats.queued), | |
| + .seq_show = bfqg_print_rwstat, | |
| + }, | |
| + | |
| + /* the same statictics which cover the bfqg and its descendants */ | |
| + { | |
| + .name = "bfq.time_recursive", | |
| + .private = offsetof(struct bfq_group, stats.time), | |
| + .seq_show = bfqg_print_stat_recursive, | |
| + }, | |
| + { | |
| + .name = "bfq.sectors_recursive", | |
| + .private = offsetof(struct bfq_group, stats.sectors), | |
| + .seq_show = bfqg_print_stat_recursive, | |
| + }, | |
| + { | |
| + .name = "bfq.io_service_bytes_recursive", | |
| + .private = offsetof(struct bfq_group, stats.service_bytes), | |
| + .seq_show = bfqg_print_rwstat_recursive, | |
| + }, | |
| + { | |
| + .name = "bfq.io_serviced_recursive", | |
| + .private = offsetof(struct bfq_group, stats.serviced), | |
| + .seq_show = bfqg_print_rwstat_recursive, | |
| + }, | |
| + { | |
| + .name = "bfq.io_service_time_recursive", | |
| + .private = offsetof(struct bfq_group, stats.service_time), | |
| + .seq_show = bfqg_print_rwstat_recursive, | |
| + }, | |
| + { | |
| + .name = "bfq.io_wait_time_recursive", | |
| + .private = offsetof(struct bfq_group, stats.wait_time), | |
| + .seq_show = bfqg_print_rwstat_recursive, | |
| + }, | |
| + { | |
| + .name = "bfq.io_merged_recursive", | |
| + .private = offsetof(struct bfq_group, stats.merged), | |
| + .seq_show = bfqg_print_rwstat_recursive, | |
| + }, | |
| + { | |
| + .name = "bfq.io_queued_recursive", | |
| + .private = offsetof(struct bfq_group, stats.queued), | |
| + .seq_show = bfqg_print_rwstat_recursive, | |
| + }, | |
| + { | |
| + .name = "bfq.avg_queue_size", | |
| + .seq_show = bfqg_print_avg_queue_size, | |
| + }, | |
| + { | |
| + .name = "bfq.group_wait_time", | |
| + .private = offsetof(struct bfq_group, stats.group_wait_time), | |
| + .seq_show = bfqg_print_stat, | |
| + }, | |
| + { | |
| + .name = "bfq.idle_time", | |
| + .private = offsetof(struct bfq_group, stats.idle_time), | |
| + .seq_show = bfqg_print_stat, | |
| + }, | |
| + { | |
| + .name = "bfq.empty_time", | |
| + .private = offsetof(struct bfq_group, stats.empty_time), | |
| + .seq_show = bfqg_print_stat, | |
| + }, | |
| + { | |
| + .name = "bfq.dequeue", | |
| + .private = offsetof(struct bfq_group, stats.dequeue), | |
| + .seq_show = bfqg_print_stat, | |
| + }, | |
| + { | |
| + .name = "bfq.unaccounted_time", | |
| + .private = offsetof(struct bfq_group, stats.unaccounted_time), | |
| + .seq_show = bfqg_print_stat, | |
| + }, | |
| + { } /* terminate */ | |
| +}; | |
| + | |
| +static struct blkcg_policy blkcg_policy_bfq = { | |
| + .dfl_cftypes = bfqio_files_dfl, | |
| + .legacy_cftypes = bfqio_files, | |
| + | |
| + .pd_alloc_fn = bfq_pd_alloc, | |
| + .pd_init_fn = bfq_pd_init, | |
| + .pd_offline_fn = bfq_pd_offline, | |
| + .pd_free_fn = bfq_pd_free, | |
| + .pd_reset_stats_fn = bfq_pd_reset_stats, | |
| + | |
| + .cpd_alloc_fn = bfq_cpd_alloc, | |
| + .cpd_init_fn = bfq_cpd_init, | |
| + .cpd_bind_fn = bfq_cpd_init, | |
| + .cpd_free_fn = bfq_cpd_free, | |
| + | |
| +}; | |
| + | |
| +#else | |
| + | |
| +static void bfq_init_entity(struct bfq_entity *entity, | |
| + struct bfq_group *bfqg) | |
| +{ | |
| + struct bfq_queue *bfqq = bfq_entity_to_bfqq(entity); | |
| + entity->weight = entity->new_weight; | |
| + entity->orig_weight = entity->new_weight; | |
| + if (bfqq) { | |
| + bfqq->ioprio = bfqq->new_ioprio; | |
| + bfqq->ioprio_class = bfqq->new_ioprio_class; | |
| + } | |
| + entity->sched_data = &bfqg->sched_data; | |
| +} | |
| + | |
| +static struct bfq_group * | |
| +bfq_bic_update_cgroup(struct bfq_io_cq *bic, struct bio *bio) | |
| +{ | |
| + struct bfq_data *bfqd = bic_to_bfqd(bic); | |
| + return bfqd->root_group; | |
| +} | |
| + | |
| +static void bfq_bfqq_move(struct bfq_data *bfqd, | |
| + struct bfq_queue *bfqq, | |
| + struct bfq_entity *entity, | |
| + struct bfq_group *bfqg) | |
| +{ | |
| +} | |
| + | |
| +static void bfq_end_wr_async(struct bfq_data *bfqd) | |
| +{ | |
| + bfq_end_wr_async_queues(bfqd, bfqd->root_group); | |
| +} | |
| + | |
| +static void bfq_disconnect_groups(struct bfq_data *bfqd) | |
| +{ | |
| + bfq_put_async_queues(bfqd, bfqd->root_group); | |
| +} | |
| + | |
| +static struct bfq_group *bfq_find_alloc_group(struct bfq_data *bfqd, | |
| + struct blkcg *blkcg) | |
| +{ | |
| + return bfqd->root_group; | |
| +} | |
| + | |
| +static struct bfq_group *bfq_create_group_hierarchy(struct bfq_data *bfqd, int node) | |
| +{ | |
| + struct bfq_group *bfqg; | |
| + int i; | |
| + | |
| + bfqg = kmalloc_node(sizeof(*bfqg), GFP_KERNEL | __GFP_ZERO, node); | |
| + if (!bfqg) | |
| + return NULL; | |
| + | |
| + for (i = 0; i < BFQ_IOPRIO_CLASSES; i++) | |
| + bfqg->sched_data.service_tree[i] = BFQ_SERVICE_TREE_INIT; | |
| + | |
| + return bfqg; | |
| +} | |
| +#endif | |
| diff -x .git -Naur linux-4.4.111/block/bfq.h linux-4.4.111-alpine/block/bfq.h | |
| --- linux-4.4.111/block/bfq.h 1969-12-31 19:00:00.000000000 -0500 | |
| +++ linux-4.4.111-alpine/block/bfq.h 2018-02-14 21:04:16.000000000 -0500 | |
| @@ -0,0 +1,867 @@ | |
| +/* | |
| + * BFQ-v7r11 for 4.4.0: data structures and common functions prototypes. | |
| + * | |
| + * Based on ideas and code from CFQ: | |
| + * Copyright (C) 2003 Jens Axboe <axboe@kernel.dk> | |
| + * | |
| + * Copyright (C) 2008 Fabio Checconi <fabio@gandalf.sssup.it> | |
| + * Paolo Valente <paolo.valente@unimore.it> | |
| + * | |
| + * Copyright (C) 2010 Paolo Valente <paolo.valente@unimore.it> | |
| + */ | |
| + | |
| +#ifndef _BFQ_H | |
| +#define _BFQ_H | |
| + | |
| +#include <linux/blktrace_api.h> | |
| +#include <linux/hrtimer.h> | |
| +#include <linux/ioprio.h> | |
| +#include <linux/rbtree.h> | |
| +#include <linux/blk-cgroup.h> | |
| + | |
| +#define BFQ_IOPRIO_CLASSES 3 | |
| +#define BFQ_CL_IDLE_TIMEOUT (HZ/5) | |
| + | |
| +#define BFQ_MIN_WEIGHT 1 | |
| +#define BFQ_MAX_WEIGHT 1000 | |
| +#define BFQ_WEIGHT_CONVERSION_COEFF 10 | |
| + | |
| +#define BFQ_DEFAULT_QUEUE_IOPRIO 4 | |
| + | |
| +#define BFQ_DEFAULT_GRP_WEIGHT 10 | |
| +#define BFQ_DEFAULT_GRP_IOPRIO 0 | |
| +#define BFQ_DEFAULT_GRP_CLASS IOPRIO_CLASS_BE | |
| + | |
| +struct bfq_entity; | |
| + | |
| +/** | |
| + * struct bfq_service_tree - per ioprio_class service tree. | |
| + * @active: tree for active entities (i.e., those backlogged). | |
| + * @idle: tree for idle entities (i.e., those not backlogged, with V <= F_i). | |
| + * @first_idle: idle entity with minimum F_i. | |
| + * @last_idle: idle entity with maximum F_i. | |
| + * @vtime: scheduler virtual time. | |
| + * @wsum: scheduler weight sum; active and idle entities contribute to it. | |
| + * | |
| + * Each service tree represents a B-WF2Q+ scheduler on its own. Each | |
| + * ioprio_class has its own independent scheduler, and so its own | |
| + * bfq_service_tree. All the fields are protected by the queue lock | |
| + * of the containing bfqd. | |
| + */ | |
| +struct bfq_service_tree { | |
| + struct rb_root active; | |
| + struct rb_root idle; | |
| + | |
| + struct bfq_entity *first_idle; | |
| + struct bfq_entity *last_idle; | |
| + | |
| + u64 vtime; | |
| + unsigned long wsum; | |
| +}; | |
| + | |
| +/** | |
| + * struct bfq_sched_data - multi-class scheduler. | |
| + * @in_service_entity: entity in service. | |
| + * @next_in_service: head-of-the-line entity in the scheduler. | |
| + * @service_tree: array of service trees, one per ioprio_class. | |
| + * | |
| + * bfq_sched_data is the basic scheduler queue. It supports three | |
| + * ioprio_classes, and can be used either as a toplevel queue or as | |
| + * an intermediate queue on a hierarchical setup. | |
| + * @next_in_service points to the active entity of the sched_data | |
| + * service trees that will be scheduled next. | |
| + * | |
| + * The supported ioprio_classes are the same as in CFQ, in descending | |
| + * priority order, IOPRIO_CLASS_RT, IOPRIO_CLASS_BE, IOPRIO_CLASS_IDLE. | |
| + * Requests from higher priority queues are served before all the | |
| + * requests from lower priority queues; among requests of the same | |
| + * queue requests are served according to B-WF2Q+. | |
| + * All the fields are protected by the queue lock of the containing bfqd. | |
| + */ | |
| +struct bfq_sched_data { | |
| + struct bfq_entity *in_service_entity; | |
| + struct bfq_entity *next_in_service; | |
| + struct bfq_service_tree service_tree[BFQ_IOPRIO_CLASSES]; | |
| +}; | |
| + | |
| +/** | |
| + * struct bfq_weight_counter - counter of the number of all active entities | |
| + * with a given weight. | |
| + * @weight: weight of the entities that this counter refers to. | |
| + * @num_active: number of active entities with this weight. | |
| + * @weights_node: weights tree member (see bfq_data's @queue_weights_tree | |
| + * and @group_weights_tree). | |
| + */ | |
| +struct bfq_weight_counter { | |
| + short int weight; | |
| + unsigned int num_active; | |
| + struct rb_node weights_node; | |
| +}; | |
| + | |
| +/** | |
| + * struct bfq_entity - schedulable entity. | |
| + * @rb_node: service_tree member. | |
| + * @weight_counter: pointer to the weight counter associated with this entity. | |
| + * @on_st: flag, true if the entity is on a tree (either the active or | |
| + * the idle one of its service_tree). | |
| + * @finish: B-WF2Q+ finish timestamp (aka F_i). | |
| + * @start: B-WF2Q+ start timestamp (aka S_i). | |
| + * @tree: tree the entity is enqueued into; %NULL if not on a tree. | |
| + * @min_start: minimum start time of the (active) subtree rooted at | |
| + * this entity; used for O(log N) lookups into active trees. | |
| + * @service: service received during the last round of service. | |
| + * @budget: budget used to calculate F_i; F_i = S_i + @budget / @weight. | |
| + * @weight: weight of the queue | |
| + * @parent: parent entity, for hierarchical scheduling. | |
| + * @my_sched_data: for non-leaf nodes in the cgroup hierarchy, the | |
| + * associated scheduler queue, %NULL on leaf nodes. | |
| + * @sched_data: the scheduler queue this entity belongs to. | |
| + * @ioprio: the ioprio in use. | |
| + * @new_weight: when a weight change is requested, the new weight value. | |
| + * @orig_weight: original weight, used to implement weight boosting | |
| + * @prio_changed: flag, true when the user requested a weight, ioprio or | |
| + * ioprio_class change. | |
| + * | |
| + * A bfq_entity is used to represent either a bfq_queue (leaf node in the | |
| + * cgroup hierarchy) or a bfq_group into the upper level scheduler. Each | |
| + * entity belongs to the sched_data of the parent group in the cgroup | |
| + * hierarchy. Non-leaf entities have also their own sched_data, stored | |
| + * in @my_sched_data. | |
| + * | |
| + * Each entity stores independently its priority values; this would | |
| + * allow different weights on different devices, but this | |
| + * functionality is not exported to userspace by now. Priorities and | |
| + * weights are updated lazily, first storing the new values into the | |
| + * new_* fields, then setting the @prio_changed flag. As soon as | |
| + * there is a transition in the entity state that allows the priority | |
| + * update to take place the effective and the requested priority | |
| + * values are synchronized. | |
| + * | |
| + * Unless cgroups are used, the weight value is calculated from the | |
| + * ioprio to export the same interface as CFQ. When dealing with | |
| + * ``well-behaved'' queues (i.e., queues that do not spend too much | |
| + * time to consume their budget and have true sequential behavior, and | |
| + * when there are no external factors breaking anticipation) the | |
| + * relative weights at each level of the cgroups hierarchy should be | |
| + * guaranteed. All the fields are protected by the queue lock of the | |
| + * containing bfqd. | |
| + */ | |
| +struct bfq_entity { | |
| + struct rb_node rb_node; | |
| + struct bfq_weight_counter *weight_counter; | |
| + | |
| + int on_st; | |
| + | |
| + u64 finish; | |
| + u64 start; | |
| + | |
| + struct rb_root *tree; | |
| + | |
| + u64 min_start; | |
| + | |
| + int service, budget; | |
| + unsigned short weight, new_weight; | |
| + unsigned short orig_weight; | |
| + | |
| + struct bfq_entity *parent; | |
| + | |
| + struct bfq_sched_data *my_sched_data; | |
| + struct bfq_sched_data *sched_data; | |
| + | |
| + int prio_changed; | |
| +}; | |
| + | |
| +struct bfq_group; | |
| + | |
| +/** | |
| + * struct bfq_queue - leaf schedulable entity. | |
| + * @ref: reference counter. | |
| + * @bfqd: parent bfq_data. | |
| + * @new_ioprio: when an ioprio change is requested, the new ioprio value. | |
| + * @ioprio_class: the ioprio_class in use. | |
| + * @new_ioprio_class: when an ioprio_class change is requested, the new | |
| + * ioprio_class value. | |
| + * @new_bfqq: shared bfq_queue if queue is cooperating with | |
| + * one or more other queues. | |
| + * @pos_node: request-position tree member (see bfq_group's @rq_pos_tree). | |
| + * @pos_root: request-position tree root (see bfq_group's @rq_pos_tree). | |
| + * @sort_list: sorted list of pending requests. | |
| + * @next_rq: if fifo isn't expired, next request to serve. | |
| + * @queued: nr of requests queued in @sort_list. | |
| + * @allocated: currently allocated requests. | |
| + * @meta_pending: pending metadata requests. | |
| + * @fifo: fifo list of requests in sort_list. | |
| + * @entity: entity representing this queue in the scheduler. | |
| + * @max_budget: maximum budget allowed from the feedback mechanism. | |
| + * @budget_timeout: budget expiration (in jiffies). | |
| + * @dispatched: number of requests on the dispatch list or inside driver. | |
| + * @flags: status flags. | |
| + * @bfqq_list: node for active/idle bfqq list inside our bfqd. | |
| + * @burst_list_node: node for the device's burst list. | |
| + * @seek_samples: number of seeks sampled | |
| + * @seek_total: sum of the distances of the seeks sampled | |
| + * @seek_mean: mean seek distance | |
| + * @last_request_pos: position of the last request enqueued | |
| + * @requests_within_timer: number of consecutive pairs of request completion | |
| + * and arrival, such that the queue becomes idle | |
| + * after the completion, but the next request arrives | |
| + * within an idle time slice; used only if the queue's | |
| + * IO_bound has been cleared. | |
| + * @pid: pid of the process owning the queue, used for logging purposes. | |
| + * @last_wr_start_finish: start time of the current weight-raising period if | |
| + * the @bfq-queue is being weight-raised, otherwise | |
| + * finish time of the last weight-raising period | |
| + * @wr_cur_max_time: current max raising time for this queue | |
| + * @soft_rt_next_start: minimum time instant such that, only if a new | |
| + * request is enqueued after this time instant in an | |
| + * idle @bfq_queue with no outstanding requests, then | |
| + * the task associated with the queue it is deemed as | |
| + * soft real-time (see the comments to the function | |
| + * bfq_bfqq_softrt_next_start()) | |
| + * @last_idle_bklogged: time of the last transition of the @bfq_queue from | |
| + * idle to backlogged | |
| + * @service_from_backlogged: cumulative service received from the @bfq_queue | |
| + * since the last transition from idle to | |
| + * backlogged | |
| + * @bic: pointer to the bfq_io_cq owning the bfq_queue, set to %NULL if the | |
| + * queue is shared | |
| + * | |
| + * A bfq_queue is a leaf request queue; it can be associated with an | |
| + * io_context or more, if it is async or shared between cooperating | |
| + * processes. @cgroup holds a reference to the cgroup, to be sure that it | |
| + * does not disappear while a bfqq still references it (mostly to avoid | |
| + * races between request issuing and task migration followed by cgroup | |
| + * destruction). | |
| + * All the fields are protected by the queue lock of the containing bfqd. | |
| + */ | |
| +struct bfq_queue { | |
| + atomic_t ref; | |
| + struct bfq_data *bfqd; | |
| + | |
| + unsigned short ioprio, new_ioprio; | |
| + unsigned short ioprio_class, new_ioprio_class; | |
| + | |
| + /* fields for cooperating queues handling */ | |
| + struct bfq_queue *new_bfqq; | |
| + struct rb_node pos_node; | |
| + struct rb_root *pos_root; | |
| + | |
| + struct rb_root sort_list; | |
| + struct request *next_rq; | |
| + int queued[2]; | |
| + int allocated[2]; | |
| + int meta_pending; | |
| + struct list_head fifo; | |
| + | |
| + struct bfq_entity entity; | |
| + | |
| + int max_budget; | |
| + unsigned long budget_timeout; | |
| + | |
| + int dispatched; | |
| + | |
| + unsigned int flags; | |
| + | |
| + struct list_head bfqq_list; | |
| + | |
| + struct hlist_node burst_list_node; | |
| + | |
| + unsigned int seek_samples; | |
| + u64 seek_total; | |
| + sector_t seek_mean; | |
| + sector_t last_request_pos; | |
| + | |
| + unsigned int requests_within_timer; | |
| + | |
| + pid_t pid; | |
| + struct bfq_io_cq *bic; | |
| + | |
| + /* weight-raising fields */ | |
| + unsigned long wr_cur_max_time; | |
| + unsigned long soft_rt_next_start; | |
| + unsigned long last_wr_start_finish; | |
| + unsigned int wr_coeff; | |
| + unsigned long last_idle_bklogged; | |
| + unsigned long service_from_backlogged; | |
| +}; | |
| + | |
| +/** | |
| + * struct bfq_ttime - per process thinktime stats. | |
| + * @ttime_total: total process thinktime | |
| + * @ttime_samples: number of thinktime samples | |
| + * @ttime_mean: average process thinktime | |
| + */ | |
| +struct bfq_ttime { | |
| + unsigned long last_end_request; | |
| + | |
| + unsigned long ttime_total; | |
| + unsigned long ttime_samples; | |
| + unsigned long ttime_mean; | |
| +}; | |
| + | |
| +/** | |
| + * struct bfq_io_cq - per (request_queue, io_context) structure. | |
| + * @icq: associated io_cq structure | |
| + * @bfqq: array of two process queues, the sync and the async | |
| + * @ttime: associated @bfq_ttime struct | |
| + * @ioprio: per (request_queue, blkcg) ioprio. | |
| + * @blkcg_id: id of the blkcg the related io_cq belongs to. | |
| + * @wr_time_left: snapshot of the time left before weight raising ends | |
| + * for the sync queue associated to this process; this | |
| + * snapshot is taken to remember this value while the weight | |
| + * raising is suspended because the queue is merged with a | |
| + * shared queue, and is used to set @raising_cur_max_time | |
| + * when the queue is split from the shared queue and its | |
| + * weight is raised again | |
| + * @saved_idle_window: same purpose as the previous field for the idle | |
| + * window | |
| + * @saved_IO_bound: same purpose as the previous two fields for the I/O | |
| + * bound classification of a queue | |
| + * @saved_in_large_burst: same purpose as the previous fields for the | |
| + * value of the field keeping the queue's belonging | |
| + * to a large burst | |
| + * @was_in_burst_list: true if the queue belonged to a burst list | |
| + * before its merge with another cooperating queue | |
| + * @cooperations: counter of consecutive successful queue merges underwent | |
| + * by any of the process' @bfq_queues | |
| + * @failed_cooperations: counter of consecutive failed queue merges of any | |
| + * of the process' @bfq_queues | |
| + */ | |
| +struct bfq_io_cq { | |
| + struct io_cq icq; /* must be the first member */ | |
| + struct bfq_queue *bfqq[2]; | |
| + struct bfq_ttime ttime; | |
| + int ioprio; | |
| + | |
| +#ifdef CONFIG_BFQ_GROUP_IOSCHED | |
| + uint64_t blkcg_id; /* the current blkcg ID */ | |
| +#endif | |
| + | |
| + unsigned int wr_time_left; | |
| + bool saved_idle_window; | |
| + bool saved_IO_bound; | |
| + | |
| + bool saved_in_large_burst; | |
| + bool was_in_burst_list; | |
| + | |
| + unsigned int cooperations; | |
| + unsigned int failed_cooperations; | |
| +}; | |
| + | |
| +enum bfq_device_speed { | |
| + BFQ_BFQD_FAST, | |
| + BFQ_BFQD_SLOW, | |
| +}; | |
| + | |
| +/** | |
| + * struct bfq_data - per device data structure. | |
| + * @queue: request queue for the managed device. | |
| + * @root_group: root bfq_group for the device. | |
| + * @active_numerous_groups: number of bfq_groups containing more than one | |
| + * active @bfq_entity. | |
| + * @queue_weights_tree: rbtree of weight counters of @bfq_queues, sorted by | |
| + * weight. Used to keep track of whether all @bfq_queues | |
| + * have the same weight. The tree contains one counter | |
| + * for each distinct weight associated to some active | |
| + * and not weight-raised @bfq_queue (see the comments to | |
| + * the functions bfq_weights_tree_[add|remove] for | |
| + * further details). | |
| + * @group_weights_tree: rbtree of non-queue @bfq_entity weight counters, sorted | |
| + * by weight. Used to keep track of whether all | |
| + * @bfq_groups have the same weight. The tree contains | |
| + * one counter for each distinct weight associated to | |
| + * some active @bfq_group (see the comments to the | |
| + * functions bfq_weights_tree_[add|remove] for further | |
| + * details). | |
| + * @busy_queues: number of bfq_queues containing requests (including the | |
| + * queue in service, even if it is idling). | |
| + * @busy_in_flight_queues: number of @bfq_queues containing pending or | |
| + * in-flight requests, plus the @bfq_queue in | |
| + * service, even if idle but waiting for the | |
| + * possible arrival of its next sync request. This | |
| + * field is updated only if the device is rotational, | |
| + * but used only if the device is also NCQ-capable. | |
| + * The reason why the field is updated also for non- | |
| + * NCQ-capable rotational devices is related to the | |
| + * fact that the value of @hw_tag may be set also | |
| + * later than when busy_in_flight_queues may need to | |
| + * be incremented for the first time(s). Taking also | |
| + * this possibility into account, to avoid unbalanced | |
| + * increments/decrements, would imply more overhead | |
| + * than just updating busy_in_flight_queues | |
| + * regardless of the value of @hw_tag. | |
| + * @const_seeky_busy_in_flight_queues: number of constantly-seeky @bfq_queues | |
| + * (that is, seeky queues that expired | |
| + * for budget timeout at least once) | |
| + * containing pending or in-flight | |
| + * requests, including the in-service | |
| + * @bfq_queue if constantly seeky. This | |
| + * field is updated only if the device | |
| + * is rotational, but used only if the | |
| + * device is also NCQ-capable (see the | |
| + * comments to @busy_in_flight_queues). | |
| + * @wr_busy_queues: number of weight-raised busy @bfq_queues. | |
| + * @queued: number of queued requests. | |
| + * @rq_in_driver: number of requests dispatched and waiting for completion. | |
| + * @sync_flight: number of sync requests in the driver. | |
| + * @max_rq_in_driver: max number of reqs in driver in the last | |
| + * @hw_tag_samples completed requests. | |
| + * @hw_tag_samples: nr of samples used to calculate hw_tag. | |
| + * @hw_tag: flag set to one if the driver is showing a queueing behavior. | |
| + * @budgets_assigned: number of budgets assigned. | |
| + * @idle_slice_timer: timer set when idling for the next sequential request | |
| + * from the queue in service. | |
| + * @unplug_work: delayed work to restart dispatching on the request queue. | |
| + * @in_service_queue: bfq_queue in service. | |
| + * @in_service_bic: bfq_io_cq (bic) associated with the @in_service_queue. | |
| + * @last_position: on-disk position of the last served request. | |
| + * @last_budget_start: beginning of the last budget. | |
| + * @last_idling_start: beginning of the last idle slice. | |
| + * @peak_rate: peak transfer rate observed for a budget. | |
| + * @peak_rate_samples: number of samples used to calculate @peak_rate. | |
| + * @bfq_max_budget: maximum budget allotted to a bfq_queue before | |
| + * rescheduling. | |
| + * @active_list: list of all the bfq_queues active on the device. | |
| + * @idle_list: list of all the bfq_queues idle on the device. | |
| + * @bfq_fifo_expire: timeout for async/sync requests; when it expires | |
| + * requests are served in fifo order. | |
| + * @bfq_back_penalty: weight of backward seeks wrt forward ones. | |
| + * @bfq_back_max: maximum allowed backward seek. | |
| + * @bfq_slice_idle: maximum idling time. | |
| + * @bfq_user_max_budget: user-configured max budget value | |
| + * (0 for auto-tuning). | |
| + * @bfq_max_budget_async_rq: maximum budget (in nr of requests) allotted to | |
| + * async queues. | |
| + * @bfq_timeout: timeout for bfq_queues to consume their budget; used to | |
| + * to prevent seeky queues to impose long latencies to well | |
| + * behaved ones (this also implies that seeky queues cannot | |
| + * receive guarantees in the service domain; after a timeout | |
| + * they are charged for the whole allocated budget, to try | |
| + * to preserve a behavior reasonably fair among them, but | |
| + * without service-domain guarantees). | |
| + * @bfq_coop_thresh: number of queue merges after which a @bfq_queue is | |
| + * no more granted any weight-raising. | |
| + * @bfq_failed_cooperations: number of consecutive failed cooperation | |
| + * chances after which weight-raising is restored | |
| + * to a queue subject to more than bfq_coop_thresh | |
| + * queue merges. | |
| + * @bfq_requests_within_timer: number of consecutive requests that must be | |
| + * issued within the idle time slice to set | |
| + * again idling to a queue which was marked as | |
| + * non-I/O-bound (see the definition of the | |
| + * IO_bound flag for further details). | |
| + * @last_ins_in_burst: last time at which a queue entered the current | |
| + * burst of queues being activated shortly after | |
| + * each other; for more details about this and the | |
| + * following parameters related to a burst of | |
| + * activations, see the comments to the function | |
| + * @bfq_handle_burst. | |
| + * @bfq_burst_interval: reference time interval used to decide whether a | |
| + * queue has been activated shortly after | |
| + * @last_ins_in_burst. | |
| + * @burst_size: number of queues in the current burst of queue activations. | |
| + * @bfq_large_burst_thresh: maximum burst size above which the current | |
| + * queue-activation burst is deemed as 'large'. | |
| + * @large_burst: true if a large queue-activation burst is in progress. | |
| + * @burst_list: head of the burst list (as for the above fields, more details | |
| + * in the comments to the function bfq_handle_burst). | |
| + * @low_latency: if set to true, low-latency heuristics are enabled. | |
| + * @bfq_wr_coeff: maximum factor by which the weight of a weight-raised | |
| + * queue is multiplied. | |
| + * @bfq_wr_max_time: maximum duration of a weight-raising period (jiffies). | |
| + * @bfq_wr_rt_max_time: maximum duration for soft real-time processes. | |
| + * @bfq_wr_min_idle_time: minimum idle period after which weight-raising | |
| + * may be reactivated for a queue (in jiffies). | |
| + * @bfq_wr_min_inter_arr_async: minimum period between request arrivals | |
| + * after which weight-raising may be | |
| + * reactivated for an already busy queue | |
| + * (in jiffies). | |
| + * @bfq_wr_max_softrt_rate: max service-rate for a soft real-time queue, | |
| + * sectors per seconds. | |
| + * @RT_prod: cached value of the product R*T used for computing the maximum | |
| + * duration of the weight raising automatically. | |
| + * @device_speed: device-speed class for the low-latency heuristic. | |
| + * @oom_bfqq: fallback dummy bfqq for extreme OOM conditions. | |
| + * | |
| + * All the fields are protected by the @queue lock. | |
| + */ | |
| +struct bfq_data { | |
| + struct request_queue *queue; | |
| + | |
| + struct bfq_group *root_group; | |
| + | |
| +#ifdef CONFIG_BFQ_GROUP_IOSCHED | |
| + int active_numerous_groups; | |
| +#endif | |
| + | |
| + struct rb_root queue_weights_tree; | |
| + struct rb_root group_weights_tree; | |
| + | |
| + int busy_queues; | |
| + int busy_in_flight_queues; | |
| + int const_seeky_busy_in_flight_queues; | |
| + int wr_busy_queues; | |
| + int queued; | |
| + int rq_in_driver; | |
| + int sync_flight; | |
| + | |
| + int max_rq_in_driver; | |
| + int hw_tag_samples; | |
| + int hw_tag; | |
| + | |
| + int budgets_assigned; | |
| + | |
| + struct timer_list idle_slice_timer; | |
| + struct work_struct unplug_work; | |
| + | |
| + struct bfq_queue *in_service_queue; | |
| + struct bfq_io_cq *in_service_bic; | |
| + | |
| + sector_t last_position; | |
| + | |
| + ktime_t last_budget_start; | |
| + ktime_t last_idling_start; | |
| + int peak_rate_samples; | |
| + u64 peak_rate; | |
| + int bfq_max_budget; | |
| + | |
| + struct list_head active_list; | |
| + struct list_head idle_list; | |
| + | |
| + unsigned int bfq_fifo_expire[2]; | |
| + unsigned int bfq_back_penalty; | |
| + unsigned int bfq_back_max; | |
| + unsigned int bfq_slice_idle; | |
| + u64 bfq_class_idle_last_service; | |
| + | |
| + int bfq_user_max_budget; | |
| + int bfq_max_budget_async_rq; | |
| + unsigned int bfq_timeout[2]; | |
| + | |
| + unsigned int bfq_coop_thresh; | |
| + unsigned int bfq_failed_cooperations; | |
| + unsigned int bfq_requests_within_timer; | |
| + | |
| + unsigned long last_ins_in_burst; | |
| + unsigned long bfq_burst_interval; | |
| + int burst_size; | |
| + unsigned long bfq_large_burst_thresh; | |
| + bool large_burst; | |
| + struct hlist_head burst_list; | |
| + | |
| + bool low_latency; | |
| + | |
| + /* parameters of the low_latency heuristics */ | |
| + unsigned int bfq_wr_coeff; | |
| + unsigned int bfq_wr_max_time; | |
| + unsigned int bfq_wr_rt_max_time; | |
| + unsigned int bfq_wr_min_idle_time; | |
| + unsigned long bfq_wr_min_inter_arr_async; | |
| + unsigned int bfq_wr_max_softrt_rate; | |
| + u64 RT_prod; | |
| + enum bfq_device_speed device_speed; | |
| + | |
| + struct bfq_queue oom_bfqq; | |
| +}; | |
| + | |
| +enum bfqq_state_flags { | |
| + BFQ_BFQQ_FLAG_busy = 0, /* has requests or is in service */ | |
| + BFQ_BFQQ_FLAG_wait_request, /* waiting for a request */ | |
| + BFQ_BFQQ_FLAG_must_alloc, /* must be allowed rq alloc */ | |
| + BFQ_BFQQ_FLAG_fifo_expire, /* FIFO checked in this slice */ | |
| + BFQ_BFQQ_FLAG_idle_window, /* slice idling enabled */ | |
| + BFQ_BFQQ_FLAG_sync, /* synchronous queue */ | |
| + BFQ_BFQQ_FLAG_budget_new, /* no completion with this budget */ | |
| + BFQ_BFQQ_FLAG_IO_bound, /* | |
| + * bfqq has timed-out at least once | |
| + * having consumed at most 2/10 of | |
| + * its budget | |
| + */ | |
| + BFQ_BFQQ_FLAG_in_large_burst, /* | |
| + * bfqq activated in a large burst, | |
| + * see comments to bfq_handle_burst. | |
| + */ | |
| + BFQ_BFQQ_FLAG_constantly_seeky, /* | |
| + * bfqq has proved to be slow and | |
| + * seeky until budget timeout | |
| + */ | |
| + BFQ_BFQQ_FLAG_softrt_update, /* | |
| + * may need softrt-next-start | |
| + * update | |
| + */ | |
| + BFQ_BFQQ_FLAG_coop, /* bfqq is shared */ | |
| + BFQ_BFQQ_FLAG_split_coop, /* shared bfqq will be split */ | |
| + BFQ_BFQQ_FLAG_just_split, /* queue has just been split */ | |
| +}; | |
| + | |
| +#define BFQ_BFQQ_FNS(name) \ | |
| +static void bfq_mark_bfqq_##name(struct bfq_queue *bfqq) \ | |
| +{ \ | |
| + (bfqq)->flags |= (1 << BFQ_BFQQ_FLAG_##name); \ | |
| +} \ | |
| +static void bfq_clear_bfqq_##name(struct bfq_queue *bfqq) \ | |
| +{ \ | |
| + (bfqq)->flags &= ~(1 << BFQ_BFQQ_FLAG_##name); \ | |
| +} \ | |
| +static int bfq_bfqq_##name(const struct bfq_queue *bfqq) \ | |
| +{ \ | |
| + return ((bfqq)->flags & (1 << BFQ_BFQQ_FLAG_##name)) != 0; \ | |
| +} | |
| + | |
| +BFQ_BFQQ_FNS(busy); | |
| +BFQ_BFQQ_FNS(wait_request); | |
| +BFQ_BFQQ_FNS(must_alloc); | |
| +BFQ_BFQQ_FNS(fifo_expire); | |
| +BFQ_BFQQ_FNS(idle_window); | |
| +BFQ_BFQQ_FNS(sync); | |
| +BFQ_BFQQ_FNS(budget_new); | |
| +BFQ_BFQQ_FNS(IO_bound); | |
| +BFQ_BFQQ_FNS(in_large_burst); | |
| +BFQ_BFQQ_FNS(constantly_seeky); | |
| +BFQ_BFQQ_FNS(coop); | |
| +BFQ_BFQQ_FNS(split_coop); | |
| +BFQ_BFQQ_FNS(just_split); | |
| +BFQ_BFQQ_FNS(softrt_update); | |
| +#undef BFQ_BFQQ_FNS | |
| + | |
| +/* Logging facilities. */ | |
| +#define bfq_log_bfqq(bfqd, bfqq, fmt, args...) \ | |
| + blk_add_trace_msg((bfqd)->queue, "bfq%d " fmt, (bfqq)->pid, ##args) | |
| + | |
| +#define bfq_log(bfqd, fmt, args...) \ | |
| + blk_add_trace_msg((bfqd)->queue, "bfq " fmt, ##args) | |
| + | |
| +/* Expiration reasons. */ | |
| +enum bfqq_expiration { | |
| + BFQ_BFQQ_TOO_IDLE = 0, /* | |
| + * queue has been idling for | |
| + * too long | |
| + */ | |
| + BFQ_BFQQ_BUDGET_TIMEOUT, /* budget took too long to be used */ | |
| + BFQ_BFQQ_BUDGET_EXHAUSTED, /* budget consumed */ | |
| + BFQ_BFQQ_NO_MORE_REQUESTS, /* the queue has no more requests */ | |
| +}; | |
| + | |
| +#ifdef CONFIG_BFQ_GROUP_IOSCHED | |
| + | |
| +struct bfqg_stats { | |
| + /* total bytes transferred */ | |
| + struct blkg_rwstat service_bytes; | |
| + /* total IOs serviced, post merge */ | |
| + struct blkg_rwstat serviced; | |
| + /* number of ios merged */ | |
| + struct blkg_rwstat merged; | |
| + /* total time spent on device in ns, may not be accurate w/ queueing */ | |
| + struct blkg_rwstat service_time; | |
| + /* total time spent waiting in scheduler queue in ns */ | |
| + struct blkg_rwstat wait_time; | |
| + /* number of IOs queued up */ | |
| + struct blkg_rwstat queued; | |
| + /* total sectors transferred */ | |
| + struct blkg_stat sectors; | |
| + /* total disk time and nr sectors dispatched by this group */ | |
| + struct blkg_stat time; | |
| + /* time not charged to this cgroup */ | |
| + struct blkg_stat unaccounted_time; | |
| + /* sum of number of ios queued across all samples */ | |
| + struct blkg_stat avg_queue_size_sum; | |
| + /* count of samples taken for average */ | |
| + struct blkg_stat avg_queue_size_samples; | |
| + /* how many times this group has been removed from service tree */ | |
| + struct blkg_stat dequeue; | |
| + /* total time spent waiting for it to be assigned a timeslice. */ | |
| + struct blkg_stat group_wait_time; | |
| + /* time spent idling for this blkcg_gq */ | |
| + struct blkg_stat idle_time; | |
| + /* total time with empty current active q with other requests queued */ | |
| + struct blkg_stat empty_time; | |
| + /* fields after this shouldn't be cleared on stat reset */ | |
| + uint64_t start_group_wait_time; | |
| + uint64_t start_idle_time; | |
| + uint64_t start_empty_time; | |
| + uint16_t flags; | |
| +}; | |
| + | |
| +/* | |
| + * struct bfq_group_data - per-blkcg storage for the blkio subsystem. | |
| + * | |
| + * @ps: @blkcg_policy_storage that this structure inherits | |
| + * @weight: weight of the bfq_group | |
| + */ | |
| +struct bfq_group_data { | |
| + /* must be the first member */ | |
| + struct blkcg_policy_data pd; | |
| + | |
| + unsigned short weight; | |
| +}; | |
| + | |
| +/** | |
| + * struct bfq_group - per (device, cgroup) data structure. | |
| + * @entity: schedulable entity to insert into the parent group sched_data. | |
| + * @sched_data: own sched_data, to contain child entities (they may be | |
| + * both bfq_queues and bfq_groups). | |
| + * @bfqd: the bfq_data for the device this group acts upon. | |
| + * @async_bfqq: array of async queues for all the tasks belonging to | |
| + * the group, one queue per ioprio value per ioprio_class, | |
| + * except for the idle class that has only one queue. | |
| + * @async_idle_bfqq: async queue for the idle class (ioprio is ignored). | |
| + * @my_entity: pointer to @entity, %NULL for the toplevel group; used | |
| + * to avoid too many special cases during group creation/ | |
| + * migration. | |
| + * @active_entities: number of active entities belonging to the group; | |
| + * unused for the root group. Used to know whether there | |
| + * are groups with more than one active @bfq_entity | |
| + * (see the comments to the function | |
| + * bfq_bfqq_must_not_expire()). | |
| + * @rq_pos_tree: rbtree sorted by next_request position, used when | |
| + * determining if two or more queues have interleaving | |
| + * requests (see bfq_find_close_cooperator()). | |
| + * | |
| + * Each (device, cgroup) pair has its own bfq_group, i.e., for each cgroup | |
| + * there is a set of bfq_groups, each one collecting the lower-level | |
| + * entities belonging to the group that are acting on the same device. | |
| + * | |
| + * Locking works as follows: | |
| + * o @bfqd is protected by the queue lock, RCU is used to access it | |
| + * from the readers. | |
| + * o All the other fields are protected by the @bfqd queue lock. | |
| + */ | |
| +struct bfq_group { | |
| + /* must be the first member */ | |
| + struct blkg_policy_data pd; | |
| + | |
| + struct bfq_entity entity; | |
| + struct bfq_sched_data sched_data; | |
| + | |
| + void *bfqd; | |
| + | |
| + struct bfq_queue *async_bfqq[2][IOPRIO_BE_NR]; | |
| + struct bfq_queue *async_idle_bfqq; | |
| + | |
| + struct bfq_entity *my_entity; | |
| + | |
| + int active_entities; | |
| + | |
| + struct rb_root rq_pos_tree; | |
| + | |
| + struct bfqg_stats stats; | |
| + struct bfqg_stats dead_stats; /* stats pushed from dead children */ | |
| +}; | |
| + | |
| +#else | |
| +struct bfq_group { | |
| + struct bfq_sched_data sched_data; | |
| + | |
| + struct bfq_queue *async_bfqq[2][IOPRIO_BE_NR]; | |
| + struct bfq_queue *async_idle_bfqq; | |
| + | |
| + struct rb_root rq_pos_tree; | |
| +}; | |
| +#endif | |
| + | |
| +static struct bfq_queue *bfq_entity_to_bfqq(struct bfq_entity *entity); | |
| + | |
| +static struct bfq_service_tree * | |
| +bfq_entity_service_tree(struct bfq_entity *entity) | |
| +{ | |
| + struct bfq_sched_data *sched_data = entity->sched_data; | |
| + struct bfq_queue *bfqq = bfq_entity_to_bfqq(entity); | |
| + unsigned int idx = bfqq ? bfqq->ioprio_class - 1 : | |
| + BFQ_DEFAULT_GRP_CLASS; | |
| + | |
| + BUG_ON(idx >= BFQ_IOPRIO_CLASSES); | |
| + BUG_ON(sched_data == NULL); | |
| + | |
| + return sched_data->service_tree + idx; | |
| +} | |
| + | |
| +static struct bfq_queue *bic_to_bfqq(struct bfq_io_cq *bic, bool is_sync) | |
| +{ | |
| + return bic->bfqq[is_sync]; | |
| +} | |
| + | |
| +static void bic_set_bfqq(struct bfq_io_cq *bic, struct bfq_queue *bfqq, | |
| + bool is_sync) | |
| +{ | |
| + bic->bfqq[is_sync] = bfqq; | |
| +} | |
| + | |
| +static struct bfq_data *bic_to_bfqd(struct bfq_io_cq *bic) | |
| +{ | |
| + return bic->icq.q->elevator->elevator_data; | |
| +} | |
| + | |
| +/** | |
| + * bfq_get_bfqd_locked - get a lock to a bfqd using a RCU protected pointer. | |
| + * @ptr: a pointer to a bfqd. | |
| + * @flags: storage for the flags to be saved. | |
| + * | |
| + * This function allows bfqg->bfqd to be protected by the | |
| + * queue lock of the bfqd they reference; the pointer is dereferenced | |
| + * under RCU, so the storage for bfqd is assured to be safe as long | |
| + * as the RCU read side critical section does not end. After the | |
| + * bfqd->queue->queue_lock is taken the pointer is rechecked, to be | |
| + * sure that no other writer accessed it. If we raced with a writer, | |
| + * the function returns NULL, with the queue unlocked, otherwise it | |
| + * returns the dereferenced pointer, with the queue locked. | |
| + */ | |
| +static struct bfq_data *bfq_get_bfqd_locked(void **ptr, unsigned long *flags) | |
| +{ | |
| + struct bfq_data *bfqd; | |
| + | |
| + rcu_read_lock(); | |
| + bfqd = rcu_dereference(*(struct bfq_data **)ptr); | |
| + | |
| + if (bfqd != NULL) { | |
| + spin_lock_irqsave(bfqd->queue->queue_lock, *flags); | |
| + if (ptr == NULL) | |
| + printk(KERN_CRIT "get_bfqd_locked pointer NULL\n"); | |
| + else if (*ptr == bfqd) | |
| + goto out; | |
| + spin_unlock_irqrestore(bfqd->queue->queue_lock, *flags); | |
| + } | |
| + | |
| + bfqd = NULL; | |
| +out: | |
| + rcu_read_unlock(); | |
| + return bfqd; | |
| +} | |
| + | |
| +static void bfq_put_bfqd_unlock(struct bfq_data *bfqd, unsigned long *flags) | |
| +{ | |
| + spin_unlock_irqrestore(bfqd->queue->queue_lock, *flags); | |
| +} | |
| + | |
| +#ifdef CONFIG_BFQ_GROUP_IOSCHED | |
| + | |
| +static struct bfq_group *bfq_bfqq_to_bfqg(struct bfq_queue *bfqq) | |
| +{ | |
| + struct bfq_entity *group_entity = bfqq->entity.parent; | |
| + | |
| + if (!group_entity) | |
| + group_entity = &bfqq->bfqd->root_group->entity; | |
| + | |
| + return container_of(group_entity, struct bfq_group, entity); | |
| +} | |
| + | |
| +#else | |
| + | |
| +static struct bfq_group *bfq_bfqq_to_bfqg(struct bfq_queue *bfqq) | |
| +{ | |
| + return bfqq->bfqd->root_group; | |
| +} | |
| + | |
| +#endif | |
| + | |
| +static void bfq_check_ioprio_change(struct bfq_io_cq *bic, struct bio *bio); | |
| +static void bfq_put_queue(struct bfq_queue *bfqq); | |
| +static void bfq_dispatch_insert(struct request_queue *q, struct request *rq); | |
| +static struct bfq_queue *bfq_get_queue(struct bfq_data *bfqd, | |
| + struct bio *bio, int is_sync, | |
| + struct bfq_io_cq *bic, gfp_t gfp_mask); | |
| +static void bfq_end_wr_async_queues(struct bfq_data *bfqd, | |
| + struct bfq_group *bfqg); | |
| +static void bfq_put_async_queues(struct bfq_data *bfqd, struct bfq_group *bfqg); | |
| +static void bfq_exit_bfqq(struct bfq_data *bfqd, struct bfq_queue *bfqq); | |
| + | |
| +#endif /* _BFQ_H */ | |
| diff -x .git -Naur linux-4.4.111/block/bfq-ioc.c linux-4.4.111-alpine/block/bfq-ioc.c | |
| --- linux-4.4.111/block/bfq-ioc.c 1969-12-31 19:00:00.000000000 -0500 | |
| +++ linux-4.4.111-alpine/block/bfq-ioc.c 2018-02-14 21:04:16.000000000 -0500 | |
| @@ -0,0 +1,36 @@ | |
| +/* | |
| + * BFQ: I/O context handling. | |
| + * | |
| + * Based on ideas and code from CFQ: | |
| + * Copyright (C) 2003 Jens Axboe <axboe@kernel.dk> | |
| + * | |
| + * Copyright (C) 2008 Fabio Checconi <fabio@gandalf.sssup.it> | |
| + * Paolo Valente <paolo.valente@unimore.it> | |
| + * | |
| + * Copyright (C) 2010 Paolo Valente <paolo.valente@unimore.it> | |
| + */ | |
| + | |
| +/** | |
| + * icq_to_bic - convert iocontext queue structure to bfq_io_cq. | |
| + * @icq: the iocontext queue. | |
| + */ | |
| +static struct bfq_io_cq *icq_to_bic(struct io_cq *icq) | |
| +{ | |
| + /* bic->icq is the first member, %NULL will convert to %NULL */ | |
| + return container_of(icq, struct bfq_io_cq, icq); | |
| +} | |
| + | |
| +/** | |
| + * bfq_bic_lookup - search into @ioc a bic associated to @bfqd. | |
| + * @bfqd: the lookup key. | |
| + * @ioc: the io_context of the process doing I/O. | |
| + * | |
| + * Queue lock must be held. | |
| + */ | |
| +static struct bfq_io_cq *bfq_bic_lookup(struct bfq_data *bfqd, | |
| + struct io_context *ioc) | |
| +{ | |
| + if (ioc) | |
| + return icq_to_bic(ioc_lookup_icq(ioc, bfqd->queue)); | |
| + return NULL; | |
| +} | |
| diff -x .git -Naur linux-4.4.111/block/bfq-iosched.c linux-4.4.111-alpine/block/bfq-iosched.c | |
| --- linux-4.4.111/block/bfq-iosched.c 1969-12-31 19:00:00.000000000 -0500 | |
| +++ linux-4.4.111-alpine/block/bfq-iosched.c 2018-02-14 21:04:16.000000000 -0500 | |
| @@ -0,0 +1,4413 @@ | |
| +/* | |
| + * Budget Fair Queueing (BFQ) disk scheduler. | |
| + * | |
| + * Based on ideas and code from CFQ: | |
| + * Copyright (C) 2003 Jens Axboe <axboe@kernel.dk> | |
| + * | |
| + * Copyright (C) 2008 Fabio Checconi <fabio@gandalf.sssup.it> | |
| + * Paolo Valente <paolo.valente@unimore.it> | |
| + * | |
| + * Copyright (C) 2010 Paolo Valente <paolo.valente@unimore.it> | |
| + * | |
| + * Licensed under the GPL-2 as detailed in the accompanying COPYING.BFQ | |
| + * file. | |
| + * | |
| + * BFQ is a proportional-share storage-I/O scheduling algorithm based on | |
| + * the slice-by-slice service scheme of CFQ. But BFQ assigns budgets, | |
| + * measured in number of sectors, to processes instead of time slices. The | |
| + * device is not granted to the in-service process for a given time slice, | |
| + * but until it has exhausted its assigned budget. This change from the time | |
| + * to the service domain allows BFQ to distribute the device throughput | |
| + * among processes as desired, without any distortion due to ZBR, workload | |
| + * fluctuations or other factors. BFQ uses an ad hoc internal scheduler, | |
| + * called B-WF2Q+, to schedule processes according to their budgets. More | |
| + * precisely, BFQ schedules queues associated to processes. Thanks to the | |
| + * accurate policy of B-WF2Q+, BFQ can afford to assign high budgets to | |
| + * I/O-bound processes issuing sequential requests (to boost the | |
| + * throughput), and yet guarantee a low latency to interactive and soft | |
| + * real-time applications. | |
| + * | |
| + * BFQ is described in [1], where also a reference to the initial, more | |
| + * theoretical paper on BFQ can be found. The interested reader can find | |
| + * in the latter paper full details on the main algorithm, as well as | |
| + * formulas of the guarantees and formal proofs of all the properties. | |
| + * With respect to the version of BFQ presented in these papers, this | |
| + * implementation adds a few more heuristics, such as the one that | |
| + * guarantees a low latency to soft real-time applications, and a | |
| + * hierarchical extension based on H-WF2Q+. | |
| + * | |
| + * B-WF2Q+ is based on WF2Q+, that is described in [2], together with | |
| + * H-WF2Q+, while the augmented tree used to implement B-WF2Q+ with O(log N) | |
| + * complexity derives from the one introduced with EEVDF in [3]. | |
| + * | |
| + * [1] P. Valente and M. Andreolini, ``Improving Application Responsiveness | |
| + * with the BFQ Disk I/O Scheduler'', | |
| + * Proceedings of the 5th Annual International Systems and Storage | |
| + * Conference (SYSTOR '12), June 2012. | |
| + * | |
| + * http://algogroup.unimo.it/people/paolo/disk_sched/bf1-v1-suite-results.pdf | |
| + * | |
| + * [2] Jon C.R. Bennett and H. Zhang, ``Hierarchical Packet Fair Queueing | |
| + * Algorithms,'' IEEE/ACM Transactions on Networking, 5(5):675-689, | |
| + * Oct 1997. | |
| + * | |
| + * http://www.cs.cmu.edu/~hzhang/papers/TON-97-Oct.ps.gz | |
| + * | |
| + * [3] I. Stoica and H. Abdel-Wahab, ``Earliest Eligible Virtual Deadline | |
| + * First: A Flexible and Accurate Mechanism for Proportional Share | |
| + * Resource Allocation,'' technical report. | |
| + * | |
| + * http://www.cs.berkeley.edu/~istoica/papers/eevdf-tr-95.pdf | |
| + */ | |
| +#include <linux/module.h> | |
| +#include <linux/slab.h> | |
| +#include <linux/blkdev.h> | |
| +#include <linux/cgroup.h> | |
| +#include <linux/elevator.h> | |
| +#include <linux/jiffies.h> | |
| +#include <linux/rbtree.h> | |
| +#include <linux/ioprio.h> | |
| +#include "bfq.h" | |
| +#include "blk.h" | |
| + | |
| +/* Expiration time of sync (0) and async (1) requests, in jiffies. */ | |
| +static const int bfq_fifo_expire[2] = { HZ / 4, HZ / 8 }; | |
| + | |
| +/* Maximum backwards seek, in KiB. */ | |
| +static const int bfq_back_max = 16 * 1024; | |
| + | |
| +/* Penalty of a backwards seek, in number of sectors. */ | |
| +static const int bfq_back_penalty = 2; | |
| + | |
| +/* Idling period duration, in jiffies. */ | |
| +static int bfq_slice_idle = HZ / 125; | |
| + | |
| +/* Minimum number of assigned budgets for which stats are safe to compute. */ | |
| +static const int bfq_stats_min_budgets = 194; | |
| + | |
| +/* Default maximum budget values, in sectors and number of requests. */ | |
| +static const int bfq_default_max_budget = 16 * 1024; | |
| +static const int bfq_max_budget_async_rq = 4; | |
| + | |
| +/* | |
| + * Async to sync throughput distribution is controlled as follows: | |
| + * when an async request is served, the entity is charged the number | |
| + * of sectors of the request, multiplied by the factor below | |
| + */ | |
| +static const int bfq_async_charge_factor = 10; | |
| + | |
| +/* Default timeout values, in jiffies, approximating CFQ defaults. */ | |
| +static const int bfq_timeout_sync = HZ / 8; | |
| +static int bfq_timeout_async = HZ / 25; | |
| + | |
| +struct kmem_cache *bfq_pool; | |
| + | |
| +/* Below this threshold (in ms), we consider thinktime immediate. */ | |
| +#define BFQ_MIN_TT 2 | |
| + | |
| +/* hw_tag detection: parallel requests threshold and min samples needed. */ | |
| +#define BFQ_HW_QUEUE_THRESHOLD 4 | |
| +#define BFQ_HW_QUEUE_SAMPLES 32 | |
| + | |
| +#define BFQQ_SEEK_THR (sector_t)(8 * 1024) | |
| +#define BFQQ_SEEKY(bfqq) ((bfqq)->seek_mean > BFQQ_SEEK_THR) | |
| + | |
| +/* Min samples used for peak rate estimation (for autotuning). */ | |
| +#define BFQ_PEAK_RATE_SAMPLES 32 | |
| + | |
| +/* Shift used for peak rate fixed precision calculations. */ | |
| +#define BFQ_RATE_SHIFT 16 | |
| + | |
| +/* | |
| + * By default, BFQ computes the duration of the weight raising for | |
| + * interactive applications automatically, using the following formula: | |
| + * duration = (R / r) * T, where r is the peak rate of the device, and | |
| + * R and T are two reference parameters. | |
| + * In particular, R is the peak rate of the reference device (see below), | |
| + * and T is a reference time: given the systems that are likely to be | |
| + * installed on the reference device according to its speed class, T is | |
| + * about the maximum time needed, under BFQ and while reading two files in | |
| + * parallel, to load typical large applications on these systems. | |
| + * In practice, the slower/faster the device at hand is, the more/less it | |
| + * takes to load applications with respect to the reference device. | |
| + * Accordingly, the longer/shorter BFQ grants weight raising to interactive | |
| + * applications. | |
| + * | |
| + * BFQ uses four different reference pairs (R, T), depending on: | |
| + * . whether the device is rotational or non-rotational; | |
| + * . whether the device is slow, such as old or portable HDDs, as well as | |
| + * SD cards, or fast, such as newer HDDs and SSDs. | |
| + * | |
| + * The device's speed class is dynamically (re)detected in | |
| + * bfq_update_peak_rate() every time the estimated peak rate is updated. | |
| + * | |
| + * In the following definitions, R_slow[0]/R_fast[0] and T_slow[0]/T_fast[0] | |
| + * are the reference values for a slow/fast rotational device, whereas | |
| + * R_slow[1]/R_fast[1] and T_slow[1]/T_fast[1] are the reference values for | |
| + * a slow/fast non-rotational device. Finally, device_speed_thresh are the | |
| + * thresholds used to switch between speed classes. | |
| + * Both the reference peak rates and the thresholds are measured in | |
| + * sectors/usec, left-shifted by BFQ_RATE_SHIFT. | |
| + */ | |
| +static int R_slow[2] = {1536, 10752}; | |
| +static int R_fast[2] = {17415, 34791}; | |
| +/* | |
| + * To improve readability, a conversion function is used to initialize the | |
| + * following arrays, which entails that they can be initialized only in a | |
| + * function. | |
| + */ | |
| +static int T_slow[2]; | |
| +static int T_fast[2]; | |
| +static int device_speed_thresh[2]; | |
| + | |
| +#define BFQ_SERVICE_TREE_INIT ((struct bfq_service_tree) \ | |
| + { RB_ROOT, RB_ROOT, NULL, NULL, 0, 0 }) | |
| + | |
| +#define RQ_BIC(rq) ((struct bfq_io_cq *) (rq)->elv.priv[0]) | |
| +#define RQ_BFQQ(rq) ((rq)->elv.priv[1]) | |
| + | |
| +static void bfq_schedule_dispatch(struct bfq_data *bfqd); | |
| + | |
| +#include "bfq-ioc.c" | |
| +#include "bfq-sched.c" | |
| +#include "bfq-cgroup.c" | |
| + | |
| +#define bfq_class_idle(bfqq) ((bfqq)->ioprio_class == IOPRIO_CLASS_IDLE) | |
| +#define bfq_class_rt(bfqq) ((bfqq)->ioprio_class == IOPRIO_CLASS_RT) | |
| + | |
| +#define bfq_sample_valid(samples) ((samples) > 80) | |
| + | |
| +/* | |
| + * We regard a request as SYNC, if either it's a read or has the SYNC bit | |
| + * set (in which case it could also be a direct WRITE). | |
| + */ | |
| +static int bfq_bio_sync(struct bio *bio) | |
| +{ | |
| + if (bio_data_dir(bio) == READ || (bio->bi_rw & REQ_SYNC)) | |
| + return 1; | |
| + | |
| + return 0; | |
| +} | |
| + | |
| +/* | |
| + * Scheduler run of queue, if there are requests pending and no one in the | |
| + * driver that will restart queueing. | |
| + */ | |
| +static void bfq_schedule_dispatch(struct bfq_data *bfqd) | |
| +{ | |
| + if (bfqd->queued != 0) { | |
| + bfq_log(bfqd, "schedule dispatch"); | |
| + kblockd_schedule_work(&bfqd->unplug_work); | |
| + } | |
| +} | |
| + | |
| +/* | |
| + * Lifted from AS - choose which of rq1 and rq2 that is best served now. | |
| + * We choose the request that is closesr to the head right now. Distance | |
| + * behind the head is penalized and only allowed to a certain extent. | |
| + */ | |
| +static struct request *bfq_choose_req(struct bfq_data *bfqd, | |
| + struct request *rq1, | |
| + struct request *rq2, | |
| + sector_t last) | |
| +{ | |
| + sector_t s1, s2, d1 = 0, d2 = 0; | |
| + unsigned long back_max; | |
| +#define BFQ_RQ1_WRAP 0x01 /* request 1 wraps */ | |
| +#define BFQ_RQ2_WRAP 0x02 /* request 2 wraps */ | |
| + unsigned wrap = 0; /* bit mask: requests behind the disk head? */ | |
| + | |
| + if (!rq1 || rq1 == rq2) | |
| + return rq2; | |
| + if (!rq2) | |
| + return rq1; | |
| + | |
| + if (rq_is_sync(rq1) && !rq_is_sync(rq2)) | |
| + return rq1; | |
| + else if (rq_is_sync(rq2) && !rq_is_sync(rq1)) | |
| + return rq2; | |
| + if ((rq1->cmd_flags & REQ_META) && !(rq2->cmd_flags & REQ_META)) | |
| + return rq1; | |
| + else if ((rq2->cmd_flags & REQ_META) && !(rq1->cmd_flags & REQ_META)) | |
| + return rq2; | |
| + | |
| + s1 = blk_rq_pos(rq1); | |
| + s2 = blk_rq_pos(rq2); | |
| + | |
| + /* | |
| + * By definition, 1KiB is 2 sectors. | |
| + */ | |
| + back_max = bfqd->bfq_back_max * 2; | |
| + | |
| + /* | |
| + * Strict one way elevator _except_ in the case where we allow | |
| + * short backward seeks which are biased as twice the cost of a | |
| + * similar forward seek. | |
| + */ | |
| + if (s1 >= last) | |
| + d1 = s1 - last; | |
| + else if (s1 + back_max >= last) | |
| + d1 = (last - s1) * bfqd->bfq_back_penalty; | |
| + else | |
| + wrap |= BFQ_RQ1_WRAP; | |
| + | |
| + if (s2 >= last) | |
| + d2 = s2 - last; | |
| + else if (s2 + back_max >= last) | |
| + d2 = (last - s2) * bfqd->bfq_back_penalty; | |
| + else | |
| + wrap |= BFQ_RQ2_WRAP; | |
| + | |
| + /* Found required data */ | |
| + | |
| + /* | |
| + * By doing switch() on the bit mask "wrap" we avoid having to | |
| + * check two variables for all permutations: --> faster! | |
| + */ | |
| + switch (wrap) { | |
| + case 0: /* common case for CFQ: rq1 and rq2 not wrapped */ | |
| + if (d1 < d2) | |
| + return rq1; | |
| + else if (d2 < d1) | |
| + return rq2; | |
| + else { | |
| + if (s1 >= s2) | |
| + return rq1; | |
| + else | |
| + return rq2; | |
| + } | |
| + | |
| + case BFQ_RQ2_WRAP: | |
| + return rq1; | |
| + case BFQ_RQ1_WRAP: | |
| + return rq2; | |
| + case (BFQ_RQ1_WRAP|BFQ_RQ2_WRAP): /* both rqs wrapped */ | |
| + default: | |
| + /* | |
| + * Since both rqs are wrapped, | |
| + * start with the one that's further behind head | |
| + * (--> only *one* back seek required), | |
| + * since back seek takes more time than forward. | |
| + */ | |
| + if (s1 <= s2) | |
| + return rq1; | |
| + else | |
| + return rq2; | |
| + } | |
| +} | |
| + | |
| +static struct bfq_queue * | |
| +bfq_rq_pos_tree_lookup(struct bfq_data *bfqd, struct rb_root *root, | |
| + sector_t sector, struct rb_node **ret_parent, | |
| + struct rb_node ***rb_link) | |
| +{ | |
| + struct rb_node **p, *parent; | |
| + struct bfq_queue *bfqq = NULL; | |
| + | |
| + parent = NULL; | |
| + p = &root->rb_node; | |
| + while (*p) { | |
| + struct rb_node **n; | |
| + | |
| + parent = *p; | |
| + bfqq = rb_entry(parent, struct bfq_queue, pos_node); | |
| + | |
| + /* | |
| + * Sort strictly based on sector. Smallest to the left, | |
| + * largest to the right. | |
| + */ | |
| + if (sector > blk_rq_pos(bfqq->next_rq)) | |
| + n = &(*p)->rb_right; | |
| + else if (sector < blk_rq_pos(bfqq->next_rq)) | |
| + n = &(*p)->rb_left; | |
| + else | |
| + break; | |
| + p = n; | |
| + bfqq = NULL; | |
| + } | |
| + | |
| + *ret_parent = parent; | |
| + if (rb_link) | |
| + *rb_link = p; | |
| + | |
| + bfq_log(bfqd, "rq_pos_tree_lookup %llu: returning %d", | |
| + (long long unsigned)sector, | |
| + bfqq ? bfqq->pid : 0); | |
| + | |
| + return bfqq; | |
| +} | |
| + | |
| +static void bfq_pos_tree_add_move(struct bfq_data *bfqd, struct bfq_queue *bfqq) | |
| +{ | |
| + struct rb_node **p, *parent; | |
| + struct bfq_queue *__bfqq; | |
| + | |
| + if (bfqq->pos_root) { | |
| + rb_erase(&bfqq->pos_node, bfqq->pos_root); | |
| + bfqq->pos_root = NULL; | |
| + } | |
| + | |
| + if (bfq_class_idle(bfqq)) | |
| + return; | |
| + if (!bfqq->next_rq) | |
| + return; | |
| + | |
| + bfqq->pos_root = &bfq_bfqq_to_bfqg(bfqq)->rq_pos_tree; | |
| + __bfqq = bfq_rq_pos_tree_lookup(bfqd, bfqq->pos_root, | |
| + blk_rq_pos(bfqq->next_rq), &parent, &p); | |
| + if (!__bfqq) { | |
| + rb_link_node(&bfqq->pos_node, parent, p); | |
| + rb_insert_color(&bfqq->pos_node, bfqq->pos_root); | |
| + } else | |
| + bfqq->pos_root = NULL; | |
| +} | |
| + | |
| +/* | |
| + * Tell whether there are active queues or groups with differentiated weights. | |
| + */ | |
| +static bool bfq_differentiated_weights(struct bfq_data *bfqd) | |
| +{ | |
| + /* | |
| + * For weights to differ, at least one of the trees must contain | |
| + * at least two nodes. | |
| + */ | |
| + return (!RB_EMPTY_ROOT(&bfqd->queue_weights_tree) && | |
| + (bfqd->queue_weights_tree.rb_node->rb_left || | |
| + bfqd->queue_weights_tree.rb_node->rb_right) | |
| +#ifdef CONFIG_BFQ_GROUP_IOSCHED | |
| + ) || | |
| + (!RB_EMPTY_ROOT(&bfqd->group_weights_tree) && | |
| + (bfqd->group_weights_tree.rb_node->rb_left || | |
| + bfqd->group_weights_tree.rb_node->rb_right) | |
| +#endif | |
| + ); | |
| +} | |
| + | |
| +/* | |
| + * The following function returns true if every queue must receive the | |
| + * same share of the throughput (this condition is used when deciding | |
| + * whether idling may be disabled, see the comments in the function | |
| + * bfq_bfqq_may_idle()). | |
| + * | |
| + * Such a scenario occurs when: | |
| + * 1) all active queues have the same weight, | |
| + * 2) all active groups at the same level in the groups tree have the same | |
| + * weight, | |
| + * 3) all active groups at the same level in the groups tree have the same | |
| + * number of children. | |
| + * | |
| + * Unfortunately, keeping the necessary state for evaluating exactly the | |
| + * above symmetry conditions would be quite complex and time-consuming. | |
| + * Therefore this function evaluates, instead, the following stronger | |
| + * sub-conditions, for which it is much easier to maintain the needed | |
| + * state: | |
| + * 1) all active queues have the same weight, | |
| + * 2) all active groups have the same weight, | |
| + * 3) all active groups have at most one active child each. | |
| + * In particular, the last two conditions are always true if hierarchical | |
| + * support and the cgroups interface are not enabled, thus no state needs | |
| + * to be maintained in this case. | |
| + */ | |
| +static bool bfq_symmetric_scenario(struct bfq_data *bfqd) | |
| +{ | |
| + return | |
| +#ifdef CONFIG_BFQ_GROUP_IOSCHED | |
| + !bfqd->active_numerous_groups && | |
| +#endif | |
| + !bfq_differentiated_weights(bfqd); | |
| +} | |
| + | |
| +/* | |
| + * If the weight-counter tree passed as input contains no counter for | |
| + * the weight of the input entity, then add that counter; otherwise just | |
| + * increment the existing counter. | |
| + * | |
| + * Note that weight-counter trees contain few nodes in mostly symmetric | |
| + * scenarios. For example, if all queues have the same weight, then the | |
| + * weight-counter tree for the queues may contain at most one node. | |
| + * This holds even if low_latency is on, because weight-raised queues | |
| + * are not inserted in the tree. | |
| + * In most scenarios, the rate at which nodes are created/destroyed | |
| + * should be low too. | |
| + */ | |
| +static void bfq_weights_tree_add(struct bfq_data *bfqd, | |
| + struct bfq_entity *entity, | |
| + struct rb_root *root) | |
| +{ | |
| + struct rb_node **new = &(root->rb_node), *parent = NULL; | |
| + | |
| + /* | |
| + * Do not insert if the entity is already associated with a | |
| + * counter, which happens if: | |
| + * 1) the entity is associated with a queue, | |
| + * 2) a request arrival has caused the queue to become both | |
| + * non-weight-raised, and hence change its weight, and | |
| + * backlogged; in this respect, each of the two events | |
| + * causes an invocation of this function, | |
| + * 3) this is the invocation of this function caused by the | |
| + * second event. This second invocation is actually useless, | |
| + * and we handle this fact by exiting immediately. More | |
| + * efficient or clearer solutions might possibly be adopted. | |
| + */ | |
| + if (entity->weight_counter) | |
| + return; | |
| + | |
| + while (*new) { | |
| + struct bfq_weight_counter *__counter = container_of(*new, | |
| + struct bfq_weight_counter, | |
| + weights_node); | |
| + parent = *new; | |
| + | |
| + if (entity->weight == __counter->weight) { | |
| + entity->weight_counter = __counter; | |
| + goto inc_counter; | |
| + } | |
| + if (entity->weight < __counter->weight) | |
| + new = &((*new)->rb_left); | |
| + else | |
| + new = &((*new)->rb_right); | |
| + } | |
| + | |
| + entity->weight_counter = kzalloc(sizeof(struct bfq_weight_counter), | |
| + GFP_ATOMIC); | |
| + entity->weight_counter->weight = entity->weight; | |
| + rb_link_node(&entity->weight_counter->weights_node, parent, new); | |
| + rb_insert_color(&entity->weight_counter->weights_node, root); | |
| + | |
| +inc_counter: | |
| + entity->weight_counter->num_active++; | |
| +} | |
| + | |
| +/* | |
| + * Decrement the weight counter associated with the entity, and, if the | |
| + * counter reaches 0, remove the counter from the tree. | |
| + * See the comments to the function bfq_weights_tree_add() for considerations | |
| + * about overhead. | |
| + */ | |
| +static void bfq_weights_tree_remove(struct bfq_data *bfqd, | |
| + struct bfq_entity *entity, | |
| + struct rb_root *root) | |
| +{ | |
| + if (!entity->weight_counter) | |
| + return; | |
| + | |
| + BUG_ON(RB_EMPTY_ROOT(root)); | |
| + BUG_ON(entity->weight_counter->weight != entity->weight); | |
| + | |
| + BUG_ON(!entity->weight_counter->num_active); | |
| + entity->weight_counter->num_active--; | |
| + if (entity->weight_counter->num_active > 0) | |
| + goto reset_entity_pointer; | |
| + | |
| + rb_erase(&entity->weight_counter->weights_node, root); | |
| + kfree(entity->weight_counter); | |
| + | |
| +reset_entity_pointer: | |
| + entity->weight_counter = NULL; | |
| +} | |
| + | |
| +static struct request *bfq_find_next_rq(struct bfq_data *bfqd, | |
| + struct bfq_queue *bfqq, | |
| + struct request *last) | |
| +{ | |
| + struct rb_node *rbnext = rb_next(&last->rb_node); | |
| + struct rb_node *rbprev = rb_prev(&last->rb_node); | |
| + struct request *next = NULL, *prev = NULL; | |
| + | |
| + BUG_ON(RB_EMPTY_NODE(&last->rb_node)); | |
| + | |
| + if (rbprev) | |
| + prev = rb_entry_rq(rbprev); | |
| + | |
| + if (rbnext) | |
| + next = rb_entry_rq(rbnext); | |
| + else { | |
| + rbnext = rb_first(&bfqq->sort_list); | |
| + if (rbnext && rbnext != &last->rb_node) | |
| + next = rb_entry_rq(rbnext); | |
| + } | |
| + | |
| + return bfq_choose_req(bfqd, next, prev, blk_rq_pos(last)); | |
| +} | |
| + | |
| +/* see the definition of bfq_async_charge_factor for details */ | |
| +static unsigned long bfq_serv_to_charge(struct request *rq, | |
| + struct bfq_queue *bfqq) | |
| +{ | |
| + return blk_rq_sectors(rq) * | |
| + (1 + ((!bfq_bfqq_sync(bfqq)) * (bfqq->wr_coeff == 1) * | |
| + bfq_async_charge_factor)); | |
| +} | |
| + | |
| +/** | |
| + * bfq_updated_next_req - update the queue after a new next_rq selection. | |
| + * @bfqd: the device data the queue belongs to. | |
| + * @bfqq: the queue to update. | |
| + * | |
| + * If the first request of a queue changes we make sure that the queue | |
| + * has enough budget to serve at least its first request (if the | |
| + * request has grown). We do this because if the queue has not enough | |
| + * budget for its first request, it has to go through two dispatch | |
| + * rounds to actually get it dispatched. | |
| + */ | |
| +static void bfq_updated_next_req(struct bfq_data *bfqd, | |
| + struct bfq_queue *bfqq) | |
| +{ | |
| + struct bfq_entity *entity = &bfqq->entity; | |
| + struct bfq_service_tree *st = bfq_entity_service_tree(entity); | |
| + struct request *next_rq = bfqq->next_rq; | |
| + unsigned long new_budget; | |
| + | |
| + if (!next_rq) | |
| + return; | |
| + | |
| + if (bfqq == bfqd->in_service_queue) | |
| + /* | |
| + * In order not to break guarantees, budgets cannot be | |
| + * changed after an entity has been selected. | |
| + */ | |
| + return; | |
| + | |
| + BUG_ON(entity->tree != &st->active); | |
| + BUG_ON(entity == entity->sched_data->in_service_entity); | |
| + | |
| + new_budget = max_t(unsigned long, bfqq->max_budget, | |
| + bfq_serv_to_charge(next_rq, bfqq)); | |
| + if (entity->budget != new_budget) { | |
| + entity->budget = new_budget; | |
| + bfq_log_bfqq(bfqd, bfqq, "updated next rq: new budget %lu", | |
| + new_budget); | |
| + bfq_activate_bfqq(bfqd, bfqq); | |
| + } | |
| +} | |
| + | |
| +static unsigned int bfq_wr_duration(struct bfq_data *bfqd) | |
| +{ | |
| + u64 dur; | |
| + | |
| + if (bfqd->bfq_wr_max_time > 0) | |
| + return bfqd->bfq_wr_max_time; | |
| + | |
| + dur = bfqd->RT_prod; | |
| + do_div(dur, bfqd->peak_rate); | |
| + | |
| + return dur; | |
| +} | |
| + | |
| +static unsigned bfq_bfqq_cooperations(struct bfq_queue *bfqq) | |
| +{ | |
| + return bfqq->bic ? bfqq->bic->cooperations : 0; | |
| +} | |
| + | |
| +static void | |
| +bfq_bfqq_resume_state(struct bfq_queue *bfqq, struct bfq_io_cq *bic) | |
| +{ | |
| + if (bic->saved_idle_window) | |
| + bfq_mark_bfqq_idle_window(bfqq); | |
| + else | |
| + bfq_clear_bfqq_idle_window(bfqq); | |
| + if (bic->saved_IO_bound) | |
| + bfq_mark_bfqq_IO_bound(bfqq); | |
| + else | |
| + bfq_clear_bfqq_IO_bound(bfqq); | |
| + /* Assuming that the flag in_large_burst is already correctly set */ | |
| + if (bic->wr_time_left && bfqq->bfqd->low_latency && | |
| + !bfq_bfqq_in_large_burst(bfqq) && | |
| + bic->cooperations < bfqq->bfqd->bfq_coop_thresh) { | |
| + /* | |
| + * Start a weight raising period with the duration given by | |
| + * the raising_time_left snapshot. | |
| + */ | |
| + if (bfq_bfqq_busy(bfqq)) | |
| + bfqq->bfqd->wr_busy_queues++; | |
| + bfqq->wr_coeff = bfqq->bfqd->bfq_wr_coeff; | |
| + bfqq->wr_cur_max_time = bic->wr_time_left; | |
| + bfqq->last_wr_start_finish = jiffies; | |
| + bfqq->entity.prio_changed = 1; | |
| + } | |
| + /* | |
| + * Clear wr_time_left to prevent bfq_bfqq_save_state() from | |
| + * getting confused about the queue's need of a weight-raising | |
| + * period. | |
| + */ | |
| + bic->wr_time_left = 0; | |
| +} | |
| + | |
| +static int bfqq_process_refs(struct bfq_queue *bfqq) | |
| +{ | |
| + int process_refs, io_refs; | |
| + | |
| + lockdep_assert_held(bfqq->bfqd->queue->queue_lock); | |
| + | |
| + io_refs = bfqq->allocated[READ] + bfqq->allocated[WRITE]; | |
| + process_refs = atomic_read(&bfqq->ref) - io_refs - bfqq->entity.on_st; | |
| + BUG_ON(process_refs < 0); | |
| + return process_refs; | |
| +} | |
| + | |
| +/* Empty burst list and add just bfqq (see comments to bfq_handle_burst) */ | |
| +static void bfq_reset_burst_list(struct bfq_data *bfqd, struct bfq_queue *bfqq) | |
| +{ | |
| + struct bfq_queue *item; | |
| + struct hlist_node *n; | |
| + | |
| + hlist_for_each_entry_safe(item, n, &bfqd->burst_list, burst_list_node) | |
| + hlist_del_init(&item->burst_list_node); | |
| + hlist_add_head(&bfqq->burst_list_node, &bfqd->burst_list); | |
| + bfqd->burst_size = 1; | |
| +} | |
| + | |
| +/* Add bfqq to the list of queues in current burst (see bfq_handle_burst) */ | |
| +static void bfq_add_to_burst(struct bfq_data *bfqd, struct bfq_queue *bfqq) | |
| +{ | |
| + /* Increment burst size to take into account also bfqq */ | |
| + bfqd->burst_size++; | |
| + | |
| + if (bfqd->burst_size == bfqd->bfq_large_burst_thresh) { | |
| + struct bfq_queue *pos, *bfqq_item; | |
| + struct hlist_node *n; | |
| + | |
| + /* | |
| + * Enough queues have been activated shortly after each | |
| + * other to consider this burst as large. | |
| + */ | |
| + bfqd->large_burst = true; | |
| + | |
| + /* | |
| + * We can now mark all queues in the burst list as | |
| + * belonging to a large burst. | |
| + */ | |
| + hlist_for_each_entry(bfqq_item, &bfqd->burst_list, | |
| + burst_list_node) | |
| + bfq_mark_bfqq_in_large_burst(bfqq_item); | |
| + bfq_mark_bfqq_in_large_burst(bfqq); | |
| + | |
| + /* | |
| + * From now on, and until the current burst finishes, any | |
| + * new queue being activated shortly after the last queue | |
| + * was inserted in the burst can be immediately marked as | |
| + * belonging to a large burst. So the burst list is not | |
| + * needed any more. Remove it. | |
| + */ | |
| + hlist_for_each_entry_safe(pos, n, &bfqd->burst_list, | |
| + burst_list_node) | |
| + hlist_del_init(&pos->burst_list_node); | |
| + } else /* burst not yet large: add bfqq to the burst list */ | |
| + hlist_add_head(&bfqq->burst_list_node, &bfqd->burst_list); | |
| +} | |
| + | |
| +/* | |
| + * If many queues happen to become active shortly after each other, then, | |
| + * to help the processes associated to these queues get their job done as | |
| + * soon as possible, it is usually better to not grant either weight-raising | |
| + * or device idling to these queues. In this comment we describe, firstly, | |
| + * the reasons why this fact holds, and, secondly, the next function, which | |
| + * implements the main steps needed to properly mark these queues so that | |
| + * they can then be treated in a different way. | |
| + * | |
| + * As for the terminology, we say that a queue becomes active, i.e., | |
| + * switches from idle to backlogged, either when it is created (as a | |
| + * consequence of the arrival of an I/O request), or, if already existing, | |
| + * when a new request for the queue arrives while the queue is idle. | |
| + * Bursts of activations, i.e., activations of different queues occurring | |
| + * shortly after each other, are typically caused by services or applications | |
| + * that spawn or reactivate many parallel threads/processes. Examples are | |
| + * systemd during boot or git grep. | |
| + * | |
| + * These services or applications benefit mostly from a high throughput: | |
| + * the quicker the requests of the activated queues are cumulatively served, | |
| + * the sooner the target job of these queues gets completed. As a consequence, | |
| + * weight-raising any of these queues, which also implies idling the device | |
| + * for it, is almost always counterproductive: in most cases it just lowers | |
| + * throughput. | |
| + * | |
| + * On the other hand, a burst of activations may be also caused by the start | |
| + * of an application that does not consist in a lot of parallel I/O-bound | |
| + * threads. In fact, with a complex application, the burst may be just a | |
| + * consequence of the fact that several processes need to be executed to | |
| + * start-up the application. To start an application as quickly as possible, | |
| + * the best thing to do is to privilege the I/O related to the application | |
| + * with respect to all other I/O. Therefore, the best strategy to start as | |
| + * quickly as possible an application that causes a burst of activations is | |
| + * to weight-raise all the queues activated during the burst. This is the | |
| + * exact opposite of the best strategy for the other type of bursts. | |
| + * | |
| + * In the end, to take the best action for each of the two cases, the two | |
| + * types of bursts need to be distinguished. Fortunately, this seems | |
| + * relatively easy to do, by looking at the sizes of the bursts. In | |
| + * particular, we found a threshold such that bursts with a larger size | |
| + * than that threshold are apparently caused only by services or commands | |
| + * such as systemd or git grep. For brevity, hereafter we call just 'large' | |
| + * these bursts. BFQ *does not* weight-raise queues whose activations occur | |
| + * in a large burst. In addition, for each of these queues BFQ performs or | |
| + * does not perform idling depending on which choice boosts the throughput | |
| + * most. The exact choice depends on the device and request pattern at | |
| + * hand. | |
| + * | |
| + * Turning back to the next function, it implements all the steps needed | |
| + * to detect the occurrence of a large burst and to properly mark all the | |
| + * queues belonging to it (so that they can then be treated in a different | |
| + * way). This goal is achieved by maintaining a special "burst list" that | |
| + * holds, temporarily, the queues that belong to the burst in progress. The | |
| + * list is then used to mark these queues as belonging to a large burst if | |
| + * the burst does become large. The main steps are the following. | |
| + * | |
| + * . when the very first queue is activated, the queue is inserted into the | |
| + * list (as it could be the first queue in a possible burst) | |
| + * | |
| + * . if the current burst has not yet become large, and a queue Q that does | |
| + * not yet belong to the burst is activated shortly after the last time | |
| + * at which a new queue entered the burst list, then the function appends | |
| + * Q to the burst list | |
| + * | |
| + * . if, as a consequence of the previous step, the burst size reaches | |
| + * the large-burst threshold, then | |
| + * | |
| + * . all the queues in the burst list are marked as belonging to a | |
| + * large burst | |
| + * | |
| + * . the burst list is deleted; in fact, the burst list already served | |
| + * its purpose (keeping temporarily track of the queues in a burst, | |
| + * so as to be able to mark them as belonging to a large burst in the | |
| + * previous sub-step), and now is not needed any more | |
| + * | |
| + * . the device enters a large-burst mode | |
| + * | |
| + * . if a queue Q that does not belong to the burst is activated while | |
| + * the device is in large-burst mode and shortly after the last time | |
| + * at which a queue either entered the burst list or was marked as | |
| + * belonging to the current large burst, then Q is immediately marked | |
| + * as belonging to a large burst. | |
| + * | |
| + * . if a queue Q that does not belong to the burst is activated a while | |
| + * later, i.e., not shortly after, than the last time at which a queue | |
| + * either entered the burst list or was marked as belonging to the | |
| + * current large burst, then the current burst is deemed as finished and: | |
| + * | |
| + * . the large-burst mode is reset if set | |
| + * | |
| + * . the burst list is emptied | |
| + * | |
| + * . Q is inserted in the burst list, as Q may be the first queue | |
| + * in a possible new burst (then the burst list contains just Q | |
| + * after this step). | |
| + */ | |
| +static void bfq_handle_burst(struct bfq_data *bfqd, struct bfq_queue *bfqq, | |
| + bool idle_for_long_time) | |
| +{ | |
| + /* | |
| + * If bfqq happened to be activated in a burst, but has been idle | |
| + * for at least as long as an interactive queue, then we assume | |
| + * that, in the overall I/O initiated in the burst, the I/O | |
| + * associated to bfqq is finished. So bfqq does not need to be | |
| + * treated as a queue belonging to a burst anymore. Accordingly, | |
| + * we reset bfqq's in_large_burst flag if set, and remove bfqq | |
| + * from the burst list if it's there. We do not decrement instead | |
| + * burst_size, because the fact that bfqq does not need to belong | |
| + * to the burst list any more does not invalidate the fact that | |
| + * bfqq may have been activated during the current burst. | |
| + */ | |
| + if (idle_for_long_time) { | |
| + hlist_del_init(&bfqq->burst_list_node); | |
| + bfq_clear_bfqq_in_large_burst(bfqq); | |
| + } | |
| + | |
| + /* | |
| + * If bfqq is already in the burst list or is part of a large | |
| + * burst, then there is nothing else to do. | |
| + */ | |
| + if (!hlist_unhashed(&bfqq->burst_list_node) || | |
| + bfq_bfqq_in_large_burst(bfqq)) | |
| + return; | |
| + | |
| + /* | |
| + * If bfqq's activation happens late enough, then the current | |
| + * burst is finished, and related data structures must be reset. | |
| + * | |
| + * In this respect, consider the special case where bfqq is the very | |
| + * first queue being activated. In this case, last_ins_in_burst is | |
| + * not yet significant when we get here. But it is easy to verify | |
| + * that, whether or not the following condition is true, bfqq will | |
| + * end up being inserted into the burst list. In particular the | |
| + * list will happen to contain only bfqq. And this is exactly what | |
| + * has to happen, as bfqq may be the first queue in a possible | |
| + * burst. | |
| + */ | |
| + if (time_is_before_jiffies(bfqd->last_ins_in_burst + | |
| + bfqd->bfq_burst_interval)) { | |
| + bfqd->large_burst = false; | |
| + bfq_reset_burst_list(bfqd, bfqq); | |
| + return; | |
| + } | |
| + | |
| + /* | |
| + * If we get here, then bfqq is being activated shortly after the | |
| + * last queue. So, if the current burst is also large, we can mark | |
| + * bfqq as belonging to this large burst immediately. | |
| + */ | |
| + if (bfqd->large_burst) { | |
| + bfq_mark_bfqq_in_large_burst(bfqq); | |
| + return; | |
| + } | |
| + | |
| + /* | |
| + * If we get here, then a large-burst state has not yet been | |
| + * reached, but bfqq is being activated shortly after the last | |
| + * queue. Then we add bfqq to the burst. | |
| + */ | |
| + bfq_add_to_burst(bfqd, bfqq); | |
| +} | |
| + | |
| +static void bfq_add_request(struct request *rq) | |
| +{ | |
| + struct bfq_queue *bfqq = RQ_BFQQ(rq); | |
| + struct bfq_entity *entity = &bfqq->entity; | |
| + struct bfq_data *bfqd = bfqq->bfqd; | |
| + struct request *next_rq, *prev; | |
| + unsigned long old_wr_coeff = bfqq->wr_coeff; | |
| + bool interactive = false; | |
| + | |
| + bfq_log_bfqq(bfqd, bfqq, "add_request %d", rq_is_sync(rq)); | |
| + bfqq->queued[rq_is_sync(rq)]++; | |
| + bfqd->queued++; | |
| + | |
| + elv_rb_add(&bfqq->sort_list, rq); | |
| + | |
| + /* | |
| + * Check if this request is a better next-serve candidate. | |
| + */ | |
| + prev = bfqq->next_rq; | |
| + next_rq = bfq_choose_req(bfqd, bfqq->next_rq, rq, bfqd->last_position); | |
| + BUG_ON(!next_rq); | |
| + bfqq->next_rq = next_rq; | |
| + | |
| + /* | |
| + * Adjust priority tree position, if next_rq changes. | |
| + */ | |
| + if (prev != bfqq->next_rq) | |
| + bfq_pos_tree_add_move(bfqd, bfqq); | |
| + | |
| + if (!bfq_bfqq_busy(bfqq)) { | |
| + bool soft_rt, coop_or_in_burst, | |
| + idle_for_long_time = time_is_before_jiffies( | |
| + bfqq->budget_timeout + | |
| + bfqd->bfq_wr_min_idle_time); | |
| + | |
| +#ifdef CONFIG_BFQ_GROUP_IOSCHED | |
| + bfqg_stats_update_io_add(bfqq_group(RQ_BFQQ(rq)), bfqq, | |
| + rq->cmd_flags); | |
| +#endif | |
| + if (bfq_bfqq_sync(bfqq)) { | |
| + bool already_in_burst = | |
| + !hlist_unhashed(&bfqq->burst_list_node) || | |
| + bfq_bfqq_in_large_burst(bfqq); | |
| + bfq_handle_burst(bfqd, bfqq, idle_for_long_time); | |
| + /* | |
| + * If bfqq was not already in the current burst, | |
| + * then, at this point, bfqq either has been | |
| + * added to the current burst or has caused the | |
| + * current burst to terminate. In particular, in | |
| + * the second case, bfqq has become the first | |
| + * queue in a possible new burst. | |
| + * In both cases last_ins_in_burst needs to be | |
| + * moved forward. | |
| + */ | |
| + if (!already_in_burst) | |
| + bfqd->last_ins_in_burst = jiffies; | |
| + } | |
| + | |
| + coop_or_in_burst = bfq_bfqq_in_large_burst(bfqq) || | |
| + bfq_bfqq_cooperations(bfqq) >= bfqd->bfq_coop_thresh; | |
| + soft_rt = bfqd->bfq_wr_max_softrt_rate > 0 && | |
| + !coop_or_in_burst && | |
| + time_is_before_jiffies(bfqq->soft_rt_next_start); | |
| + interactive = !coop_or_in_burst && idle_for_long_time; | |
| + entity->budget = max_t(unsigned long, bfqq->max_budget, | |
| + bfq_serv_to_charge(next_rq, bfqq)); | |
| + | |
| + if (!bfq_bfqq_IO_bound(bfqq)) { | |
| + if (time_before(jiffies, | |
| + RQ_BIC(rq)->ttime.last_end_request + | |
| + bfqd->bfq_slice_idle)) { | |
| + bfqq->requests_within_timer++; | |
| + if (bfqq->requests_within_timer >= | |
| + bfqd->bfq_requests_within_timer) | |
| + bfq_mark_bfqq_IO_bound(bfqq); | |
| + } else | |
| + bfqq->requests_within_timer = 0; | |
| + } | |
| + | |
| + if (!bfqd->low_latency) | |
| + goto add_bfqq_busy; | |
| + | |
| + if (bfq_bfqq_just_split(bfqq)) | |
| + goto set_prio_changed; | |
| + | |
| + /* | |
| + * If the queue: | |
| + * - is not being boosted, | |
| + * - has been idle for enough time, | |
| + * - is not a sync queue or is linked to a bfq_io_cq (it is | |
| + * shared "for its nature" or it is not shared and its | |
| + * requests have not been redirected to a shared queue) | |
| + * start a weight-raising period. | |
| + */ | |
| + if (old_wr_coeff == 1 && (interactive || soft_rt) && | |
| + (!bfq_bfqq_sync(bfqq) || bfqq->bic)) { | |
| + bfqq->wr_coeff = bfqd->bfq_wr_coeff; | |
| + if (interactive) | |
| + bfqq->wr_cur_max_time = bfq_wr_duration(bfqd); | |
| + else | |
| + bfqq->wr_cur_max_time = | |
| + bfqd->bfq_wr_rt_max_time; | |
| + bfq_log_bfqq(bfqd, bfqq, | |
| + "wrais starting at %lu, rais_max_time %u", | |
| + jiffies, | |
| + jiffies_to_msecs(bfqq->wr_cur_max_time)); | |
| + } else if (old_wr_coeff > 1) { | |
| + if (interactive) | |
| + bfqq->wr_cur_max_time = bfq_wr_duration(bfqd); | |
| + else if (coop_or_in_burst || | |
| + (bfqq->wr_cur_max_time == | |
| + bfqd->bfq_wr_rt_max_time && | |
| + !soft_rt)) { | |
| + bfqq->wr_coeff = 1; | |
| + bfq_log_bfqq(bfqd, bfqq, | |
| + "wrais ending at %lu, rais_max_time %u", | |
| + jiffies, | |
| + jiffies_to_msecs(bfqq-> | |
| + wr_cur_max_time)); | |
| + } else if (time_before( | |
| + bfqq->last_wr_start_finish + | |
| + bfqq->wr_cur_max_time, | |
| + jiffies + | |
| + bfqd->bfq_wr_rt_max_time) && | |
| + soft_rt) { | |
| + /* | |
| + * | |
| + * The remaining weight-raising time is lower | |
| + * than bfqd->bfq_wr_rt_max_time, which means | |
| + * that the application is enjoying weight | |
| + * raising either because deemed soft-rt in | |
| + * the near past, or because deemed interactive | |
| + * a long ago. | |
| + * In both cases, resetting now the current | |
| + * remaining weight-raising time for the | |
| + * application to the weight-raising duration | |
| + * for soft rt applications would not cause any | |
| + * latency increase for the application (as the | |
| + * new duration would be higher than the | |
| + * remaining time). | |
| + * | |
| + * In addition, the application is now meeting | |
| + * the requirements for being deemed soft rt. | |
| + * In the end we can correctly and safely | |
| + * (re)charge the weight-raising duration for | |
| + * the application with the weight-raising | |
| + * duration for soft rt applications. | |
| + * | |
| + * In particular, doing this recharge now, i.e., | |
| + * before the weight-raising period for the | |
| + * application finishes, reduces the probability | |
| + * of the following negative scenario: | |
| + * 1) the weight of a soft rt application is | |
| + * raised at startup (as for any newly | |
| + * created application), | |
| + * 2) since the application is not interactive, | |
| + * at a certain time weight-raising is | |
| + * stopped for the application, | |
| + * 3) at that time the application happens to | |
| + * still have pending requests, and hence | |
| + * is destined to not have a chance to be | |
| + * deemed soft rt before these requests are | |
| + * completed (see the comments to the | |
| + * function bfq_bfqq_softrt_next_start() | |
| + * for details on soft rt detection), | |
| + * 4) these pending requests experience a high | |
| + * latency because the application is not | |
| + * weight-raised while they are pending. | |
| + */ | |
| + bfqq->last_wr_start_finish = jiffies; | |
| + bfqq->wr_cur_max_time = | |
| + bfqd->bfq_wr_rt_max_time; | |
| + } | |
| + } | |
| +set_prio_changed: | |
| + if (old_wr_coeff != bfqq->wr_coeff) | |
| + entity->prio_changed = 1; | |
| +add_bfqq_busy: | |
| + bfqq->last_idle_bklogged = jiffies; | |
| + bfqq->service_from_backlogged = 0; | |
| + bfq_clear_bfqq_softrt_update(bfqq); | |
| + bfq_add_bfqq_busy(bfqd, bfqq); | |
| + } else { | |
| + if (bfqd->low_latency && old_wr_coeff == 1 && !rq_is_sync(rq) && | |
| + time_is_before_jiffies( | |
| + bfqq->last_wr_start_finish + | |
| + bfqd->bfq_wr_min_inter_arr_async)) { | |
| + bfqq->wr_coeff = bfqd->bfq_wr_coeff; | |
| + bfqq->wr_cur_max_time = bfq_wr_duration(bfqd); | |
| + | |
| + bfqd->wr_busy_queues++; | |
| + entity->prio_changed = 1; | |
| + bfq_log_bfqq(bfqd, bfqq, | |
| + "non-idle wrais starting at %lu, rais_max_time %u", | |
| + jiffies, | |
| + jiffies_to_msecs(bfqq->wr_cur_max_time)); | |
| + } | |
| + if (prev != bfqq->next_rq) | |
| + bfq_updated_next_req(bfqd, bfqq); | |
| + } | |
| + | |
| + if (bfqd->low_latency && | |
| + (old_wr_coeff == 1 || bfqq->wr_coeff == 1 || interactive)) | |
| + bfqq->last_wr_start_finish = jiffies; | |
| +} | |
| + | |
| +static struct request *bfq_find_rq_fmerge(struct bfq_data *bfqd, | |
| + struct bio *bio) | |
| +{ | |
| + struct task_struct *tsk = current; | |
| + struct bfq_io_cq *bic; | |
| + struct bfq_queue *bfqq; | |
| + | |
| + bic = bfq_bic_lookup(bfqd, tsk->io_context); | |
| + if (!bic) | |
| + return NULL; | |
| + | |
| + bfqq = bic_to_bfqq(bic, bfq_bio_sync(bio)); | |
| + if (bfqq) | |
| + return elv_rb_find(&bfqq->sort_list, bio_end_sector(bio)); | |
| + | |
| + return NULL; | |
| +} | |
| + | |
| +static void bfq_activate_request(struct request_queue *q, struct request *rq) | |
| +{ | |
| + struct bfq_data *bfqd = q->elevator->elevator_data; | |
| + | |
| + bfqd->rq_in_driver++; | |
| + bfqd->last_position = blk_rq_pos(rq) + blk_rq_sectors(rq); | |
| + bfq_log(bfqd, "activate_request: new bfqd->last_position %llu", | |
| + (long long unsigned)bfqd->last_position); | |
| +} | |
| + | |
| +static void bfq_deactivate_request(struct request_queue *q, struct request *rq) | |
| +{ | |
| + struct bfq_data *bfqd = q->elevator->elevator_data; | |
| + | |
| + BUG_ON(bfqd->rq_in_driver == 0); | |
| + bfqd->rq_in_driver--; | |
| +} | |
| + | |
| +static void bfq_remove_request(struct request *rq) | |
| +{ | |
| + struct bfq_queue *bfqq = RQ_BFQQ(rq); | |
| + struct bfq_data *bfqd = bfqq->bfqd; | |
| + const int sync = rq_is_sync(rq); | |
| + | |
| + if (bfqq->next_rq == rq) { | |
| + bfqq->next_rq = bfq_find_next_rq(bfqd, bfqq, rq); | |
| + bfq_updated_next_req(bfqd, bfqq); | |
| + } | |
| + | |
| + if (rq->queuelist.prev != &rq->queuelist) | |
| + list_del_init(&rq->queuelist); | |
| + BUG_ON(bfqq->queued[sync] == 0); | |
| + bfqq->queued[sync]--; | |
| + bfqd->queued--; | |
| + elv_rb_del(&bfqq->sort_list, rq); | |
| + | |
| + if (RB_EMPTY_ROOT(&bfqq->sort_list)) { | |
| + if (bfq_bfqq_busy(bfqq) && bfqq != bfqd->in_service_queue) | |
| + bfq_del_bfqq_busy(bfqd, bfqq, 1); | |
| + /* | |
| + * Remove queue from request-position tree as it is empty. | |
| + */ | |
| + if (bfqq->pos_root) { | |
| + rb_erase(&bfqq->pos_node, bfqq->pos_root); | |
| + bfqq->pos_root = NULL; | |
| + } | |
| + } | |
| + | |
| + if (rq->cmd_flags & REQ_META) { | |
| + BUG_ON(bfqq->meta_pending == 0); | |
| + bfqq->meta_pending--; | |
| + } | |
| +#ifdef CONFIG_BFQ_GROUP_IOSCHED | |
| + bfqg_stats_update_io_remove(bfqq_group(bfqq), rq->cmd_flags); | |
| +#endif | |
| +} | |
| + | |
| +static int bfq_merge(struct request_queue *q, struct request **req, | |
| + struct bio *bio) | |
| +{ | |
| + struct bfq_data *bfqd = q->elevator->elevator_data; | |
| + struct request *__rq; | |
| + | |
| + __rq = bfq_find_rq_fmerge(bfqd, bio); | |
| + if (__rq && elv_rq_merge_ok(__rq, bio)) { | |
| + *req = __rq; | |
| + return ELEVATOR_FRONT_MERGE; | |
| + } | |
| + | |
| + return ELEVATOR_NO_MERGE; | |
| +} | |
| + | |
| +static void bfq_merged_request(struct request_queue *q, struct request *req, | |
| + int type) | |
| +{ | |
| + if (type == ELEVATOR_FRONT_MERGE && | |
| + rb_prev(&req->rb_node) && | |
| + blk_rq_pos(req) < | |
| + blk_rq_pos(container_of(rb_prev(&req->rb_node), | |
| + struct request, rb_node))) { | |
| + struct bfq_queue *bfqq = RQ_BFQQ(req); | |
| + struct bfq_data *bfqd = bfqq->bfqd; | |
| + struct request *prev, *next_rq; | |
| + | |
| + /* Reposition request in its sort_list */ | |
| + elv_rb_del(&bfqq->sort_list, req); | |
| + elv_rb_add(&bfqq->sort_list, req); | |
| + /* Choose next request to be served for bfqq */ | |
| + prev = bfqq->next_rq; | |
| + next_rq = bfq_choose_req(bfqd, bfqq->next_rq, req, | |
| + bfqd->last_position); | |
| + BUG_ON(!next_rq); | |
| + bfqq->next_rq = next_rq; | |
| + /* | |
| + * If next_rq changes, update both the queue's budget to | |
| + * fit the new request and the queue's position in its | |
| + * rq_pos_tree. | |
| + */ | |
| + if (prev != bfqq->next_rq) { | |
| + bfq_updated_next_req(bfqd, bfqq); | |
| + bfq_pos_tree_add_move(bfqd, bfqq); | |
| + } | |
| + } | |
| +} | |
| + | |
| +#ifdef CONFIG_BFQ_GROUP_IOSCHED | |
| +static void bfq_bio_merged(struct request_queue *q, struct request *req, | |
| + struct bio *bio) | |
| +{ | |
| + bfqg_stats_update_io_merged(bfqq_group(RQ_BFQQ(req)), bio->bi_rw); | |
| +} | |
| +#endif | |
| + | |
| +static void bfq_merged_requests(struct request_queue *q, struct request *rq, | |
| + struct request *next) | |
| +{ | |
| + struct bfq_queue *bfqq = RQ_BFQQ(rq), *next_bfqq = RQ_BFQQ(next); | |
| + | |
| + /* | |
| + * If next and rq belong to the same bfq_queue and next is older | |
| + * than rq, then reposition rq in the fifo (by substituting next | |
| + * with rq). Otherwise, if next and rq belong to different | |
| + * bfq_queues, never reposition rq: in fact, we would have to | |
| + * reposition it with respect to next's position in its own fifo, | |
| + * which would most certainly be too expensive with respect to | |
| + * the benefits. | |
| + */ | |
| + if (bfqq == next_bfqq && | |
| + !list_empty(&rq->queuelist) && !list_empty(&next->queuelist) && | |
| + time_before(next->fifo_time, rq->fifo_time)) { | |
| + list_del_init(&rq->queuelist); | |
| + list_replace_init(&next->queuelist, &rq->queuelist); | |
| + rq->fifo_time = next->fifo_time; | |
| + } | |
| + | |
| + if (bfqq->next_rq == next) | |
| + bfqq->next_rq = rq; | |
| + | |
| + bfq_remove_request(next); | |
| +#ifdef CONFIG_BFQ_GROUP_IOSCHED | |
| + bfqg_stats_update_io_merged(bfqq_group(bfqq), next->cmd_flags); | |
| +#endif | |
| +} | |
| + | |
| +/* Must be called with bfqq != NULL */ | |
| +static void bfq_bfqq_end_wr(struct bfq_queue *bfqq) | |
| +{ | |
| + BUG_ON(!bfqq); | |
| + if (bfq_bfqq_busy(bfqq)) | |
| + bfqq->bfqd->wr_busy_queues--; | |
| + bfqq->wr_coeff = 1; | |
| + bfqq->wr_cur_max_time = 0; | |
| + /* Trigger a weight change on the next activation of the queue */ | |
| + bfqq->entity.prio_changed = 1; | |
| +} | |
| + | |
| +static void bfq_end_wr_async_queues(struct bfq_data *bfqd, | |
| + struct bfq_group *bfqg) | |
| +{ | |
| + int i, j; | |
| + | |
| + for (i = 0; i < 2; i++) | |
| + for (j = 0; j < IOPRIO_BE_NR; j++) | |
| + if (bfqg->async_bfqq[i][j]) | |
| + bfq_bfqq_end_wr(bfqg->async_bfqq[i][j]); | |
| + if (bfqg->async_idle_bfqq) | |
| + bfq_bfqq_end_wr(bfqg->async_idle_bfqq); | |
| +} | |
| + | |
| +static void bfq_end_wr(struct bfq_data *bfqd) | |
| +{ | |
| + struct bfq_queue *bfqq; | |
| + | |
| + spin_lock_irq(bfqd->queue->queue_lock); | |
| + | |
| + list_for_each_entry(bfqq, &bfqd->active_list, bfqq_list) | |
| + bfq_bfqq_end_wr(bfqq); | |
| + list_for_each_entry(bfqq, &bfqd->idle_list, bfqq_list) | |
| + bfq_bfqq_end_wr(bfqq); | |
| + bfq_end_wr_async(bfqd); | |
| + | |
| + spin_unlock_irq(bfqd->queue->queue_lock); | |
| +} | |
| + | |
| +static sector_t bfq_io_struct_pos(void *io_struct, bool request) | |
| +{ | |
| + if (request) | |
| + return blk_rq_pos(io_struct); | |
| + else | |
| + return ((struct bio *)io_struct)->bi_iter.bi_sector; | |
| +} | |
| + | |
| +static int bfq_rq_close_to_sector(void *io_struct, bool request, | |
| + sector_t sector) | |
| +{ | |
| + return abs(bfq_io_struct_pos(io_struct, request) - sector) <= | |
| + BFQQ_SEEK_THR; | |
| +} | |
| + | |
| +static struct bfq_queue *bfqq_find_close(struct bfq_data *bfqd, | |
| + struct bfq_queue *bfqq, | |
| + sector_t sector) | |
| +{ | |
| + struct rb_root *root = &bfq_bfqq_to_bfqg(bfqq)->rq_pos_tree; | |
| + struct rb_node *parent, *node; | |
| + struct bfq_queue *__bfqq; | |
| + | |
| + if (RB_EMPTY_ROOT(root)) | |
| + return NULL; | |
| + | |
| + /* | |
| + * First, if we find a request starting at the end of the last | |
| + * request, choose it. | |
| + */ | |
| + __bfqq = bfq_rq_pos_tree_lookup(bfqd, root, sector, &parent, NULL); | |
| + if (__bfqq) | |
| + return __bfqq; | |
| + | |
| + /* | |
| + * If the exact sector wasn't found, the parent of the NULL leaf | |
| + * will contain the closest sector (rq_pos_tree sorted by | |
| + * next_request position). | |
| + */ | |
| + __bfqq = rb_entry(parent, struct bfq_queue, pos_node); | |
| + if (bfq_rq_close_to_sector(__bfqq->next_rq, true, sector)) | |
| + return __bfqq; | |
| + | |
| + if (blk_rq_pos(__bfqq->next_rq) < sector) | |
| + node = rb_next(&__bfqq->pos_node); | |
| + else | |
| + node = rb_prev(&__bfqq->pos_node); | |
| + if (!node) | |
| + return NULL; | |
| + | |
| + __bfqq = rb_entry(node, struct bfq_queue, pos_node); | |
| + if (bfq_rq_close_to_sector(__bfqq->next_rq, true, sector)) | |
| + return __bfqq; | |
| + | |
| + return NULL; | |
| +} | |
| + | |
| +static struct bfq_queue *bfq_find_close_cooperator(struct bfq_data *bfqd, | |
| + struct bfq_queue *cur_bfqq, | |
| + sector_t sector) | |
| +{ | |
| + struct bfq_queue *bfqq; | |
| + | |
| + /* | |
| + * We shall notice if some of the queues are cooperating, | |
| + * e.g., working closely on the same area of the device. In | |
| + * that case, we can group them together and: 1) don't waste | |
| + * time idling, and 2) serve the union of their requests in | |
| + * the best possible order for throughput. | |
| + */ | |
| + bfqq = bfqq_find_close(bfqd, cur_bfqq, sector); | |
| + if (!bfqq || bfqq == cur_bfqq) | |
| + return NULL; | |
| + | |
| + return bfqq; | |
| +} | |
| + | |
| +static struct bfq_queue * | |
| +bfq_setup_merge(struct bfq_queue *bfqq, struct bfq_queue *new_bfqq) | |
| +{ | |
| + int process_refs, new_process_refs; | |
| + struct bfq_queue *__bfqq; | |
| + | |
| + /* | |
| + * If there are no process references on the new_bfqq, then it is | |
| + * unsafe to follow the ->new_bfqq chain as other bfqq's in the chain | |
| + * may have dropped their last reference (not just their last process | |
| + * reference). | |
| + */ | |
| + if (!bfqq_process_refs(new_bfqq)) | |
| + return NULL; | |
| + | |
| + /* Avoid a circular list and skip interim queue merges. */ | |
| + while ((__bfqq = new_bfqq->new_bfqq)) { | |
| + if (__bfqq == bfqq) | |
| + return NULL; | |
| + new_bfqq = __bfqq; | |
| + } | |
| + | |
| + process_refs = bfqq_process_refs(bfqq); | |
| + new_process_refs = bfqq_process_refs(new_bfqq); | |
| + /* | |
| + * If the process for the bfqq has gone away, there is no | |
| + * sense in merging the queues. | |
| + */ | |
| + if (process_refs == 0 || new_process_refs == 0) | |
| + return NULL; | |
| + | |
| + bfq_log_bfqq(bfqq->bfqd, bfqq, "scheduling merge with queue %d", | |
| + new_bfqq->pid); | |
| + | |
| + /* | |
| + * Merging is just a redirection: the requests of the process | |
| + * owning one of the two queues are redirected to the other queue. | |
| + * The latter queue, in its turn, is set as shared if this is the | |
| + * first time that the requests of some process are redirected to | |
| + * it. | |
| + * | |
| + * We redirect bfqq to new_bfqq and not the opposite, because we | |
| + * are in the context of the process owning bfqq, hence we have | |
| + * the io_cq of this process. So we can immediately configure this | |
| + * io_cq to redirect the requests of the process to new_bfqq. | |
| + * | |
| + * NOTE, even if new_bfqq coincides with the in-service queue, the | |
| + * io_cq of new_bfqq is not available, because, if the in-service | |
| + * queue is shared, bfqd->in_service_bic may not point to the | |
| + * io_cq of the in-service queue. | |
| + * Redirecting the requests of the process owning bfqq to the | |
| + * currently in-service queue is in any case the best option, as | |
| + * we feed the in-service queue with new requests close to the | |
| + * last request served and, by doing so, hopefully increase the | |
| + * throughput. | |
| + */ | |
| + bfqq->new_bfqq = new_bfqq; | |
| + atomic_add(process_refs, &new_bfqq->ref); | |
| + return new_bfqq; | |
| +} | |
| + | |
| +static bool bfq_may_be_close_cooperator(struct bfq_queue *bfqq, | |
| + struct bfq_queue *new_bfqq) | |
| +{ | |
| + if (bfq_class_idle(bfqq) || bfq_class_idle(new_bfqq) || | |
| + (bfqq->ioprio_class != new_bfqq->ioprio_class)) | |
| + return false; | |
| + | |
| + /* | |
| + * If either of the queues has already been detected as seeky, | |
| + * then merging it with the other queue is unlikely to lead to | |
| + * sequential I/O. | |
| + */ | |
| + if (BFQQ_SEEKY(bfqq) || BFQQ_SEEKY(new_bfqq)) | |
| + return false; | |
| + | |
| + /* | |
| + * Interleaved I/O is known to be done by (some) applications | |
| + * only for reads, so it does not make sense to merge async | |
| + * queues. | |
| + */ | |
| + if (!bfq_bfqq_sync(bfqq) || !bfq_bfqq_sync(new_bfqq)) | |
| + return false; | |
| + | |
| + return true; | |
| +} | |
| + | |
| +/* | |
| + * Attempt to schedule a merge of bfqq with the currently in-service queue | |
| + * or with a close queue among the scheduled queues. | |
| + * Return NULL if no merge was scheduled, a pointer to the shared bfq_queue | |
| + * structure otherwise. | |
| + * | |
| + * The OOM queue is not allowed to participate to cooperation: in fact, since | |
| + * the requests temporarily redirected to the OOM queue could be redirected | |
| + * again to dedicated queues at any time, the state needed to correctly | |
| + * handle merging with the OOM queue would be quite complex and expensive | |
| + * to maintain. Besides, in such a critical condition as an out of memory, | |
| + * the benefits of queue merging may be little relevant, or even negligible. | |
| + */ | |
| +static struct bfq_queue * | |
| +bfq_setup_cooperator(struct bfq_data *bfqd, struct bfq_queue *bfqq, | |
| + void *io_struct, bool request) | |
| +{ | |
| + struct bfq_queue *in_service_bfqq, *new_bfqq; | |
| + | |
| + if (bfqq->new_bfqq) | |
| + return bfqq->new_bfqq; | |
| + if (!io_struct || unlikely(bfqq == &bfqd->oom_bfqq)) | |
| + return NULL; | |
| + /* If device has only one backlogged bfq_queue, don't search. */ | |
| + if (bfqd->busy_queues == 1) | |
| + return NULL; | |
| + | |
| + in_service_bfqq = bfqd->in_service_queue; | |
| + | |
| + if (!in_service_bfqq || in_service_bfqq == bfqq || | |
| + !bfqd->in_service_bic || | |
| + unlikely(in_service_bfqq == &bfqd->oom_bfqq)) | |
| + goto check_scheduled; | |
| + | |
| + if (bfq_rq_close_to_sector(io_struct, request, bfqd->last_position) && | |
| + bfqq->entity.parent == in_service_bfqq->entity.parent && | |
| + bfq_may_be_close_cooperator(bfqq, in_service_bfqq)) { | |
| + new_bfqq = bfq_setup_merge(bfqq, in_service_bfqq); | |
| + if (new_bfqq) | |
| + return new_bfqq; | |
| + } | |
| + /* | |
| + * Check whether there is a cooperator among currently scheduled | |
| + * queues. The only thing we need is that the bio/request is not | |
| + * NULL, as we need it to establish whether a cooperator exists. | |
| + */ | |
| +check_scheduled: | |
| + new_bfqq = bfq_find_close_cooperator(bfqd, bfqq, | |
| + bfq_io_struct_pos(io_struct, request)); | |
| + | |
| + BUG_ON(new_bfqq && bfqq->entity.parent != new_bfqq->entity.parent); | |
| + | |
| + if (new_bfqq && likely(new_bfqq != &bfqd->oom_bfqq) && | |
| + bfq_may_be_close_cooperator(bfqq, new_bfqq)) | |
| + return bfq_setup_merge(bfqq, new_bfqq); | |
| + | |
| + return NULL; | |
| +} | |
| + | |
| +static void bfq_bfqq_save_state(struct bfq_queue *bfqq) | |
| +{ | |
| + /* | |
| + * If !bfqq->bic, the queue is already shared or its requests | |
| + * have already been redirected to a shared queue; both idle window | |
| + * and weight raising state have already been saved. Do nothing. | |
| + */ | |
| + if (!bfqq->bic) | |
| + return; | |
| + if (bfqq->bic->wr_time_left) | |
| + /* | |
| + * This is the queue of a just-started process, and would | |
| + * deserve weight raising: we set wr_time_left to the full | |
| + * weight-raising duration to trigger weight-raising when | |
| + * and if the queue is split and the first request of the | |
| + * queue is enqueued. | |
| + */ | |
| + bfqq->bic->wr_time_left = bfq_wr_duration(bfqq->bfqd); | |
| + else if (bfqq->wr_coeff > 1) { | |
| + unsigned long wr_duration = | |
| + jiffies - bfqq->last_wr_start_finish; | |
| + /* | |
| + * It may happen that a queue's weight raising period lasts | |
| + * longer than its wr_cur_max_time, as weight raising is | |
| + * handled only when a request is enqueued or dispatched (it | |
| + * does not use any timer). If the weight raising period is | |
| + * about to end, don't save it. | |
| + */ | |
| + if (bfqq->wr_cur_max_time <= wr_duration) | |
| + bfqq->bic->wr_time_left = 0; | |
| + else | |
| + bfqq->bic->wr_time_left = | |
| + bfqq->wr_cur_max_time - wr_duration; | |
| + /* | |
| + * The bfq_queue is becoming shared or the requests of the | |
| + * process owning the queue are being redirected to a shared | |
| + * queue. Stop the weight raising period of the queue, as in | |
| + * both cases it should not be owned by an interactive or | |
| + * soft real-time application. | |
| + */ | |
| + bfq_bfqq_end_wr(bfqq); | |
| + } else | |
| + bfqq->bic->wr_time_left = 0; | |
| + bfqq->bic->saved_idle_window = bfq_bfqq_idle_window(bfqq); | |
| + bfqq->bic->saved_IO_bound = bfq_bfqq_IO_bound(bfqq); | |
| + bfqq->bic->saved_in_large_burst = bfq_bfqq_in_large_burst(bfqq); | |
| + bfqq->bic->was_in_burst_list = !hlist_unhashed(&bfqq->burst_list_node); | |
| + bfqq->bic->cooperations++; | |
| + bfqq->bic->failed_cooperations = 0; | |
| +} | |
| + | |
| +static void bfq_get_bic_reference(struct bfq_queue *bfqq) | |
| +{ | |
| + /* | |
| + * If bfqq->bic has a non-NULL value, the bic to which it belongs | |
| + * is about to begin using a shared bfq_queue. | |
| + */ | |
| + if (bfqq->bic) | |
| + atomic_long_inc(&bfqq->bic->icq.ioc->refcount); | |
| +} | |
| + | |
| +static void | |
| +bfq_merge_bfqqs(struct bfq_data *bfqd, struct bfq_io_cq *bic, | |
| + struct bfq_queue *bfqq, struct bfq_queue *new_bfqq) | |
| +{ | |
| + bfq_log_bfqq(bfqd, bfqq, "merging with queue %lu", | |
| + (long unsigned)new_bfqq->pid); | |
| + /* Save weight raising and idle window of the merged queues */ | |
| + bfq_bfqq_save_state(bfqq); | |
| + bfq_bfqq_save_state(new_bfqq); | |
| + if (bfq_bfqq_IO_bound(bfqq)) | |
| + bfq_mark_bfqq_IO_bound(new_bfqq); | |
| + bfq_clear_bfqq_IO_bound(bfqq); | |
| + /* | |
| + * Grab a reference to the bic, to prevent it from being destroyed | |
| + * before being possibly touched by a bfq_split_bfqq(). | |
| + */ | |
| + bfq_get_bic_reference(bfqq); | |
| + bfq_get_bic_reference(new_bfqq); | |
| + /* | |
| + * Merge queues (that is, let bic redirect its requests to new_bfqq) | |
| + */ | |
| + bic_set_bfqq(bic, new_bfqq, 1); | |
| + bfq_mark_bfqq_coop(new_bfqq); | |
| + /* | |
| + * new_bfqq now belongs to at least two bics (it is a shared queue): | |
| + * set new_bfqq->bic to NULL. bfqq either: | |
| + * - does not belong to any bic any more, and hence bfqq->bic must | |
| + * be set to NULL, or | |
| + * - is a queue whose owning bics have already been redirected to a | |
| + * different queue, hence the queue is destined to not belong to | |
| + * any bic soon and bfqq->bic is already NULL (therefore the next | |
| + * assignment causes no harm). | |
| + */ | |
| + new_bfqq->bic = NULL; | |
| + bfqq->bic = NULL; | |
| + bfq_put_queue(bfqq); | |
| +} | |
| + | |
| +static void bfq_bfqq_increase_failed_cooperations(struct bfq_queue *bfqq) | |
| +{ | |
| + struct bfq_io_cq *bic = bfqq->bic; | |
| + struct bfq_data *bfqd = bfqq->bfqd; | |
| + | |
| + if (bic && bfq_bfqq_cooperations(bfqq) >= bfqd->bfq_coop_thresh) { | |
| + bic->failed_cooperations++; | |
| + if (bic->failed_cooperations >= bfqd->bfq_failed_cooperations) | |
| + bic->cooperations = 0; | |
| + } | |
| +} | |
| + | |
| +static int bfq_allow_merge(struct request_queue *q, struct request *rq, | |
| + struct bio *bio) | |
| +{ | |
| + struct bfq_data *bfqd = q->elevator->elevator_data; | |
| + struct bfq_io_cq *bic; | |
| + struct bfq_queue *bfqq, *new_bfqq; | |
| + | |
| + /* | |
| + * Disallow merge of a sync bio into an async request. | |
| + */ | |
| + if (bfq_bio_sync(bio) && !rq_is_sync(rq)) | |
| + return 0; | |
| + | |
| + /* | |
| + * Lookup the bfqq that this bio will be queued with. Allow | |
| + * merge only if rq is queued there. | |
| + * Queue lock is held here. | |
| + */ | |
| + bic = bfq_bic_lookup(bfqd, current->io_context); | |
| + if (!bic) | |
| + return 0; | |
| + | |
| + bfqq = bic_to_bfqq(bic, bfq_bio_sync(bio)); | |
| + /* | |
| + * We take advantage of this function to perform an early merge | |
| + * of the queues of possible cooperating processes. | |
| + */ | |
| + if (bfqq) { | |
| + new_bfqq = bfq_setup_cooperator(bfqd, bfqq, bio, false); | |
| + if (new_bfqq) { | |
| + bfq_merge_bfqqs(bfqd, bic, bfqq, new_bfqq); | |
| + /* | |
| + * If we get here, the bio will be queued in the | |
| + * shared queue, i.e., new_bfqq, so use new_bfqq | |
| + * to decide whether bio and rq can be merged. | |
| + */ | |
| + bfqq = new_bfqq; | |
| + } else | |
| + bfq_bfqq_increase_failed_cooperations(bfqq); | |
| + } | |
| + | |
| + return bfqq == RQ_BFQQ(rq); | |
| +} | |
| + | |
| +static void __bfq_set_in_service_queue(struct bfq_data *bfqd, | |
| + struct bfq_queue *bfqq) | |
| +{ | |
| + if (bfqq) { | |
| +#ifdef CONFIG_BFQ_GROUP_IOSCHED | |
| + bfqg_stats_update_avg_queue_size(bfqq_group(bfqq)); | |
| +#endif | |
| + bfq_mark_bfqq_must_alloc(bfqq); | |
| + bfq_mark_bfqq_budget_new(bfqq); | |
| + bfq_clear_bfqq_fifo_expire(bfqq); | |
| + | |
| + bfqd->budgets_assigned = (bfqd->budgets_assigned*7 + 256) / 8; | |
| + | |
| + bfq_log_bfqq(bfqd, bfqq, | |
| + "set_in_service_queue, cur-budget = %d", | |
| + bfqq->entity.budget); | |
| + } | |
| + | |
| + bfqd->in_service_queue = bfqq; | |
| +} | |
| + | |
| +/* | |
| + * Get and set a new queue for service. | |
| + */ | |
| +static struct bfq_queue *bfq_set_in_service_queue(struct bfq_data *bfqd) | |
| +{ | |
| + struct bfq_queue *bfqq = bfq_get_next_queue(bfqd); | |
| + | |
| + __bfq_set_in_service_queue(bfqd, bfqq); | |
| + return bfqq; | |
| +} | |
| + | |
| +/* | |
| + * If enough samples have been computed, return the current max budget | |
| + * stored in bfqd, which is dynamically updated according to the | |
| + * estimated disk peak rate; otherwise return the default max budget | |
| + */ | |
| +static int bfq_max_budget(struct bfq_data *bfqd) | |
| +{ | |
| + if (bfqd->budgets_assigned < bfq_stats_min_budgets) | |
| + return bfq_default_max_budget; | |
| + else | |
| + return bfqd->bfq_max_budget; | |
| +} | |
| + | |
| +/* | |
| + * Return min budget, which is a fraction of the current or default | |
| + * max budget (trying with 1/32) | |
| + */ | |
| +static int bfq_min_budget(struct bfq_data *bfqd) | |
| +{ | |
| + if (bfqd->budgets_assigned < bfq_stats_min_budgets) | |
| + return bfq_default_max_budget / 32; | |
| + else | |
| + return bfqd->bfq_max_budget / 32; | |
| +} | |
| + | |
| +static void bfq_arm_slice_timer(struct bfq_data *bfqd) | |
| +{ | |
| + struct bfq_queue *bfqq = bfqd->in_service_queue; | |
| + struct bfq_io_cq *bic; | |
| + unsigned long sl; | |
| + | |
| + BUG_ON(!RB_EMPTY_ROOT(&bfqq->sort_list)); | |
| + | |
| + /* Processes have exited, don't wait. */ | |
| + bic = bfqd->in_service_bic; | |
| + if (!bic || atomic_read(&bic->icq.ioc->active_ref) == 0) | |
| + return; | |
| + | |
| + bfq_mark_bfqq_wait_request(bfqq); | |
| + | |
| + /* | |
| + * We don't want to idle for seeks, but we do want to allow | |
| + * fair distribution of slice time for a process doing back-to-back | |
| + * seeks. So allow a little bit of time for him to submit a new rq. | |
| + * | |
| + * To prevent processes with (partly) seeky workloads from | |
| + * being too ill-treated, grant them a small fraction of the | |
| + * assigned budget before reducing the waiting time to | |
| + * BFQ_MIN_TT. This happened to help reduce latency. | |
| + */ | |
| + sl = bfqd->bfq_slice_idle; | |
| + /* | |
| + * Unless the queue is being weight-raised or the scenario is | |
| + * asymmetric, grant only minimum idle time if the queue either | |
| + * has been seeky for long enough or has already proved to be | |
| + * constantly seeky. | |
| + */ | |
| + if (bfq_sample_valid(bfqq->seek_samples) && | |
| + ((BFQQ_SEEKY(bfqq) && bfqq->entity.service > | |
| + bfq_max_budget(bfqq->bfqd) / 8) || | |
| + bfq_bfqq_constantly_seeky(bfqq)) && bfqq->wr_coeff == 1 && | |
| + bfq_symmetric_scenario(bfqd)) | |
| + sl = min(sl, msecs_to_jiffies(BFQ_MIN_TT)); | |
| + else if (bfqq->wr_coeff > 1) | |
| + sl = sl * 3; | |
| + bfqd->last_idling_start = ktime_get(); | |
| + mod_timer(&bfqd->idle_slice_timer, jiffies + sl); | |
| +#ifdef CONFIG_BFQ_GROUP_IOSCHED | |
| + bfqg_stats_set_start_idle_time(bfqq_group(bfqq)); | |
| +#endif | |
| + bfq_log(bfqd, "arm idle: %u/%u ms", | |
| + jiffies_to_msecs(sl), jiffies_to_msecs(bfqd->bfq_slice_idle)); | |
| +} | |
| + | |
| +/* | |
| + * Set the maximum time for the in-service queue to consume its | |
| + * budget. This prevents seeky processes from lowering the disk | |
| + * throughput (always guaranteed with a time slice scheme as in CFQ). | |
| + */ | |
| +static void bfq_set_budget_timeout(struct bfq_data *bfqd) | |
| +{ | |
| + struct bfq_queue *bfqq = bfqd->in_service_queue; | |
| + unsigned int timeout_coeff; | |
| + if (bfqq->wr_cur_max_time == bfqd->bfq_wr_rt_max_time) | |
| + timeout_coeff = 1; | |
| + else | |
| + timeout_coeff = bfqq->entity.weight / bfqq->entity.orig_weight; | |
| + | |
| + bfqd->last_budget_start = ktime_get(); | |
| + | |
| + bfq_clear_bfqq_budget_new(bfqq); | |
| + bfqq->budget_timeout = jiffies + | |
| + bfqd->bfq_timeout[bfq_bfqq_sync(bfqq)] * timeout_coeff; | |
| + | |
| + bfq_log_bfqq(bfqd, bfqq, "set budget_timeout %u", | |
| + jiffies_to_msecs(bfqd->bfq_timeout[bfq_bfqq_sync(bfqq)] * | |
| + timeout_coeff)); | |
| +} | |
| + | |
| +/* | |
| + * Move request from internal lists to the request queue dispatch list. | |
| + */ | |
| +static void bfq_dispatch_insert(struct request_queue *q, struct request *rq) | |
| +{ | |
| + struct bfq_data *bfqd = q->elevator->elevator_data; | |
| + struct bfq_queue *bfqq = RQ_BFQQ(rq); | |
| + | |
| + /* | |
| + * For consistency, the next instruction should have been executed | |
| + * after removing the request from the queue and dispatching it. | |
| + * We execute instead this instruction before bfq_remove_request() | |
| + * (and hence introduce a temporary inconsistency), for efficiency. | |
| + * In fact, in a forced_dispatch, this prevents two counters related | |
| + * to bfqq->dispatched to risk to be uselessly decremented if bfqq | |
| + * is not in service, and then to be incremented again after | |
| + * incrementing bfqq->dispatched. | |
| + */ | |
| + bfqq->dispatched++; | |
| + bfq_remove_request(rq); | |
| + elv_dispatch_sort(q, rq); | |
| + | |
| + if (bfq_bfqq_sync(bfqq)) | |
| + bfqd->sync_flight++; | |
| +#ifdef CONFIG_BFQ_GROUP_IOSCHED | |
| + bfqg_stats_update_dispatch(bfqq_group(bfqq), blk_rq_bytes(rq), | |
| + rq->cmd_flags); | |
| +#endif | |
| +} | |
| + | |
| +/* | |
| + * Return expired entry, or NULL to just start from scratch in rbtree. | |
| + */ | |
| +static struct request *bfq_check_fifo(struct bfq_queue *bfqq) | |
| +{ | |
| + struct request *rq = NULL; | |
| + | |
| + if (bfq_bfqq_fifo_expire(bfqq)) | |
| + return NULL; | |
| + | |
| + bfq_mark_bfqq_fifo_expire(bfqq); | |
| + | |
| + if (list_empty(&bfqq->fifo)) | |
| + return NULL; | |
| + | |
| + rq = rq_entry_fifo(bfqq->fifo.next); | |
| + | |
| + if (time_before(jiffies, rq->fifo_time)) | |
| + return NULL; | |
| + | |
| + return rq; | |
| +} | |
| + | |
| +static int bfq_bfqq_budget_left(struct bfq_queue *bfqq) | |
| +{ | |
| + struct bfq_entity *entity = &bfqq->entity; | |
| + return entity->budget - entity->service; | |
| +} | |
| + | |
| +static void __bfq_bfqq_expire(struct bfq_data *bfqd, struct bfq_queue *bfqq) | |
| +{ | |
| + BUG_ON(bfqq != bfqd->in_service_queue); | |
| + | |
| + __bfq_bfqd_reset_in_service(bfqd); | |
| + | |
| + /* | |
| + * If this bfqq is shared between multiple processes, check | |
| + * to make sure that those processes are still issuing I/Os | |
| + * within the mean seek distance. If not, it may be time to | |
| + * break the queues apart again. | |
| + */ | |
| + if (bfq_bfqq_coop(bfqq) && BFQQ_SEEKY(bfqq)) | |
| + bfq_mark_bfqq_split_coop(bfqq); | |
| + | |
| + if (RB_EMPTY_ROOT(&bfqq->sort_list)) { | |
| + /* | |
| + * Overloading budget_timeout field to store the time | |
| + * at which the queue remains with no backlog; used by | |
| + * the weight-raising mechanism. | |
| + */ | |
| + bfqq->budget_timeout = jiffies; | |
| + bfq_del_bfqq_busy(bfqd, bfqq, 1); | |
| + } else { | |
| + bfq_activate_bfqq(bfqd, bfqq); | |
| + /* | |
| + * Resort priority tree of potential close cooperators. | |
| + */ | |
| + bfq_pos_tree_add_move(bfqd, bfqq); | |
| + } | |
| +} | |
| + | |
| +/** | |
| + * __bfq_bfqq_recalc_budget - try to adapt the budget to the @bfqq behavior. | |
| + * @bfqd: device data. | |
| + * @bfqq: queue to update. | |
| + * @reason: reason for expiration. | |
| + * | |
| + * Handle the feedback on @bfqq budget at queue expiration. | |
| + * See the body for detailed comments. | |
| + */ | |
| +static void __bfq_bfqq_recalc_budget(struct bfq_data *bfqd, | |
| + struct bfq_queue *bfqq, | |
| + enum bfqq_expiration reason) | |
| +{ | |
| + struct request *next_rq; | |
| + int budget, min_budget; | |
| + | |
| + budget = bfqq->max_budget; | |
| + min_budget = bfq_min_budget(bfqd); | |
| + | |
| + BUG_ON(bfqq != bfqd->in_service_queue); | |
| + | |
| + bfq_log_bfqq(bfqd, bfqq, "recalc_budg: last budg %d, budg left %d", | |
| + bfqq->entity.budget, bfq_bfqq_budget_left(bfqq)); | |
| + bfq_log_bfqq(bfqd, bfqq, "recalc_budg: last max_budg %d, min budg %d", | |
| + budget, bfq_min_budget(bfqd)); | |
| + bfq_log_bfqq(bfqd, bfqq, "recalc_budg: sync %d, seeky %d", | |
| + bfq_bfqq_sync(bfqq), BFQQ_SEEKY(bfqd->in_service_queue)); | |
| + | |
| + if (bfq_bfqq_sync(bfqq)) { | |
| + switch (reason) { | |
| + /* | |
| + * Caveat: in all the following cases we trade latency | |
| + * for throughput. | |
| + */ | |
| + case BFQ_BFQQ_TOO_IDLE: | |
| + /* | |
| + * This is the only case where we may reduce | |
| + * the budget: if there is no request of the | |
| + * process still waiting for completion, then | |
| + * we assume (tentatively) that the timer has | |
| + * expired because the batch of requests of | |
| + * the process could have been served with a | |
| + * smaller budget. Hence, betting that | |
| + * process will behave in the same way when it | |
| + * becomes backlogged again, we reduce its | |
| + * next budget. As long as we guess right, | |
| + * this budget cut reduces the latency | |
| + * experienced by the process. | |
| + * | |
| + * However, if there are still outstanding | |
| + * requests, then the process may have not yet | |
| + * issued its next request just because it is | |
| + * still waiting for the completion of some of | |
| + * the still outstanding ones. So in this | |
| + * subcase we do not reduce its budget, on the | |
| + * contrary we increase it to possibly boost | |
| + * the throughput, as discussed in the | |
| + * comments to the BUDGET_TIMEOUT case. | |
| + */ | |
| + if (bfqq->dispatched > 0) /* still outstanding reqs */ | |
| + budget = min(budget * 2, bfqd->bfq_max_budget); | |
| + else { | |
| + if (budget > 5 * min_budget) | |
| + budget -= 4 * min_budget; | |
| + else | |
| + budget = min_budget; | |
| + } | |
| + break; | |
| + case BFQ_BFQQ_BUDGET_TIMEOUT: | |
| + /* | |
| + * We double the budget here because: 1) it | |
| + * gives the chance to boost the throughput if | |
| + * this is not a seeky process (which may have | |
| + * bumped into this timeout because of, e.g., | |
| + * ZBR), 2) together with charge_full_budget | |
| + * it helps give seeky processes higher | |
| + * timestamps, and hence be served less | |
| + * frequently. | |
| + */ | |
| + budget = min(budget * 2, bfqd->bfq_max_budget); | |
| + break; | |
| + case BFQ_BFQQ_BUDGET_EXHAUSTED: | |
| + /* | |
| + * The process still has backlog, and did not | |
| + * let either the budget timeout or the disk | |
| + * idling timeout expire. Hence it is not | |
| + * seeky, has a short thinktime and may be | |
| + * happy with a higher budget too. So | |
| + * definitely increase the budget of this good | |
| + * candidate to boost the disk throughput. | |
| + */ | |
| + budget = min(budget * 4, bfqd->bfq_max_budget); | |
| + break; | |
| + case BFQ_BFQQ_NO_MORE_REQUESTS: | |
| + /* | |
| + * Leave the budget unchanged. | |
| + */ | |
| + default: | |
| + return; | |
| + } | |
| + } else | |
| + /* | |
| + * Async queues get always the maximum possible budget | |
| + * (their ability to dispatch is limited by | |
| + * @bfqd->bfq_max_budget_async_rq). | |
| + */ | |
| + budget = bfqd->bfq_max_budget; | |
| + | |
| + bfqq->max_budget = budget; | |
| + | |
| + if (bfqd->budgets_assigned >= bfq_stats_min_budgets && | |
| + !bfqd->bfq_user_max_budget) | |
| + bfqq->max_budget = min(bfqq->max_budget, bfqd->bfq_max_budget); | |
| + | |
| + /* | |
| + * Make sure that we have enough budget for the next request. | |
| + * Since the finish time of the bfqq must be kept in sync with | |
| + * the budget, be sure to call __bfq_bfqq_expire() after the | |
| + * update. | |
| + */ | |
| + next_rq = bfqq->next_rq; | |
| + if (next_rq) | |
| + bfqq->entity.budget = max_t(unsigned long, bfqq->max_budget, | |
| + bfq_serv_to_charge(next_rq, bfqq)); | |
| + else | |
| + bfqq->entity.budget = bfqq->max_budget; | |
| + | |
| + bfq_log_bfqq(bfqd, bfqq, "head sect: %u, new budget %d", | |
| + next_rq ? blk_rq_sectors(next_rq) : 0, | |
| + bfqq->entity.budget); | |
| +} | |
| + | |
| +static unsigned long bfq_calc_max_budget(u64 peak_rate, u64 timeout) | |
| +{ | |
| + unsigned long max_budget; | |
| + | |
| + /* | |
| + * The max_budget calculated when autotuning is equal to the | |
| + * amount of sectors transfered in timeout_sync at the | |
| + * estimated peak rate. | |
| + */ | |
| + max_budget = (unsigned long)(peak_rate * 1000 * | |
| + timeout >> BFQ_RATE_SHIFT); | |
| + | |
| + return max_budget; | |
| +} | |
| + | |
| +/* | |
| + * In addition to updating the peak rate, checks whether the process | |
| + * is "slow", and returns 1 if so. This slow flag is used, in addition | |
| + * to the budget timeout, to reduce the amount of service provided to | |
| + * seeky processes, and hence reduce their chances to lower the | |
| + * throughput. See the code for more details. | |
| + */ | |
| +static bool bfq_update_peak_rate(struct bfq_data *bfqd, struct bfq_queue *bfqq, | |
| + bool compensate, enum bfqq_expiration reason) | |
| +{ | |
| + u64 bw, usecs, expected, timeout; | |
| + ktime_t delta; | |
| + int update = 0; | |
| + | |
| + if (!bfq_bfqq_sync(bfqq) || bfq_bfqq_budget_new(bfqq)) | |
| + return false; | |
| + | |
| + if (compensate) | |
| + delta = bfqd->last_idling_start; | |
| + else | |
| + delta = ktime_get(); | |
| + delta = ktime_sub(delta, bfqd->last_budget_start); | |
| + usecs = ktime_to_us(delta); | |
| + | |
| + /* Don't trust short/unrealistic values. */ | |
| + if (usecs < 100 || usecs >= LONG_MAX) | |
| + return false; | |
| + | |
| + /* | |
| + * Calculate the bandwidth for the last slice. We use a 64 bit | |
| + * value to store the peak rate, in sectors per usec in fixed | |
| + * point math. We do so to have enough precision in the estimate | |
| + * and to avoid overflows. | |
| + */ | |
| + bw = (u64)bfqq->entity.service << BFQ_RATE_SHIFT; | |
| + do_div(bw, (unsigned long)usecs); | |
| + | |
| + timeout = jiffies_to_msecs(bfqd->bfq_timeout[BLK_RW_SYNC]); | |
| + | |
| + /* | |
| + * Use only long (> 20ms) intervals to filter out spikes for | |
| + * the peak rate estimation. | |
| + */ | |
| + if (usecs > 20000) { | |
| + if (bw > bfqd->peak_rate || | |
| + (!BFQQ_SEEKY(bfqq) && | |
| + reason == BFQ_BFQQ_BUDGET_TIMEOUT)) { | |
| + bfq_log(bfqd, "measured bw =%llu", bw); | |
| + /* | |
| + * To smooth oscillations use a low-pass filter with | |
| + * alpha=7/8, i.e., | |
| + * new_rate = (7/8) * old_rate + (1/8) * bw | |
| + */ | |
| + do_div(bw, 8); | |
| + if (bw == 0) | |
| + return 0; | |
| + bfqd->peak_rate *= 7; | |
| + do_div(bfqd->peak_rate, 8); | |
| + bfqd->peak_rate += bw; | |
| + update = 1; | |
| + bfq_log(bfqd, "new peak_rate=%llu", bfqd->peak_rate); | |
| + } | |
| + | |
| + update |= bfqd->peak_rate_samples == BFQ_PEAK_RATE_SAMPLES - 1; | |
| + | |
| + if (bfqd->peak_rate_samples < BFQ_PEAK_RATE_SAMPLES) | |
| + bfqd->peak_rate_samples++; | |
| + | |
| + if (bfqd->peak_rate_samples == BFQ_PEAK_RATE_SAMPLES && | |
| + update) { | |
| + int dev_type = blk_queue_nonrot(bfqd->queue); | |
| + if (bfqd->bfq_user_max_budget == 0) { | |
| + bfqd->bfq_max_budget = | |
| + bfq_calc_max_budget(bfqd->peak_rate, | |
| + timeout); | |
| + bfq_log(bfqd, "new max_budget=%d", | |
| + bfqd->bfq_max_budget); | |
| + } | |
| + if (bfqd->device_speed == BFQ_BFQD_FAST && | |
| + bfqd->peak_rate < device_speed_thresh[dev_type]) { | |
| + bfqd->device_speed = BFQ_BFQD_SLOW; | |
| + bfqd->RT_prod = R_slow[dev_type] * | |
| + T_slow[dev_type]; | |
| + } else if (bfqd->device_speed == BFQ_BFQD_SLOW && | |
| + bfqd->peak_rate > device_speed_thresh[dev_type]) { | |
| + bfqd->device_speed = BFQ_BFQD_FAST; | |
| + bfqd->RT_prod = R_fast[dev_type] * | |
| + T_fast[dev_type]; | |
| + } | |
| + } | |
| + } | |
| + | |
| + /* | |
| + * If the process has been served for a too short time | |
| + * interval to let its possible sequential accesses prevail on | |
| + * the initial seek time needed to move the disk head on the | |
| + * first sector it requested, then give the process a chance | |
| + * and for the moment return false. | |
| + */ | |
| + if (bfqq->entity.budget <= bfq_max_budget(bfqd) / 8) | |
| + return false; | |
| + | |
| + /* | |
| + * A process is considered ``slow'' (i.e., seeky, so that we | |
| + * cannot treat it fairly in the service domain, as it would | |
| + * slow down too much the other processes) if, when a slice | |
| + * ends for whatever reason, it has received service at a | |
| + * rate that would not be high enough to complete the budget | |
| + * before the budget timeout expiration. | |
| + */ | |
| + expected = bw * 1000 * timeout >> BFQ_RATE_SHIFT; | |
| + | |
| + /* | |
| + * Caveat: processes doing IO in the slower disk zones will | |
| + * tend to be slow(er) even if not seeky. And the estimated | |
| + * peak rate will actually be an average over the disk | |
| + * surface. Hence, to not be too harsh with unlucky processes, | |
| + * we keep a budget/3 margin of safety before declaring a | |
| + * process slow. | |
| + */ | |
| + return expected > (4 * bfqq->entity.budget) / 3; | |
| +} | |
| + | |
| +/* | |
| + * To be deemed as soft real-time, an application must meet two | |
| + * requirements. First, the application must not require an average | |
| + * bandwidth higher than the approximate bandwidth required to playback or | |
| + * record a compressed high-definition video. | |
| + * The next function is invoked on the completion of the last request of a | |
| + * batch, to compute the next-start time instant, soft_rt_next_start, such | |
| + * that, if the next request of the application does not arrive before | |
| + * soft_rt_next_start, then the above requirement on the bandwidth is met. | |
| + * | |
| + * The second requirement is that the request pattern of the application is | |
| + * isochronous, i.e., that, after issuing a request or a batch of requests, | |
| + * the application stops issuing new requests until all its pending requests | |
| + * have been completed. After that, the application may issue a new batch, | |
| + * and so on. | |
| + * For this reason the next function is invoked to compute | |
| + * soft_rt_next_start only for applications that meet this requirement, | |
| + * whereas soft_rt_next_start is set to infinity for applications that do | |
| + * not. | |
| + * | |
| + * Unfortunately, even a greedy application may happen to behave in an | |
| + * isochronous way if the CPU load is high. In fact, the application may | |
| + * stop issuing requests while the CPUs are busy serving other processes, | |
| + * then restart, then stop again for a while, and so on. In addition, if | |
| + * the disk achieves a low enough throughput with the request pattern | |
| + * issued by the application (e.g., because the request pattern is random | |
| + * and/or the device is slow), then the application may meet the above | |
| + * bandwidth requirement too. To prevent such a greedy application to be | |
| + * deemed as soft real-time, a further rule is used in the computation of | |
| + * soft_rt_next_start: soft_rt_next_start must be higher than the current | |
| + * time plus the maximum time for which the arrival of a request is waited | |
| + * for when a sync queue becomes idle, namely bfqd->bfq_slice_idle. | |
| + * This filters out greedy applications, as the latter issue instead their | |
| + * next request as soon as possible after the last one has been completed | |
| + * (in contrast, when a batch of requests is completed, a soft real-time | |
| + * application spends some time processing data). | |
| + * | |
| + * Unfortunately, the last filter may easily generate false positives if | |
| + * only bfqd->bfq_slice_idle is used as a reference time interval and one | |
| + * or both the following cases occur: | |
| + * 1) HZ is so low that the duration of a jiffy is comparable to or higher | |
| + * than bfqd->bfq_slice_idle. This happens, e.g., on slow devices with | |
| + * HZ=100. | |
| + * 2) jiffies, instead of increasing at a constant rate, may stop increasing | |
| + * for a while, then suddenly 'jump' by several units to recover the lost | |
| + * increments. This seems to happen, e.g., inside virtual machines. | |
| + * To address this issue, we do not use as a reference time interval just | |
| + * bfqd->bfq_slice_idle, but bfqd->bfq_slice_idle plus a few jiffies. In | |
| + * particular we add the minimum number of jiffies for which the filter | |
| + * seems to be quite precise also in embedded systems and KVM/QEMU virtual | |
| + * machines. | |
| + */ | |
| +static unsigned long bfq_bfqq_softrt_next_start(struct bfq_data *bfqd, | |
| + struct bfq_queue *bfqq) | |
| +{ | |
| + return max(bfqq->last_idle_bklogged + | |
| + HZ * bfqq->service_from_backlogged / | |
| + bfqd->bfq_wr_max_softrt_rate, | |
| + jiffies + bfqq->bfqd->bfq_slice_idle + 4); | |
| +} | |
| + | |
| +/* | |
| + * Return the largest-possible time instant such that, for as long as possible, | |
| + * the current time will be lower than this time instant according to the macro | |
| + * time_is_before_jiffies(). | |
| + */ | |
| +static unsigned long bfq_infinity_from_now(unsigned long now) | |
| +{ | |
| + return now + ULONG_MAX / 2; | |
| +} | |
| + | |
| +/** | |
| + * bfq_bfqq_expire - expire a queue. | |
| + * @bfqd: device owning the queue. | |
| + * @bfqq: the queue to expire. | |
| + * @compensate: if true, compensate for the time spent idling. | |
| + * @reason: the reason causing the expiration. | |
| + * | |
| + * | |
| + * If the process associated to the queue is slow (i.e., seeky), or in | |
| + * case of budget timeout, or, finally, if it is async, we | |
| + * artificially charge it an entire budget (independently of the | |
| + * actual service it received). As a consequence, the queue will get | |
| + * higher timestamps than the correct ones upon reactivation, and | |
| + * hence it will be rescheduled as if it had received more service | |
| + * than what it actually received. In the end, this class of processes | |
| + * will receive less service in proportion to how slowly they consume | |
| + * their budgets (and hence how seriously they tend to lower the | |
| + * throughput). | |
| + * | |
| + * In contrast, when a queue expires because it has been idling for | |
| + * too much or because it exhausted its budget, we do not touch the | |
| + * amount of service it has received. Hence when the queue will be | |
| + * reactivated and its timestamps updated, the latter will be in sync | |
| + * with the actual service received by the queue until expiration. | |
| + * | |
| + * Charging a full budget to the first type of queues and the exact | |
| + * service to the others has the effect of using the WF2Q+ policy to | |
| + * schedule the former on a timeslice basis, without violating the | |
| + * service domain guarantees of the latter. | |
| + */ | |
| +static void bfq_bfqq_expire(struct bfq_data *bfqd, | |
| + struct bfq_queue *bfqq, | |
| + bool compensate, | |
| + enum bfqq_expiration reason) | |
| +{ | |
| + bool slow; | |
| + BUG_ON(bfqq != bfqd->in_service_queue); | |
| + | |
| + /* | |
| + * Update disk peak rate for autotuning and check whether the | |
| + * process is slow (see bfq_update_peak_rate). | |
| + */ | |
| + slow = bfq_update_peak_rate(bfqd, bfqq, compensate, reason); | |
| + | |
| + /* | |
| + * As above explained, 'punish' slow (i.e., seeky), timed-out | |
| + * and async queues, to favor sequential sync workloads. | |
| + * | |
| + * Processes doing I/O in the slower disk zones will tend to be | |
| + * slow(er) even if not seeky. Hence, since the estimated peak | |
| + * rate is actually an average over the disk surface, these | |
| + * processes may timeout just for bad luck. To avoid punishing | |
| + * them we do not charge a full budget to a process that | |
| + * succeeded in consuming at least 2/3 of its budget. | |
| + */ | |
| + if (slow || (reason == BFQ_BFQQ_BUDGET_TIMEOUT && | |
| + bfq_bfqq_budget_left(bfqq) >= bfqq->entity.budget / 3)) | |
| + bfq_bfqq_charge_full_budget(bfqq); | |
| + | |
| + bfqq->service_from_backlogged += bfqq->entity.service; | |
| + | |
| + if (BFQQ_SEEKY(bfqq) && reason == BFQ_BFQQ_BUDGET_TIMEOUT && | |
| + !bfq_bfqq_constantly_seeky(bfqq)) { | |
| + bfq_mark_bfqq_constantly_seeky(bfqq); | |
| + if (!blk_queue_nonrot(bfqd->queue)) | |
| + bfqd->const_seeky_busy_in_flight_queues++; | |
| + } | |
| + | |
| + if (reason == BFQ_BFQQ_TOO_IDLE && | |
| + bfqq->entity.service <= 2 * bfqq->entity.budget / 10 ) | |
| + bfq_clear_bfqq_IO_bound(bfqq); | |
| + | |
| + if (bfqd->low_latency && bfqq->wr_coeff == 1) | |
| + bfqq->last_wr_start_finish = jiffies; | |
| + | |
| + if (bfqd->low_latency && bfqd->bfq_wr_max_softrt_rate > 0 && | |
| + RB_EMPTY_ROOT(&bfqq->sort_list)) { | |
| + /* | |
| + * If we get here, and there are no outstanding requests, | |
| + * then the request pattern is isochronous (see the comments | |
| + * to the function bfq_bfqq_softrt_next_start()). Hence we | |
| + * can compute soft_rt_next_start. If, instead, the queue | |
| + * still has outstanding requests, then we have to wait | |
| + * for the completion of all the outstanding requests to | |
| + * discover whether the request pattern is actually | |
| + * isochronous. | |
| + */ | |
| + if (bfqq->dispatched == 0) | |
| + bfqq->soft_rt_next_start = | |
| + bfq_bfqq_softrt_next_start(bfqd, bfqq); | |
| + else { | |
| + /* | |
| + * The application is still waiting for the | |
| + * completion of one or more requests: | |
| + * prevent it from possibly being incorrectly | |
| + * deemed as soft real-time by setting its | |
| + * soft_rt_next_start to infinity. In fact, | |
| + * without this assignment, the application | |
| + * would be incorrectly deemed as soft | |
| + * real-time if: | |
| + * 1) it issued a new request before the | |
| + * completion of all its in-flight | |
| + * requests, and | |
| + * 2) at that time, its soft_rt_next_start | |
| + * happened to be in the past. | |
| + */ | |
| + bfqq->soft_rt_next_start = | |
| + bfq_infinity_from_now(jiffies); | |
| + /* | |
| + * Schedule an update of soft_rt_next_start to when | |
| + * the task may be discovered to be isochronous. | |
| + */ | |
| + bfq_mark_bfqq_softrt_update(bfqq); | |
| + } | |
| + } | |
| + | |
| + bfq_log_bfqq(bfqd, bfqq, | |
| + "expire (%d, slow %d, num_disp %d, idle_win %d)", reason, | |
| + slow, bfqq->dispatched, bfq_bfqq_idle_window(bfqq)); | |
| + | |
| + /* | |
| + * Increase, decrease or leave budget unchanged according to | |
| + * reason. | |
| + */ | |
| + __bfq_bfqq_recalc_budget(bfqd, bfqq, reason); | |
| + __bfq_bfqq_expire(bfqd, bfqq); | |
| +} | |
| + | |
| +/* | |
| + * Budget timeout is not implemented through a dedicated timer, but | |
| + * just checked on request arrivals and completions, as well as on | |
| + * idle timer expirations. | |
| + */ | |
| +static bool bfq_bfqq_budget_timeout(struct bfq_queue *bfqq) | |
| +{ | |
| + if (bfq_bfqq_budget_new(bfqq) || | |
| + time_before(jiffies, bfqq->budget_timeout)) | |
| + return false; | |
| + return true; | |
| +} | |
| + | |
| +/* | |
| + * If we expire a queue that is waiting for the arrival of a new | |
| + * request, we may prevent the fictitious timestamp back-shifting that | |
| + * allows the guarantees of the queue to be preserved (see [1] for | |
| + * this tricky aspect). Hence we return true only if this condition | |
| + * does not hold, or if the queue is slow enough to deserve only to be | |
| + * kicked off for preserving a high throughput. | |
| +*/ | |
| +static bool bfq_may_expire_for_budg_timeout(struct bfq_queue *bfqq) | |
| +{ | |
| + bfq_log_bfqq(bfqq->bfqd, bfqq, | |
| + "may_budget_timeout: wait_request %d left %d timeout %d", | |
| + bfq_bfqq_wait_request(bfqq), | |
| + bfq_bfqq_budget_left(bfqq) >= bfqq->entity.budget / 3, | |
| + bfq_bfqq_budget_timeout(bfqq)); | |
| + | |
| + return (!bfq_bfqq_wait_request(bfqq) || | |
| + bfq_bfqq_budget_left(bfqq) >= bfqq->entity.budget / 3) | |
| + && | |
| + bfq_bfqq_budget_timeout(bfqq); | |
| +} | |
| + | |
| +/* | |
| + * For a queue that becomes empty, device idling is allowed only if | |
| + * this function returns true for that queue. As a consequence, since | |
| + * device idling plays a critical role for both throughput boosting | |
| + * and service guarantees, the return value of this function plays a | |
| + * critical role as well. | |
| + * | |
| + * In a nutshell, this function returns true only if idling is | |
| + * beneficial for throughput or, even if detrimental for throughput, | |
| + * idling is however necessary to preserve service guarantees (low | |
| + * latency, desired throughput distribution, ...). In particular, on | |
| + * NCQ-capable devices, this function tries to return false, so as to | |
| + * help keep the drives' internal queues full, whenever this helps the | |
| + * device boost the throughput without causing any service-guarantee | |
| + * issue. | |
| + * | |
| + * In more detail, the return value of this function is obtained by, | |
| + * first, computing a number of boolean variables that take into | |
| + * account throughput and service-guarantee issues, and, then, | |
| + * combining these variables in a logical expression. Most of the | |
| + * issues taken into account are not trivial. We discuss these issues | |
| + * while introducing the variables. | |
| + */ | |
| +static bool bfq_bfqq_may_idle(struct bfq_queue *bfqq) | |
| +{ | |
| + struct bfq_data *bfqd = bfqq->bfqd; | |
| + bool idling_boosts_thr, idling_boosts_thr_without_issues, | |
| + all_queues_seeky, on_hdd_and_not_all_queues_seeky, | |
| + idling_needed_for_service_guarantees, | |
| + asymmetric_scenario; | |
| + | |
| + /* | |
| + * The next variable takes into account the cases where idling | |
| + * boosts the throughput. | |
| + * | |
| + * The value of the variable is computed considering, first, that | |
| + * idling is virtually always beneficial for the throughput if: | |
| + * (a) the device is not NCQ-capable, or | |
| + * (b) regardless of the presence of NCQ, the device is rotational | |
| + * and the request pattern for bfqq is I/O-bound and sequential. | |
| + * | |
| + * Secondly, and in contrast to the above item (b), idling an | |
| + * NCQ-capable flash-based device would not boost the | |
| + * throughput even with sequential I/O; rather it would lower | |
| + * the throughput in proportion to how fast the device | |
| + * is. Accordingly, the next variable is true if any of the | |
| + * above conditions (a) and (b) is true, and, in particular, | |
| + * happens to be false if bfqd is an NCQ-capable flash-based | |
| + * device. | |
| + */ | |
| + idling_boosts_thr = !bfqd->hw_tag || | |
| + (!blk_queue_nonrot(bfqd->queue) && bfq_bfqq_IO_bound(bfqq) && | |
| + bfq_bfqq_idle_window(bfqq)) ; | |
| + | |
| + /* | |
| + * The value of the next variable, | |
| + * idling_boosts_thr_without_issues, is equal to that of | |
| + * idling_boosts_thr, unless a special case holds. In this | |
| + * special case, described below, idling may cause problems to | |
| + * weight-raised queues. | |
| + * | |
| + * When the request pool is saturated (e.g., in the presence | |
| + * of write hogs), if the processes associated with | |
| + * non-weight-raised queues ask for requests at a lower rate, | |
| + * then processes associated with weight-raised queues have a | |
| + * higher probability to get a request from the pool | |
| + * immediately (or at least soon) when they need one. Thus | |
| + * they have a higher probability to actually get a fraction | |
| + * of the device throughput proportional to their high | |
| + * weight. This is especially true with NCQ-capable drives, | |
| + * which enqueue several requests in advance, and further | |
| + * reorder internally-queued requests. | |
| + * | |
| + * For this reason, we force to false the value of | |
| + * idling_boosts_thr_without_issues if there are weight-raised | |
| + * busy queues. In this case, and if bfqq is not weight-raised, | |
| + * this guarantees that the device is not idled for bfqq (if, | |
| + * instead, bfqq is weight-raised, then idling will be | |
| + * guaranteed by another variable, see below). Combined with | |
| + * the timestamping rules of BFQ (see [1] for details), this | |
| + * behavior causes bfqq, and hence any sync non-weight-raised | |
| + * queue, to get a lower number of requests served, and thus | |
| + * to ask for a lower number of requests from the request | |
| + * pool, before the busy weight-raised queues get served | |
| + * again. This often mitigates starvation problems in the | |
| + * presence of heavy write workloads and NCQ, thereby | |
| + * guaranteeing a higher application and system responsiveness | |
| + * in these hostile scenarios. | |
| + */ | |
| + idling_boosts_thr_without_issues = idling_boosts_thr && | |
| + bfqd->wr_busy_queues == 0; | |
| + | |
| + /* | |
| + * There are then two cases where idling must be performed not | |
| + * for throughput concerns, but to preserve service | |
| + * guarantees. In the description of these cases, we say, for | |
| + * short, that a queue is sequential/random if the process | |
| + * associated to the queue issues sequential/random requests | |
| + * (in the second case the queue may be tagged as seeky or | |
| + * even constantly_seeky). | |
| + * | |
| + * To introduce the first case, we note that, since | |
| + * bfq_bfqq_idle_window(bfqq) is false if the device is | |
| + * NCQ-capable and bfqq is random (see | |
| + * bfq_update_idle_window()), then, from the above two | |
| + * assignments it follows that | |
| + * idling_boosts_thr_without_issues is false if the device is | |
| + * NCQ-capable and bfqq is random. Therefore, for this case, | |
| + * device idling would never be allowed if we used just | |
| + * idling_boosts_thr_without_issues to decide whether to allow | |
| + * it. And, beneficially, this would imply that throughput | |
| + * would always be boosted also with random I/O on NCQ-capable | |
| + * HDDs. | |
| + * | |
| + * But we must be careful on this point, to avoid an unfair | |
| + * treatment for bfqq. In fact, because of the same above | |
| + * assignments, idling_boosts_thr_without_issues is, on the | |
| + * other hand, true if 1) the device is an HDD and bfqq is | |
| + * sequential, and 2) there are no busy weight-raised | |
| + * queues. As a consequence, if we used just | |
| + * idling_boosts_thr_without_issues to decide whether to idle | |
| + * the device, then with an HDD we might easily bump into a | |
| + * scenario where queues that are sequential and I/O-bound | |
| + * would enjoy idling, whereas random queues would not. The | |
| + * latter might then get a low share of the device throughput, | |
| + * simply because the former would get many requests served | |
| + * after being set as in service, while the latter would not. | |
| + * | |
| + * To address this issue, we start by setting to true a | |
| + * sentinel variable, on_hdd_and_not_all_queues_seeky, if the | |
| + * device is rotational and not all queues with pending or | |
| + * in-flight requests are constantly seeky (i.e., there are | |
| + * active sequential queues, and bfqq might then be mistreated | |
| + * if it does not enjoy idling because it is random). | |
| + */ | |
| + all_queues_seeky = bfq_bfqq_constantly_seeky(bfqq) && | |
| + bfqd->busy_in_flight_queues == | |
| + bfqd->const_seeky_busy_in_flight_queues; | |
| + | |
| + on_hdd_and_not_all_queues_seeky = | |
| + !blk_queue_nonrot(bfqd->queue) && !all_queues_seeky; | |
| + | |
| + /* | |
| + * To introduce the second case where idling needs to be | |
| + * performed to preserve service guarantees, we can note that | |
| + * allowing the drive to enqueue more than one request at a | |
| + * time, and hence delegating de facto final scheduling | |
| + * decisions to the drive's internal scheduler, causes loss of | |
| + * control on the actual request service order. In particular, | |
| + * the critical situation is when requests from different | |
| + * processes happens to be present, at the same time, in the | |
| + * internal queue(s) of the drive. In such a situation, the | |
| + * drive, by deciding the service order of the | |
| + * internally-queued requests, does determine also the actual | |
| + * throughput distribution among these processes. But the | |
| + * drive typically has no notion or concern about per-process | |
| + * throughput distribution, and makes its decisions only on a | |
| + * per-request basis. Therefore, the service distribution | |
| + * enforced by the drive's internal scheduler is likely to | |
| + * coincide with the desired device-throughput distribution | |
| + * only in a completely symmetric scenario where: | |
| + * (i) each of these processes must get the same throughput as | |
| + * the others; | |
| + * (ii) all these processes have the same I/O pattern | |
| + (either sequential or random). | |
| + * In fact, in such a scenario, the drive will tend to treat | |
| + * the requests of each of these processes in about the same | |
| + * way as the requests of the others, and thus to provide | |
| + * each of these processes with about the same throughput | |
| + * (which is exactly the desired throughput distribution). In | |
| + * contrast, in any asymmetric scenario, device idling is | |
| + * certainly needed to guarantee that bfqq receives its | |
| + * assigned fraction of the device throughput (see [1] for | |
| + * details). | |
| + * | |
| + * We address this issue by controlling, actually, only the | |
| + * symmetry sub-condition (i), i.e., provided that | |
| + * sub-condition (i) holds, idling is not performed, | |
| + * regardless of whether sub-condition (ii) holds. In other | |
| + * words, only if sub-condition (i) holds, then idling is | |
| + * allowed, and the device tends to be prevented from queueing | |
| + * many requests, possibly of several processes. The reason | |
| + * for not controlling also sub-condition (ii) is that, first, | |
| + * in the case of an HDD, the asymmetry in terms of types of | |
| + * I/O patterns is already taken in to account in the above | |
| + * sentinel variable | |
| + * on_hdd_and_not_all_queues_seeky. Secondly, in the case of a | |
| + * flash-based device, we prefer however to privilege | |
| + * throughput (and idling lowers throughput for this type of | |
| + * devices), for the following reasons: | |
| + * 1) differently from HDDs, the service time of random | |
| + * requests is not orders of magnitudes lower than the service | |
| + * time of sequential requests; thus, even if processes doing | |
| + * sequential I/O get a preferential treatment with respect to | |
| + * others doing random I/O, the consequences are not as | |
| + * dramatic as with HDDs; | |
| + * 2) if a process doing random I/O does need strong | |
| + * throughput guarantees, it is hopefully already being | |
| + * weight-raised, or the user is likely to have assigned it a | |
| + * higher weight than the other processes (and thus | |
| + * sub-condition (i) is likely to be false, which triggers | |
| + * idling). | |
| + * | |
| + * According to the above considerations, the next variable is | |
| + * true (only) if sub-condition (i) holds. To compute the | |
| + * value of this variable, we not only use the return value of | |
| + * the function bfq_symmetric_scenario(), but also check | |
| + * whether bfqq is being weight-raised, because | |
| + * bfq_symmetric_scenario() does not take into account also | |
| + * weight-raised queues (see comments to | |
| + * bfq_weights_tree_add()). | |
| + * | |
| + * As a side note, it is worth considering that the above | |
| + * device-idling countermeasures may however fail in the | |
| + * following unlucky scenario: if idling is (correctly) | |
| + * disabled in a time period during which all symmetry | |
| + * sub-conditions hold, and hence the device is allowed to | |
| + * enqueue many requests, but at some later point in time some | |
| + * sub-condition stops to hold, then it may become impossible | |
| + * to let requests be served in the desired order until all | |
| + * the requests already queued in the device have been served. | |
| + */ | |
| + asymmetric_scenario = bfqq->wr_coeff > 1 || | |
| + !bfq_symmetric_scenario(bfqd); | |
| + | |
| + /* | |
| + * Finally, there is a case where maximizing throughput is the | |
| + * best choice even if it may cause unfairness toward | |
| + * bfqq. Such a case is when bfqq became active in a burst of | |
| + * queue activations. Queues that became active during a large | |
| + * burst benefit only from throughput, as discussed in the | |
| + * comments to bfq_handle_burst. Thus, if bfqq became active | |
| + * in a burst and not idling the device maximizes throughput, | |
| + * then the device must no be idled, because not idling the | |
| + * device provides bfqq and all other queues in the burst with | |
| + * maximum benefit. Combining this and the two cases above, we | |
| + * can now establish when idling is actually needed to | |
| + * preserve service guarantees. | |
| + */ | |
| + idling_needed_for_service_guarantees = | |
| + (on_hdd_and_not_all_queues_seeky || asymmetric_scenario) && | |
| + !bfq_bfqq_in_large_burst(bfqq); | |
| + | |
| + /* | |
| + * We have now all the components we need to compute the return | |
| + * value of the function, which is true only if both the following | |
| + * conditions hold: | |
| + * 1) bfqq is sync, because idling make sense only for sync queues; | |
| + * 2) idling either boosts the throughput (without issues), or | |
| + * is necessary to preserve service guarantees. | |
| + */ | |
| + return bfq_bfqq_sync(bfqq) && | |
| + (idling_boosts_thr_without_issues || | |
| + idling_needed_for_service_guarantees); | |
| +} | |
| + | |
| +/* | |
| + * If the in-service queue is empty but the function bfq_bfqq_may_idle | |
| + * returns true, then: | |
| + * 1) the queue must remain in service and cannot be expired, and | |
| + * 2) the device must be idled to wait for the possible arrival of a new | |
| + * request for the queue. | |
| + * See the comments to the function bfq_bfqq_may_idle for the reasons | |
| + * why performing device idling is the best choice to boost the throughput | |
| + * and preserve service guarantees when bfq_bfqq_may_idle itself | |
| + * returns true. | |
| + */ | |
| +static bool bfq_bfqq_must_idle(struct bfq_queue *bfqq) | |
| +{ | |
| + struct bfq_data *bfqd = bfqq->bfqd; | |
| + | |
| + return RB_EMPTY_ROOT(&bfqq->sort_list) && bfqd->bfq_slice_idle != 0 && | |
| + bfq_bfqq_may_idle(bfqq); | |
| +} | |
| + | |
| +/* | |
| + * Select a queue for service. If we have a current queue in service, | |
| + * check whether to continue servicing it, or retrieve and set a new one. | |
| + */ | |
| +static struct bfq_queue *bfq_select_queue(struct bfq_data *bfqd) | |
| +{ | |
| + struct bfq_queue *bfqq; | |
| + struct request *next_rq; | |
| + enum bfqq_expiration reason = BFQ_BFQQ_BUDGET_TIMEOUT; | |
| + | |
| + bfqq = bfqd->in_service_queue; | |
| + if (!bfqq) | |
| + goto new_queue; | |
| + | |
| + bfq_log_bfqq(bfqd, bfqq, "select_queue: already in-service queue"); | |
| + | |
| + if (bfq_may_expire_for_budg_timeout(bfqq) && | |
| + !timer_pending(&bfqd->idle_slice_timer) && | |
| + !bfq_bfqq_must_idle(bfqq)) | |
| + goto expire; | |
| + | |
| + next_rq = bfqq->next_rq; | |
| + /* | |
| + * If bfqq has requests queued and it has enough budget left to | |
| + * serve them, keep the queue, otherwise expire it. | |
| + */ | |
| + if (next_rq) { | |
| + if (bfq_serv_to_charge(next_rq, bfqq) > | |
| + bfq_bfqq_budget_left(bfqq)) { | |
| + reason = BFQ_BFQQ_BUDGET_EXHAUSTED; | |
| + goto expire; | |
| + } else { | |
| + /* | |
| + * The idle timer may be pending because we may | |
| + * not disable disk idling even when a new request | |
| + * arrives. | |
| + */ | |
| + if (timer_pending(&bfqd->idle_slice_timer)) { | |
| + /* | |
| + * If we get here: 1) at least a new request | |
| + * has arrived but we have not disabled the | |
| + * timer because the request was too small, | |
| + * 2) then the block layer has unplugged | |
| + * the device, causing the dispatch to be | |
| + * invoked. | |
| + * | |
| + * Since the device is unplugged, now the | |
| + * requests are probably large enough to | |
| + * provide a reasonable throughput. | |
| + * So we disable idling. | |
| + */ | |
| + bfq_clear_bfqq_wait_request(bfqq); | |
| + del_timer(&bfqd->idle_slice_timer); | |
| +#ifdef CONFIG_BFQ_GROUP_IOSCHED | |
| + bfqg_stats_update_idle_time(bfqq_group(bfqq)); | |
| +#endif | |
| + } | |
| + goto keep_queue; | |
| + } | |
| + } | |
| + | |
| + /* | |
| + * No requests pending. However, if the in-service queue is idling | |
| + * for a new request, or has requests waiting for a completion and | |
| + * may idle after their completion, then keep it anyway. | |
| + */ | |
| + if (timer_pending(&bfqd->idle_slice_timer) || | |
| + (bfqq->dispatched != 0 && bfq_bfqq_may_idle(bfqq))) { | |
| + bfqq = NULL; | |
| + goto keep_queue; | |
| + } | |
| + | |
| + reason = BFQ_BFQQ_NO_MORE_REQUESTS; | |
| +expire: | |
| + bfq_bfqq_expire(bfqd, bfqq, false, reason); | |
| +new_queue: | |
| + bfqq = bfq_set_in_service_queue(bfqd); | |
| + bfq_log(bfqd, "select_queue: new queue %d returned", | |
| + bfqq ? bfqq->pid : 0); | |
| +keep_queue: | |
| + return bfqq; | |
| +} | |
| + | |
| +static void bfq_update_wr_data(struct bfq_data *bfqd, struct bfq_queue *bfqq) | |
| +{ | |
| + struct bfq_entity *entity = &bfqq->entity; | |
| + if (bfqq->wr_coeff > 1) { /* queue is being weight-raised */ | |
| + bfq_log_bfqq(bfqd, bfqq, | |
| + "raising period dur %u/%u msec, old coeff %u, w %d(%d)", | |
| + jiffies_to_msecs(jiffies - bfqq->last_wr_start_finish), | |
| + jiffies_to_msecs(bfqq->wr_cur_max_time), | |
| + bfqq->wr_coeff, | |
| + bfqq->entity.weight, bfqq->entity.orig_weight); | |
| + | |
| + BUG_ON(bfqq != bfqd->in_service_queue && entity->weight != | |
| + entity->orig_weight * bfqq->wr_coeff); | |
| + if (entity->prio_changed) | |
| + bfq_log_bfqq(bfqd, bfqq, "WARN: pending prio change"); | |
| + | |
| + /* | |
| + * If the queue was activated in a burst, or | |
| + * too much time has elapsed from the beginning | |
| + * of this weight-raising period, or the queue has | |
| + * exceeded the acceptable number of cooperations, | |
| + * then end weight raising. | |
| + */ | |
| + if (bfq_bfqq_in_large_burst(bfqq) || | |
| + bfq_bfqq_cooperations(bfqq) >= bfqd->bfq_coop_thresh || | |
| + time_is_before_jiffies(bfqq->last_wr_start_finish + | |
| + bfqq->wr_cur_max_time)) { | |
| + bfqq->last_wr_start_finish = jiffies; | |
| + bfq_log_bfqq(bfqd, bfqq, | |
| + "wrais ending at %lu, rais_max_time %u", | |
| + bfqq->last_wr_start_finish, | |
| + jiffies_to_msecs(bfqq->wr_cur_max_time)); | |
| + bfq_bfqq_end_wr(bfqq); | |
| + } | |
| + } | |
| + /* Update weight both if it must be raised and if it must be lowered */ | |
| + if ((entity->weight > entity->orig_weight) != (bfqq->wr_coeff > 1)) | |
| + __bfq_entity_update_weight_prio( | |
| + bfq_entity_service_tree(entity), | |
| + entity); | |
| +} | |
| + | |
| +/* | |
| + * Dispatch one request from bfqq, moving it to the request queue | |
| + * dispatch list. | |
| + */ | |
| +static int bfq_dispatch_request(struct bfq_data *bfqd, | |
| + struct bfq_queue *bfqq) | |
| +{ | |
| + int dispatched = 0; | |
| + struct request *rq; | |
| + unsigned long service_to_charge; | |
| + | |
| + BUG_ON(RB_EMPTY_ROOT(&bfqq->sort_list)); | |
| + | |
| + /* Follow expired path, else get first next available. */ | |
| + rq = bfq_check_fifo(bfqq); | |
| + if (!rq) | |
| + rq = bfqq->next_rq; | |
| + service_to_charge = bfq_serv_to_charge(rq, bfqq); | |
| + | |
| + if (service_to_charge > bfq_bfqq_budget_left(bfqq)) { | |
| + /* | |
| + * This may happen if the next rq is chosen in fifo order | |
| + * instead of sector order. The budget is properly | |
| + * dimensioned to be always sufficient to serve the next | |
| + * request only if it is chosen in sector order. The reason | |
| + * is that it would be quite inefficient and little useful | |
| + * to always make sure that the budget is large enough to | |
| + * serve even the possible next rq in fifo order. | |
| + * In fact, requests are seldom served in fifo order. | |
| + * | |
| + * Expire the queue for budget exhaustion, and make sure | |
| + * that the next act_budget is enough to serve the next | |
| + * request, even if it comes from the fifo expired path. | |
| + */ | |
| + bfqq->next_rq = rq; | |
| + /* | |
| + * Since this dispatch is failed, make sure that | |
| + * a new one will be performed | |
| + */ | |
| + if (!bfqd->rq_in_driver) | |
| + bfq_schedule_dispatch(bfqd); | |
| + goto expire; | |
| + } | |
| + | |
| + /* Finally, insert request into driver dispatch list. */ | |
| + bfq_bfqq_served(bfqq, service_to_charge); | |
| + bfq_dispatch_insert(bfqd->queue, rq); | |
| + | |
| + bfq_update_wr_data(bfqd, bfqq); | |
| + | |
| + bfq_log_bfqq(bfqd, bfqq, | |
| + "dispatched %u sec req (%llu), budg left %d", | |
| + blk_rq_sectors(rq), | |
| + (long long unsigned)blk_rq_pos(rq), | |
| + bfq_bfqq_budget_left(bfqq)); | |
| + | |
| + dispatched++; | |
| + | |
| + if (!bfqd->in_service_bic) { | |
| + atomic_long_inc(&RQ_BIC(rq)->icq.ioc->refcount); | |
| + bfqd->in_service_bic = RQ_BIC(rq); | |
| + } | |
| + | |
| + if (bfqd->busy_queues > 1 && ((!bfq_bfqq_sync(bfqq) && | |
| + dispatched >= bfqd->bfq_max_budget_async_rq) || | |
| + bfq_class_idle(bfqq))) | |
| + goto expire; | |
| + | |
| + return dispatched; | |
| + | |
| +expire: | |
| + bfq_bfqq_expire(bfqd, bfqq, false, BFQ_BFQQ_BUDGET_EXHAUSTED); | |
| + return dispatched; | |
| +} | |
| + | |
| +static int __bfq_forced_dispatch_bfqq(struct bfq_queue *bfqq) | |
| +{ | |
| + int dispatched = 0; | |
| + | |
| + while (bfqq->next_rq) { | |
| + bfq_dispatch_insert(bfqq->bfqd->queue, bfqq->next_rq); | |
| + dispatched++; | |
| + } | |
| + | |
| + BUG_ON(!list_empty(&bfqq->fifo)); | |
| + return dispatched; | |
| +} | |
| + | |
| +/* | |
| + * Drain our current requests. | |
| + * Used for barriers and when switching io schedulers on-the-fly. | |
| + */ | |
| +static int bfq_forced_dispatch(struct bfq_data *bfqd) | |
| +{ | |
| + struct bfq_queue *bfqq, *n; | |
| + struct bfq_service_tree *st; | |
| + int dispatched = 0; | |
| + | |
| + bfqq = bfqd->in_service_queue; | |
| + if (bfqq) | |
| + __bfq_bfqq_expire(bfqd, bfqq); | |
| + | |
| + /* | |
| + * Loop through classes, and be careful to leave the scheduler | |
| + * in a consistent state, as feedback mechanisms and vtime | |
| + * updates cannot be disabled during the process. | |
| + */ | |
| + list_for_each_entry_safe(bfqq, n, &bfqd->active_list, bfqq_list) { | |
| + st = bfq_entity_service_tree(&bfqq->entity); | |
| + | |
| + dispatched += __bfq_forced_dispatch_bfqq(bfqq); | |
| + bfqq->max_budget = bfq_max_budget(bfqd); | |
| + | |
| + bfq_forget_idle(st); | |
| + } | |
| + | |
| + BUG_ON(bfqd->busy_queues != 0); | |
| + | |
| + return dispatched; | |
| +} | |
| + | |
| +static int bfq_dispatch_requests(struct request_queue *q, int force) | |
| +{ | |
| + struct bfq_data *bfqd = q->elevator->elevator_data; | |
| + struct bfq_queue *bfqq; | |
| + int max_dispatch; | |
| + | |
| + bfq_log(bfqd, "dispatch requests: %d busy queues", bfqd->busy_queues); | |
| + if (bfqd->busy_queues == 0) | |
| + return 0; | |
| + | |
| + if (unlikely(force)) | |
| + return bfq_forced_dispatch(bfqd); | |
| + | |
| + bfqq = bfq_select_queue(bfqd); | |
| + if (!bfqq) | |
| + return 0; | |
| + | |
| + if (bfq_class_idle(bfqq)) | |
| + max_dispatch = 1; | |
| + | |
| + if (!bfq_bfqq_sync(bfqq)) | |
| + max_dispatch = bfqd->bfq_max_budget_async_rq; | |
| + | |
| + if (!bfq_bfqq_sync(bfqq) && bfqq->dispatched >= max_dispatch) { | |
| + if (bfqd->busy_queues > 1) | |
| + return 0; | |
| + if (bfqq->dispatched >= 4 * max_dispatch) | |
| + return 0; | |
| + } | |
| + | |
| + if (bfqd->sync_flight != 0 && !bfq_bfqq_sync(bfqq)) | |
| + return 0; | |
| + | |
| + bfq_clear_bfqq_wait_request(bfqq); | |
| + BUG_ON(timer_pending(&bfqd->idle_slice_timer)); | |
| + | |
| + if (!bfq_dispatch_request(bfqd, bfqq)) | |
| + return 0; | |
| + | |
| + bfq_log_bfqq(bfqd, bfqq, "dispatched %s request", | |
| + bfq_bfqq_sync(bfqq) ? "sync" : "async"); | |
| + | |
| + return 1; | |
| +} | |
| + | |
| +/* | |
| + * Task holds one reference to the queue, dropped when task exits. Each rq | |
| + * in-flight on this queue also holds a reference, dropped when rq is freed. | |
| + * | |
| + * Queue lock must be held here. | |
| + */ | |
| +static void bfq_put_queue(struct bfq_queue *bfqq) | |
| +{ | |
| + struct bfq_data *bfqd = bfqq->bfqd; | |
| +#ifdef CONFIG_BFQ_GROUP_IOSCHED | |
| + struct bfq_group *bfqg = bfqq_group(bfqq); | |
| +#endif | |
| + | |
| + BUG_ON(atomic_read(&bfqq->ref) <= 0); | |
| + | |
| + bfq_log_bfqq(bfqd, bfqq, "put_queue: %p %d", bfqq, | |
| + atomic_read(&bfqq->ref)); | |
| + if (!atomic_dec_and_test(&bfqq->ref)) | |
| + return; | |
| + | |
| + BUG_ON(rb_first(&bfqq->sort_list)); | |
| + BUG_ON(bfqq->allocated[READ] + bfqq->allocated[WRITE] != 0); | |
| + BUG_ON(bfqq->entity.tree); | |
| + BUG_ON(bfq_bfqq_busy(bfqq)); | |
| + BUG_ON(bfqd->in_service_queue == bfqq); | |
| + | |
| + if (bfq_bfqq_sync(bfqq)) | |
| + /* | |
| + * The fact that this queue is being destroyed does not | |
| + * invalidate the fact that this queue may have been | |
| + * activated during the current burst. As a consequence, | |
| + * although the queue does not exist anymore, and hence | |
| + * needs to be removed from the burst list if there, | |
| + * the burst size has not to be decremented. | |
| + */ | |
| + hlist_del_init(&bfqq->burst_list_node); | |
| + | |
| + bfq_log_bfqq(bfqd, bfqq, "put_queue: %p freed", bfqq); | |
| + | |
| + kmem_cache_free(bfq_pool, bfqq); | |
| +#ifdef CONFIG_BFQ_GROUP_IOSCHED | |
| + bfqg_put(bfqg); | |
| +#endif | |
| +} | |
| + | |
| +static void bfq_put_cooperator(struct bfq_queue *bfqq) | |
| +{ | |
| + struct bfq_queue *__bfqq, *next; | |
| + | |
| + /* | |
| + * If this queue was scheduled to merge with another queue, be | |
| + * sure to drop the reference taken on that queue (and others in | |
| + * the merge chain). See bfq_setup_merge and bfq_merge_bfqqs. | |
| + */ | |
| + __bfqq = bfqq->new_bfqq; | |
| + while (__bfqq) { | |
| + if (__bfqq == bfqq) | |
| + break; | |
| + next = __bfqq->new_bfqq; | |
| + bfq_put_queue(__bfqq); | |
| + __bfqq = next; | |
| + } | |
| +} | |
| + | |
| +static void bfq_exit_bfqq(struct bfq_data *bfqd, struct bfq_queue *bfqq) | |
| +{ | |
| + if (bfqq == bfqd->in_service_queue) { | |
| + __bfq_bfqq_expire(bfqd, bfqq); | |
| + bfq_schedule_dispatch(bfqd); | |
| + } | |
| + | |
| + bfq_log_bfqq(bfqd, bfqq, "exit_bfqq: %p, %d", bfqq, | |
| + atomic_read(&bfqq->ref)); | |
| + | |
| + bfq_put_cooperator(bfqq); | |
| + | |
| + bfq_put_queue(bfqq); | |
| +} | |
| + | |
| +static void bfq_init_icq(struct io_cq *icq) | |
| +{ | |
| + struct bfq_io_cq *bic = icq_to_bic(icq); | |
| + | |
| + bic->ttime.last_end_request = jiffies; | |
| + /* | |
| + * A newly created bic indicates that the process has just | |
| + * started doing I/O, and is probably mapping into memory its | |
| + * executable and libraries: it definitely needs weight raising. | |
| + * There is however the possibility that the process performs, | |
| + * for a while, I/O close to some other process. EQM intercepts | |
| + * this behavior and may merge the queue corresponding to the | |
| + * process with some other queue, BEFORE the weight of the queue | |
| + * is raised. Merged queues are not weight-raised (they are assumed | |
| + * to belong to processes that benefit only from high throughput). | |
| + * If the merge is basically the consequence of an accident, then | |
| + * the queue will be split soon and will get back its old weight. | |
| + * It is then important to write down somewhere that this queue | |
| + * does need weight raising, even if it did not make it to get its | |
| + * weight raised before being merged. To this purpose, we overload | |
| + * the field raising_time_left and assign 1 to it, to mark the queue | |
| + * as needing weight raising. | |
| + */ | |
| + bic->wr_time_left = 1; | |
| +} | |
| + | |
| +static void bfq_exit_icq(struct io_cq *icq) | |
| +{ | |
| + struct bfq_io_cq *bic = icq_to_bic(icq); | |
| + struct bfq_data *bfqd = bic_to_bfqd(bic); | |
| + | |
| + if (bic->bfqq[BLK_RW_ASYNC]) { | |
| + bfq_exit_bfqq(bfqd, bic->bfqq[BLK_RW_ASYNC]); | |
| + bic->bfqq[BLK_RW_ASYNC] = NULL; | |
| + } | |
| + | |
| + if (bic->bfqq[BLK_RW_SYNC]) { | |
| + /* | |
| + * If the bic is using a shared queue, put the reference | |
| + * taken on the io_context when the bic started using a | |
| + * shared bfq_queue. | |
| + */ | |
| + if (bfq_bfqq_coop(bic->bfqq[BLK_RW_SYNC])) | |
| + put_io_context(icq->ioc); | |
| + bfq_exit_bfqq(bfqd, bic->bfqq[BLK_RW_SYNC]); | |
| + bic->bfqq[BLK_RW_SYNC] = NULL; | |
| + } | |
| +} | |
| + | |
| +/* | |
| + * Update the entity prio values; note that the new values will not | |
| + * be used until the next (re)activation. | |
| + */ | |
| +static void bfq_set_next_ioprio_data(struct bfq_queue *bfqq, struct bfq_io_cq *bic) | |
| +{ | |
| + struct task_struct *tsk = current; | |
| + int ioprio_class; | |
| + | |
| + ioprio_class = IOPRIO_PRIO_CLASS(bic->ioprio); | |
| + switch (ioprio_class) { | |
| + default: | |
| + dev_err(bfqq->bfqd->queue->backing_dev_info.dev, | |
| + "bfq: bad prio class %d\n", ioprio_class); | |
| + case IOPRIO_CLASS_NONE: | |
| + /* | |
| + * No prio set, inherit CPU scheduling settings. | |
| + */ | |
| + bfqq->new_ioprio = task_nice_ioprio(tsk); | |
| + bfqq->new_ioprio_class = task_nice_ioclass(tsk); | |
| + break; | |
| + case IOPRIO_CLASS_RT: | |
| + bfqq->new_ioprio = IOPRIO_PRIO_DATA(bic->ioprio); | |
| + bfqq->new_ioprio_class = IOPRIO_CLASS_RT; | |
| + break; | |
| + case IOPRIO_CLASS_BE: | |
| + bfqq->new_ioprio = IOPRIO_PRIO_DATA(bic->ioprio); | |
| + bfqq->new_ioprio_class = IOPRIO_CLASS_BE; | |
| + break; | |
| + case IOPRIO_CLASS_IDLE: | |
| + bfqq->new_ioprio_class = IOPRIO_CLASS_IDLE; | |
| + bfqq->new_ioprio = 7; | |
| + bfq_clear_bfqq_idle_window(bfqq); | |
| + break; | |
| + } | |
| + | |
| + if (bfqq->new_ioprio < 0 || bfqq->new_ioprio >= IOPRIO_BE_NR) { | |
| + printk(KERN_CRIT "bfq_set_next_ioprio_data: new_ioprio %d\n", | |
| + bfqq->new_ioprio); | |
| + BUG(); | |
| + } | |
| + | |
| + bfqq->entity.new_weight = bfq_ioprio_to_weight(bfqq->new_ioprio); | |
| + bfqq->entity.prio_changed = 1; | |
| +} | |
| + | |
| +static void bfq_check_ioprio_change(struct bfq_io_cq *bic, struct bio *bio) | |
| +{ | |
| + struct bfq_data *bfqd; | |
| + struct bfq_queue *bfqq, *new_bfqq; | |
| + unsigned long uninitialized_var(flags); | |
| + int ioprio = bic->icq.ioc->ioprio; | |
| + | |
| + bfqd = bfq_get_bfqd_locked(&(bic->icq.q->elevator->elevator_data), | |
| + &flags); | |
| + /* | |
| + * This condition may trigger on a newly created bic, be sure to | |
| + * drop the lock before returning. | |
| + */ | |
| + if (unlikely(!bfqd) || likely(bic->ioprio == ioprio)) | |
| + goto out; | |
| + | |
| + bic->ioprio = ioprio; | |
| + | |
| + bfqq = bic->bfqq[BLK_RW_ASYNC]; | |
| + if (bfqq) { | |
| + new_bfqq = bfq_get_queue(bfqd, bio, BLK_RW_ASYNC, bic, | |
| + GFP_ATOMIC); | |
| + if (new_bfqq) { | |
| + bic->bfqq[BLK_RW_ASYNC] = new_bfqq; | |
| + bfq_log_bfqq(bfqd, bfqq, | |
| + "check_ioprio_change: bfqq %p %d", | |
| + bfqq, atomic_read(&bfqq->ref)); | |
| + bfq_put_queue(bfqq); | |
| + } | |
| + } | |
| + | |
| + bfqq = bic->bfqq[BLK_RW_SYNC]; | |
| + if (bfqq) | |
| + bfq_set_next_ioprio_data(bfqq, bic); | |
| + | |
| +out: | |
| + bfq_put_bfqd_unlock(bfqd, &flags); | |
| +} | |
| + | |
| +static void bfq_init_bfqq(struct bfq_data *bfqd, struct bfq_queue *bfqq, | |
| + struct bfq_io_cq *bic, pid_t pid, int is_sync) | |
| +{ | |
| + RB_CLEAR_NODE(&bfqq->entity.rb_node); | |
| + INIT_LIST_HEAD(&bfqq->fifo); | |
| + INIT_HLIST_NODE(&bfqq->burst_list_node); | |
| + | |
| + atomic_set(&bfqq->ref, 0); | |
| + bfqq->bfqd = bfqd; | |
| + | |
| + if (bic) | |
| + bfq_set_next_ioprio_data(bfqq, bic); | |
| + | |
| + if (is_sync) { | |
| + if (!bfq_class_idle(bfqq)) | |
| + bfq_mark_bfqq_idle_window(bfqq); | |
| + bfq_mark_bfqq_sync(bfqq); | |
| + } else | |
| + bfq_clear_bfqq_sync(bfqq); | |
| + bfq_mark_bfqq_IO_bound(bfqq); | |
| + | |
| + /* Tentative initial value to trade off between thr and lat */ | |
| + bfqq->max_budget = (2 * bfq_max_budget(bfqd)) / 3; | |
| + bfqq->pid = pid; | |
| + | |
| + bfqq->wr_coeff = 1; | |
| + bfqq->last_wr_start_finish = 0; | |
| + /* | |
| + * Set to the value for which bfqq will not be deemed as | |
| + * soft rt when it becomes backlogged. | |
| + */ | |
| + bfqq->soft_rt_next_start = bfq_infinity_from_now(jiffies); | |
| +} | |
| + | |
| +static struct bfq_queue *bfq_find_alloc_queue(struct bfq_data *bfqd, | |
| + struct bio *bio, int is_sync, | |
| + struct bfq_io_cq *bic, | |
| + gfp_t gfp_mask) | |
| +{ | |
| + struct bfq_group *bfqg; | |
| + struct bfq_queue *bfqq, *new_bfqq = NULL; | |
| + struct blkcg *blkcg; | |
| + | |
| +retry: | |
| + rcu_read_lock(); | |
| + | |
| + blkcg = bio_blkcg(bio); | |
| + bfqg = bfq_find_alloc_group(bfqd, blkcg); | |
| + /* bic always exists here */ | |
| + bfqq = bic_to_bfqq(bic, is_sync); | |
| + | |
| + /* | |
| + * Always try a new alloc if we fall back to the OOM bfqq | |
| + * originally, since it should just be a temporary situation. | |
| + */ | |
| + if (!bfqq || bfqq == &bfqd->oom_bfqq) { | |
| + bfqq = NULL; | |
| + if (new_bfqq) { | |
| + bfqq = new_bfqq; | |
| + new_bfqq = NULL; | |
| + } else if (gfpflags_allow_blocking(gfp_mask)) { | |
| + rcu_read_unlock(); | |
| + spin_unlock_irq(bfqd->queue->queue_lock); | |
| + new_bfqq = kmem_cache_alloc_node(bfq_pool, | |
| + gfp_mask | __GFP_ZERO, | |
| + bfqd->queue->node); | |
| + spin_lock_irq(bfqd->queue->queue_lock); | |
| + if (new_bfqq) | |
| + goto retry; | |
| + } else { | |
| + bfqq = kmem_cache_alloc_node(bfq_pool, | |
| + gfp_mask | __GFP_ZERO, | |
| + bfqd->queue->node); | |
| + } | |
| + | |
| + if (bfqq) { | |
| + bfq_init_bfqq(bfqd, bfqq, bic, current->pid, | |
| + is_sync); | |
| + bfq_init_entity(&bfqq->entity, bfqg); | |
| + bfq_log_bfqq(bfqd, bfqq, "allocated"); | |
| + } else { | |
| + bfqq = &bfqd->oom_bfqq; | |
| + bfq_log_bfqq(bfqd, bfqq, "using oom bfqq"); | |
| + } | |
| + } | |
| + | |
| + if (new_bfqq) | |
| + kmem_cache_free(bfq_pool, new_bfqq); | |
| + | |
| + rcu_read_unlock(); | |
| + | |
| + return bfqq; | |
| +} | |
| + | |
| +static struct bfq_queue **bfq_async_queue_prio(struct bfq_data *bfqd, | |
| + struct bfq_group *bfqg, | |
| + int ioprio_class, int ioprio) | |
| +{ | |
| + switch (ioprio_class) { | |
| + case IOPRIO_CLASS_RT: | |
| + return &bfqg->async_bfqq[0][ioprio]; | |
| + case IOPRIO_CLASS_NONE: | |
| + ioprio = IOPRIO_NORM; | |
| + /* fall through */ | |
| + case IOPRIO_CLASS_BE: | |
| + return &bfqg->async_bfqq[1][ioprio]; | |
| + case IOPRIO_CLASS_IDLE: | |
| + return &bfqg->async_idle_bfqq; | |
| + default: | |
| + BUG(); | |
| + } | |
| +} | |
| + | |
| +static struct bfq_queue *bfq_get_queue(struct bfq_data *bfqd, | |
| + struct bio *bio, int is_sync, | |
| + struct bfq_io_cq *bic, gfp_t gfp_mask) | |
| +{ | |
| + const int ioprio = IOPRIO_PRIO_DATA(bic->ioprio); | |
| + const int ioprio_class = IOPRIO_PRIO_CLASS(bic->ioprio); | |
| + struct bfq_queue **async_bfqq = NULL; | |
| + struct bfq_queue *bfqq = NULL; | |
| + | |
| + if (!is_sync) { | |
| + struct blkcg *blkcg; | |
| + struct bfq_group *bfqg; | |
| + | |
| + rcu_read_lock(); | |
| + blkcg = bio_blkcg(bio); | |
| + rcu_read_unlock(); | |
| + bfqg = bfq_find_alloc_group(bfqd, blkcg); | |
| + async_bfqq = bfq_async_queue_prio(bfqd, bfqg, ioprio_class, | |
| + ioprio); | |
| + bfqq = *async_bfqq; | |
| + } | |
| + | |
| + if (!bfqq) | |
| + bfqq = bfq_find_alloc_queue(bfqd, bio, is_sync, bic, gfp_mask); | |
| + | |
| + /* | |
| + * Pin the queue now that it's allocated, scheduler exit will | |
| + * prune it. | |
| + */ | |
| + if (!is_sync && !(*async_bfqq)) { | |
| + atomic_inc(&bfqq->ref); | |
| + bfq_log_bfqq(bfqd, bfqq, "get_queue, bfqq not in async: %p, %d", | |
| + bfqq, atomic_read(&bfqq->ref)); | |
| + *async_bfqq = bfqq; | |
| + } | |
| + | |
| + atomic_inc(&bfqq->ref); | |
| + bfq_log_bfqq(bfqd, bfqq, "get_queue, at end: %p, %d", bfqq, | |
| + atomic_read(&bfqq->ref)); | |
| + return bfqq; | |
| +} | |
| + | |
| +static void bfq_update_io_thinktime(struct bfq_data *bfqd, | |
| + struct bfq_io_cq *bic) | |
| +{ | |
| + unsigned long elapsed = jiffies - bic->ttime.last_end_request; | |
| + unsigned long ttime = min(elapsed, 2UL * bfqd->bfq_slice_idle); | |
| + | |
| + bic->ttime.ttime_samples = (7*bic->ttime.ttime_samples + 256) / 8; | |
| + bic->ttime.ttime_total = (7*bic->ttime.ttime_total + 256*ttime) / 8; | |
| + bic->ttime.ttime_mean = (bic->ttime.ttime_total + 128) / | |
| + bic->ttime.ttime_samples; | |
| +} | |
| + | |
| +static void bfq_update_io_seektime(struct bfq_data *bfqd, | |
| + struct bfq_queue *bfqq, | |
| + struct request *rq) | |
| +{ | |
| + sector_t sdist; | |
| + u64 total; | |
| + | |
| + if (bfqq->last_request_pos < blk_rq_pos(rq)) | |
| + sdist = blk_rq_pos(rq) - bfqq->last_request_pos; | |
| + else | |
| + sdist = bfqq->last_request_pos - blk_rq_pos(rq); | |
| + | |
| + /* | |
| + * Don't allow the seek distance to get too large from the | |
| + * odd fragment, pagein, etc. | |
| + */ | |
| + if (bfqq->seek_samples == 0) /* first request, not really a seek */ | |
| + sdist = 0; | |
| + else if (bfqq->seek_samples <= 60) /* second & third seek */ | |
| + sdist = min(sdist, (bfqq->seek_mean * 4) + 2*1024*1024); | |
| + else | |
| + sdist = min(sdist, (bfqq->seek_mean * 4) + 2*1024*64); | |
| + | |
| + bfqq->seek_samples = (7*bfqq->seek_samples + 256) / 8; | |
| + bfqq->seek_total = (7*bfqq->seek_total + (u64)256*sdist) / 8; | |
| + total = bfqq->seek_total + (bfqq->seek_samples/2); | |
| + do_div(total, bfqq->seek_samples); | |
| + bfqq->seek_mean = (sector_t)total; | |
| + | |
| + bfq_log_bfqq(bfqd, bfqq, "dist=%llu mean=%llu", (u64)sdist, | |
| + (u64)bfqq->seek_mean); | |
| +} | |
| + | |
| +/* | |
| + * Disable idle window if the process thinks too long or seeks so much that | |
| + * it doesn't matter. | |
| + */ | |
| +static void bfq_update_idle_window(struct bfq_data *bfqd, | |
| + struct bfq_queue *bfqq, | |
| + struct bfq_io_cq *bic) | |
| +{ | |
| + int enable_idle; | |
| + | |
| + /* Don't idle for async or idle io prio class. */ | |
| + if (!bfq_bfqq_sync(bfqq) || bfq_class_idle(bfqq)) | |
| + return; | |
| + | |
| + /* Idle window just restored, statistics are meaningless. */ | |
| + if (bfq_bfqq_just_split(bfqq)) | |
| + return; | |
| + | |
| + enable_idle = bfq_bfqq_idle_window(bfqq); | |
| + | |
| + if (atomic_read(&bic->icq.ioc->active_ref) == 0 || | |
| + bfqd->bfq_slice_idle == 0 || | |
| + (bfqd->hw_tag && BFQQ_SEEKY(bfqq) && | |
| + bfqq->wr_coeff == 1)) | |
| + enable_idle = 0; | |
| + else if (bfq_sample_valid(bic->ttime.ttime_samples)) { | |
| + if (bic->ttime.ttime_mean > bfqd->bfq_slice_idle && | |
| + bfqq->wr_coeff == 1) | |
| + enable_idle = 0; | |
| + else | |
| + enable_idle = 1; | |
| + } | |
| + bfq_log_bfqq(bfqd, bfqq, "update_idle_window: enable_idle %d", | |
| + enable_idle); | |
| + | |
| + if (enable_idle) | |
| + bfq_mark_bfqq_idle_window(bfqq); | |
| + else | |
| + bfq_clear_bfqq_idle_window(bfqq); | |
| +} | |
| + | |
| +/* | |
| + * Called when a new fs request (rq) is added to bfqq. Check if there's | |
| + * something we should do about it. | |
| + */ | |
| +static void bfq_rq_enqueued(struct bfq_data *bfqd, struct bfq_queue *bfqq, | |
| + struct request *rq) | |
| +{ | |
| + struct bfq_io_cq *bic = RQ_BIC(rq); | |
| + | |
| + if (rq->cmd_flags & REQ_META) | |
| + bfqq->meta_pending++; | |
| + | |
| + bfq_update_io_thinktime(bfqd, bic); | |
| + bfq_update_io_seektime(bfqd, bfqq, rq); | |
| + if (!BFQQ_SEEKY(bfqq) && bfq_bfqq_constantly_seeky(bfqq)) { | |
| + bfq_clear_bfqq_constantly_seeky(bfqq); | |
| + if (!blk_queue_nonrot(bfqd->queue)) { | |
| + BUG_ON(!bfqd->const_seeky_busy_in_flight_queues); | |
| + bfqd->const_seeky_busy_in_flight_queues--; | |
| + } | |
| + } | |
| + if (bfqq->entity.service > bfq_max_budget(bfqd) / 8 || | |
| + !BFQQ_SEEKY(bfqq)) | |
| + bfq_update_idle_window(bfqd, bfqq, bic); | |
| + bfq_clear_bfqq_just_split(bfqq); | |
| + | |
| + bfq_log_bfqq(bfqd, bfqq, | |
| + "rq_enqueued: idle_window=%d (seeky %d, mean %llu)", | |
| + bfq_bfqq_idle_window(bfqq), BFQQ_SEEKY(bfqq), | |
| + (long long unsigned)bfqq->seek_mean); | |
| + | |
| + bfqq->last_request_pos = blk_rq_pos(rq) + blk_rq_sectors(rq); | |
| + | |
| + if (bfqq == bfqd->in_service_queue && bfq_bfqq_wait_request(bfqq)) { | |
| + bool small_req = bfqq->queued[rq_is_sync(rq)] == 1 && | |
| + blk_rq_sectors(rq) < 32; | |
| + bool budget_timeout = bfq_bfqq_budget_timeout(bfqq); | |
| + | |
| + /* | |
| + * There is just this request queued: if the request | |
| + * is small and the queue is not to be expired, then | |
| + * just exit. | |
| + * | |
| + * In this way, if the disk is being idled to wait for | |
| + * a new request from the in-service queue, we avoid | |
| + * unplugging the device and committing the disk to serve | |
| + * just a small request. On the contrary, we wait for | |
| + * the block layer to decide when to unplug the device: | |
| + * hopefully, new requests will be merged to this one | |
| + * quickly, then the device will be unplugged and | |
| + * larger requests will be dispatched. | |
| + */ | |
| + if (small_req && !budget_timeout) | |
| + return; | |
| + | |
| + /* | |
| + * A large enough request arrived, or the queue is to | |
| + * be expired: in both cases disk idling is to be | |
| + * stopped, so clear wait_request flag and reset | |
| + * timer. | |
| + */ | |
| + bfq_clear_bfqq_wait_request(bfqq); | |
| + del_timer(&bfqd->idle_slice_timer); | |
| +#ifdef CONFIG_BFQ_GROUP_IOSCHED | |
| + bfqg_stats_update_idle_time(bfqq_group(bfqq)); | |
| +#endif | |
| + | |
| + /* | |
| + * The queue is not empty, because a new request just | |
| + * arrived. Hence we can safely expire the queue, in | |
| + * case of budget timeout, without risking that the | |
| + * timestamps of the queue are not updated correctly. | |
| + * See [1] for more details. | |
| + */ | |
| + if (budget_timeout) | |
| + bfq_bfqq_expire(bfqd, bfqq, false, | |
| + BFQ_BFQQ_BUDGET_TIMEOUT); | |
| + | |
| + /* | |
| + * Let the request rip immediately, or let a new queue be | |
| + * selected if bfqq has just been expired. | |
| + */ | |
| + __blk_run_queue(bfqd->queue); | |
| + } | |
| +} | |
| + | |
| +static void bfq_insert_request(struct request_queue *q, struct request *rq) | |
| +{ | |
| + struct bfq_data *bfqd = q->elevator->elevator_data; | |
| + struct bfq_queue *bfqq = RQ_BFQQ(rq), *new_bfqq; | |
| + | |
| + assert_spin_locked(bfqd->queue->queue_lock); | |
| + | |
| + /* | |
| + * An unplug may trigger a requeue of a request from the device | |
| + * driver: make sure we are in process context while trying to | |
| + * merge two bfq_queues. | |
| + */ | |
| + if (!in_interrupt()) { | |
| + new_bfqq = bfq_setup_cooperator(bfqd, bfqq, rq, true); | |
| + if (new_bfqq) { | |
| + if (bic_to_bfqq(RQ_BIC(rq), 1) != bfqq) | |
| + new_bfqq = bic_to_bfqq(RQ_BIC(rq), 1); | |
| + /* | |
| + * Release the request's reference to the old bfqq | |
| + * and make sure one is taken to the shared queue. | |
| + */ | |
| + new_bfqq->allocated[rq_data_dir(rq)]++; | |
| + bfqq->allocated[rq_data_dir(rq)]--; | |
| + atomic_inc(&new_bfqq->ref); | |
| + bfq_put_queue(bfqq); | |
| + if (bic_to_bfqq(RQ_BIC(rq), 1) == bfqq) | |
| + bfq_merge_bfqqs(bfqd, RQ_BIC(rq), | |
| + bfqq, new_bfqq); | |
| + rq->elv.priv[1] = new_bfqq; | |
| + bfqq = new_bfqq; | |
| + } else | |
| + bfq_bfqq_increase_failed_cooperations(bfqq); | |
| + } | |
| + | |
| + bfq_add_request(rq); | |
| + | |
| + /* | |
| + * Here a newly-created bfq_queue has already started a weight-raising | |
| + * period: clear raising_time_left to prevent bfq_bfqq_save_state() | |
| + * from assigning it a full weight-raising period. See the detailed | |
| + * comments about this field in bfq_init_icq(). | |
| + */ | |
| + if (bfqq->bic) | |
| + bfqq->bic->wr_time_left = 0; | |
| + rq->fifo_time = jiffies + bfqd->bfq_fifo_expire[rq_is_sync(rq)]; | |
| + list_add_tail(&rq->queuelist, &bfqq->fifo); | |
| + | |
| + bfq_rq_enqueued(bfqd, bfqq, rq); | |
| +} | |
| + | |
| +static void bfq_update_hw_tag(struct bfq_data *bfqd) | |
| +{ | |
| + bfqd->max_rq_in_driver = max(bfqd->max_rq_in_driver, | |
| + bfqd->rq_in_driver); | |
| + | |
| + if (bfqd->hw_tag == 1) | |
| + return; | |
| + | |
| + /* | |
| + * This sample is valid if the number of outstanding requests | |
| + * is large enough to allow a queueing behavior. Note that the | |
| + * sum is not exact, as it's not taking into account deactivated | |
| + * requests. | |
| + */ | |
| + if (bfqd->rq_in_driver + bfqd->queued < BFQ_HW_QUEUE_THRESHOLD) | |
| + return; | |
| + | |
| + if (bfqd->hw_tag_samples++ < BFQ_HW_QUEUE_SAMPLES) | |
| + return; | |
| + | |
| + bfqd->hw_tag = bfqd->max_rq_in_driver > BFQ_HW_QUEUE_THRESHOLD; | |
| + bfqd->max_rq_in_driver = 0; | |
| + bfqd->hw_tag_samples = 0; | |
| +} | |
| + | |
| +static void bfq_completed_request(struct request_queue *q, struct request *rq) | |
| +{ | |
| + struct bfq_queue *bfqq = RQ_BFQQ(rq); | |
| + struct bfq_data *bfqd = bfqq->bfqd; | |
| + bool sync = bfq_bfqq_sync(bfqq); | |
| + | |
| + bfq_log_bfqq(bfqd, bfqq, "completed one req with %u sects left (%d)", | |
| + blk_rq_sectors(rq), sync); | |
| + | |
| + bfq_update_hw_tag(bfqd); | |
| + | |
| + BUG_ON(!bfqd->rq_in_driver); | |
| + BUG_ON(!bfqq->dispatched); | |
| + bfqd->rq_in_driver--; | |
| + bfqq->dispatched--; | |
| +#ifdef CONFIG_BFQ_GROUP_IOSCHED | |
| + bfqg_stats_update_completion(bfqq_group(bfqq), | |
| + rq_start_time_ns(rq), | |
| + rq_io_start_time_ns(rq), rq->cmd_flags); | |
| +#endif | |
| + | |
| + if (!bfqq->dispatched && !bfq_bfqq_busy(bfqq)) { | |
| + bfq_weights_tree_remove(bfqd, &bfqq->entity, | |
| + &bfqd->queue_weights_tree); | |
| + if (!blk_queue_nonrot(bfqd->queue)) { | |
| + BUG_ON(!bfqd->busy_in_flight_queues); | |
| + bfqd->busy_in_flight_queues--; | |
| + if (bfq_bfqq_constantly_seeky(bfqq)) { | |
| + BUG_ON(!bfqd-> | |
| + const_seeky_busy_in_flight_queues); | |
| + bfqd->const_seeky_busy_in_flight_queues--; | |
| + } | |
| + } | |
| + } | |
| + | |
| + if (sync) { | |
| + bfqd->sync_flight--; | |
| + RQ_BIC(rq)->ttime.last_end_request = jiffies; | |
| + } | |
| + | |
| + /* | |
| + * If we are waiting to discover whether the request pattern of the | |
| + * task associated with the queue is actually isochronous, and | |
| + * both requisites for this condition to hold are satisfied, then | |
| + * compute soft_rt_next_start (see the comments to the function | |
| + * bfq_bfqq_softrt_next_start()). | |
| + */ | |
| + if (bfq_bfqq_softrt_update(bfqq) && bfqq->dispatched == 0 && | |
| + RB_EMPTY_ROOT(&bfqq->sort_list)) | |
| + bfqq->soft_rt_next_start = | |
| + bfq_bfqq_softrt_next_start(bfqd, bfqq); | |
| + | |
| + /* | |
| + * If this is the in-service queue, check if it needs to be expired, | |
| + * or if we want to idle in case it has no pending requests. | |
| + */ | |
| + if (bfqd->in_service_queue == bfqq) { | |
| + if (bfq_bfqq_budget_new(bfqq)) | |
| + bfq_set_budget_timeout(bfqd); | |
| + | |
| + if (bfq_bfqq_must_idle(bfqq)) { | |
| + bfq_arm_slice_timer(bfqd); | |
| + goto out; | |
| + } else if (bfq_may_expire_for_budg_timeout(bfqq)) | |
| + bfq_bfqq_expire(bfqd, bfqq, false, | |
| + BFQ_BFQQ_BUDGET_TIMEOUT); | |
| + else if (RB_EMPTY_ROOT(&bfqq->sort_list) && | |
| + (bfqq->dispatched == 0 || | |
| + !bfq_bfqq_may_idle(bfqq))) | |
| + bfq_bfqq_expire(bfqd, bfqq, false, | |
| + BFQ_BFQQ_NO_MORE_REQUESTS); | |
| + } | |
| + | |
| + if (!bfqd->rq_in_driver) | |
| + bfq_schedule_dispatch(bfqd); | |
| + | |
| +out: | |
| + return; | |
| +} | |
| + | |
| +static int __bfq_may_queue(struct bfq_queue *bfqq) | |
| +{ | |
| + if (bfq_bfqq_wait_request(bfqq) && bfq_bfqq_must_alloc(bfqq)) { | |
| + bfq_clear_bfqq_must_alloc(bfqq); | |
| + return ELV_MQUEUE_MUST; | |
| + } | |
| + | |
| + return ELV_MQUEUE_MAY; | |
| +} | |
| + | |
| +static int bfq_may_queue(struct request_queue *q, int rw) | |
| +{ | |
| + struct bfq_data *bfqd = q->elevator->elevator_data; | |
| + struct task_struct *tsk = current; | |
| + struct bfq_io_cq *bic; | |
| + struct bfq_queue *bfqq; | |
| + | |
| + /* | |
| + * Don't force setup of a queue from here, as a call to may_queue | |
| + * does not necessarily imply that a request actually will be | |
| + * queued. So just lookup a possibly existing queue, or return | |
| + * 'may queue' if that fails. | |
| + */ | |
| + bic = bfq_bic_lookup(bfqd, tsk->io_context); | |
| + if (!bic) | |
| + return ELV_MQUEUE_MAY; | |
| + | |
| + bfqq = bic_to_bfqq(bic, rw_is_sync(rw)); | |
| + if (bfqq) | |
| + return __bfq_may_queue(bfqq); | |
| + | |
| + return ELV_MQUEUE_MAY; | |
| +} | |
| + | |
| +/* | |
| + * Queue lock held here. | |
| + */ | |
| +static void bfq_put_request(struct request *rq) | |
| +{ | |
| + struct bfq_queue *bfqq = RQ_BFQQ(rq); | |
| + | |
| + if (bfqq) { | |
| + const int rw = rq_data_dir(rq); | |
| + | |
| + BUG_ON(!bfqq->allocated[rw]); | |
| + bfqq->allocated[rw]--; | |
| + | |
| + rq->elv.priv[0] = NULL; | |
| + rq->elv.priv[1] = NULL; | |
| + | |
| + bfq_log_bfqq(bfqq->bfqd, bfqq, "put_request %p, %d", | |
| + bfqq, atomic_read(&bfqq->ref)); | |
| + bfq_put_queue(bfqq); | |
| + } | |
| +} | |
| + | |
| +/* | |
| + * Returns NULL if a new bfqq should be allocated, or the old bfqq if this | |
| + * was the last process referring to said bfqq. | |
| + */ | |
| +static struct bfq_queue * | |
| +bfq_split_bfqq(struct bfq_io_cq *bic, struct bfq_queue *bfqq) | |
| +{ | |
| + bfq_log_bfqq(bfqq->bfqd, bfqq, "splitting queue"); | |
| + | |
| + put_io_context(bic->icq.ioc); | |
| + | |
| + if (bfqq_process_refs(bfqq) == 1) { | |
| + bfqq->pid = current->pid; | |
| + bfq_clear_bfqq_coop(bfqq); | |
| + bfq_clear_bfqq_split_coop(bfqq); | |
| + return bfqq; | |
| + } | |
| + | |
| + bic_set_bfqq(bic, NULL, 1); | |
| + | |
| + bfq_put_cooperator(bfqq); | |
| + | |
| + bfq_put_queue(bfqq); | |
| + return NULL; | |
| +} | |
| + | |
| +/* | |
| + * Allocate bfq data structures associated with this request. | |
| + */ | |
| +static int bfq_set_request(struct request_queue *q, struct request *rq, | |
| + struct bio *bio, gfp_t gfp_mask) | |
| +{ | |
| + struct bfq_data *bfqd = q->elevator->elevator_data; | |
| + struct bfq_io_cq *bic = icq_to_bic(rq->elv.icq); | |
| + const int rw = rq_data_dir(rq); | |
| + const int is_sync = rq_is_sync(rq); | |
| + struct bfq_queue *bfqq; | |
| + unsigned long flags; | |
| + bool split = false; | |
| + | |
| + might_sleep_if(gfpflags_allow_blocking(gfp_mask)); | |
| + | |
| + bfq_check_ioprio_change(bic, bio); | |
| + | |
| + spin_lock_irqsave(q->queue_lock, flags); | |
| + | |
| + if (!bic) | |
| + goto queue_fail; | |
| + | |
| + bfq_bic_update_cgroup(bic, bio); | |
| + | |
| +new_queue: | |
| + bfqq = bic_to_bfqq(bic, is_sync); | |
| + if (!bfqq || bfqq == &bfqd->oom_bfqq) { | |
| + bfqq = bfq_get_queue(bfqd, bio, is_sync, bic, gfp_mask); | |
| + bic_set_bfqq(bic, bfqq, is_sync); | |
| + if (split && is_sync) { | |
| + if ((bic->was_in_burst_list && bfqd->large_burst) || | |
| + bic->saved_in_large_burst) | |
| + bfq_mark_bfqq_in_large_burst(bfqq); | |
| + else { | |
| + bfq_clear_bfqq_in_large_burst(bfqq); | |
| + if (bic->was_in_burst_list) | |
| + hlist_add_head(&bfqq->burst_list_node, | |
| + &bfqd->burst_list); | |
| + } | |
| + } | |
| + } else { | |
| + /* If the queue was seeky for too long, break it apart. */ | |
| + if (bfq_bfqq_coop(bfqq) && bfq_bfqq_split_coop(bfqq)) { | |
| + bfq_log_bfqq(bfqd, bfqq, "breaking apart bfqq"); | |
| + bfqq = bfq_split_bfqq(bic, bfqq); | |
| + split = true; | |
| + if (!bfqq) | |
| + goto new_queue; | |
| + } | |
| + } | |
| + | |
| + bfqq->allocated[rw]++; | |
| + atomic_inc(&bfqq->ref); | |
| + bfq_log_bfqq(bfqd, bfqq, "set_request: bfqq %p, %d", bfqq, | |
| + atomic_read(&bfqq->ref)); | |
| + | |
| + rq->elv.priv[0] = bic; | |
| + rq->elv.priv[1] = bfqq; | |
| + | |
| + /* | |
| + * If a bfq_queue has only one process reference, it is owned | |
| + * by only one bfq_io_cq: we can set the bic field of the | |
| + * bfq_queue to the address of that structure. Also, if the | |
| + * queue has just been split, mark a flag so that the | |
| + * information is available to the other scheduler hooks. | |
| + */ | |
| + if (likely(bfqq != &bfqd->oom_bfqq) && bfqq_process_refs(bfqq) == 1) { | |
| + bfqq->bic = bic; | |
| + if (split) { | |
| + bfq_mark_bfqq_just_split(bfqq); | |
| + /* | |
| + * If the queue has just been split from a shared | |
| + * queue, restore the idle window and the possible | |
| + * weight raising period. | |
| + */ | |
| + bfq_bfqq_resume_state(bfqq, bic); | |
| + } | |
| + } | |
| + | |
| + spin_unlock_irqrestore(q->queue_lock, flags); | |
| + | |
| + return 0; | |
| + | |
| +queue_fail: | |
| + bfq_schedule_dispatch(bfqd); | |
| + spin_unlock_irqrestore(q->queue_lock, flags); | |
| + | |
| + return 1; | |
| +} | |
| + | |
| +static void bfq_kick_queue(struct work_struct *work) | |
| +{ | |
| + struct bfq_data *bfqd = | |
| + container_of(work, struct bfq_data, unplug_work); | |
| + struct request_queue *q = bfqd->queue; | |
| + | |
| + spin_lock_irq(q->queue_lock); | |
| + __blk_run_queue(q); | |
| + spin_unlock_irq(q->queue_lock); | |
| +} | |
| + | |
| +/* | |
| + * Handler of the expiration of the timer running if the in-service queue | |
| + * is idling inside its time slice. | |
| + */ | |
| +static void bfq_idle_slice_timer(unsigned long data) | |
| +{ | |
| + struct bfq_data *bfqd = (struct bfq_data *)data; | |
| + struct bfq_queue *bfqq; | |
| + unsigned long flags; | |
| + enum bfqq_expiration reason; | |
| + | |
| + spin_lock_irqsave(bfqd->queue->queue_lock, flags); | |
| + | |
| + bfqq = bfqd->in_service_queue; | |
| + /* | |
| + * Theoretical race here: the in-service queue can be NULL or | |
| + * different from the queue that was idling if the timer handler | |
| + * spins on the queue_lock and a new request arrives for the | |
| + * current queue and there is a full dispatch cycle that changes | |
| + * the in-service queue. This can hardly happen, but in the worst | |
| + * case we just expire a queue too early. | |
| + */ | |
| + if (bfqq) { | |
| + bfq_log_bfqq(bfqd, bfqq, "slice_timer expired"); | |
| + if (bfq_bfqq_budget_timeout(bfqq)) | |
| + /* | |
| + * Also here the queue can be safely expired | |
| + * for budget timeout without wasting | |
| + * guarantees | |
| + */ | |
| + reason = BFQ_BFQQ_BUDGET_TIMEOUT; | |
| + else if (bfqq->queued[0] == 0 && bfqq->queued[1] == 0) | |
| + /* | |
| + * The queue may not be empty upon timer expiration, | |
| + * because we may not disable the timer when the | |
| + * first request of the in-service queue arrives | |
| + * during disk idling. | |
| + */ | |
| + reason = BFQ_BFQQ_TOO_IDLE; | |
| + else | |
| + goto schedule_dispatch; | |
| + | |
| + bfq_bfqq_expire(bfqd, bfqq, true, reason); | |
| + } | |
| + | |
| +schedule_dispatch: | |
| + bfq_schedule_dispatch(bfqd); | |
| + | |
| + spin_unlock_irqrestore(bfqd->queue->queue_lock, flags); | |
| +} | |
| + | |
| +static void bfq_shutdown_timer_wq(struct bfq_data *bfqd) | |
| +{ | |
| + del_timer_sync(&bfqd->idle_slice_timer); | |
| + cancel_work_sync(&bfqd->unplug_work); | |
| +} | |
| + | |
| +static void __bfq_put_async_bfqq(struct bfq_data *bfqd, | |
| + struct bfq_queue **bfqq_ptr) | |
| +{ | |
| + struct bfq_group *root_group = bfqd->root_group; | |
| + struct bfq_queue *bfqq = *bfqq_ptr; | |
| + | |
| + bfq_log(bfqd, "put_async_bfqq: %p", bfqq); | |
| + if (bfqq) { | |
| + bfq_bfqq_move(bfqd, bfqq, &bfqq->entity, root_group); | |
| + bfq_log_bfqq(bfqd, bfqq, "put_async_bfqq: putting %p, %d", | |
| + bfqq, atomic_read(&bfqq->ref)); | |
| + bfq_put_queue(bfqq); | |
| + *bfqq_ptr = NULL; | |
| + } | |
| +} | |
| + | |
| +/* | |
| + * Release all the bfqg references to its async queues. If we are | |
| + * deallocating the group these queues may still contain requests, so | |
| + * we reparent them to the root cgroup (i.e., the only one that will | |
| + * exist for sure until all the requests on a device are gone). | |
| + */ | |
| +static void bfq_put_async_queues(struct bfq_data *bfqd, struct bfq_group *bfqg) | |
| +{ | |
| + int i, j; | |
| + | |
| + for (i = 0; i < 2; i++) | |
| + for (j = 0; j < IOPRIO_BE_NR; j++) | |
| + __bfq_put_async_bfqq(bfqd, &bfqg->async_bfqq[i][j]); | |
| + | |
| + __bfq_put_async_bfqq(bfqd, &bfqg->async_idle_bfqq); | |
| +} | |
| + | |
| +static void bfq_exit_queue(struct elevator_queue *e) | |
| +{ | |
| + struct bfq_data *bfqd = e->elevator_data; | |
| + struct request_queue *q = bfqd->queue; | |
| + struct bfq_queue *bfqq, *n; | |
| + | |
| + bfq_shutdown_timer_wq(bfqd); | |
| + | |
| + spin_lock_irq(q->queue_lock); | |
| + | |
| + BUG_ON(bfqd->in_service_queue); | |
| + list_for_each_entry_safe(bfqq, n, &bfqd->idle_list, bfqq_list) | |
| + bfq_deactivate_bfqq(bfqd, bfqq, 0); | |
| + | |
| + spin_unlock_irq(q->queue_lock); | |
| + | |
| + bfq_shutdown_timer_wq(bfqd); | |
| + | |
| + synchronize_rcu(); | |
| + | |
| + BUG_ON(timer_pending(&bfqd->idle_slice_timer)); | |
| + | |
| +#ifdef CONFIG_BFQ_GROUP_IOSCHED | |
| + blkcg_deactivate_policy(q, &blkcg_policy_bfq); | |
| +#else | |
| + kfree(bfqd->root_group); | |
| +#endif | |
| + | |
| + kfree(bfqd); | |
| +} | |
| + | |
| +static void bfq_init_root_group(struct bfq_group *root_group, | |
| + struct bfq_data *bfqd) | |
| +{ | |
| + int i; | |
| + | |
| +#ifdef CONFIG_BFQ_GROUP_IOSCHED | |
| + root_group->entity.parent = NULL; | |
| + root_group->my_entity = NULL; | |
| + root_group->bfqd = bfqd; | |
| +#endif | |
| + root_group->rq_pos_tree = RB_ROOT; | |
| + for (i = 0; i < BFQ_IOPRIO_CLASSES; i++) | |
| + root_group->sched_data.service_tree[i] = BFQ_SERVICE_TREE_INIT; | |
| +} | |
| + | |
| +static int bfq_init_queue(struct request_queue *q, struct elevator_type *e) | |
| +{ | |
| + struct bfq_data *bfqd; | |
| + struct elevator_queue *eq; | |
| + | |
| + eq = elevator_alloc(q, e); | |
| + if (!eq) | |
| + return -ENOMEM; | |
| + | |
| + bfqd = kzalloc_node(sizeof(*bfqd), GFP_KERNEL, q->node); | |
| + if (!bfqd) { | |
| + kobject_put(&eq->kobj); | |
| + return -ENOMEM; | |
| + } | |
| + eq->elevator_data = bfqd; | |
| + | |
| + /* | |
| + * Our fallback bfqq if bfq_find_alloc_queue() runs into OOM issues. | |
| + * Grab a permanent reference to it, so that the normal code flow | |
| + * will not attempt to free it. | |
| + */ | |
| + bfq_init_bfqq(bfqd, &bfqd->oom_bfqq, NULL, 1, 0); | |
| + atomic_inc(&bfqd->oom_bfqq.ref); | |
| + bfqd->oom_bfqq.new_ioprio = BFQ_DEFAULT_QUEUE_IOPRIO; | |
| + bfqd->oom_bfqq.new_ioprio_class = IOPRIO_CLASS_BE; | |
| + bfqd->oom_bfqq.entity.new_weight = | |
| + bfq_ioprio_to_weight(bfqd->oom_bfqq.new_ioprio); | |
| + /* | |
| + * Trigger weight initialization, according to ioprio, at the | |
| + * oom_bfqq's first activation. The oom_bfqq's ioprio and ioprio | |
| + * class won't be changed any more. | |
| + */ | |
| + bfqd->oom_bfqq.entity.prio_changed = 1; | |
| + | |
| + bfqd->queue = q; | |
| + | |
| + spin_lock_irq(q->queue_lock); | |
| + q->elevator = eq; | |
| + spin_unlock_irq(q->queue_lock); | |
| + | |
| + bfqd->root_group = bfq_create_group_hierarchy(bfqd, q->node); | |
| + if (!bfqd->root_group) | |
| + goto out_free; | |
| + bfq_init_root_group(bfqd->root_group, bfqd); | |
| + bfq_init_entity(&bfqd->oom_bfqq.entity, bfqd->root_group); | |
| +#ifdef CONFIG_BFQ_GROUP_IOSCHED | |
| + bfqd->active_numerous_groups = 0; | |
| +#endif | |
| + | |
| + init_timer(&bfqd->idle_slice_timer); | |
| + bfqd->idle_slice_timer.function = bfq_idle_slice_timer; | |
| + bfqd->idle_slice_timer.data = (unsigned long)bfqd; | |
| + | |
| + bfqd->queue_weights_tree = RB_ROOT; | |
| + bfqd->group_weights_tree = RB_ROOT; | |
| + | |
| + INIT_WORK(&bfqd->unplug_work, bfq_kick_queue); | |
| + | |
| + INIT_LIST_HEAD(&bfqd->active_list); | |
| + INIT_LIST_HEAD(&bfqd->idle_list); | |
| + INIT_HLIST_HEAD(&bfqd->burst_list); | |
| + | |
| + bfqd->hw_tag = -1; | |
| + | |
| + bfqd->bfq_max_budget = bfq_default_max_budget; | |
| + | |
| + bfqd->bfq_fifo_expire[0] = bfq_fifo_expire[0]; | |
| + bfqd->bfq_fifo_expire[1] = bfq_fifo_expire[1]; | |
| + bfqd->bfq_back_max = bfq_back_max; | |
| + bfqd->bfq_back_penalty = bfq_back_penalty; | |
| + bfqd->bfq_slice_idle = bfq_slice_idle; | |
| + bfqd->bfq_class_idle_last_service = 0; | |
| + bfqd->bfq_max_budget_async_rq = bfq_max_budget_async_rq; | |
| + bfqd->bfq_timeout[BLK_RW_ASYNC] = bfq_timeout_async; | |
| + bfqd->bfq_timeout[BLK_RW_SYNC] = bfq_timeout_sync; | |
| + | |
| + bfqd->bfq_coop_thresh = 2; | |
| + bfqd->bfq_failed_cooperations = 7000; | |
| + bfqd->bfq_requests_within_timer = 120; | |
| + | |
| + bfqd->bfq_large_burst_thresh = 11; | |
| + bfqd->bfq_burst_interval = msecs_to_jiffies(500); | |
| + | |
| + bfqd->low_latency = true; | |
| + | |
| + bfqd->bfq_wr_coeff = 20; | |
| + bfqd->bfq_wr_rt_max_time = msecs_to_jiffies(300); | |
| + bfqd->bfq_wr_max_time = 0; | |
| + bfqd->bfq_wr_min_idle_time = msecs_to_jiffies(2000); | |
| + bfqd->bfq_wr_min_inter_arr_async = msecs_to_jiffies(500); | |
| + bfqd->bfq_wr_max_softrt_rate = 7000; /* | |
| + * Approximate rate required | |
| + * to playback or record a | |
| + * high-definition compressed | |
| + * video. | |
| + */ | |
| + bfqd->wr_busy_queues = 0; | |
| + bfqd->busy_in_flight_queues = 0; | |
| + bfqd->const_seeky_busy_in_flight_queues = 0; | |
| + | |
| + /* | |
| + * Begin by assuming, optimistically, that the device peak rate is | |
| + * equal to the highest reference rate. | |
| + */ | |
| + bfqd->RT_prod = R_fast[blk_queue_nonrot(bfqd->queue)] * | |
| + T_fast[blk_queue_nonrot(bfqd->queue)]; | |
| + bfqd->peak_rate = R_fast[blk_queue_nonrot(bfqd->queue)]; | |
| + bfqd->device_speed = BFQ_BFQD_FAST; | |
| + | |
| + return 0; | |
| + | |
| +out_free: | |
| + kfree(bfqd); | |
| + kobject_put(&eq->kobj); | |
| + return -ENOMEM; | |
| +} | |
| + | |
| +static void bfq_slab_kill(void) | |
| +{ | |
| + if (bfq_pool) | |
| + kmem_cache_destroy(bfq_pool); | |
| +} | |
| + | |
| +static int __init bfq_slab_setup(void) | |
| +{ | |
| + bfq_pool = KMEM_CACHE(bfq_queue, 0); | |
| + if (!bfq_pool) | |
| + return -ENOMEM; | |
| + return 0; | |
| +} | |
| + | |
| +static ssize_t bfq_var_show(unsigned int var, char *page) | |
| +{ | |
| + return sprintf(page, "%d\n", var); | |
| +} | |
| + | |
| +static ssize_t bfq_var_store(unsigned long *var, const char *page, | |
| + size_t count) | |
| +{ | |
| + unsigned long new_val; | |
| + int ret = kstrtoul(page, 10, &new_val); | |
| + | |
| + if (ret == 0) | |
| + *var = new_val; | |
| + | |
| + return count; | |
| +} | |
| + | |
| +static ssize_t bfq_wr_max_time_show(struct elevator_queue *e, char *page) | |
| +{ | |
| + struct bfq_data *bfqd = e->elevator_data; | |
| + return sprintf(page, "%d\n", bfqd->bfq_wr_max_time > 0 ? | |
| + jiffies_to_msecs(bfqd->bfq_wr_max_time) : | |
| + jiffies_to_msecs(bfq_wr_duration(bfqd))); | |
| +} | |
| + | |
| +static ssize_t bfq_weights_show(struct elevator_queue *e, char *page) | |
| +{ | |
| + struct bfq_queue *bfqq; | |
| + struct bfq_data *bfqd = e->elevator_data; | |
| + ssize_t num_char = 0; | |
| + | |
| + num_char += sprintf(page + num_char, "Tot reqs queued %d\n\n", | |
| + bfqd->queued); | |
| + | |
| + spin_lock_irq(bfqd->queue->queue_lock); | |
| + | |
| + num_char += sprintf(page + num_char, "Active:\n"); | |
| + list_for_each_entry(bfqq, &bfqd->active_list, bfqq_list) { | |
| + num_char += sprintf(page + num_char, | |
| + "pid%d: weight %hu, nr_queued %d %d, dur %d/%u\n", | |
| + bfqq->pid, | |
| + bfqq->entity.weight, | |
| + bfqq->queued[0], | |
| + bfqq->queued[1], | |
| + jiffies_to_msecs(jiffies - bfqq->last_wr_start_finish), | |
| + jiffies_to_msecs(bfqq->wr_cur_max_time)); | |
| + } | |
| + | |
| + num_char += sprintf(page + num_char, "Idle:\n"); | |
| + list_for_each_entry(bfqq, &bfqd->idle_list, bfqq_list) { | |
| + num_char += sprintf(page + num_char, | |
| + "pid%d: weight %hu, dur %d/%u\n", | |
| + bfqq->pid, | |
| + bfqq->entity.weight, | |
| + jiffies_to_msecs(jiffies - | |
| + bfqq->last_wr_start_finish), | |
| + jiffies_to_msecs(bfqq->wr_cur_max_time)); | |
| + } | |
| + | |
| + spin_unlock_irq(bfqd->queue->queue_lock); | |
| + | |
| + return num_char; | |
| +} | |
| + | |
| +#define SHOW_FUNCTION(__FUNC, __VAR, __CONV) \ | |
| +static ssize_t __FUNC(struct elevator_queue *e, char *page) \ | |
| +{ \ | |
| + struct bfq_data *bfqd = e->elevator_data; \ | |
| + unsigned int __data = __VAR; \ | |
| + if (__CONV) \ | |
| + __data = jiffies_to_msecs(__data); \ | |
| + return bfq_var_show(__data, (page)); \ | |
| +} | |
| +SHOW_FUNCTION(bfq_fifo_expire_sync_show, bfqd->bfq_fifo_expire[1], 1); | |
| +SHOW_FUNCTION(bfq_fifo_expire_async_show, bfqd->bfq_fifo_expire[0], 1); | |
| +SHOW_FUNCTION(bfq_back_seek_max_show, bfqd->bfq_back_max, 0); | |
| +SHOW_FUNCTION(bfq_back_seek_penalty_show, bfqd->bfq_back_penalty, 0); | |
| +SHOW_FUNCTION(bfq_slice_idle_show, bfqd->bfq_slice_idle, 1); | |
| +SHOW_FUNCTION(bfq_max_budget_show, bfqd->bfq_user_max_budget, 0); | |
| +SHOW_FUNCTION(bfq_max_budget_async_rq_show, | |
| + bfqd->bfq_max_budget_async_rq, 0); | |
| +SHOW_FUNCTION(bfq_timeout_sync_show, bfqd->bfq_timeout[BLK_RW_SYNC], 1); | |
| +SHOW_FUNCTION(bfq_timeout_async_show, bfqd->bfq_timeout[BLK_RW_ASYNC], 1); | |
| +SHOW_FUNCTION(bfq_low_latency_show, bfqd->low_latency, 0); | |
| +SHOW_FUNCTION(bfq_wr_coeff_show, bfqd->bfq_wr_coeff, 0); | |
| +SHOW_FUNCTION(bfq_wr_rt_max_time_show, bfqd->bfq_wr_rt_max_time, 1); | |
| +SHOW_FUNCTION(bfq_wr_min_idle_time_show, bfqd->bfq_wr_min_idle_time, 1); | |
| +SHOW_FUNCTION(bfq_wr_min_inter_arr_async_show, bfqd->bfq_wr_min_inter_arr_async, | |
| + 1); | |
| +SHOW_FUNCTION(bfq_wr_max_softrt_rate_show, bfqd->bfq_wr_max_softrt_rate, 0); | |
| +#undef SHOW_FUNCTION | |
| + | |
| +#define STORE_FUNCTION(__FUNC, __PTR, MIN, MAX, __CONV) \ | |
| +static ssize_t \ | |
| +__FUNC(struct elevator_queue *e, const char *page, size_t count) \ | |
| +{ \ | |
| + struct bfq_data *bfqd = e->elevator_data; \ | |
| + unsigned long uninitialized_var(__data); \ | |
| + int ret = bfq_var_store(&__data, (page), count); \ | |
| + if (__data < (MIN)) \ | |
| + __data = (MIN); \ | |
| + else if (__data > (MAX)) \ | |
| + __data = (MAX); \ | |
| + if (__CONV) \ | |
| + *(__PTR) = msecs_to_jiffies(__data); \ | |
| + else \ | |
| + *(__PTR) = __data; \ | |
| + return ret; \ | |
| +} | |
| +STORE_FUNCTION(bfq_fifo_expire_sync_store, &bfqd->bfq_fifo_expire[1], 1, | |
| + INT_MAX, 1); | |
| +STORE_FUNCTION(bfq_fifo_expire_async_store, &bfqd->bfq_fifo_expire[0], 1, | |
| + INT_MAX, 1); | |
| +STORE_FUNCTION(bfq_back_seek_max_store, &bfqd->bfq_back_max, 0, INT_MAX, 0); | |
| +STORE_FUNCTION(bfq_back_seek_penalty_store, &bfqd->bfq_back_penalty, 1, | |
| + INT_MAX, 0); | |
| +STORE_FUNCTION(bfq_slice_idle_store, &bfqd->bfq_slice_idle, 0, INT_MAX, 1); | |
| +STORE_FUNCTION(bfq_max_budget_async_rq_store, &bfqd->bfq_max_budget_async_rq, | |
| + 1, INT_MAX, 0); | |
| +STORE_FUNCTION(bfq_timeout_async_store, &bfqd->bfq_timeout[BLK_RW_ASYNC], 0, | |
| + INT_MAX, 1); | |
| +STORE_FUNCTION(bfq_wr_coeff_store, &bfqd->bfq_wr_coeff, 1, INT_MAX, 0); | |
| +STORE_FUNCTION(bfq_wr_max_time_store, &bfqd->bfq_wr_max_time, 0, INT_MAX, 1); | |
| +STORE_FUNCTION(bfq_wr_rt_max_time_store, &bfqd->bfq_wr_rt_max_time, 0, INT_MAX, | |
| + 1); | |
| +STORE_FUNCTION(bfq_wr_min_idle_time_store, &bfqd->bfq_wr_min_idle_time, 0, | |
| + INT_MAX, 1); | |
| +STORE_FUNCTION(bfq_wr_min_inter_arr_async_store, | |
| + &bfqd->bfq_wr_min_inter_arr_async, 0, INT_MAX, 1); | |
| +STORE_FUNCTION(bfq_wr_max_softrt_rate_store, &bfqd->bfq_wr_max_softrt_rate, 0, | |
| + INT_MAX, 0); | |
| +#undef STORE_FUNCTION | |
| + | |
| +/* do nothing for the moment */ | |
| +static ssize_t bfq_weights_store(struct elevator_queue *e, | |
| + const char *page, size_t count) | |
| +{ | |
| + return count; | |
| +} | |
| + | |
| +static unsigned long bfq_estimated_max_budget(struct bfq_data *bfqd) | |
| +{ | |
| + u64 timeout = jiffies_to_msecs(bfqd->bfq_timeout[BLK_RW_SYNC]); | |
| + | |
| + if (bfqd->peak_rate_samples >= BFQ_PEAK_RATE_SAMPLES) | |
| + return bfq_calc_max_budget(bfqd->peak_rate, timeout); | |
| + else | |
| + return bfq_default_max_budget; | |
| +} | |
| + | |
| +static ssize_t bfq_max_budget_store(struct elevator_queue *e, | |
| + const char *page, size_t count) | |
| +{ | |
| + struct bfq_data *bfqd = e->elevator_data; | |
| + unsigned long uninitialized_var(__data); | |
| + int ret = bfq_var_store(&__data, (page), count); | |
| + | |
| + if (__data == 0) | |
| + bfqd->bfq_max_budget = bfq_estimated_max_budget(bfqd); | |
| + else { | |
| + if (__data > INT_MAX) | |
| + __data = INT_MAX; | |
| + bfqd->bfq_max_budget = __data; | |
| + } | |
| + | |
| + bfqd->bfq_user_max_budget = __data; | |
| + | |
| + return ret; | |
| +} | |
| + | |
| +static ssize_t bfq_timeout_sync_store(struct elevator_queue *e, | |
| + const char *page, size_t count) | |
| +{ | |
| + struct bfq_data *bfqd = e->elevator_data; | |
| + unsigned long uninitialized_var(__data); | |
| + int ret = bfq_var_store(&__data, (page), count); | |
| + | |
| + if (__data < 1) | |
| + __data = 1; | |
| + else if (__data > INT_MAX) | |
| + __data = INT_MAX; | |
| + | |
| + bfqd->bfq_timeout[BLK_RW_SYNC] = msecs_to_jiffies(__data); | |
| + if (bfqd->bfq_user_max_budget == 0) | |
| + bfqd->bfq_max_budget = bfq_estimated_max_budget(bfqd); | |
| + | |
| + return ret; | |
| +} | |
| + | |
| +static ssize_t bfq_low_latency_store(struct elevator_queue *e, | |
| + const char *page, size_t count) | |
| +{ | |
| + struct bfq_data *bfqd = e->elevator_data; | |
| + unsigned long uninitialized_var(__data); | |
| + int ret = bfq_var_store(&__data, (page), count); | |
| + | |
| + if (__data > 1) | |
| + __data = 1; | |
| + if (__data == 0 && bfqd->low_latency != 0) | |
| + bfq_end_wr(bfqd); | |
| + bfqd->low_latency = __data; | |
| + | |
| + return ret; | |
| +} | |
| + | |
| +#define BFQ_ATTR(name) \ | |
| + __ATTR(name, S_IRUGO|S_IWUSR, bfq_##name##_show, bfq_##name##_store) | |
| + | |
| +static struct elv_fs_entry bfq_attrs[] = { | |
| + BFQ_ATTR(fifo_expire_sync), | |
| + BFQ_ATTR(fifo_expire_async), | |
| + BFQ_ATTR(back_seek_max), | |
| + BFQ_ATTR(back_seek_penalty), | |
| + BFQ_ATTR(slice_idle), | |
| + BFQ_ATTR(max_budget), | |
| + BFQ_ATTR(max_budget_async_rq), | |
| + BFQ_ATTR(timeout_sync), | |
| + BFQ_ATTR(timeout_async), | |
| + BFQ_ATTR(low_latency), | |
| + BFQ_ATTR(wr_coeff), | |
| + BFQ_ATTR(wr_max_time), | |
| + BFQ_ATTR(wr_rt_max_time), | |
| + BFQ_ATTR(wr_min_idle_time), | |
| + BFQ_ATTR(wr_min_inter_arr_async), | |
| + BFQ_ATTR(wr_max_softrt_rate), | |
| + BFQ_ATTR(weights), | |
| + __ATTR_NULL | |
| +}; | |
| + | |
| +static struct elevator_type iosched_bfq = { | |
| + .ops = { | |
| + .elevator_merge_fn = bfq_merge, | |
| + .elevator_merged_fn = bfq_merged_request, | |
| + .elevator_merge_req_fn = bfq_merged_requests, | |
| +#ifdef CONFIG_BFQ_GROUP_IOSCHED | |
| + .elevator_bio_merged_fn = bfq_bio_merged, | |
| +#endif | |
| + .elevator_allow_merge_fn = bfq_allow_merge, | |
| + .elevator_dispatch_fn = bfq_dispatch_requests, | |
| + .elevator_add_req_fn = bfq_insert_request, | |
| + .elevator_activate_req_fn = bfq_activate_request, | |
| + .elevator_deactivate_req_fn = bfq_deactivate_request, | |
| + .elevator_completed_req_fn = bfq_completed_request, | |
| + .elevator_former_req_fn = elv_rb_former_request, | |
| + .elevator_latter_req_fn = elv_rb_latter_request, | |
| + .elevator_init_icq_fn = bfq_init_icq, | |
| + .elevator_exit_icq_fn = bfq_exit_icq, | |
| + .elevator_set_req_fn = bfq_set_request, | |
| + .elevator_put_req_fn = bfq_put_request, | |
| + .elevator_may_queue_fn = bfq_may_queue, | |
| + .elevator_init_fn = bfq_init_queue, | |
| + .elevator_exit_fn = bfq_exit_queue, | |
| + }, | |
| + .icq_size = sizeof(struct bfq_io_cq), | |
| + .icq_align = __alignof__(struct bfq_io_cq), | |
| + .elevator_attrs = bfq_attrs, | |
| + .elevator_name = "bfq", | |
| + .elevator_owner = THIS_MODULE, | |
| +}; | |
| + | |
| +static int __init bfq_init(void) | |
| +{ | |
| + int ret; | |
| + | |
| + /* | |
| + * Can be 0 on HZ < 1000 setups. | |
| + */ | |
| + if (bfq_slice_idle == 0) | |
| + bfq_slice_idle = 1; | |
| + | |
| + if (bfq_timeout_async == 0) | |
| + bfq_timeout_async = 1; | |
| + | |
| +#ifdef CONFIG_BFQ_GROUP_IOSCHED | |
| + ret = blkcg_policy_register(&blkcg_policy_bfq); | |
| + if (ret) | |
| + return ret; | |
| +#endif | |
| + | |
| + ret = -ENOMEM; | |
| + if (bfq_slab_setup()) | |
| + goto err_pol_unreg; | |
| + | |
| + /* | |
| + * Times to load large popular applications for the typical systems | |
| + * installed on the reference devices (see the comments before the | |
| + * definitions of the two arrays). | |
| + */ | |
| + T_slow[0] = msecs_to_jiffies(2600); | |
| + T_slow[1] = msecs_to_jiffies(1000); | |
| + T_fast[0] = msecs_to_jiffies(5500); | |
| + T_fast[1] = msecs_to_jiffies(2000); | |
| + | |
| + /* | |
| + * Thresholds that determine the switch between speed classes (see | |
| + * the comments before the definition of the array). | |
| + */ | |
| + device_speed_thresh[0] = (R_fast[0] + R_slow[0]) / 2; | |
| + device_speed_thresh[1] = (R_fast[1] + R_slow[1]) / 2; | |
| + | |
| + ret = elv_register(&iosched_bfq); | |
| + if (ret) | |
| + goto err_pol_unreg; | |
| + | |
| + pr_info("BFQ I/O-scheduler: v7r11"); | |
| + | |
| + return 0; | |
| + | |
| +err_pol_unreg: | |
| +#ifdef CONFIG_BFQ_GROUP_IOSCHED | |
| + blkcg_policy_unregister(&blkcg_policy_bfq); | |
| +#endif | |
| + return ret; | |
| +} | |
| + | |
| +static void __exit bfq_exit(void) | |
| +{ | |
| + elv_unregister(&iosched_bfq); | |
| +#ifdef CONFIG_BFQ_GROUP_IOSCHED | |
| + blkcg_policy_unregister(&blkcg_policy_bfq); | |
| +#endif | |
| + bfq_slab_kill(); | |
| +} | |
| + | |
| +module_init(bfq_init); | |
| +module_exit(bfq_exit); | |
| + | |
| +MODULE_AUTHOR("Arianna Avanzini, Fabio Checconi, Paolo Valente"); | |
| +MODULE_LICENSE("GPL"); | |
| diff -x .git -Naur linux-4.4.111/block/bfq-sched.c linux-4.4.111-alpine/block/bfq-sched.c | |
| --- linux-4.4.111/block/bfq-sched.c 1969-12-31 19:00:00.000000000 -0500 | |
| +++ linux-4.4.111-alpine/block/bfq-sched.c 2018-02-14 21:04:16.000000000 -0500 | |
| @@ -0,0 +1,1200 @@ | |
| +/* | |
| + * BFQ: Hierarchical B-WF2Q+ scheduler. | |
| + * | |
| + * Based on ideas and code from CFQ: | |
| + * Copyright (C) 2003 Jens Axboe <axboe@kernel.dk> | |
| + * | |
| + * Copyright (C) 2008 Fabio Checconi <fabio@gandalf.sssup.it> | |
| + * Paolo Valente <paolo.valente@unimore.it> | |
| + * | |
| + * Copyright (C) 2010 Paolo Valente <paolo.valente@unimore.it> | |
| + */ | |
| + | |
| +#ifdef CONFIG_BFQ_GROUP_IOSCHED | |
| +#define for_each_entity(entity) \ | |
| + for (; entity ; entity = entity->parent) | |
| + | |
| +#define for_each_entity_safe(entity, parent) \ | |
| + for (; entity && ({ parent = entity->parent; 1; }); entity = parent) | |
| + | |
| + | |
| +static struct bfq_entity *bfq_lookup_next_entity(struct bfq_sched_data *sd, | |
| + int extract, | |
| + struct bfq_data *bfqd); | |
| + | |
| +static struct bfq_group *bfqq_group(struct bfq_queue *bfqq); | |
| + | |
| +static void bfq_update_budget(struct bfq_entity *next_in_service) | |
| +{ | |
| + struct bfq_entity *bfqg_entity; | |
| + struct bfq_group *bfqg; | |
| + struct bfq_sched_data *group_sd; | |
| + | |
| + BUG_ON(!next_in_service); | |
| + | |
| + group_sd = next_in_service->sched_data; | |
| + | |
| + bfqg = container_of(group_sd, struct bfq_group, sched_data); | |
| + /* | |
| + * bfq_group's my_entity field is not NULL only if the group | |
| + * is not the root group. We must not touch the root entity | |
| + * as it must never become an in-service entity. | |
| + */ | |
| + bfqg_entity = bfqg->my_entity; | |
| + if (bfqg_entity) | |
| + bfqg_entity->budget = next_in_service->budget; | |
| +} | |
| + | |
| +static int bfq_update_next_in_service(struct bfq_sched_data *sd) | |
| +{ | |
| + struct bfq_entity *next_in_service; | |
| + | |
| + if (sd->in_service_entity) | |
| + /* will update/requeue at the end of service */ | |
| + return 0; | |
| + | |
| + /* | |
| + * NOTE: this can be improved in many ways, such as returning | |
| + * 1 (and thus propagating upwards the update) only when the | |
| + * budget changes, or caching the bfqq that will be scheduled | |
| + * next from this subtree. By now we worry more about | |
| + * correctness than about performance... | |
| + */ | |
| + next_in_service = bfq_lookup_next_entity(sd, 0, NULL); | |
| + sd->next_in_service = next_in_service; | |
| + | |
| + if (next_in_service) | |
| + bfq_update_budget(next_in_service); | |
| + | |
| + return 1; | |
| +} | |
| + | |
| +static void bfq_check_next_in_service(struct bfq_sched_data *sd, | |
| + struct bfq_entity *entity) | |
| +{ | |
| + BUG_ON(sd->next_in_service != entity); | |
| +} | |
| +#else | |
| +#define for_each_entity(entity) \ | |
| + for (; entity ; entity = NULL) | |
| + | |
| +#define for_each_entity_safe(entity, parent) \ | |
| + for (parent = NULL; entity ; entity = parent) | |
| + | |
| +static int bfq_update_next_in_service(struct bfq_sched_data *sd) | |
| +{ | |
| + return 0; | |
| +} | |
| + | |
| +static void bfq_check_next_in_service(struct bfq_sched_data *sd, | |
| + struct bfq_entity *entity) | |
| +{ | |
| +} | |
| + | |
| +static void bfq_update_budget(struct bfq_entity *next_in_service) | |
| +{ | |
| +} | |
| +#endif | |
| + | |
| +/* | |
| + * Shift for timestamp calculations. This actually limits the maximum | |
| + * service allowed in one timestamp delta (small shift values increase it), | |
| + * the maximum total weight that can be used for the queues in the system | |
| + * (big shift values increase it), and the period of virtual time | |
| + * wraparounds. | |
| + */ | |
| +#define WFQ_SERVICE_SHIFT 22 | |
| + | |
| +/** | |
| + * bfq_gt - compare two timestamps. | |
| + * @a: first ts. | |
| + * @b: second ts. | |
| + * | |
| + * Return @a > @b, dealing with wrapping correctly. | |
| + */ | |
| +static int bfq_gt(u64 a, u64 b) | |
| +{ | |
| + return (s64)(a - b) > 0; | |
| +} | |
| + | |
| +static struct bfq_queue *bfq_entity_to_bfqq(struct bfq_entity *entity) | |
| +{ | |
| + struct bfq_queue *bfqq = NULL; | |
| + | |
| + BUG_ON(!entity); | |
| + | |
| + if (!entity->my_sched_data) | |
| + bfqq = container_of(entity, struct bfq_queue, entity); | |
| + | |
| + return bfqq; | |
| +} | |
| + | |
| + | |
| +/** | |
| + * bfq_delta - map service into the virtual time domain. | |
| + * @service: amount of service. | |
| + * @weight: scale factor (weight of an entity or weight sum). | |
| + */ | |
| +static u64 bfq_delta(unsigned long service, unsigned long weight) | |
| +{ | |
| + u64 d = (u64)service << WFQ_SERVICE_SHIFT; | |
| + | |
| + do_div(d, weight); | |
| + return d; | |
| +} | |
| + | |
| +/** | |
| + * bfq_calc_finish - assign the finish time to an entity. | |
| + * @entity: the entity to act upon. | |
| + * @service: the service to be charged to the entity. | |
| + */ | |
| +static void bfq_calc_finish(struct bfq_entity *entity, unsigned long service) | |
| +{ | |
| + struct bfq_queue *bfqq = bfq_entity_to_bfqq(entity); | |
| + | |
| + BUG_ON(entity->weight == 0); | |
| + | |
| + entity->finish = entity->start + | |
| + bfq_delta(service, entity->weight); | |
| + | |
| + if (bfqq) { | |
| + bfq_log_bfqq(bfqq->bfqd, bfqq, | |
| + "calc_finish: serv %lu, w %d", | |
| + service, entity->weight); | |
| + bfq_log_bfqq(bfqq->bfqd, bfqq, | |
| + "calc_finish: start %llu, finish %llu, delta %llu", | |
| + entity->start, entity->finish, | |
| + bfq_delta(service, entity->weight)); | |
| + } | |
| +} | |
| + | |
| +/** | |
| + * bfq_entity_of - get an entity from a node. | |
| + * @node: the node field of the entity. | |
| + * | |
| + * Convert a node pointer to the relative entity. This is used only | |
| + * to simplify the logic of some functions and not as the generic | |
| + * conversion mechanism because, e.g., in the tree walking functions, | |
| + * the check for a %NULL value would be redundant. | |
| + */ | |
| +static struct bfq_entity *bfq_entity_of(struct rb_node *node) | |
| +{ | |
| + struct bfq_entity *entity = NULL; | |
| + | |
| + if (node) | |
| + entity = rb_entry(node, struct bfq_entity, rb_node); | |
| + | |
| + return entity; | |
| +} | |
| + | |
| +/** | |
| + * bfq_extract - remove an entity from a tree. | |
| + * @root: the tree root. | |
| + * @entity: the entity to remove. | |
| + */ | |
| +static void bfq_extract(struct rb_root *root, struct bfq_entity *entity) | |
| +{ | |
| + BUG_ON(entity->tree != root); | |
| + | |
| + entity->tree = NULL; | |
| + rb_erase(&entity->rb_node, root); | |
| +} | |
| + | |
| +/** | |
| + * bfq_idle_extract - extract an entity from the idle tree. | |
| + * @st: the service tree of the owning @entity. | |
| + * @entity: the entity being removed. | |
| + */ | |
| +static void bfq_idle_extract(struct bfq_service_tree *st, | |
| + struct bfq_entity *entity) | |
| +{ | |
| + struct bfq_queue *bfqq = bfq_entity_to_bfqq(entity); | |
| + struct rb_node *next; | |
| + | |
| + BUG_ON(entity->tree != &st->idle); | |
| + | |
| + if (entity == st->first_idle) { | |
| + next = rb_next(&entity->rb_node); | |
| + st->first_idle = bfq_entity_of(next); | |
| + } | |
| + | |
| + if (entity == st->last_idle) { | |
| + next = rb_prev(&entity->rb_node); | |
| + st->last_idle = bfq_entity_of(next); | |
| + } | |
| + | |
| + bfq_extract(&st->idle, entity); | |
| + | |
| + if (bfqq) | |
| + list_del(&bfqq->bfqq_list); | |
| +} | |
| + | |
| +/** | |
| + * bfq_insert - generic tree insertion. | |
| + * @root: tree root. | |
| + * @entity: entity to insert. | |
| + * | |
| + * This is used for the idle and the active tree, since they are both | |
| + * ordered by finish time. | |
| + */ | |
| +static void bfq_insert(struct rb_root *root, struct bfq_entity *entity) | |
| +{ | |
| + struct bfq_entity *entry; | |
| + struct rb_node **node = &root->rb_node; | |
| + struct rb_node *parent = NULL; | |
| + | |
| + BUG_ON(entity->tree); | |
| + | |
| + while (*node) { | |
| + parent = *node; | |
| + entry = rb_entry(parent, struct bfq_entity, rb_node); | |
| + | |
| + if (bfq_gt(entry->finish, entity->finish)) | |
| + node = &parent->rb_left; | |
| + else | |
| + node = &parent->rb_right; | |
| + } | |
| + | |
| + rb_link_node(&entity->rb_node, parent, node); | |
| + rb_insert_color(&entity->rb_node, root); | |
| + | |
| + entity->tree = root; | |
| +} | |
| + | |
| +/** | |
| + * bfq_update_min - update the min_start field of a entity. | |
| + * @entity: the entity to update. | |
| + * @node: one of its children. | |
| + * | |
| + * This function is called when @entity may store an invalid value for | |
| + * min_start due to updates to the active tree. The function assumes | |
| + * that the subtree rooted at @node (which may be its left or its right | |
| + * child) has a valid min_start value. | |
| + */ | |
| +static void bfq_update_min(struct bfq_entity *entity, struct rb_node *node) | |
| +{ | |
| + struct bfq_entity *child; | |
| + | |
| + if (node) { | |
| + child = rb_entry(node, struct bfq_entity, rb_node); | |
| + if (bfq_gt(entity->min_start, child->min_start)) | |
| + entity->min_start = child->min_start; | |
| + } | |
| +} | |
| + | |
| +/** | |
| + * bfq_update_active_node - recalculate min_start. | |
| + * @node: the node to update. | |
| + * | |
| + * @node may have changed position or one of its children may have moved, | |
| + * this function updates its min_start value. The left and right subtrees | |
| + * are assumed to hold a correct min_start value. | |
| + */ | |
| +static void bfq_update_active_node(struct rb_node *node) | |
| +{ | |
| + struct bfq_entity *entity = rb_entry(node, struct bfq_entity, rb_node); | |
| + | |
| + entity->min_start = entity->start; | |
| + bfq_update_min(entity, node->rb_right); | |
| + bfq_update_min(entity, node->rb_left); | |
| +} | |
| + | |
| +/** | |
| + * bfq_update_active_tree - update min_start for the whole active tree. | |
| + * @node: the starting node. | |
| + * | |
| + * @node must be the deepest modified node after an update. This function | |
| + * updates its min_start using the values held by its children, assuming | |
| + * that they did not change, and then updates all the nodes that may have | |
| + * changed in the path to the root. The only nodes that may have changed | |
| + * are the ones in the path or their siblings. | |
| + */ | |
| +static void bfq_update_active_tree(struct rb_node *node) | |
| +{ | |
| + struct rb_node *parent; | |
| + | |
| +up: | |
| + bfq_update_active_node(node); | |
| + | |
| + parent = rb_parent(node); | |
| + if (!parent) | |
| + return; | |
| + | |
| + if (node == parent->rb_left && parent->rb_right) | |
| + bfq_update_active_node(parent->rb_right); | |
| + else if (parent->rb_left) | |
| + bfq_update_active_node(parent->rb_left); | |
| + | |
| + node = parent; | |
| + goto up; | |
| +} | |
| + | |
| +static void bfq_weights_tree_add(struct bfq_data *bfqd, | |
| + struct bfq_entity *entity, | |
| + struct rb_root *root); | |
| + | |
| +static void bfq_weights_tree_remove(struct bfq_data *bfqd, | |
| + struct bfq_entity *entity, | |
| + struct rb_root *root); | |
| + | |
| + | |
| +/** | |
| + * bfq_active_insert - insert an entity in the active tree of its | |
| + * group/device. | |
| + * @st: the service tree of the entity. | |
| + * @entity: the entity being inserted. | |
| + * | |
| + * The active tree is ordered by finish time, but an extra key is kept | |
| + * per each node, containing the minimum value for the start times of | |
| + * its children (and the node itself), so it's possible to search for | |
| + * the eligible node with the lowest finish time in logarithmic time. | |
| + */ | |
| +static void bfq_active_insert(struct bfq_service_tree *st, | |
| + struct bfq_entity *entity) | |
| +{ | |
| + struct bfq_queue *bfqq = bfq_entity_to_bfqq(entity); | |
| + struct rb_node *node = &entity->rb_node; | |
| +#ifdef CONFIG_BFQ_GROUP_IOSCHED | |
| + struct bfq_sched_data *sd = NULL; | |
| + struct bfq_group *bfqg = NULL; | |
| + struct bfq_data *bfqd = NULL; | |
| +#endif | |
| + | |
| + bfq_insert(&st->active, entity); | |
| + | |
| + if (node->rb_left) | |
| + node = node->rb_left; | |
| + else if (node->rb_right) | |
| + node = node->rb_right; | |
| + | |
| + bfq_update_active_tree(node); | |
| + | |
| +#ifdef CONFIG_BFQ_GROUP_IOSCHED | |
| + sd = entity->sched_data; | |
| + bfqg = container_of(sd, struct bfq_group, sched_data); | |
| + BUG_ON(!bfqg); | |
| + bfqd = (struct bfq_data *)bfqg->bfqd; | |
| +#endif | |
| + if (bfqq) | |
| + list_add(&bfqq->bfqq_list, &bfqq->bfqd->active_list); | |
| +#ifdef CONFIG_BFQ_GROUP_IOSCHED | |
| + else { /* bfq_group */ | |
| + BUG_ON(!bfqd); | |
| + bfq_weights_tree_add(bfqd, entity, &bfqd->group_weights_tree); | |
| + } | |
| + if (bfqg != bfqd->root_group) { | |
| + BUG_ON(!bfqg); | |
| + BUG_ON(!bfqd); | |
| + bfqg->active_entities++; | |
| + if (bfqg->active_entities == 2) | |
| + bfqd->active_numerous_groups++; | |
| + } | |
| +#endif | |
| +} | |
| + | |
| +/** | |
| + * bfq_ioprio_to_weight - calc a weight from an ioprio. | |
| + * @ioprio: the ioprio value to convert. | |
| + */ | |
| +static unsigned short bfq_ioprio_to_weight(int ioprio) | |
| +{ | |
| + BUG_ON(ioprio < 0 || ioprio >= IOPRIO_BE_NR); | |
| + return IOPRIO_BE_NR * BFQ_WEIGHT_CONVERSION_COEFF - ioprio; | |
| +} | |
| + | |
| +/** | |
| + * bfq_weight_to_ioprio - calc an ioprio from a weight. | |
| + * @weight: the weight value to convert. | |
| + * | |
| + * To preserve as much as possible the old only-ioprio user interface, | |
| + * 0 is used as an escape ioprio value for weights (numerically) equal or | |
| + * larger than IOPRIO_BE_NR * BFQ_WEIGHT_CONVERSION_COEFF. | |
| + */ | |
| +static unsigned short bfq_weight_to_ioprio(int weight) | |
| +{ | |
| + BUG_ON(weight < BFQ_MIN_WEIGHT || weight > BFQ_MAX_WEIGHT); | |
| + return IOPRIO_BE_NR * BFQ_WEIGHT_CONVERSION_COEFF - weight < 0 ? | |
| + 0 : IOPRIO_BE_NR * BFQ_WEIGHT_CONVERSION_COEFF - weight; | |
| +} | |
| + | |
| +static void bfq_get_entity(struct bfq_entity *entity) | |
| +{ | |
| + struct bfq_queue *bfqq = bfq_entity_to_bfqq(entity); | |
| + | |
| + if (bfqq) { | |
| + atomic_inc(&bfqq->ref); | |
| + bfq_log_bfqq(bfqq->bfqd, bfqq, "get_entity: %p %d", | |
| + bfqq, atomic_read(&bfqq->ref)); | |
| + } | |
| +} | |
| + | |
| +/** | |
| + * bfq_find_deepest - find the deepest node that an extraction can modify. | |
| + * @node: the node being removed. | |
| + * | |
| + * Do the first step of an extraction in an rb tree, looking for the | |
| + * node that will replace @node, and returning the deepest node that | |
| + * the following modifications to the tree can touch. If @node is the | |
| + * last node in the tree return %NULL. | |
| + */ | |
| +static struct rb_node *bfq_find_deepest(struct rb_node *node) | |
| +{ | |
| + struct rb_node *deepest; | |
| + | |
| + if (!node->rb_right && !node->rb_left) | |
| + deepest = rb_parent(node); | |
| + else if (!node->rb_right) | |
| + deepest = node->rb_left; | |
| + else if (!node->rb_left) | |
| + deepest = node->rb_right; | |
| + else { | |
| + deepest = rb_next(node); | |
| + if (deepest->rb_right) | |
| + deepest = deepest->rb_right; | |
| + else if (rb_parent(deepest) != node) | |
| + deepest = rb_parent(deepest); | |
| + } | |
| + | |
| + return deepest; | |
| +} | |
| + | |
| +/** | |
| + * bfq_active_extract - remove an entity from the active tree. | |
| + * @st: the service_tree containing the tree. | |
| + * @entity: the entity being removed. | |
| + */ | |
| +static void bfq_active_extract(struct bfq_service_tree *st, | |
| + struct bfq_entity *entity) | |
| +{ | |
| + struct bfq_queue *bfqq = bfq_entity_to_bfqq(entity); | |
| + struct rb_node *node; | |
| +#ifdef CONFIG_BFQ_GROUP_IOSCHED | |
| + struct bfq_sched_data *sd = NULL; | |
| + struct bfq_group *bfqg = NULL; | |
| + struct bfq_data *bfqd = NULL; | |
| +#endif | |
| + | |
| + node = bfq_find_deepest(&entity->rb_node); | |
| + bfq_extract(&st->active, entity); | |
| + | |
| + if (node) | |
| + bfq_update_active_tree(node); | |
| + | |
| +#ifdef CONFIG_BFQ_GROUP_IOSCHED | |
| + sd = entity->sched_data; | |
| + bfqg = container_of(sd, struct bfq_group, sched_data); | |
| + BUG_ON(!bfqg); | |
| + bfqd = (struct bfq_data *)bfqg->bfqd; | |
| +#endif | |
| + if (bfqq) | |
| + list_del(&bfqq->bfqq_list); | |
| +#ifdef CONFIG_BFQ_GROUP_IOSCHED | |
| + else { /* bfq_group */ | |
| + BUG_ON(!bfqd); | |
| + bfq_weights_tree_remove(bfqd, entity, | |
| + &bfqd->group_weights_tree); | |
| + } | |
| + if (bfqg != bfqd->root_group) { | |
| + BUG_ON(!bfqg); | |
| + BUG_ON(!bfqd); | |
| + BUG_ON(!bfqg->active_entities); | |
| + bfqg->active_entities--; | |
| + if (bfqg->active_entities == 1) { | |
| + BUG_ON(!bfqd->active_numerous_groups); | |
| + bfqd->active_numerous_groups--; | |
| + } | |
| + } | |
| +#endif | |
| +} | |
| + | |
| +/** | |
| + * bfq_idle_insert - insert an entity into the idle tree. | |
| + * @st: the service tree containing the tree. | |
| + * @entity: the entity to insert. | |
| + */ | |
| +static void bfq_idle_insert(struct bfq_service_tree *st, | |
| + struct bfq_entity *entity) | |
| +{ | |
| + struct bfq_queue *bfqq = bfq_entity_to_bfqq(entity); | |
| + struct bfq_entity *first_idle = st->first_idle; | |
| + struct bfq_entity *last_idle = st->last_idle; | |
| + | |
| + if (!first_idle || bfq_gt(first_idle->finish, entity->finish)) | |
| + st->first_idle = entity; | |
| + if (!last_idle || bfq_gt(entity->finish, last_idle->finish)) | |
| + st->last_idle = entity; | |
| + | |
| + bfq_insert(&st->idle, entity); | |
| + | |
| + if (bfqq) | |
| + list_add(&bfqq->bfqq_list, &bfqq->bfqd->idle_list); | |
| +} | |
| + | |
| +/** | |
| + * bfq_forget_entity - remove an entity from the wfq trees. | |
| + * @st: the service tree. | |
| + * @entity: the entity being removed. | |
| + * | |
| + * Update the device status and forget everything about @entity, putting | |
| + * the device reference to it, if it is a queue. Entities belonging to | |
| + * groups are not refcounted. | |
| + */ | |
| +static void bfq_forget_entity(struct bfq_service_tree *st, | |
| + struct bfq_entity *entity) | |
| +{ | |
| + struct bfq_queue *bfqq = bfq_entity_to_bfqq(entity); | |
| + struct bfq_sched_data *sd; | |
| + | |
| + BUG_ON(!entity->on_st); | |
| + | |
| + entity->on_st = 0; | |
| + st->wsum -= entity->weight; | |
| + if (bfqq) { | |
| + sd = entity->sched_data; | |
| + bfq_log_bfqq(bfqq->bfqd, bfqq, "forget_entity: %p %d", | |
| + bfqq, atomic_read(&bfqq->ref)); | |
| + bfq_put_queue(bfqq); | |
| + } | |
| +} | |
| + | |
| +/** | |
| + * bfq_put_idle_entity - release the idle tree ref of an entity. | |
| + * @st: service tree for the entity. | |
| + * @entity: the entity being released. | |
| + */ | |
| +static void bfq_put_idle_entity(struct bfq_service_tree *st, | |
| + struct bfq_entity *entity) | |
| +{ | |
| + bfq_idle_extract(st, entity); | |
| + bfq_forget_entity(st, entity); | |
| +} | |
| + | |
| +/** | |
| + * bfq_forget_idle - update the idle tree if necessary. | |
| + * @st: the service tree to act upon. | |
| + * | |
| + * To preserve the global O(log N) complexity we only remove one entry here; | |
| + * as the idle tree will not grow indefinitely this can be done safely. | |
| + */ | |
| +static void bfq_forget_idle(struct bfq_service_tree *st) | |
| +{ | |
| + struct bfq_entity *first_idle = st->first_idle; | |
| + struct bfq_entity *last_idle = st->last_idle; | |
| + | |
| + if (RB_EMPTY_ROOT(&st->active) && last_idle && | |
| + !bfq_gt(last_idle->finish, st->vtime)) { | |
| + /* | |
| + * Forget the whole idle tree, increasing the vtime past | |
| + * the last finish time of idle entities. | |
| + */ | |
| + st->vtime = last_idle->finish; | |
| + } | |
| + | |
| + if (first_idle && !bfq_gt(first_idle->finish, st->vtime)) | |
| + bfq_put_idle_entity(st, first_idle); | |
| +} | |
| + | |
| +static struct bfq_service_tree * | |
| +__bfq_entity_update_weight_prio(struct bfq_service_tree *old_st, | |
| + struct bfq_entity *entity) | |
| +{ | |
| + struct bfq_service_tree *new_st = old_st; | |
| + | |
| + if (entity->prio_changed) { | |
| + struct bfq_queue *bfqq = bfq_entity_to_bfqq(entity); | |
| + unsigned short prev_weight, new_weight; | |
| + struct bfq_data *bfqd = NULL; | |
| + struct rb_root *root; | |
| +#ifdef CONFIG_BFQ_GROUP_IOSCHED | |
| + struct bfq_sched_data *sd; | |
| + struct bfq_group *bfqg; | |
| +#endif | |
| + | |
| + if (bfqq) | |
| + bfqd = bfqq->bfqd; | |
| +#ifdef CONFIG_BFQ_GROUP_IOSCHED | |
| + else { | |
| + sd = entity->my_sched_data; | |
| + bfqg = container_of(sd, struct bfq_group, sched_data); | |
| + BUG_ON(!bfqg); | |
| + bfqd = (struct bfq_data *)bfqg->bfqd; | |
| + BUG_ON(!bfqd); | |
| + } | |
| +#endif | |
| + | |
| + BUG_ON(old_st->wsum < entity->weight); | |
| + old_st->wsum -= entity->weight; | |
| + | |
| + if (entity->new_weight != entity->orig_weight) { | |
| + if (entity->new_weight < BFQ_MIN_WEIGHT || | |
| + entity->new_weight > BFQ_MAX_WEIGHT) { | |
| + printk(KERN_CRIT "update_weight_prio: " | |
| + "new_weight %d\n", | |
| + entity->new_weight); | |
| + BUG(); | |
| + } | |
| + entity->orig_weight = entity->new_weight; | |
| + if (bfqq) | |
| + bfqq->ioprio = | |
| + bfq_weight_to_ioprio(entity->orig_weight); | |
| + } | |
| + | |
| + if (bfqq) | |
| + bfqq->ioprio_class = bfqq->new_ioprio_class; | |
| + entity->prio_changed = 0; | |
| + | |
| + /* | |
| + * NOTE: here we may be changing the weight too early, | |
| + * this will cause unfairness. The correct approach | |
| + * would have required additional complexity to defer | |
| + * weight changes to the proper time instants (i.e., | |
| + * when entity->finish <= old_st->vtime). | |
| + */ | |
| + new_st = bfq_entity_service_tree(entity); | |
| + | |
| + prev_weight = entity->weight; | |
| + new_weight = entity->orig_weight * | |
| + (bfqq ? bfqq->wr_coeff : 1); | |
| + /* | |
| + * If the weight of the entity changes, remove the entity | |
| + * from its old weight counter (if there is a counter | |
| + * associated with the entity), and add it to the counter | |
| + * associated with its new weight. | |
| + */ | |
| + if (prev_weight != new_weight) { | |
| + root = bfqq ? &bfqd->queue_weights_tree : | |
| + &bfqd->group_weights_tree; | |
| + bfq_weights_tree_remove(bfqd, entity, root); | |
| + } | |
| + entity->weight = new_weight; | |
| + /* | |
| + * Add the entity to its weights tree only if it is | |
| + * not associated with a weight-raised queue. | |
| + */ | |
| + if (prev_weight != new_weight && | |
| + (bfqq ? bfqq->wr_coeff == 1 : 1)) | |
| + /* If we get here, root has been initialized. */ | |
| + bfq_weights_tree_add(bfqd, entity, root); | |
| + | |
| + new_st->wsum += entity->weight; | |
| + | |
| + if (new_st != old_st) | |
| + entity->start = new_st->vtime; | |
| + } | |
| + | |
| + return new_st; | |
| +} | |
| + | |
| +#ifdef CONFIG_BFQ_GROUP_IOSCHED | |
| +static void bfqg_stats_set_start_empty_time(struct bfq_group *bfqg); | |
| +#endif | |
| + | |
| +/** | |
| + * bfq_bfqq_served - update the scheduler status after selection for | |
| + * service. | |
| + * @bfqq: the queue being served. | |
| + * @served: bytes to transfer. | |
| + * | |
| + * NOTE: this can be optimized, as the timestamps of upper level entities | |
| + * are synchronized every time a new bfqq is selected for service. By now, | |
| + * we keep it to better check consistency. | |
| + */ | |
| +static void bfq_bfqq_served(struct bfq_queue *bfqq, int served) | |
| +{ | |
| + struct bfq_entity *entity = &bfqq->entity; | |
| + struct bfq_service_tree *st; | |
| + | |
| + for_each_entity(entity) { | |
| + st = bfq_entity_service_tree(entity); | |
| + | |
| + entity->service += served; | |
| + BUG_ON(entity->service > entity->budget); | |
| + BUG_ON(st->wsum == 0); | |
| + | |
| + st->vtime += bfq_delta(served, st->wsum); | |
| + bfq_forget_idle(st); | |
| + } | |
| +#ifdef CONFIG_BFQ_GROUP_IOSCHED | |
| + bfqg_stats_set_start_empty_time(bfqq_group(bfqq)); | |
| +#endif | |
| + bfq_log_bfqq(bfqq->bfqd, bfqq, "bfqq_served %d secs", served); | |
| +} | |
| + | |
| +/** | |
| + * bfq_bfqq_charge_full_budget - set the service to the entity budget. | |
| + * @bfqq: the queue that needs a service update. | |
| + * | |
| + * When it's not possible to be fair in the service domain, because | |
| + * a queue is not consuming its budget fast enough (the meaning of | |
| + * fast depends on the timeout parameter), we charge it a full | |
| + * budget. In this way we should obtain a sort of time-domain | |
| + * fairness among all the seeky/slow queues. | |
| + */ | |
| +static void bfq_bfqq_charge_full_budget(struct bfq_queue *bfqq) | |
| +{ | |
| + struct bfq_entity *entity = &bfqq->entity; | |
| + | |
| + bfq_log_bfqq(bfqq->bfqd, bfqq, "charge_full_budget"); | |
| + | |
| + bfq_bfqq_served(bfqq, entity->budget - entity->service); | |
| +} | |
| + | |
| +/** | |
| + * __bfq_activate_entity - activate an entity. | |
| + * @entity: the entity being activated. | |
| + * | |
| + * Called whenever an entity is activated, i.e., it is not active and one | |
| + * of its children receives a new request, or has to be reactivated due to | |
| + * budget exhaustion. It uses the current budget of the entity (and the | |
| + * service received if @entity is active) of the queue to calculate its | |
| + * timestamps. | |
| + */ | |
| +static void __bfq_activate_entity(struct bfq_entity *entity) | |
| +{ | |
| + struct bfq_sched_data *sd = entity->sched_data; | |
| + struct bfq_service_tree *st = bfq_entity_service_tree(entity); | |
| + | |
| + if (entity == sd->in_service_entity) { | |
| + BUG_ON(entity->tree); | |
| + /* | |
| + * If we are requeueing the current entity we have | |
| + * to take care of not charging to it service it has | |
| + * not received. | |
| + */ | |
| + bfq_calc_finish(entity, entity->service); | |
| + entity->start = entity->finish; | |
| + sd->in_service_entity = NULL; | |
| + } else if (entity->tree == &st->active) { | |
| + /* | |
| + * Requeueing an entity due to a change of some | |
| + * next_in_service entity below it. We reuse the | |
| + * old start time. | |
| + */ | |
| + bfq_active_extract(st, entity); | |
| + } else if (entity->tree == &st->idle) { | |
| + /* | |
| + * Must be on the idle tree, bfq_idle_extract() will | |
| + * check for that. | |
| + */ | |
| + bfq_idle_extract(st, entity); | |
| + entity->start = bfq_gt(st->vtime, entity->finish) ? | |
| + st->vtime : entity->finish; | |
| + } else { | |
| + /* | |
| + * The finish time of the entity may be invalid, and | |
| + * it is in the past for sure, otherwise the queue | |
| + * would have been on the idle tree. | |
| + */ | |
| + entity->start = st->vtime; | |
| + st->wsum += entity->weight; | |
| + bfq_get_entity(entity); | |
| + | |
| + BUG_ON(entity->on_st); | |
| + entity->on_st = 1; | |
| + } | |
| + | |
| + st = __bfq_entity_update_weight_prio(st, entity); | |
| + bfq_calc_finish(entity, entity->budget); | |
| + bfq_active_insert(st, entity); | |
| +} | |
| + | |
| +/** | |
| + * bfq_activate_entity - activate an entity and its ancestors if necessary. | |
| + * @entity: the entity to activate. | |
| + * | |
| + * Activate @entity and all the entities on the path from it to the root. | |
| + */ | |
| +static void bfq_activate_entity(struct bfq_entity *entity) | |
| +{ | |
| + struct bfq_sched_data *sd; | |
| + | |
| + for_each_entity(entity) { | |
| + __bfq_activate_entity(entity); | |
| + | |
| + sd = entity->sched_data; | |
| + if (!bfq_update_next_in_service(sd)) | |
| + /* | |
| + * No need to propagate the activation to the | |
| + * upper entities, as they will be updated when | |
| + * the in-service entity is rescheduled. | |
| + */ | |
| + break; | |
| + } | |
| +} | |
| + | |
| +/** | |
| + * __bfq_deactivate_entity - deactivate an entity from its service tree. | |
| + * @entity: the entity to deactivate. | |
| + * @requeue: if false, the entity will not be put into the idle tree. | |
| + * | |
| + * Deactivate an entity, independently from its previous state. If the | |
| + * entity was not on a service tree just return, otherwise if it is on | |
| + * any scheduler tree, extract it from that tree, and if necessary | |
| + * and if the caller did not specify @requeue, put it on the idle tree. | |
| + * | |
| + * Return %1 if the caller should update the entity hierarchy, i.e., | |
| + * if the entity was in service or if it was the next_in_service for | |
| + * its sched_data; return %0 otherwise. | |
| + */ | |
| +static int __bfq_deactivate_entity(struct bfq_entity *entity, int requeue) | |
| +{ | |
| + struct bfq_sched_data *sd = entity->sched_data; | |
| + struct bfq_service_tree *st; | |
| + int was_in_service; | |
| + int ret = 0; | |
| + | |
| + if (sd == NULL || !entity->on_st) /* never activated, or inactive */ | |
| + return 0; | |
| + | |
| + st = bfq_entity_service_tree(entity); | |
| + was_in_service = entity == sd->in_service_entity; | |
| + | |
| + BUG_ON(was_in_service && entity->tree); | |
| + | |
| + if (was_in_service) { | |
| + bfq_calc_finish(entity, entity->service); | |
| + sd->in_service_entity = NULL; | |
| + } else if (entity->tree == &st->active) | |
| + bfq_active_extract(st, entity); | |
| + else if (entity->tree == &st->idle) | |
| + bfq_idle_extract(st, entity); | |
| + else if (entity->tree) | |
| + BUG(); | |
| + | |
| + if (was_in_service || sd->next_in_service == entity) | |
| + ret = bfq_update_next_in_service(sd); | |
| + | |
| + if (!requeue || !bfq_gt(entity->finish, st->vtime)) | |
| + bfq_forget_entity(st, entity); | |
| + else | |
| + bfq_idle_insert(st, entity); | |
| + | |
| + BUG_ON(sd->in_service_entity == entity); | |
| + BUG_ON(sd->next_in_service == entity); | |
| + | |
| + return ret; | |
| +} | |
| + | |
| +/** | |
| + * bfq_deactivate_entity - deactivate an entity. | |
| + * @entity: the entity to deactivate. | |
| + * @requeue: true if the entity can be put on the idle tree | |
| + */ | |
| +static void bfq_deactivate_entity(struct bfq_entity *entity, int requeue) | |
| +{ | |
| + struct bfq_sched_data *sd; | |
| + struct bfq_entity *parent; | |
| + | |
| + for_each_entity_safe(entity, parent) { | |
| + sd = entity->sched_data; | |
| + | |
| + if (!__bfq_deactivate_entity(entity, requeue)) | |
| + /* | |
| + * The parent entity is still backlogged, and | |
| + * we don't need to update it as it is still | |
| + * in service. | |
| + */ | |
| + break; | |
| + | |
| + if (sd->next_in_service) | |
| + /* | |
| + * The parent entity is still backlogged and | |
| + * the budgets on the path towards the root | |
| + * need to be updated. | |
| + */ | |
| + goto update; | |
| + | |
| + /* | |
| + * If we reach there the parent is no more backlogged and | |
| + * we want to propagate the dequeue upwards. | |
| + */ | |
| + requeue = 1; | |
| + } | |
| + | |
| + return; | |
| + | |
| +update: | |
| + entity = parent; | |
| + for_each_entity(entity) { | |
| + __bfq_activate_entity(entity); | |
| + | |
| + sd = entity->sched_data; | |
| + if (!bfq_update_next_in_service(sd)) | |
| + break; | |
| + } | |
| +} | |
| + | |
| +/** | |
| + * bfq_update_vtime - update vtime if necessary. | |
| + * @st: the service tree to act upon. | |
| + * | |
| + * If necessary update the service tree vtime to have at least one | |
| + * eligible entity, skipping to its start time. Assumes that the | |
| + * active tree of the device is not empty. | |
| + * | |
| + * NOTE: this hierarchical implementation updates vtimes quite often, | |
| + * we may end up with reactivated processes getting timestamps after a | |
| + * vtime skip done because we needed a ->first_active entity on some | |
| + * intermediate node. | |
| + */ | |
| +static void bfq_update_vtime(struct bfq_service_tree *st) | |
| +{ | |
| + struct bfq_entity *entry; | |
| + struct rb_node *node = st->active.rb_node; | |
| + | |
| + entry = rb_entry(node, struct bfq_entity, rb_node); | |
| + if (bfq_gt(entry->min_start, st->vtime)) { | |
| + st->vtime = entry->min_start; | |
| + bfq_forget_idle(st); | |
| + } | |
| +} | |
| + | |
| +/** | |
| + * bfq_first_active_entity - find the eligible entity with | |
| + * the smallest finish time | |
| + * @st: the service tree to select from. | |
| + * | |
| + * This function searches the first schedulable entity, starting from the | |
| + * root of the tree and going on the left every time on this side there is | |
| + * a subtree with at least one eligible (start >= vtime) entity. The path on | |
| + * the right is followed only if a) the left subtree contains no eligible | |
| + * entities and b) no eligible entity has been found yet. | |
| + */ | |
| +static struct bfq_entity *bfq_first_active_entity(struct bfq_service_tree *st) | |
| +{ | |
| + struct bfq_entity *entry, *first = NULL; | |
| + struct rb_node *node = st->active.rb_node; | |
| + | |
| + while (node) { | |
| + entry = rb_entry(node, struct bfq_entity, rb_node); | |
| +left: | |
| + if (!bfq_gt(entry->start, st->vtime)) | |
| + first = entry; | |
| + | |
| + BUG_ON(bfq_gt(entry->min_start, st->vtime)); | |
| + | |
| + if (node->rb_left) { | |
| + entry = rb_entry(node->rb_left, | |
| + struct bfq_entity, rb_node); | |
| + if (!bfq_gt(entry->min_start, st->vtime)) { | |
| + node = node->rb_left; | |
| + goto left; | |
| + } | |
| + } | |
| + if (first) | |
| + break; | |
| + node = node->rb_right; | |
| + } | |
| + | |
| + BUG_ON(!first && !RB_EMPTY_ROOT(&st->active)); | |
| + return first; | |
| +} | |
| + | |
| +/** | |
| + * __bfq_lookup_next_entity - return the first eligible entity in @st. | |
| + * @st: the service tree. | |
| + * | |
| + * Update the virtual time in @st and return the first eligible entity | |
| + * it contains. | |
| + */ | |
| +static struct bfq_entity *__bfq_lookup_next_entity(struct bfq_service_tree *st, | |
| + bool force) | |
| +{ | |
| + struct bfq_entity *entity, *new_next_in_service = NULL; | |
| + | |
| + if (RB_EMPTY_ROOT(&st->active)) | |
| + return NULL; | |
| + | |
| + bfq_update_vtime(st); | |
| + entity = bfq_first_active_entity(st); | |
| + BUG_ON(bfq_gt(entity->start, st->vtime)); | |
| + | |
| + /* | |
| + * If the chosen entity does not match with the sched_data's | |
| + * next_in_service and we are forcedly serving the IDLE priority | |
| + * class tree, bubble up budget update. | |
| + */ | |
| + if (unlikely(force && entity != entity->sched_data->next_in_service)) { | |
| + new_next_in_service = entity; | |
| + for_each_entity(new_next_in_service) | |
| + bfq_update_budget(new_next_in_service); | |
| + } | |
| + | |
| + return entity; | |
| +} | |
| + | |
| +/** | |
| + * bfq_lookup_next_entity - return the first eligible entity in @sd. | |
| + * @sd: the sched_data. | |
| + * @extract: if true the returned entity will be also extracted from @sd. | |
| + * | |
| + * NOTE: since we cache the next_in_service entity at each level of the | |
| + * hierarchy, the complexity of the lookup can be decreased with | |
| + * absolutely no effort just returning the cached next_in_service value; | |
| + * we prefer to do full lookups to test the consistency of * the data | |
| + * structures. | |
| + */ | |
| +static struct bfq_entity *bfq_lookup_next_entity(struct bfq_sched_data *sd, | |
| + int extract, | |
| + struct bfq_data *bfqd) | |
| +{ | |
| + struct bfq_service_tree *st = sd->service_tree; | |
| + struct bfq_entity *entity; | |
| + int i = 0; | |
| + | |
| + BUG_ON(sd->in_service_entity); | |
| + | |
| + if (bfqd && | |
| + jiffies - bfqd->bfq_class_idle_last_service > BFQ_CL_IDLE_TIMEOUT) { | |
| + entity = __bfq_lookup_next_entity(st + BFQ_IOPRIO_CLASSES - 1, | |
| + true); | |
| + if (entity) { | |
| + i = BFQ_IOPRIO_CLASSES - 1; | |
| + bfqd->bfq_class_idle_last_service = jiffies; | |
| + sd->next_in_service = entity; | |
| + } | |
| + } | |
| + for (; i < BFQ_IOPRIO_CLASSES; i++) { | |
| + entity = __bfq_lookup_next_entity(st + i, false); | |
| + if (entity) { | |
| + if (extract) { | |
| + bfq_check_next_in_service(sd, entity); | |
| + bfq_active_extract(st + i, entity); | |
| + sd->in_service_entity = entity; | |
| + sd->next_in_service = NULL; | |
| + } | |
| + break; | |
| + } | |
| + } | |
| + | |
| + return entity; | |
| +} | |
| + | |
| +/* | |
| + * Get next queue for service. | |
| + */ | |
| +static struct bfq_queue *bfq_get_next_queue(struct bfq_data *bfqd) | |
| +{ | |
| + struct bfq_entity *entity = NULL; | |
| + struct bfq_sched_data *sd; | |
| + struct bfq_queue *bfqq; | |
| + | |
| + BUG_ON(bfqd->in_service_queue); | |
| + | |
| + if (bfqd->busy_queues == 0) | |
| + return NULL; | |
| + | |
| + sd = &bfqd->root_group->sched_data; | |
| + for (; sd ; sd = entity->my_sched_data) { | |
| + entity = bfq_lookup_next_entity(sd, 1, bfqd); | |
| + BUG_ON(!entity); | |
| + entity->service = 0; | |
| + } | |
| + | |
| + bfqq = bfq_entity_to_bfqq(entity); | |
| + BUG_ON(!bfqq); | |
| + | |
| + return bfqq; | |
| +} | |
| + | |
| +static void __bfq_bfqd_reset_in_service(struct bfq_data *bfqd) | |
| +{ | |
| + if (bfqd->in_service_bic) { | |
| + put_io_context(bfqd->in_service_bic->icq.ioc); | |
| + bfqd->in_service_bic = NULL; | |
| + } | |
| + | |
| + bfqd->in_service_queue = NULL; | |
| + del_timer(&bfqd->idle_slice_timer); | |
| +} | |
| + | |
| +static void bfq_deactivate_bfqq(struct bfq_data *bfqd, struct bfq_queue *bfqq, | |
| + int requeue) | |
| +{ | |
| + struct bfq_entity *entity = &bfqq->entity; | |
| + | |
| + if (bfqq == bfqd->in_service_queue) | |
| + __bfq_bfqd_reset_in_service(bfqd); | |
| + | |
| + bfq_deactivate_entity(entity, requeue); | |
| +} | |
| + | |
| +static void bfq_activate_bfqq(struct bfq_data *bfqd, struct bfq_queue *bfqq) | |
| +{ | |
| + struct bfq_entity *entity = &bfqq->entity; | |
| + | |
| + bfq_activate_entity(entity); | |
| +} | |
| + | |
| +#ifdef CONFIG_BFQ_GROUP_IOSCHED | |
| +static void bfqg_stats_update_dequeue(struct bfq_group *bfqg); | |
| +#endif | |
| + | |
| +/* | |
| + * Called when the bfqq no longer has requests pending, remove it from | |
| + * the service tree. | |
| + */ | |
| +static void bfq_del_bfqq_busy(struct bfq_data *bfqd, struct bfq_queue *bfqq, | |
| + int requeue) | |
| +{ | |
| + BUG_ON(!bfq_bfqq_busy(bfqq)); | |
| + BUG_ON(!RB_EMPTY_ROOT(&bfqq->sort_list)); | |
| + | |
| + bfq_log_bfqq(bfqd, bfqq, "del from busy"); | |
| + | |
| + bfq_clear_bfqq_busy(bfqq); | |
| + | |
| + BUG_ON(bfqd->busy_queues == 0); | |
| + bfqd->busy_queues--; | |
| + | |
| + if (!bfqq->dispatched) { | |
| + bfq_weights_tree_remove(bfqd, &bfqq->entity, | |
| + &bfqd->queue_weights_tree); | |
| + if (!blk_queue_nonrot(bfqd->queue)) { | |
| + BUG_ON(!bfqd->busy_in_flight_queues); | |
| + bfqd->busy_in_flight_queues--; | |
| + if (bfq_bfqq_constantly_seeky(bfqq)) { | |
| + BUG_ON(!bfqd-> | |
| + const_seeky_busy_in_flight_queues); | |
| + bfqd->const_seeky_busy_in_flight_queues--; | |
| + } | |
| + } | |
| + } | |
| + if (bfqq->wr_coeff > 1) | |
| + bfqd->wr_busy_queues--; | |
| + | |
| +#ifdef CONFIG_BFQ_GROUP_IOSCHED | |
| + bfqg_stats_update_dequeue(bfqq_group(bfqq)); | |
| +#endif | |
| + | |
| + bfq_deactivate_bfqq(bfqd, bfqq, requeue); | |
| +} | |
| + | |
| +/* | |
| + * Called when an inactive queue receives a new request. | |
| + */ | |
| +static void bfq_add_bfqq_busy(struct bfq_data *bfqd, struct bfq_queue *bfqq) | |
| +{ | |
| + BUG_ON(bfq_bfqq_busy(bfqq)); | |
| + BUG_ON(bfqq == bfqd->in_service_queue); | |
| + | |
| + bfq_log_bfqq(bfqd, bfqq, "add to busy"); | |
| + | |
| + bfq_activate_bfqq(bfqd, bfqq); | |
| + | |
| + bfq_mark_bfqq_busy(bfqq); | |
| + bfqd->busy_queues++; | |
| + | |
| + if (!bfqq->dispatched) { | |
| + if (bfqq->wr_coeff == 1) | |
| + bfq_weights_tree_add(bfqd, &bfqq->entity, | |
| + &bfqd->queue_weights_tree); | |
| + if (!blk_queue_nonrot(bfqd->queue)) { | |
| + bfqd->busy_in_flight_queues++; | |
| + if (bfq_bfqq_constantly_seeky(bfqq)) | |
| + bfqd->const_seeky_busy_in_flight_queues++; | |
| + } | |
| + } | |
| + if (bfqq->wr_coeff > 1) | |
| + bfqd->wr_busy_queues++; | |
| +} | |
| diff -x .git -Naur linux-4.4.111/block/blk-timeout.c linux-4.4.111-alpine/block/blk-timeout.c | |
| --- linux-4.4.111/block/blk-timeout.c 2018-02-20 12:32:40.378080254 -0500 | |
| +++ linux-4.4.111-alpine/block/blk-timeout.c 2018-02-14 21:04:16.000000000 -0500 | |
| @@ -139,8 +139,10 @@ | |
| list_for_each_entry_safe(rq, tmp, &q->timeout_list, timeout_list) | |
| blk_rq_check_expired(rq, &next, &next_set); | |
| + if (!test_bit(QUEUE_FLAG_NO_ROUND, &q->queue_flags)) | |
| + next = round_jiffies_up(next); | |
| if (next_set) | |
| - mod_timer(&q->timeout, round_jiffies_up(next)); | |
| + mod_timer(&q->timeout, next); | |
| spin_unlock_irqrestore(q->queue_lock, flags); | |
| } | |
| @@ -217,7 +219,10 @@ | |
| * than an existing one, modify the timer. Round up to next nearest | |
| * second. | |
| */ | |
| - expiry = blk_rq_timeout(round_jiffies_up(req->deadline)); | |
| + if (test_bit(QUEUE_FLAG_NO_ROUND, &q->queue_flags)) | |
| + expiry = req->deadline; | |
| + else | |
| + expiry = blk_rq_timeout(round_jiffies_up(req->deadline)); | |
| if (!timer_pending(&q->timeout) || | |
| time_before(expiry, q->timeout.expires)) { | |
| diff -x .git -Naur linux-4.4.111/block/genhd.c linux-4.4.111-alpine/block/genhd.c | |
| --- linux-4.4.111/block/genhd.c 2018-02-20 12:32:40.388080293 -0500 | |
| +++ linux-4.4.111-alpine/block/genhd.c 2018-02-14 21:04:16.000000000 -0500 | |
| @@ -20,6 +20,7 @@ | |
| #include <linux/idr.h> | |
| #include <linux/log2.h> | |
| #include <linux/pm_runtime.h> | |
| +#include <linux/badblocks.h> | |
| #include "blk.h" | |
| @@ -505,6 +506,16 @@ | |
| return 0; | |
| } | |
| +int disk_alloc_badblocks(struct gendisk *disk) | |
| +{ | |
| + disk->bb = kzalloc(sizeof(*(disk->bb)), GFP_KERNEL); | |
| + if (!disk->bb) | |
| + return -ENOMEM; | |
| + | |
| + return badblocks_init(disk->bb, 1); | |
| +} | |
| +EXPORT_SYMBOL(disk_alloc_badblocks); | |
| + | |
| static void register_disk(struct gendisk *disk) | |
| { | |
| struct device *ddev = disk_to_dev(disk); | |
| @@ -671,6 +682,63 @@ | |
| } | |
| EXPORT_SYMBOL(del_gendisk); | |
| +/* | |
| + * The gendisk usage of badblocks does not track acknowledgements for | |
| + * badblocks. We always assume they are acknowledged. | |
| + */ | |
| +int disk_check_badblocks(struct gendisk *disk, sector_t s, int sectors, | |
| + sector_t *first_bad, int *bad_sectors) | |
| +{ | |
| + if (!disk->bb) | |
| + return 0; | |
| + | |
| + return badblocks_check(disk->bb, s, sectors, first_bad, bad_sectors); | |
| +} | |
| +EXPORT_SYMBOL(disk_check_badblocks); | |
| + | |
| +int disk_set_badblocks(struct gendisk *disk, sector_t s, int sectors) | |
| +{ | |
| + if (!disk->bb) | |
| + return 0; | |
| + | |
| + return badblocks_set(disk->bb, s, sectors, 1); | |
| +} | |
| +EXPORT_SYMBOL(disk_set_badblocks); | |
| + | |
| +int disk_clear_badblocks(struct gendisk *disk, sector_t s, int sectors) | |
| +{ | |
| + if (!disk->bb) | |
| + return 0; | |
| + | |
| + return badblocks_clear(disk->bb, s, sectors); | |
| +} | |
| +EXPORT_SYMBOL(disk_clear_badblocks); | |
| + | |
| +/* sysfs access to bad-blocks list. */ | |
| +static ssize_t disk_badblocks_show(struct device *dev, | |
| + struct device_attribute *attr, | |
| + char *page) | |
| +{ | |
| + struct gendisk *disk = dev_to_disk(dev); | |
| + | |
| + if (!disk->bb) | |
| + return sprintf(page, "\n"); | |
| + | |
| + return badblocks_show(disk->bb, page, 0); | |
| +} | |
| + | |
| +static ssize_t disk_badblocks_store(struct device *dev, | |
| + struct device_attribute *attr, | |
| + const char *page, size_t len) | |
| +{ | |
| + struct gendisk *disk = dev_to_disk(dev); | |
| + | |
| + if (!disk->bb) | |
| + return -ENXIO; | |
| + | |
| + return badblocks_store(disk->bb, page, len, 0); | |
| +} | |
| + | |
| /** | |
| * get_gendisk - get partitioning information for a given device | |
| * @devt: device to get partitioning information for | |
| @@ -990,6 +1058,8 @@ | |
| static DEVICE_ATTR(capability, S_IRUGO, disk_capability_show, NULL); | |
| static DEVICE_ATTR(stat, S_IRUGO, part_stat_show, NULL); | |
| static DEVICE_ATTR(inflight, S_IRUGO, part_inflight_show, NULL); | |
| +static DEVICE_ATTR(badblocks, S_IRUGO | S_IWUSR, disk_badblocks_show, | |
| + disk_badblocks_store); | |
| #ifdef CONFIG_FAIL_MAKE_REQUEST | |
| static struct device_attribute dev_attr_fail = | |
| __ATTR(make-it-fail, S_IRUGO|S_IWUSR, part_fail_show, part_fail_store); | |
| @@ -1011,6 +1081,7 @@ | |
| &dev_attr_capability.attr, | |
| &dev_attr_stat.attr, | |
| &dev_attr_inflight.attr, | |
| + &dev_attr_badblocks.attr, | |
| #ifdef CONFIG_FAIL_MAKE_REQUEST | |
| &dev_attr_fail.attr, | |
| #endif | |
| @@ -1286,11 +1357,7 @@ | |
| * converted to make use of bd_mutex and sequence counters. | |
| */ | |
| seqcount_init(&disk->part0.nr_sects_seq); | |
| - if (hd_ref_init(&disk->part0)) { | |
| - hd_free_part(&disk->part0); | |
| - kfree(disk); | |
| - return NULL; | |
| - } | |
| + hd_ref_init(&disk->part0); | |
| disk->minors = minors; | |
| rand_initialize_disk(disk); | |
| diff -x .git -Naur linux-4.4.111/block/Kconfig.iosched linux-4.4.111-alpine/block/Kconfig.iosched | |
| --- linux-4.4.111/block/Kconfig.iosched 2018-02-20 12:32:40.348080136 -0500 | |
| +++ linux-4.4.111-alpine/block/Kconfig.iosched 2018-02-14 21:04:16.000000000 -0500 | |
| @@ -39,6 +39,25 @@ | |
| ---help--- | |
| Enable group IO scheduling in CFQ. | |
| +config IOSCHED_BFQ | |
| + tristate "BFQ I/O scheduler" | |
| + default n | |
| + ---help--- | |
| + The BFQ I/O scheduler tries to distribute bandwidth among | |
| + all processes according to their weights. | |
| + It aims at distributing the bandwidth as desired, independently of | |
| + the disk parameters and with any workload. It also tries to | |
| + guarantee low latency to interactive and soft real-time | |
| + applications. If compiled built-in (saying Y here), BFQ can | |
| + be configured to support hierarchical scheduling. | |
| + | |
| +config BFQ_GROUP_IOSCHED | |
| + bool "BFQ hierarchical scheduling support" | |
| + depends on CGROUPS && IOSCHED_BFQ=y | |
| + default n | |
| + ---help--- | |
| + Enable hierarchical scheduling in BFQ, using the blkio controller. | |
| + | |
| choice | |
| prompt "Default I/O scheduler" | |
| default DEFAULT_CFQ | |
| @@ -52,6 +71,16 @@ | |
| config DEFAULT_CFQ | |
| bool "CFQ" if IOSCHED_CFQ=y | |
| + config DEFAULT_BFQ | |
| + bool "BFQ" if IOSCHED_BFQ=y | |
| + help | |
| + Selects BFQ as the default I/O scheduler which will be | |
| + used by default for all block devices. | |
| + The BFQ I/O scheduler aims at distributing the bandwidth | |
| + as desired, independently of the disk parameters and with | |
| + any workload. It also tries to guarantee low latency to | |
| + interactive and soft real-time applications. | |
| + | |
| config DEFAULT_NOOP | |
| bool "No-op" | |
| @@ -61,6 +90,7 @@ | |
| string | |
| default "deadline" if DEFAULT_DEADLINE | |
| default "cfq" if DEFAULT_CFQ | |
| + default "bfq" if DEFAULT_BFQ | |
| default "noop" if DEFAULT_NOOP | |
| endmenu | |
| diff -x .git -Naur linux-4.4.111/block/Makefile linux-4.4.111-alpine/block/Makefile | |
| --- linux-4.4.111/block/Makefile 2018-02-20 12:32:40.348080136 -0500 | |
| +++ linux-4.4.111-alpine/block/Makefile 2018-02-14 21:04:16.000000000 -0500 | |
| @@ -8,7 +8,7 @@ | |
| blk-iopoll.o blk-lib.o blk-mq.o blk-mq-tag.o \ | |
| blk-mq-sysfs.o blk-mq-cpu.o blk-mq-cpumap.o ioctl.o \ | |
| genhd.o scsi_ioctl.o partition-generic.o ioprio.o \ | |
| - partitions/ | |
| + badblocks.o partitions/ | |
| obj-$(CONFIG_BOUNCE) += bounce.o | |
| obj-$(CONFIG_BLK_DEV_BSG) += bsg.o | |
| @@ -18,6 +18,7 @@ | |
| obj-$(CONFIG_IOSCHED_NOOP) += noop-iosched.o | |
| obj-$(CONFIG_IOSCHED_DEADLINE) += deadline-iosched.o | |
| obj-$(CONFIG_IOSCHED_CFQ) += cfq-iosched.o | |
| +obj-$(CONFIG_IOSCHED_BFQ) += bfq-iosched.o | |
| obj-$(CONFIG_BLOCK_COMPAT) += compat_ioctl.o | |
| obj-$(CONFIG_BLK_CMDLINE_PARSER) += cmdline-parser.o | |
| diff -x .git -Naur linux-4.4.111/block/partition-generic.c linux-4.4.111-alpine/block/partition-generic.c | |
| --- linux-4.4.111/block/partition-generic.c 2018-02-20 12:32:40.388080293 -0500 | |
| +++ linux-4.4.111-alpine/block/partition-generic.c 2018-02-14 21:04:16.000000000 -0500 | |
| @@ -232,9 +232,8 @@ | |
| put_device(part_to_dev(part)); | |
| } | |
| -void __delete_partition(struct percpu_ref *ref) | |
| +void __delete_partition(struct hd_struct *part) | |
| { | |
| - struct hd_struct *part = container_of(ref, struct hd_struct, ref); | |
| call_rcu(&part->rcu_head, delete_partition_rcu_cb); | |
| } | |
| @@ -255,7 +254,7 @@ | |
| kobject_put(part->holder_dir); | |
| device_del(part_to_dev(part)); | |
| - hd_struct_kill(part); | |
| + hd_struct_put(part); | |
| } | |
| static ssize_t whole_disk_show(struct device *dev, | |
| @@ -349,19 +348,14 @@ | |
| goto out_del; | |
| } | |
| - err = hd_ref_init(p); | |
| - if (err) { | |
| - if (flags & ADDPART_FLAG_WHOLEDISK) | |
| - goto out_remove_file; | |
| - goto out_del; | |
| - } | |
| - | |
| /* everything is up and running, commence */ | |
| rcu_assign_pointer(ptbl->part[partno], p); | |
| /* suppress uevent if the disk suppresses it */ | |
| if (!dev_get_uevent_suppress(ddev)) | |
| kobject_uevent(&pdev->kobj, KOBJ_ADD); | |
| + | |
| + hd_ref_init(p); | |
| return p; | |
| out_free_info: | |
| @@ -371,8 +365,6 @@ | |
| out_free: | |
| kfree(p); | |
| return ERR_PTR(err); | |
| -out_remove_file: | |
| - device_remove_file(pdev, &dev_attr_whole_disk); | |
| out_del: | |
| kobject_put(p->holder_dir); | |
| device_del(pdev); | |
| diff -x .git -Naur linux-4.4.111/.config.netgear-rn214 linux-4.4.111-alpine/.config.netgear-rn214 | |
| --- linux-4.4.111/.config.netgear-rn214 1969-12-31 19:00:00.000000000 -0500 | |
| +++ linux-4.4.111-alpine/.config.netgear-rn214 2018-02-20 12:34:07.458421314 -0500 | |
| @@ -0,0 +1,3439 @@ | |
| +# | |
| +# Automatically generated file; DO NOT EDIT. | |
| +# Linux/arm 4.4.111 Kernel Configuration | |
| +# | |
| +CONFIG_ARM=y | |
| +CONFIG_ARM_HAS_SG_CHAIN=y | |
| +CONFIG_MIGHT_HAVE_PCI=y | |
| +CONFIG_SYS_SUPPORTS_APM_EMULATION=y | |
| +CONFIG_HAVE_PROC_CPU=y | |
| +CONFIG_STACKTRACE_SUPPORT=y | |
| +CONFIG_LOCKDEP_SUPPORT=y | |
| +CONFIG_TRACE_IRQFLAGS_SUPPORT=y | |
| +CONFIG_RWSEM_XCHGADD_ALGORITHM=y | |
| +CONFIG_FIX_EARLYCON_MEM=y | |
| +CONFIG_GENERIC_HWEIGHT=y | |
| +CONFIG_GENERIC_CALIBRATE_DELAY=y | |
| +CONFIG_NEED_DMA_MAP_STATE=y | |
| +CONFIG_ARCH_SUPPORTS_UPROBES=y | |
| +CONFIG_VECTORS_BASE=0xffff0000 | |
| +CONFIG_ARM_PATCH_PHYS_VIRT=y | |
| +CONFIG_GENERIC_BUG=y | |
| +CONFIG_PGTABLE_LEVELS=3 | |
| +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" | |
| +CONFIG_IRQ_WORK=y | |
| +CONFIG_BUILDTIME_EXTABLE_SORT=y | |
| + | |
| +# | |
| +# General setup | |
| +# | |
| +CONFIG_INIT_ENV_ARG_LIMIT=32 | |
| +CONFIG_CROSS_COMPILE="" | |
| +# CONFIG_COMPILE_TEST is not set | |
| +CONFIG_LOCALVERSION="" | |
| +CONFIG_LOCALVERSION_AUTO=y | |
| +CONFIG_HAVE_KERNEL_GZIP=y | |
| +CONFIG_HAVE_KERNEL_LZMA=y | |
| +CONFIG_HAVE_KERNEL_XZ=y | |
| +CONFIG_HAVE_KERNEL_LZO=y | |
| +CONFIG_HAVE_KERNEL_LZ4=y | |
| +# CONFIG_KERNEL_GZIP is not set | |
| +# CONFIG_KERNEL_LZMA is not set | |
| +CONFIG_KERNEL_XZ=y | |
| +# CONFIG_KERNEL_LZO is not set | |
| +# CONFIG_KERNEL_LZ4 is not set | |
| +CONFIG_DEFAULT_HOSTNAME="readynasos" | |
| +CONFIG_SWAP=y | |
| +CONFIG_SYSVIPC=y | |
| +CONFIG_SYSVIPC_SYSCTL=y | |
| +CONFIG_POSIX_MQUEUE=y | |
| +CONFIG_POSIX_MQUEUE_SYSCTL=y | |
| +CONFIG_CROSS_MEMORY_ATTACH=y | |
| +CONFIG_FHANDLE=y | |
| +CONFIG_USELIB=y | |
| +# CONFIG_AUDIT is not set | |
| +CONFIG_HAVE_ARCH_AUDITSYSCALL=y | |
| + | |
| +# | |
| +# IRQ subsystem | |
| +# | |
| +CONFIG_GENERIC_IRQ_PROBE=y | |
| +CONFIG_GENERIC_IRQ_SHOW=y | |
| +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y | |
| +CONFIG_HARDIRQS_SW_RESEND=y | |
| +CONFIG_GENERIC_IRQ_CHIP=y | |
| +CONFIG_IRQ_DOMAIN=y | |
| +CONFIG_IRQ_DOMAIN_HIERARCHY=y | |
| +CONFIG_GENERIC_MSI_IRQ=y | |
| +CONFIG_GENERIC_MSI_IRQ_DOMAIN=y | |
| +CONFIG_HANDLE_DOMAIN_IRQ=y | |
| +CONFIG_IRQ_FORCED_THREADING=y | |
| +CONFIG_SPARSE_IRQ=y | |
| +CONFIG_GENERIC_TIME_VSYSCALL=y | |
| +CONFIG_GENERIC_CLOCKEVENTS=y | |
| +CONFIG_ARCH_HAS_TICK_BROADCAST=y | |
| +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y | |
| + | |
| +# | |
| +# Timers subsystem | |
| +# | |
| +CONFIG_TICK_ONESHOT=y | |
| +CONFIG_NO_HZ_COMMON=y | |
| +# CONFIG_HZ_PERIODIC is not set | |
| +CONFIG_NO_HZ_IDLE=y | |
| +# CONFIG_NO_HZ_FULL is not set | |
| +CONFIG_NO_HZ=y | |
| +# CONFIG_HIGH_RES_TIMERS is not set | |
| + | |
| +# | |
| +# CPU/Task time and stats accounting | |
| +# | |
| +CONFIG_TICK_CPU_ACCOUNTING=y | |
| +# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set | |
| +# CONFIG_IRQ_TIME_ACCOUNTING is not set | |
| +CONFIG_BSD_PROCESS_ACCT=y | |
| +# CONFIG_BSD_PROCESS_ACCT_V3 is not set | |
| +CONFIG_TASKSTATS=y | |
| +CONFIG_TASK_DELAY_ACCT=y | |
| +CONFIG_TASK_XACCT=y | |
| +CONFIG_TASK_IO_ACCOUNTING=y | |
| + | |
| +# | |
| +# RCU Subsystem | |
| +# | |
| +CONFIG_TREE_RCU=y | |
| +# CONFIG_RCU_EXPERT is not set | |
| +CONFIG_SRCU=y | |
| +# CONFIG_TASKS_RCU is not set | |
| +CONFIG_RCU_STALL_COMMON=y | |
| +# CONFIG_TREE_RCU_TRACE is not set | |
| +# CONFIG_RCU_EXPEDITE_BOOT is not set | |
| +CONFIG_BUILD_BIN2C=y | |
| +CONFIG_IKCONFIG=m | |
| +CONFIG_IKCONFIG_PROC=y | |
| +CONFIG_LOG_BUF_SHIFT=17 | |
| +CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 | |
| +CONFIG_GENERIC_SCHED_CLOCK=y | |
| +CONFIG_CGROUPS=y | |
| +# CONFIG_CGROUP_DEBUG is not set | |
| +CONFIG_CGROUP_FREEZER=y | |
| +# CONFIG_CGROUP_PIDS is not set | |
| +CONFIG_CGROUP_DEVICE=y | |
| +CONFIG_CPUSETS=y | |
| +# CONFIG_PROC_PID_CPUSET is not set | |
| +CONFIG_CGROUP_CPUACCT=y | |
| +# CONFIG_MEMCG is not set | |
| +CONFIG_CGROUP_SCHED=y | |
| +CONFIG_FAIR_GROUP_SCHED=y | |
| +CONFIG_CFS_BANDWIDTH=y | |
| +CONFIG_RT_GROUP_SCHED=y | |
| +CONFIG_BLK_CGROUP=y | |
| +# CONFIG_DEBUG_BLK_CGROUP is not set | |
| +# CONFIG_CHECKPOINT_RESTORE is not set | |
| +CONFIG_NAMESPACES=y | |
| +CONFIG_UTS_NS=y | |
| +CONFIG_IPC_NS=y | |
| +CONFIG_USER_NS=y | |
| +CONFIG_PID_NS=y | |
| +CONFIG_NET_NS=y | |
| +# CONFIG_SCHED_AUTOGROUP is not set | |
| +# CONFIG_SYSFS_DEPRECATED is not set | |
| +# CONFIG_RELAY is not set | |
| +CONFIG_BLK_DEV_INITRD=y | |
| +CONFIG_INITRAMFS_SOURCE="" | |
| +CONFIG_RD_GZIP=y | |
| +# CONFIG_RD_BZIP2 is not set | |
| +CONFIG_RD_LZMA=y | |
| +CONFIG_RD_XZ=y | |
| +# CONFIG_RD_LZO is not set | |
| +# CONFIG_RD_LZ4 is not set | |
| +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set | |
| +CONFIG_SYSCTL=y | |
| +CONFIG_ANON_INODES=y | |
| +CONFIG_HAVE_UID16=y | |
| +CONFIG_BPF=y | |
| +CONFIG_EXPERT=y | |
| +CONFIG_UID16=y | |
| +CONFIG_MULTIUSER=y | |
| +CONFIG_SGETMASK_SYSCALL=y | |
| +CONFIG_SYSFS_SYSCALL=y | |
| +CONFIG_SYSCTL_SYSCALL=y | |
| +CONFIG_KALLSYMS=y | |
| +# CONFIG_KALLSYMS_ALL is not set | |
| +CONFIG_PRINTK=y | |
| +CONFIG_BUG=y | |
| +CONFIG_ELF_CORE=y | |
| +CONFIG_BASE_FULL=y | |
| +CONFIG_FUTEX=y | |
| +CONFIG_EPOLL=y | |
| +CONFIG_SIGNALFD=y | |
| +CONFIG_TIMERFD=y | |
| +CONFIG_EVENTFD=y | |
| +# CONFIG_BPF_SYSCALL is not set | |
| +CONFIG_SHMEM=y | |
| +CONFIG_AIO=y | |
| +CONFIG_ADVISE_SYSCALLS=y | |
| +# CONFIG_USERFAULTFD is not set | |
| +CONFIG_PCI_QUIRKS=y | |
| +CONFIG_MEMBARRIER=y | |
| +CONFIG_EMBEDDED=y | |
| +CONFIG_HAVE_PERF_EVENTS=y | |
| +CONFIG_PERF_USE_VMALLOC=y | |
| + | |
| +# | |
| +# Kernel Performance Events And Counters | |
| +# | |
| +# CONFIG_PERF_EVENTS is not set | |
| +CONFIG_VM_EVENT_COUNTERS=y | |
| +CONFIG_SLUB_DEBUG=y | |
| +# CONFIG_COMPAT_BRK is not set | |
| +# CONFIG_SLAB is not set | |
| +CONFIG_SLUB=y | |
| +# CONFIG_SLOB is not set | |
| +CONFIG_SLUB_CPU_PARTIAL=y | |
| +# CONFIG_SYSTEM_DATA_VERIFICATION is not set | |
| +# CONFIG_PROFILING is not set | |
| +CONFIG_HAVE_OPROFILE=y | |
| +# CONFIG_KPROBES is not set | |
| +CONFIG_JUMP_LABEL=y | |
| +# CONFIG_STATIC_KEYS_SELFTEST is not set | |
| +# CONFIG_UPROBES is not set | |
| +# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set | |
| +CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y | |
| +CONFIG_ARCH_USE_BUILTIN_BSWAP=y | |
| +CONFIG_HAVE_KPROBES=y | |
| +CONFIG_HAVE_KRETPROBES=y | |
| +CONFIG_HAVE_OPTPROBES=y | |
| +CONFIG_HAVE_ARCH_TRACEHOOK=y | |
| +CONFIG_HAVE_DMA_ATTRS=y | |
| +CONFIG_HAVE_DMA_CONTIGUOUS=y | |
| +CONFIG_GENERIC_SMP_IDLE_THREAD=y | |
| +CONFIG_GENERIC_IDLE_POLL_SETUP=y | |
| +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y | |
| +CONFIG_HAVE_CLK=y | |
| +CONFIG_HAVE_DMA_API_DEBUG=y | |
| +CONFIG_HAVE_PERF_REGS=y | |
| +CONFIG_HAVE_PERF_USER_STACK_DUMP=y | |
| +CONFIG_HAVE_ARCH_JUMP_LABEL=y | |
| +CONFIG_HAVE_RCU_TABLE_FREE=y | |
| +CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y | |
| +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y | |
| +CONFIG_SECCOMP_FILTER=y | |
| +CONFIG_HAVE_CC_STACKPROTECTOR=y | |
| +# CONFIG_CC_STACKPROTECTOR is not set | |
| +CONFIG_CC_STACKPROTECTOR_NONE=y | |
| +# CONFIG_CC_STACKPROTECTOR_REGULAR is not set | |
| +# CONFIG_CC_STACKPROTECTOR_STRONG is not set | |
| +CONFIG_HAVE_CONTEXT_TRACKING=y | |
| +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y | |
| +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y | |
| +CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y | |
| +CONFIG_HAVE_MOD_ARCH_SPECIFIC=y | |
| +CONFIG_MODULES_USE_ELF_REL=y | |
| +CONFIG_ARCH_HAS_ELF_RANDOMIZE=y | |
| +CONFIG_CLONE_BACKWARDS=y | |
| +CONFIG_OLD_SIGSUSPEND3=y | |
| +CONFIG_OLD_SIGACTION=y | |
| + | |
| +# | |
| +# GCOV-based kernel profiling | |
| +# | |
| +CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y | |
| +CONFIG_HAVE_GENERIC_DMA_COHERENT=y | |
| +CONFIG_SLABINFO=y | |
| +CONFIG_RT_MUTEXES=y | |
| +CONFIG_BASE_SMALL=0 | |
| +CONFIG_MODULES=y | |
| +# CONFIG_MODULE_FORCE_LOAD is not set | |
| +CONFIG_MODULE_UNLOAD=y | |
| +# CONFIG_MODULE_FORCE_UNLOAD is not set | |
| +CONFIG_MODVERSIONS=y | |
| +# CONFIG_MODULE_SRCVERSION_ALL is not set | |
| +# CONFIG_MODULE_SIG is not set | |
| +# CONFIG_MODULE_COMPRESS is not set | |
| +CONFIG_BLOCK=y | |
| +CONFIG_LBDAF=y | |
| +CONFIG_BLK_DEV_BSG=y | |
| +CONFIG_BLK_DEV_BSGLIB=y | |
| +# CONFIG_BLK_DEV_INTEGRITY is not set | |
| +# CONFIG_BLK_DEV_THROTTLING is not set | |
| +# CONFIG_BLK_CMDLINE_PARSER is not set | |
| + | |
| +# | |
| +# Partition Types | |
| +# | |
| +CONFIG_PARTITION_ADVANCED=y | |
| +# CONFIG_ACORN_PARTITION is not set | |
| +# CONFIG_AIX_PARTITION is not set | |
| +# CONFIG_OSF_PARTITION is not set | |
| +# CONFIG_AMIGA_PARTITION is not set | |
| +# CONFIG_ATARI_PARTITION is not set | |
| +# CONFIG_MAC_PARTITION is not set | |
| +CONFIG_MSDOS_PARTITION=y | |
| +CONFIG_BSD_DISKLABEL=y | |
| +# CONFIG_MINIX_SUBPARTITION is not set | |
| +CONFIG_SOLARIS_X86_PARTITION=y | |
| +CONFIG_UNIXWARE_DISKLABEL=y | |
| +CONFIG_LDM_PARTITION=y | |
| +# CONFIG_LDM_DEBUG is not set | |
| +# CONFIG_SGI_PARTITION is not set | |
| +# CONFIG_ULTRIX_PARTITION is not set | |
| +# CONFIG_SUN_PARTITION is not set | |
| +# CONFIG_KARMA_PARTITION is not set | |
| +CONFIG_EFI_PARTITION=y | |
| +# CONFIG_SYSV68_PARTITION is not set | |
| +# CONFIG_CMDLINE_PARTITION is not set | |
| + | |
| +# | |
| +# IO Schedulers | |
| +# | |
| +CONFIG_IOSCHED_NOOP=y | |
| +CONFIG_IOSCHED_DEADLINE=y | |
| +CONFIG_IOSCHED_CFQ=y | |
| +# CONFIG_CFQ_GROUP_IOSCHED is not set | |
| +CONFIG_IOSCHED_BFQ=y | |
| +CONFIG_BFQ_GROUP_IOSCHED=y | |
| +# CONFIG_DEFAULT_DEADLINE is not set | |
| +CONFIG_DEFAULT_CFQ=y | |
| +# CONFIG_DEFAULT_BFQ is not set | |
| +# CONFIG_DEFAULT_NOOP is not set | |
| +CONFIG_DEFAULT_IOSCHED="cfq" | |
| +CONFIG_INLINE_SPIN_UNLOCK_IRQ=y | |
| +CONFIG_INLINE_READ_UNLOCK=y | |
| +CONFIG_INLINE_READ_UNLOCK_IRQ=y | |
| +CONFIG_INLINE_WRITE_UNLOCK=y | |
| +CONFIG_INLINE_WRITE_UNLOCK_IRQ=y | |
| +CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y | |
| +CONFIG_MUTEX_SPIN_ON_OWNER=y | |
| +CONFIG_RWSEM_SPIN_ON_OWNER=y | |
| +CONFIG_LOCK_SPIN_ON_OWNER=y | |
| +CONFIG_FREEZER=y | |
| + | |
| +# | |
| +# System Type | |
| +# | |
| +CONFIG_MMU=y | |
| +CONFIG_ARCH_MULTIPLATFORM=y | |
| +# CONFIG_ARCH_REALVIEW is not set | |
| +# CONFIG_ARCH_VERSATILE is not set | |
| +# CONFIG_ARCH_CLPS711X is not set | |
| +# CONFIG_ARCH_GEMINI is not set | |
| +# CONFIG_ARCH_EBSA110 is not set | |
| +# CONFIG_ARCH_EP93XX is not set | |
| +# CONFIG_ARCH_FOOTBRIDGE is not set | |
| +# CONFIG_ARCH_NETX is not set | |
| +# CONFIG_ARCH_IOP13XX is not set | |
| +# CONFIG_ARCH_IOP32X is not set | |
| +# CONFIG_ARCH_IOP33X is not set | |
| +# CONFIG_ARCH_IXP4XX is not set | |
| +# CONFIG_ARCH_DOVE is not set | |
| +# CONFIG_ARCH_MV78XX0 is not set | |
| +# CONFIG_ARCH_ORION5X is not set | |
| +# CONFIG_ARCH_MMP is not set | |
| +# CONFIG_ARCH_KS8695 is not set | |
| +# CONFIG_ARCH_W90X900 is not set | |
| +# CONFIG_ARCH_LPC32XX is not set | |
| +# CONFIG_ARCH_PXA is not set | |
| +# CONFIG_ARCH_RPC is not set | |
| +# CONFIG_ARCH_SA1100 is not set | |
| +# CONFIG_ARCH_S3C24XX is not set | |
| +# CONFIG_ARCH_S3C64XX is not set | |
| +# CONFIG_ARCH_DAVINCI is not set | |
| +# CONFIG_ARCH_OMAP1 is not set | |
| + | |
| +# | |
| +# Multiple platform selection | |
| +# | |
| + | |
| +# | |
| +# CPU Core family selection | |
| +# | |
| +# CONFIG_ARCH_MULTI_V6 is not set | |
| +CONFIG_ARCH_MULTI_V7=y | |
| +CONFIG_ARCH_MULTI_V6_V7=y | |
| +# CONFIG_ARCH_MULTI_CPU_AUTO is not set | |
| +# CONFIG_ARCH_VIRT is not set | |
| +# CONFIG_ARCH_MVEBU is not set | |
| +CONFIG_ARCH_ALPINE=y | |
| +# CONFIG_ARCH_AT91 is not set | |
| +# CONFIG_ARCH_AXXIA is not set | |
| +# CONFIG_ARCH_BCM is not set | |
| +# CONFIG_ARCH_BERLIN is not set | |
| +# CONFIG_ARCH_DIGICOLOR is not set | |
| +# CONFIG_ARCH_HIGHBANK is not set | |
| +# CONFIG_ARCH_HISI is not set | |
| +# CONFIG_ARCH_KEYSTONE is not set | |
| +# CONFIG_ARCH_MESON is not set | |
| +# CONFIG_ARCH_MXC is not set | |
| +# CONFIG_ARCH_MEDIATEK is not set | |
| + | |
| +# | |
| +# TI OMAP/AM/DM/DRA Family | |
| +# | |
| +# CONFIG_ARCH_OMAP3 is not set | |
| +# CONFIG_ARCH_OMAP4 is not set | |
| +# CONFIG_SOC_OMAP5 is not set | |
| +# CONFIG_SOC_AM33XX is not set | |
| +# CONFIG_SOC_AM43XX is not set | |
| +# CONFIG_SOC_DRA7XX is not set | |
| +# CONFIG_ARCH_QCOM is not set | |
| +# CONFIG_ARCH_ROCKCHIP is not set | |
| +# CONFIG_ARCH_SOCFPGA is not set | |
| +# CONFIG_PLAT_SPEAR is not set | |
| +# CONFIG_ARCH_STI is not set | |
| +# CONFIG_ARCH_S5PV210 is not set | |
| +# CONFIG_ARCH_EXYNOS is not set | |
| +# CONFIG_ARCH_SHMOBILE_MULTI is not set | |
| +# CONFIG_ARCH_SUNXI is not set | |
| +# CONFIG_ARCH_SIRF is not set | |
| +# CONFIG_ARCH_TEGRA is not set | |
| +# CONFIG_ARCH_UNIPHIER is not set | |
| +# CONFIG_ARCH_U8500 is not set | |
| +# CONFIG_ARCH_VEXPRESS is not set | |
| +# CONFIG_ARCH_WM8850 is not set | |
| +# CONFIG_ARCH_ZX is not set | |
| +# CONFIG_ARCH_ZYNQ is not set | |
| + | |
| +# | |
| +# Processor Type | |
| +# | |
| +CONFIG_CPU_V7=y | |
| +CONFIG_CPU_32v6K=y | |
| +CONFIG_CPU_32v7=y | |
| +CONFIG_CPU_ABRT_EV7=y | |
| +CONFIG_CPU_PABRT_V7=y | |
| +CONFIG_CPU_CACHE_V7=y | |
| +CONFIG_CPU_CACHE_VIPT=y | |
| +CONFIG_CPU_COPY_V6=y | |
| +CONFIG_CPU_TLB_V7=y | |
| +CONFIG_CPU_HAS_ASID=y | |
| +CONFIG_CPU_CP15=y | |
| +CONFIG_CPU_CP15_MMU=y | |
| + | |
| +# | |
| +# Processor Features | |
| +# | |
| +CONFIG_ARM_LPAE=y | |
| +CONFIG_ARCH_PHYS_ADDR_T_64BIT=y | |
| +CONFIG_ARM_THUMB=y | |
| +# CONFIG_ARM_THUMBEE is not set | |
| +CONFIG_ARM_VIRT_EXT=y | |
| +CONFIG_SWP_EMULATE=y | |
| +# CONFIG_CPU_ICACHE_DISABLE is not set | |
| +# CONFIG_CPU_BPREDICT_DISABLE is not set | |
| +CONFIG_KUSER_HELPERS=y | |
| +CONFIG_VDSO=y | |
| +CONFIG_MIGHT_HAVE_CACHE_L2X0=y | |
| +# CONFIG_CACHE_L2X0 is not set | |
| +CONFIG_ARM_L1_CACHE_SHIFT_6=y | |
| +CONFIG_ARM_L1_CACHE_SHIFT=6 | |
| +CONFIG_ARM_DMA_MEM_BUFFERABLE=y | |
| +# CONFIG_ARM_KERNMEM_PERMS is not set | |
| +CONFIG_MULTI_IRQ_HANDLER=y | |
| +# CONFIG_ARM_ERRATA_430973 is not set | |
| +# CONFIG_ARM_ERRATA_643719 is not set | |
| +CONFIG_ARM_ERRATA_720789=y | |
| +# CONFIG_ARM_ERRATA_754322 is not set | |
| +# CONFIG_ARM_ERRATA_754327 is not set | |
| +# CONFIG_ARM_ERRATA_764369 is not set | |
| +# CONFIG_ARM_ERRATA_775420 is not set | |
| +# CONFIG_ARM_ERRATA_798181 is not set | |
| +# CONFIG_ARM_ERRATA_773022 is not set | |
| + | |
| +# | |
| +# Bus support | |
| +# | |
| +CONFIG_PCI=y | |
| +CONFIG_PCI_DOMAINS=y | |
| +CONFIG_PCI_DOMAINS_GENERIC=y | |
| +CONFIG_PCI_SYSCALL=y | |
| +CONFIG_PCI_MSI=y | |
| +CONFIG_PCI_MSI_IRQ_DOMAIN=y | |
| +# CONFIG_PCI_DEBUG is not set | |
| +# CONFIG_PCI_REALLOC_ENABLE_AUTO is not set | |
| +# CONFIG_PCI_STUB is not set | |
| +CONFIG_PCI_ATS=y | |
| +CONFIG_PCI_IOV=y | |
| +# CONFIG_PCI_PRI is not set | |
| +# CONFIG_PCI_PASID is not set | |
| + | |
| +# | |
| +# PCI host controller drivers | |
| +# | |
| +CONFIG_PCI_INTERNAL_ALPINE=y | |
| +CONFIG_PCI_EXTERNAL_ALPINE=y | |
| +# CONFIG_PCI_HOST_GENERIC is not set | |
| +# CONFIG_PCI_LAYERSCAPE is not set | |
| +# CONFIG_PCIE_IPROC is not set | |
| +# CONFIG_PCIE_ALTERA is not set | |
| +# CONFIG_PCIEPORTBUS is not set | |
| +# CONFIG_PCCARD is not set | |
| + | |
| +# | |
| +# Kernel Features | |
| +# | |
| +CONFIG_HAVE_SMP=y | |
| +CONFIG_SMP=y | |
| +# CONFIG_SMP_ON_UP is not set | |
| +CONFIG_ARM_CPU_TOPOLOGY=y | |
| +# CONFIG_SCHED_MC is not set | |
| +# CONFIG_SCHED_SMT is not set | |
| +CONFIG_HAVE_ARM_ARCH_TIMER=y | |
| +# CONFIG_MCPM is not set | |
| +# CONFIG_BIG_LITTLE is not set | |
| +CONFIG_VMSPLIT_3G=y | |
| +# CONFIG_VMSPLIT_3G_OPT is not set | |
| +# CONFIG_VMSPLIT_2G is not set | |
| +# CONFIG_VMSPLIT_1G is not set | |
| +CONFIG_PAGE_OFFSET=0xC0000000 | |
| +CONFIG_NR_CPUS=4 | |
| +CONFIG_HOTPLUG_CPU=y | |
| +# CONFIG_ARM_PSCI is not set | |
| +CONFIG_ARCH_NR_GPIO=0 | |
| +# CONFIG_PREEMPT_NONE is not set | |
| +CONFIG_PREEMPT_VOLUNTARY=y | |
| +# CONFIG_PREEMPT is not set | |
| +CONFIG_HZ_FIXED=0 | |
| +CONFIG_HZ_100=y | |
| +# CONFIG_HZ_200 is not set | |
| +# CONFIG_HZ_250 is not set | |
| +# CONFIG_HZ_300 is not set | |
| +# CONFIG_HZ_500 is not set | |
| +# CONFIG_HZ_1000 is not set | |
| +CONFIG_HZ=100 | |
| +# CONFIG_SCHED_HRTICK is not set | |
| +# CONFIG_THUMB2_KERNEL is not set | |
| +CONFIG_AEABI=y | |
| +# CONFIG_OABI_COMPAT is not set | |
| +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set | |
| +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set | |
| +CONFIG_HAVE_ARCH_PFN_VALID=y | |
| +CONFIG_HAVE_GENERIC_RCU_GUP=y | |
| +CONFIG_HIGHMEM=y | |
| +# CONFIG_HIGHPTE is not set | |
| +CONFIG_SYS_SUPPORTS_HUGETLBFS=y | |
| +CONFIG_ARCH_WANT_GENERAL_HUGETLB=y | |
| +# CONFIG_ARM_MODULE_PLTS is not set | |
| +CONFIG_FLATMEM=y | |
| +CONFIG_FLAT_NODE_MEM_MAP=y | |
| +CONFIG_HAVE_MEMBLOCK=y | |
| +CONFIG_NO_BOOTMEM=y | |
| +# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set | |
| +CONFIG_SPLIT_PTLOCK_CPUS=4 | |
| +# CONFIG_COMPACTION is not set | |
| +CONFIG_PHYS_ADDR_T_64BIT=y | |
| +CONFIG_ZONE_DMA_FLAG=0 | |
| +CONFIG_BOUNCE=y | |
| +# CONFIG_KSM is not set | |
| +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 | |
| +# CONFIG_TRANSPARENT_HUGEPAGE is not set | |
| +# CONFIG_CLEANCACHE is not set | |
| +# CONFIG_FRONTSWAP is not set | |
| +# CONFIG_CMA is not set | |
| +# CONFIG_ZPOOL is not set | |
| +# CONFIG_ZBUD is not set | |
| +CONFIG_ZSMALLOC=y | |
| +CONFIG_PGTABLE_MAPPING=y | |
| +# CONFIG_ZSMALLOC_STAT is not set | |
| +# CONFIG_IDLE_PAGE_TRACKING is not set | |
| +CONFIG_FORCE_MAX_ZONEORDER=11 | |
| +CONFIG_ALIGNMENT_TRAP=y | |
| +CONFIG_UACCESS_WITH_MEMCPY=y | |
| +CONFIG_SECCOMP=y | |
| +CONFIG_SWIOTLB=y | |
| +CONFIG_IOMMU_HELPER=y | |
| +# CONFIG_XEN is not set | |
| + | |
| +# | |
| +# Boot options | |
| +# | |
| +CONFIG_USE_OF=y | |
| +CONFIG_ATAGS=y | |
| +# CONFIG_DEPRECATED_PARAM_STRUCT is not set | |
| +CONFIG_ZBOOT_ROM_TEXT=0x0 | |
| +CONFIG_ZBOOT_ROM_BSS=0x0 | |
| +# CONFIG_ARM_APPENDED_DTB is not set | |
| +CONFIG_CMDLINE="" | |
| +# CONFIG_CRASH_DUMP is not set | |
| +CONFIG_AUTO_ZRELADDR=y | |
| + | |
| +# | |
| +# CPU Power Management | |
| +# | |
| + | |
| +# | |
| +# CPU Frequency scaling | |
| +# | |
| +# CONFIG_CPU_FREQ is not set | |
| + | |
| +# | |
| +# CPU Idle | |
| +# | |
| +CONFIG_CPU_IDLE=y | |
| +CONFIG_CPU_IDLE_GOV_LADDER=y | |
| +CONFIG_CPU_IDLE_GOV_MENU=y | |
| + | |
| +# | |
| +# ARM CPU Idle Drivers | |
| +# | |
| +# CONFIG_ARM_CPUIDLE is not set | |
| +# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set | |
| + | |
| +# | |
| +# Floating point emulation | |
| +# | |
| + | |
| +# | |
| +# At least one emulation must be selected | |
| +# | |
| +CONFIG_VFP=y | |
| +CONFIG_VFPv3=y | |
| +CONFIG_NEON=y | |
| +# CONFIG_KERNEL_MODE_NEON is not set | |
| + | |
| +# | |
| +# Userspace binary formats | |
| +# | |
| +CONFIG_BINFMT_ELF=y | |
| +CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y | |
| +CONFIG_BINFMT_SCRIPT=y | |
| +# CONFIG_HAVE_AOUT is not set | |
| +# CONFIG_BINFMT_MISC is not set | |
| +CONFIG_COREDUMP=y | |
| + | |
| +# | |
| +# Power management options | |
| +# | |
| +# CONFIG_SUSPEND is not set | |
| +# CONFIG_HIBERNATION is not set | |
| +CONFIG_PM=y | |
| +# CONFIG_PM_DEBUG is not set | |
| +# CONFIG_APM_EMULATION is not set | |
| +CONFIG_PM_CLK=y | |
| +# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set | |
| +CONFIG_CPU_PM=y | |
| +CONFIG_ARCH_SUSPEND_POSSIBLE=y | |
| +# CONFIG_ARM_CPU_SUSPEND is not set | |
| +CONFIG_ARCH_HIBERNATION_POSSIBLE=y | |
| +CONFIG_NET=y | |
| + | |
| +# | |
| +# Networking options | |
| +# | |
| +CONFIG_PACKET=y | |
| +# CONFIG_PACKET_DIAG is not set | |
| +CONFIG_UNIX=y | |
| +# CONFIG_UNIX_DIAG is not set | |
| +CONFIG_XFRM=y | |
| +CONFIG_XFRM_ALGO=m | |
| +CONFIG_XFRM_USER=m | |
| +# CONFIG_XFRM_SUB_POLICY is not set | |
| +# CONFIG_XFRM_MIGRATE is not set | |
| +# CONFIG_XFRM_STATISTICS is not set | |
| +# CONFIG_NET_KEY is not set | |
| +CONFIG_INET=y | |
| +CONFIG_IP_MULTICAST=y | |
| +CONFIG_IP_ADVANCED_ROUTER=y | |
| +# CONFIG_IP_FIB_TRIE_STATS is not set | |
| +CONFIG_IP_MULTIPLE_TABLES=y | |
| +# CONFIG_IP_ROUTE_MULTIPATH is not set | |
| +# CONFIG_IP_ROUTE_VERBOSE is not set | |
| +# CONFIG_IP_PNP is not set | |
| +CONFIG_NET_IPIP=m | |
| +# CONFIG_NET_IPGRE_DEMUX is not set | |
| +CONFIG_NET_IP_TUNNEL=m | |
| +# CONFIG_IP_MROUTE is not set | |
| +# CONFIG_SYN_COOKIES is not set | |
| +CONFIG_NET_UDP_TUNNEL=m | |
| +# CONFIG_NET_FOU is not set | |
| +# CONFIG_NET_FOU_IP_TUNNELS is not set | |
| +# CONFIG_INET_AH is not set | |
| +CONFIG_INET_ESP=m | |
| +# CONFIG_INET_IPCOMP is not set | |
| +# CONFIG_INET_XFRM_TUNNEL is not set | |
| +CONFIG_INET_TUNNEL=m | |
| +CONFIG_INET_XFRM_MODE_TRANSPORT=m | |
| +# CONFIG_INET_XFRM_MODE_TUNNEL is not set | |
| +# CONFIG_INET_XFRM_MODE_BEET is not set | |
| +CONFIG_INET_LRO=y | |
| +CONFIG_INET_DIAG=y | |
| +CONFIG_INET_TCP_DIAG=y | |
| +CONFIG_INET_UDP_DIAG=y | |
| +CONFIG_TCP_CONG_ADVANCED=y | |
| +# CONFIG_TCP_CONG_BIC is not set | |
| +CONFIG_TCP_CONG_CUBIC=y | |
| +# CONFIG_TCP_CONG_WESTWOOD is not set | |
| +# CONFIG_TCP_CONG_HTCP is not set | |
| +# CONFIG_TCP_CONG_HSTCP is not set | |
| +# CONFIG_TCP_CONG_HYBLA is not set | |
| +# CONFIG_TCP_CONG_VEGAS is not set | |
| +# CONFIG_TCP_CONG_SCALABLE is not set | |
| +# CONFIG_TCP_CONG_LP is not set | |
| +# CONFIG_TCP_CONG_VENO is not set | |
| +# CONFIG_TCP_CONG_YEAH is not set | |
| +# CONFIG_TCP_CONG_ILLINOIS is not set | |
| +# CONFIG_TCP_CONG_DCTCP is not set | |
| +# CONFIG_TCP_CONG_CDG is not set | |
| +CONFIG_DEFAULT_CUBIC=y | |
| +# CONFIG_DEFAULT_RENO is not set | |
| +CONFIG_DEFAULT_TCP_CONG="cubic" | |
| +# CONFIG_TCP_MD5SIG is not set | |
| +CONFIG_IPV6=y | |
| +CONFIG_IPV6_ROUTER_PREF=y | |
| +CONFIG_IPV6_ROUTE_INFO=y | |
| +CONFIG_IPV6_OPTIMISTIC_DAD=y | |
| +# CONFIG_INET6_AH is not set | |
| +# CONFIG_INET6_ESP is not set | |
| +# CONFIG_INET6_IPCOMP is not set | |
| +# CONFIG_IPV6_MIP6 is not set | |
| +# CONFIG_IPV6_ILA is not set | |
| +# CONFIG_INET6_XFRM_TUNNEL is not set | |
| +# CONFIG_INET6_TUNNEL is not set | |
| +CONFIG_INET6_XFRM_MODE_TRANSPORT=y | |
| +CONFIG_INET6_XFRM_MODE_TUNNEL=y | |
| +CONFIG_INET6_XFRM_MODE_BEET=y | |
| +# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set | |
| +# CONFIG_IPV6_VTI is not set | |
| +# CONFIG_IPV6_SIT is not set | |
| +# CONFIG_IPV6_TUNNEL is not set | |
| +# CONFIG_IPV6_GRE is not set | |
| +# CONFIG_IPV6_MULTIPLE_TABLES is not set | |
| +# CONFIG_IPV6_MROUTE is not set | |
| +# CONFIG_NETLABEL is not set | |
| +# CONFIG_NETWORK_SECMARK is not set | |
| +# CONFIG_NET_PTP_CLASSIFY is not set | |
| +# CONFIG_NETWORK_PHY_TIMESTAMPING is not set | |
| +CONFIG_NETFILTER=y | |
| +# CONFIG_NETFILTER_DEBUG is not set | |
| +CONFIG_NETFILTER_ADVANCED=y | |
| +CONFIG_BRIDGE_NETFILTER=m | |
| + | |
| +# | |
| +# Core Netfilter Configuration | |
| +# | |
| +# CONFIG_NETFILTER_INGRESS is not set | |
| +CONFIG_NETFILTER_NETLINK=m | |
| +# CONFIG_NETFILTER_NETLINK_ACCT is not set | |
| +CONFIG_NETFILTER_NETLINK_QUEUE=m | |
| +# CONFIG_NETFILTER_NETLINK_LOG is not set | |
| +CONFIG_NF_CONNTRACK=m | |
| +CONFIG_NF_CONNTRACK_MARK=y | |
| +# CONFIG_NF_CONNTRACK_PROCFS is not set | |
| +# CONFIG_NF_CONNTRACK_EVENTS is not set | |
| +# CONFIG_NF_CONNTRACK_TIMEOUT is not set | |
| +# CONFIG_NF_CONNTRACK_TIMESTAMP is not set | |
| +# CONFIG_NF_CT_PROTO_DCCP is not set | |
| +# CONFIG_NF_CT_PROTO_SCTP is not set | |
| +# CONFIG_NF_CT_PROTO_UDPLITE is not set | |
| +# CONFIG_NF_CONNTRACK_AMANDA is not set | |
| +# CONFIG_NF_CONNTRACK_FTP is not set | |
| +# CONFIG_NF_CONNTRACK_H323 is not set | |
| +# CONFIG_NF_CONNTRACK_IRC is not set | |
| +# CONFIG_NF_CONNTRACK_NETBIOS_NS is not set | |
| +# CONFIG_NF_CONNTRACK_SNMP is not set | |
| +# CONFIG_NF_CONNTRACK_PPTP is not set | |
| +# CONFIG_NF_CONNTRACK_SANE is not set | |
| +# CONFIG_NF_CONNTRACK_SIP is not set | |
| +# CONFIG_NF_CONNTRACK_TFTP is not set | |
| +# CONFIG_NF_CT_NETLINK is not set | |
| +# CONFIG_NF_CT_NETLINK_TIMEOUT is not set | |
| +CONFIG_NF_NAT=m | |
| +CONFIG_NF_NAT_NEEDED=y | |
| +# CONFIG_NF_NAT_AMANDA is not set | |
| +# CONFIG_NF_NAT_FTP is not set | |
| +# CONFIG_NF_NAT_IRC is not set | |
| +# CONFIG_NF_NAT_SIP is not set | |
| +# CONFIG_NF_NAT_TFTP is not set | |
| +# CONFIG_NF_NAT_REDIRECT is not set | |
| +# CONFIG_NF_TABLES is not set | |
| +CONFIG_NETFILTER_XTABLES=y | |
| + | |
| +# | |
| +# Xtables combined modules | |
| +# | |
| +# CONFIG_NETFILTER_XT_MARK is not set | |
| +# CONFIG_NETFILTER_XT_CONNMARK is not set | |
| + | |
| +# | |
| +# Xtables targets | |
| +# | |
| +# CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set | |
| +# CONFIG_NETFILTER_XT_TARGET_CONNMARK is not set | |
| +# CONFIG_NETFILTER_XT_TARGET_HMARK is not set | |
| +# CONFIG_NETFILTER_XT_TARGET_IDLETIMER is not set | |
| +# CONFIG_NETFILTER_XT_TARGET_LED is not set | |
| +# CONFIG_NETFILTER_XT_TARGET_LOG is not set | |
| +# CONFIG_NETFILTER_XT_TARGET_MARK is not set | |
| +CONFIG_NETFILTER_XT_NAT=m | |
| +# CONFIG_NETFILTER_XT_TARGET_NETMAP is not set | |
| +# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set | |
| +# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set | |
| +# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set | |
| +# CONFIG_NETFILTER_XT_TARGET_REDIRECT is not set | |
| +# CONFIG_NETFILTER_XT_TARGET_TEE is not set | |
| +# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set | |
| + | |
| +# | |
| +# Xtables matches | |
| +# | |
| +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m | |
| +# CONFIG_NETFILTER_XT_MATCH_BPF is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_CGROUP is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_CLUSTER is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_CONNBYTES is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_CONNLABEL is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_CONNLIMIT is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_CONNMARK is not set | |
| +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m | |
| +# CONFIG_NETFILTER_XT_MATCH_CPU is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_DCCP is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_DEVGROUP is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_DSCP is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_ECN is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_ESP is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_HELPER is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_HL is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_IPCOMP is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set | |
| +CONFIG_NETFILTER_XT_MATCH_IPVS=m | |
| +# CONFIG_NETFILTER_XT_MATCH_L2TP is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_LIMIT is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_MAC is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_MARK is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_NFACCT is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_OSF is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_OWNER is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_POLICY is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_PHYSDEV is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_REALM is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_RECENT is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_SCTP is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_SOCKET is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_STATE is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_STRING is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_TIME is not set | |
| +# CONFIG_NETFILTER_XT_MATCH_U32 is not set | |
| +# CONFIG_IP_SET is not set | |
| +CONFIG_IP_VS=m | |
| +# CONFIG_IP_VS_IPV6 is not set | |
| +# CONFIG_IP_VS_DEBUG is not set | |
| +CONFIG_IP_VS_TAB_BITS=12 | |
| + | |
| +# | |
| +# IPVS transport protocol load balancing support | |
| +# | |
| +# CONFIG_IP_VS_PROTO_TCP is not set | |
| +# CONFIG_IP_VS_PROTO_UDP is not set | |
| +# CONFIG_IP_VS_PROTO_AH_ESP is not set | |
| +# CONFIG_IP_VS_PROTO_ESP is not set | |
| +# CONFIG_IP_VS_PROTO_AH is not set | |
| +# CONFIG_IP_VS_PROTO_SCTP is not set | |
| + | |
| +# | |
| +# IPVS scheduler | |
| +# | |
| +# CONFIG_IP_VS_RR is not set | |
| +# CONFIG_IP_VS_WRR is not set | |
| +# CONFIG_IP_VS_LC is not set | |
| +# CONFIG_IP_VS_WLC is not set | |
| +# CONFIG_IP_VS_FO is not set | |
| +# CONFIG_IP_VS_OVF is not set | |
| +# CONFIG_IP_VS_LBLC is not set | |
| +# CONFIG_IP_VS_LBLCR is not set | |
| +# CONFIG_IP_VS_DH is not set | |
| +# CONFIG_IP_VS_SH is not set | |
| +# CONFIG_IP_VS_SED is not set | |
| +# CONFIG_IP_VS_NQ is not set | |
| + | |
| +# | |
| +# IPVS SH scheduler | |
| +# | |
| +CONFIG_IP_VS_SH_TAB_BITS=8 | |
| + | |
| +# | |
| +# IPVS application helper | |
| +# | |
| +# CONFIG_IP_VS_NFCT is not set | |
| + | |
| +# | |
| +# IP: Netfilter Configuration | |
| +# | |
| +CONFIG_NF_DEFRAG_IPV4=m | |
| +CONFIG_NF_CONNTRACK_IPV4=m | |
| +# CONFIG_NF_DUP_IPV4 is not set | |
| +# CONFIG_NF_LOG_ARP is not set | |
| +# CONFIG_NF_LOG_IPV4 is not set | |
| +CONFIG_NF_REJECT_IPV4=y | |
| +CONFIG_NF_NAT_IPV4=m | |
| +CONFIG_NF_NAT_MASQUERADE_IPV4=m | |
| +# CONFIG_NF_NAT_PPTP is not set | |
| +# CONFIG_NF_NAT_H323 is not set | |
| +CONFIG_IP_NF_IPTABLES=y | |
| +# CONFIG_IP_NF_MATCH_AH is not set | |
| +# CONFIG_IP_NF_MATCH_ECN is not set | |
| +# CONFIG_IP_NF_MATCH_TTL is not set | |
| +CONFIG_IP_NF_FILTER=y | |
| +CONFIG_IP_NF_TARGET_REJECT=y | |
| +# CONFIG_IP_NF_TARGET_SYNPROXY is not set | |
| +CONFIG_IP_NF_NAT=m | |
| +CONFIG_IP_NF_TARGET_MASQUERADE=m | |
| +# CONFIG_IP_NF_TARGET_NETMAP is not set | |
| +# CONFIG_IP_NF_TARGET_REDIRECT is not set | |
| +# CONFIG_IP_NF_MANGLE is not set | |
| +# CONFIG_IP_NF_RAW is not set | |
| +# CONFIG_IP_NF_SECURITY is not set | |
| +# CONFIG_IP_NF_ARPTABLES is not set | |
| + | |
| +# | |
| +# IPv6: Netfilter Configuration | |
| +# | |
| +CONFIG_NF_DEFRAG_IPV6=m | |
| +CONFIG_NF_CONNTRACK_IPV6=m | |
| +# CONFIG_NF_DUP_IPV6 is not set | |
| +CONFIG_NF_REJECT_IPV6=y | |
| +# CONFIG_NF_LOG_IPV6 is not set | |
| +CONFIG_NF_NAT_IPV6=m | |
| +CONFIG_NF_NAT_MASQUERADE_IPV6=m | |
| +CONFIG_IP6_NF_IPTABLES=m | |
| +# CONFIG_IP6_NF_MATCH_AH is not set | |
| +# CONFIG_IP6_NF_MATCH_EUI64 is not set | |
| +# CONFIG_IP6_NF_MATCH_FRAG is not set | |
| +# CONFIG_IP6_NF_MATCH_OPTS is not set | |
| +# CONFIG_IP6_NF_MATCH_HL is not set | |
| +# CONFIG_IP6_NF_MATCH_IPV6HEADER is not set | |
| +# CONFIG_IP6_NF_MATCH_MH is not set | |
| +# CONFIG_IP6_NF_MATCH_RT is not set | |
| +CONFIG_IP6_NF_FILTER=m | |
| +CONFIG_IP6_NF_TARGET_REJECT=m | |
| +# CONFIG_IP6_NF_TARGET_SYNPROXY is not set | |
| +# CONFIG_IP6_NF_MANGLE is not set | |
| +# CONFIG_IP6_NF_RAW is not set | |
| +# CONFIG_IP6_NF_SECURITY is not set | |
| +CONFIG_IP6_NF_NAT=m | |
| +CONFIG_IP6_NF_TARGET_MASQUERADE=m | |
| +# CONFIG_IP6_NF_TARGET_NPT is not set | |
| +# CONFIG_BRIDGE_NF_EBTABLES is not set | |
| +# CONFIG_IP_DCCP is not set | |
| +# CONFIG_IP_SCTP is not set | |
| +# CONFIG_RDS is not set | |
| +# CONFIG_TIPC is not set | |
| +# CONFIG_ATM is not set | |
| +# CONFIG_L2TP is not set | |
| +CONFIG_STP=m | |
| +CONFIG_BRIDGE=m | |
| +CONFIG_BRIDGE_IGMP_SNOOPING=y | |
| +CONFIG_BRIDGE_VLAN_FILTERING=y | |
| +CONFIG_HAVE_NET_DSA=y | |
| +# CONFIG_NET_DSA is not set | |
| +CONFIG_VLAN_8021Q=y | |
| +# CONFIG_VLAN_8021Q_GVRP is not set | |
| +# CONFIG_VLAN_8021Q_MVRP is not set | |
| +# CONFIG_DECNET is not set | |
| +CONFIG_LLC=m | |
| +# CONFIG_LLC2 is not set | |
| +# CONFIG_IPX is not set | |
| +# CONFIG_ATALK is not set | |
| +# CONFIG_X25 is not set | |
| +# CONFIG_LAPB is not set | |
| +# CONFIG_PHONET is not set | |
| +# CONFIG_6LOWPAN is not set | |
| +# CONFIG_IEEE802154 is not set | |
| +CONFIG_NET_SCHED=y | |
| + | |
| +# | |
| +# Queueing/Scheduling | |
| +# | |
| +# CONFIG_NET_SCH_CBQ is not set | |
| +# CONFIG_NET_SCH_HTB is not set | |
| +# CONFIG_NET_SCH_HFSC is not set | |
| +# CONFIG_NET_SCH_PRIO is not set | |
| +# CONFIG_NET_SCH_MULTIQ is not set | |
| +# CONFIG_NET_SCH_RED is not set | |
| +# CONFIG_NET_SCH_SFB is not set | |
| +# CONFIG_NET_SCH_SFQ is not set | |
| +# CONFIG_NET_SCH_TEQL is not set | |
| +# CONFIG_NET_SCH_TBF is not set | |
| +# CONFIG_NET_SCH_GRED is not set | |
| +# CONFIG_NET_SCH_DSMARK is not set | |
| +CONFIG_NET_SCH_NETEM=m | |
| +# CONFIG_NET_SCH_DRR is not set | |
| +# CONFIG_NET_SCH_MQPRIO is not set | |
| +# CONFIG_NET_SCH_CHOKE is not set | |
| +# CONFIG_NET_SCH_QFQ is not set | |
| +# CONFIG_NET_SCH_CODEL is not set | |
| +# CONFIG_NET_SCH_FQ_CODEL is not set | |
| +# CONFIG_NET_SCH_FQ is not set | |
| +# CONFIG_NET_SCH_HHF is not set | |
| +# CONFIG_NET_SCH_PIE is not set | |
| +# CONFIG_NET_SCH_PLUG is not set | |
| + | |
| +# | |
| +# Classification | |
| +# | |
| +# CONFIG_NET_CLS_BASIC is not set | |
| +# CONFIG_NET_CLS_TCINDEX is not set | |
| +# CONFIG_NET_CLS_ROUTE4 is not set | |
| +# CONFIG_NET_CLS_FW is not set | |
| +# CONFIG_NET_CLS_U32 is not set | |
| +# CONFIG_NET_CLS_RSVP is not set | |
| +# CONFIG_NET_CLS_RSVP6 is not set | |
| +# CONFIG_NET_CLS_FLOW is not set | |
| +# CONFIG_NET_CLS_CGROUP is not set | |
| +# CONFIG_NET_CLS_BPF is not set | |
| +# CONFIG_NET_CLS_FLOWER is not set | |
| +# CONFIG_NET_EMATCH is not set | |
| +# CONFIG_NET_CLS_ACT is not set | |
| +CONFIG_NET_SCH_FIFO=y | |
| +# CONFIG_DCB is not set | |
| +CONFIG_DNS_RESOLVER=y | |
| +# CONFIG_BATMAN_ADV is not set | |
| +# CONFIG_OPENVSWITCH is not set | |
| +# CONFIG_VSOCKETS is not set | |
| +# CONFIG_NETLINK_DIAG is not set | |
| +# CONFIG_MPLS is not set | |
| +# CONFIG_HSR is not set | |
| +# CONFIG_NET_SWITCHDEV is not set | |
| +# CONFIG_NET_L3_MASTER_DEV is not set | |
| +CONFIG_RPS=y | |
| +CONFIG_RFS_ACCEL=y | |
| +CONFIG_XPS=y | |
| +# CONFIG_CGROUP_NET_PRIO is not set | |
| +# CONFIG_CGROUP_NET_CLASSID is not set | |
| +CONFIG_NET_RX_BUSY_POLL=y | |
| +CONFIG_BQL=y | |
| +# CONFIG_BPF_JIT is not set | |
| +CONFIG_NET_FLOW_LIMIT=y | |
| + | |
| +# | |
| +# Network testing | |
| +# | |
| +# CONFIG_NET_PKTGEN is not set | |
| +# CONFIG_HAMRADIO is not set | |
| +# CONFIG_CAN is not set | |
| +# CONFIG_IRDA is not set | |
| +CONFIG_BT=y | |
| +CONFIG_BT_BREDR=y | |
| +CONFIG_BT_RFCOMM=m | |
| +# CONFIG_BT_RFCOMM_TTY is not set | |
| +CONFIG_BT_BNEP=m | |
| +# CONFIG_BT_BNEP_MC_FILTER is not set | |
| +# CONFIG_BT_BNEP_PROTO_FILTER is not set | |
| +# CONFIG_BT_HIDP is not set | |
| +CONFIG_BT_HS=y | |
| +CONFIG_BT_LE=y | |
| +# CONFIG_BT_SELFTEST is not set | |
| + | |
| +# | |
| +# Bluetooth device drivers | |
| +# | |
| +CONFIG_BT_INTEL=y | |
| +CONFIG_BT_HCIBTUSB=y | |
| +# CONFIG_BT_HCIBTUSB_BCM is not set | |
| +# CONFIG_BT_HCIBTUSB_RTL is not set | |
| +# CONFIG_BT_HCIUART is not set | |
| +# CONFIG_BT_HCIBCM203X is not set | |
| +# CONFIG_BT_HCIBFUSB is not set | |
| +# CONFIG_BT_HCIVHCI is not set | |
| +# CONFIG_BT_MRVL is not set | |
| +# CONFIG_BT_ATH3K is not set | |
| +# CONFIG_AF_RXRPC is not set | |
| +CONFIG_FIB_RULES=y | |
| +# CONFIG_WIRELESS is not set | |
| +# CONFIG_WIMAX is not set | |
| +CONFIG_RFKILL=y | |
| +CONFIG_RFKILL_LEDS=y | |
| +# CONFIG_RFKILL_INPUT is not set | |
| +# CONFIG_RFKILL_GPIO is not set | |
| +# CONFIG_NET_9P is not set | |
| +# CONFIG_CAIF is not set | |
| +# CONFIG_CEPH_LIB is not set | |
| +# CONFIG_NFC is not set | |
| +# CONFIG_LWTUNNEL is not set | |
| +CONFIG_HAVE_BPF_JIT=y | |
| + | |
| +# | |
| +# Device Drivers | |
| +# | |
| +CONFIG_ARM_AMBA=y | |
| +# CONFIG_TEGRA_AHB is not set | |
| + | |
| +# | |
| +# Generic Driver Options | |
| +# | |
| +CONFIG_UEVENT_HELPER=y | |
| +CONFIG_UEVENT_HELPER_PATH="/sbin/mdev" | |
| +CONFIG_DEVTMPFS=y | |
| +# CONFIG_DEVTMPFS_MOUNT is not set | |
| +CONFIG_STANDALONE=y | |
| +CONFIG_PREVENT_FIRMWARE_BUILD=y | |
| +CONFIG_FW_LOADER=y | |
| +# CONFIG_FIRMWARE_IN_KERNEL is not set | |
| +CONFIG_EXTRA_FIRMWARE="" | |
| +# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set | |
| +# CONFIG_ALLOW_DEV_COREDUMP is not set | |
| +# CONFIG_DEBUG_DRIVER is not set | |
| +# CONFIG_DEBUG_DEVRES is not set | |
| +# CONFIG_SYS_HYPERVISOR is not set | |
| +# CONFIG_GENERIC_CPU_DEVICES is not set | |
| +CONFIG_REGMAP=y | |
| +CONFIG_REGMAP_MMIO=y | |
| +# CONFIG_DMA_SHARED_BUFFER is not set | |
| + | |
| +# | |
| +# Bus devices | |
| +# | |
| +# CONFIG_BRCMSTB_GISB_ARB is not set | |
| +CONFIG_VEXPRESS_CONFIG=y | |
| +# CONFIG_CONNECTOR is not set | |
| +CONFIG_MTD=y | |
| +# CONFIG_MTD_TESTS is not set | |
| +# CONFIG_MTD_REDBOOT_PARTS is not set | |
| +CONFIG_MTD_CMDLINE_PARTS=y | |
| +# CONFIG_MTD_AFS_PARTS is not set | |
| +CONFIG_MTD_OF_PARTS=y | |
| +# CONFIG_MTD_AR7_PARTS is not set | |
| + | |
| +# | |
| +# User Modules And Translation Layers | |
| +# | |
| +CONFIG_MTD_BLKDEVS=y | |
| +CONFIG_MTD_BLOCK=y | |
| +# CONFIG_FTL is not set | |
| +# CONFIG_NFTL is not set | |
| +# CONFIG_INFTL is not set | |
| +# CONFIG_RFD_FTL is not set | |
| +# CONFIG_SSFDC is not set | |
| +# CONFIG_SM_FTL is not set | |
| +# CONFIG_MTD_OOPS is not set | |
| +# CONFIG_MTD_SWAP is not set | |
| +# CONFIG_MTD_PARTITIONED_MASTER is not set | |
| + | |
| +# | |
| +# RAM/ROM/Flash chip drivers | |
| +# | |
| +CONFIG_MTD_CFI=y | |
| +CONFIG_MTD_JEDECPROBE=y | |
| +CONFIG_MTD_GEN_PROBE=y | |
| +CONFIG_MTD_CFI_ADV_OPTIONS=y | |
| +CONFIG_MTD_CFI_NOSWAP=y | |
| +# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set | |
| +# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set | |
| +CONFIG_MTD_CFI_GEOMETRY=y | |
| +CONFIG_MTD_MAP_BANK_WIDTH_1=y | |
| +CONFIG_MTD_MAP_BANK_WIDTH_2=y | |
| +# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set | |
| +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set | |
| +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set | |
| +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set | |
| +CONFIG_MTD_CFI_I1=y | |
| +CONFIG_MTD_CFI_I2=y | |
| +# CONFIG_MTD_CFI_I4 is not set | |
| +# CONFIG_MTD_CFI_I8 is not set | |
| +# CONFIG_MTD_OTP is not set | |
| +CONFIG_MTD_CFI_INTELEXT=y | |
| +# CONFIG_MTD_CFI_AMDSTD is not set | |
| +CONFIG_MTD_CFI_STAA=y | |
| +CONFIG_MTD_CFI_UTIL=y | |
| +# CONFIG_MTD_RAM is not set | |
| +# CONFIG_MTD_ROM is not set | |
| +# CONFIG_MTD_ABSENT is not set | |
| + | |
| +# | |
| +# Mapping drivers for chip access | |
| +# | |
| +# CONFIG_MTD_COMPLEX_MAPPINGS is not set | |
| +CONFIG_MTD_PHYSMAP=y | |
| +# CONFIG_MTD_PHYSMAP_COMPAT is not set | |
| +CONFIG_MTD_PHYSMAP_OF=y | |
| +# CONFIG_MTD_IMPA7 is not set | |
| +# CONFIG_MTD_INTEL_VR_NOR is not set | |
| +# CONFIG_MTD_PLATRAM is not set | |
| + | |
| +# | |
| +# Self-contained MTD device drivers | |
| +# | |
| +# CONFIG_MTD_PMC551 is not set | |
| +# CONFIG_MTD_SLRAM is not set | |
| +# CONFIG_MTD_PHRAM is not set | |
| +# CONFIG_MTD_MTDRAM is not set | |
| +# CONFIG_MTD_BLOCK2MTD is not set | |
| + | |
| +# | |
| +# Disk-On-Chip Device Drivers | |
| +# | |
| +# CONFIG_MTD_DOCG3 is not set | |
| +CONFIG_MTD_NAND_ECC=y | |
| +# CONFIG_MTD_NAND_ECC_SMC is not set | |
| +CONFIG_MTD_NAND=y | |
| +# CONFIG_MTD_NAND_ECC_BCH is not set | |
| +# CONFIG_MTD_SM_COMMON is not set | |
| +# CONFIG_MTD_NAND_DENALI_PCI is not set | |
| +# CONFIG_MTD_NAND_DENALI_DT is not set | |
| +# CONFIG_MTD_NAND_GPIO is not set | |
| +# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set | |
| +CONFIG_MTD_NAND_IDS=y | |
| +# CONFIG_MTD_NAND_RICOH is not set | |
| +# CONFIG_MTD_NAND_DISKONCHIP is not set | |
| +# CONFIG_MTD_NAND_DOCG4 is not set | |
| +# CONFIG_MTD_NAND_CAFE is not set | |
| +# CONFIG_MTD_NAND_NANDSIM is not set | |
| +# CONFIG_MTD_NAND_BRCMNAND is not set | |
| +# CONFIG_MTD_NAND_PLATFORM is not set | |
| +# CONFIG_MTD_NAND_HISI504 is not set | |
| +CONFIG_MTD_NAND_AL=y | |
| +# CONFIG_MTD_ONENAND is not set | |
| + | |
| +# | |
| +# LPDDR & LPDDR2 PCM memory drivers | |
| +# | |
| +# CONFIG_MTD_LPDDR is not set | |
| +# CONFIG_MTD_LPDDR2_NVM is not set | |
| +# CONFIG_MTD_SPI_NOR is not set | |
| +CONFIG_MTD_UBI=y | |
| +CONFIG_MTD_UBI_WL_THRESHOLD=4096 | |
| +CONFIG_MTD_UBI_BEB_LIMIT=20 | |
| +# CONFIG_MTD_UBI_FASTMAP is not set | |
| +# CONFIG_MTD_UBI_GLUEBI is not set | |
| +# CONFIG_MTD_UBI_BLOCK is not set | |
| +CONFIG_DTC=y | |
| +CONFIG_OF=y | |
| +# CONFIG_OF_UNITTEST is not set | |
| +CONFIG_OF_FLATTREE=y | |
| +CONFIG_OF_EARLY_FLATTREE=y | |
| +CONFIG_OF_ADDRESS=y | |
| +CONFIG_OF_ADDRESS_PCI=y | |
| +CONFIG_OF_IRQ=y | |
| +CONFIG_OF_NET=y | |
| +CONFIG_OF_MDIO=y | |
| +CONFIG_OF_PCI=y | |
| +CONFIG_OF_PCI_IRQ=y | |
| +CONFIG_OF_MTD=y | |
| +CONFIG_OF_RESERVED_MEM=y | |
| +# CONFIG_OF_OVERLAY is not set | |
| +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y | |
| +# CONFIG_PARPORT is not set | |
| +CONFIG_BLK_DEV=y | |
| +# CONFIG_BLK_DEV_NULL_BLK is not set | |
| +# CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set | |
| +CONFIG_ZRAM=m | |
| +# CONFIG_ZRAM_LZ4_COMPRESS is not set | |
| +# CONFIG_BLK_CPQ_CISS_DA is not set | |
| +# CONFIG_BLK_DEV_DAC960 is not set | |
| +# CONFIG_BLK_DEV_UMEM is not set | |
| +# CONFIG_BLK_DEV_COW_COMMON is not set | |
| +CONFIG_BLK_DEV_LOOP=y | |
| +CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 | |
| +CONFIG_BLK_DEV_CRYPTOLOOP=y | |
| +# CONFIG_BLK_DEV_DRBD is not set | |
| +# CONFIG_BLK_DEV_NBD is not set | |
| +# CONFIG_BLK_DEV_SX8 is not set | |
| +# CONFIG_BLK_DEV_RAM is not set | |
| +# CONFIG_CDROM_PKTCDVD is not set | |
| +# CONFIG_ATA_OVER_ETH is not set | |
| +# CONFIG_MG_DISK is not set | |
| +# CONFIG_BLK_DEV_RBD is not set | |
| +# CONFIG_BLK_DEV_RSXX is not set | |
| +# CONFIG_BLK_DEV_NVME is not set | |
| + | |
| +# | |
| +# Misc devices | |
| +# | |
| +# CONFIG_SENSORS_LIS3LV02D is not set | |
| +# CONFIG_AD525X_DPOT is not set | |
| +# CONFIG_DUMMY_IRQ is not set | |
| +# CONFIG_PHANTOM is not set | |
| +# CONFIG_SGI_IOC4 is not set | |
| +# CONFIG_TIFM_CORE is not set | |
| +# CONFIG_ICS932S401 is not set | |
| +# CONFIG_ENCLOSURE_SERVICES is not set | |
| +# CONFIG_HP_ILO is not set | |
| +# CONFIG_APDS9802ALS is not set | |
| +# CONFIG_ISL29003 is not set | |
| +# CONFIG_ISL29020 is not set | |
| +# CONFIG_SENSORS_TSL2550 is not set | |
| +# CONFIG_SENSORS_BH1780 is not set | |
| +# CONFIG_SENSORS_BH1770 is not set | |
| +# CONFIG_SENSORS_APDS990X is not set | |
| +# CONFIG_HMC6352 is not set | |
| +# CONFIG_DS1682 is not set | |
| +# CONFIG_BMP085_I2C is not set | |
| +# CONFIG_USB_SWITCH_FSA9480 is not set | |
| +# CONFIG_SRAM is not set | |
| +CONFIG_VEXPRESS_SYSCFG=y | |
| +# CONFIG_C2PORT is not set | |
| + | |
| +# | |
| +# EEPROM support | |
| +# | |
| +# CONFIG_EEPROM_AT24 is not set | |
| +# CONFIG_EEPROM_LEGACY is not set | |
| +# CONFIG_EEPROM_MAX6875 is not set | |
| +# CONFIG_EEPROM_93CX6 is not set | |
| +# CONFIG_CB710_CORE is not set | |
| + | |
| +# | |
| +# Texas Instruments shared transport line discipline | |
| +# | |
| +# CONFIG_TI_ST is not set | |
| +# CONFIG_SENSORS_LIS3_I2C is not set | |
| + | |
| +# | |
| +# Altera FPGA firmware download module | |
| +# | |
| +# CONFIG_ALTERA_STAPL is not set | |
| + | |
| +# | |
| +# Intel MIC Bus Driver | |
| +# | |
| + | |
| +# | |
| +# SCIF Bus Driver | |
| +# | |
| + | |
| +# | |
| +# Intel MIC Host Driver | |
| +# | |
| + | |
| +# | |
| +# Intel MIC Card Driver | |
| +# | |
| + | |
| +# | |
| +# SCIF Driver | |
| +# | |
| + | |
| +# | |
| +# Intel MIC Coprocessor State Management (COSM) Drivers | |
| +# | |
| +# CONFIG_ECHO is not set | |
| +# CONFIG_CXL_BASE is not set | |
| +# CONFIG_CXL_KERNEL_API is not set | |
| +# CONFIG_CXL_EEH is not set | |
| +CONFIG_HAVE_IDE=y | |
| +# CONFIG_IDE is not set | |
| + | |
| +# | |
| +# SCSI device support | |
| +# | |
| +CONFIG_SCSI_MOD=y | |
| +# CONFIG_RAID_ATTRS is not set | |
| +CONFIG_SCSI=y | |
| +CONFIG_SCSI_DMA=y | |
| +# CONFIG_SCSI_NETLINK is not set | |
| +# CONFIG_SCSI_MQ_DEFAULT is not set | |
| +# CONFIG_SCSI_PROC_FS is not set | |
| + | |
| +# | |
| +# SCSI support type (disk, tape, CD-ROM) | |
| +# | |
| +CONFIG_BLK_DEV_SD=y | |
| +# CONFIG_CHR_DEV_ST is not set | |
| +# CONFIG_CHR_DEV_OSST is not set | |
| +# CONFIG_BLK_DEV_SR is not set | |
| +# CONFIG_CHR_DEV_SG is not set | |
| +# CONFIG_CHR_DEV_SCH is not set | |
| +# CONFIG_SCSI_CONSTANTS is not set | |
| +# CONFIG_SCSI_LOGGING is not set | |
| +# CONFIG_SCSI_SCAN_ASYNC is not set | |
| +CONFIG_MV_STAGGERED_SPINUP=y | |
| + | |
| +# | |
| +# SCSI Transports | |
| +# | |
| +# CONFIG_SCSI_SPI_ATTRS is not set | |
| +# CONFIG_SCSI_FC_ATTRS is not set | |
| +CONFIG_SCSI_ISCSI_ATTRS=m | |
| +# CONFIG_SCSI_SAS_ATTRS is not set | |
| +# CONFIG_SCSI_SAS_LIBSAS is not set | |
| +# CONFIG_SCSI_SRP_ATTRS is not set | |
| +CONFIG_SCSI_LOWLEVEL=y | |
| +CONFIG_ISCSI_TCP=m | |
| +# CONFIG_ISCSI_BOOT_SYSFS is not set | |
| +# CONFIG_SCSI_CXGB3_ISCSI is not set | |
| +# CONFIG_SCSI_CXGB4_ISCSI is not set | |
| +# CONFIG_SCSI_BNX2_ISCSI is not set | |
| +# CONFIG_BE2ISCSI is not set | |
| +# CONFIG_BLK_DEV_3W_XXXX_RAID is not set | |
| +# CONFIG_SCSI_HPSA is not set | |
| +# CONFIG_SCSI_3W_9XXX is not set | |
| +# CONFIG_SCSI_3W_SAS is not set | |
| +# CONFIG_SCSI_ACARD is not set | |
| +# CONFIG_SCSI_AACRAID is not set | |
| +# CONFIG_SCSI_AIC7XXX is not set | |
| +# CONFIG_SCSI_AIC79XX is not set | |
| +# CONFIG_SCSI_AIC94XX is not set | |
| +# CONFIG_SCSI_MVSAS is not set | |
| +# CONFIG_SCSI_MVUMI is not set | |
| +# CONFIG_SCSI_ADVANSYS is not set | |
| +# CONFIG_SCSI_ARCMSR is not set | |
| +# CONFIG_SCSI_ESAS2R is not set | |
| +# CONFIG_MEGARAID_NEWGEN is not set | |
| +# CONFIG_MEGARAID_LEGACY is not set | |
| +# CONFIG_MEGARAID_SAS is not set | |
| +# CONFIG_SCSI_MPT3SAS is not set | |
| +# CONFIG_SCSI_MPT2SAS is not set | |
| +# CONFIG_SCSI_UFSHCD is not set | |
| +# CONFIG_SCSI_HPTIOP is not set | |
| +# CONFIG_SCSI_SNIC is not set | |
| +# CONFIG_SCSI_DMX3191D is not set | |
| +# CONFIG_SCSI_FUTURE_DOMAIN is not set | |
| +# CONFIG_SCSI_IPS is not set | |
| +# CONFIG_SCSI_INITIO is not set | |
| +# CONFIG_SCSI_INIA100 is not set | |
| +# CONFIG_SCSI_STEX is not set | |
| +# CONFIG_SCSI_SYM53C8XX_2 is not set | |
| +# CONFIG_SCSI_IPR is not set | |
| +# CONFIG_SCSI_QLOGIC_1280 is not set | |
| +# CONFIG_SCSI_QLA_ISCSI is not set | |
| +# CONFIG_SCSI_DC395x is not set | |
| +# CONFIG_SCSI_AM53C974 is not set | |
| +# CONFIG_SCSI_NSP32 is not set | |
| +# CONFIG_SCSI_WD719X is not set | |
| +# CONFIG_SCSI_DEBUG is not set | |
| +# CONFIG_SCSI_PMCRAID is not set | |
| +# CONFIG_SCSI_PM8001 is not set | |
| +CONFIG_SCSI_DH=y | |
| +# CONFIG_SCSI_DH_RDAC is not set | |
| +# CONFIG_SCSI_DH_HP_SW is not set | |
| +# CONFIG_SCSI_DH_EMC is not set | |
| +# CONFIG_SCSI_DH_ALUA is not set | |
| +# CONFIG_SCSI_OSD_INITIATOR is not set | |
| +CONFIG_ATA=y | |
| +# CONFIG_ATA_NONSTANDARD is not set | |
| +CONFIG_ATA_VERBOSE_ERROR=y | |
| +CONFIG_SATA_PMP=y | |
| + | |
| +# | |
| +# Controllers with non-SFF native interface | |
| +# | |
| +CONFIG_SATA_AHCI=y | |
| +CONFIG_SATA_AHCI_PLATFORM=y | |
| +# CONFIG_AHCI_CEVA is not set | |
| +CONFIG_AHCI_ALPINE=y | |
| +# CONFIG_AHCI_QORIQ is not set | |
| +# CONFIG_SATA_INIC162X is not set | |
| +# CONFIG_SATA_ACARD_AHCI is not set | |
| +# CONFIG_SATA_SIL24 is not set | |
| +CONFIG_ATA_SFF=y | |
| + | |
| +# | |
| +# SFF controllers with custom DMA interface | |
| +# | |
| +# CONFIG_PDC_ADMA is not set | |
| +# CONFIG_SATA_QSTOR is not set | |
| +# CONFIG_SATA_SX4 is not set | |
| +CONFIG_ATA_BMDMA=y | |
| + | |
| +# | |
| +# SATA SFF controllers with BMDMA | |
| +# | |
| +# CONFIG_ATA_PIIX is not set | |
| +# CONFIG_SATA_MV is not set | |
| +# CONFIG_SATA_NV is not set | |
| +# CONFIG_SATA_PROMISE is not set | |
| +# CONFIG_SATA_SIL is not set | |
| +# CONFIG_SATA_SIS is not set | |
| +# CONFIG_SATA_SVW is not set | |
| +# CONFIG_SATA_ULI is not set | |
| +# CONFIG_SATA_VIA is not set | |
| +# CONFIG_SATA_VITESSE is not set | |
| + | |
| +# | |
| +# PATA SFF controllers with BMDMA | |
| +# | |
| +# CONFIG_PATA_ALI is not set | |
| +# CONFIG_PATA_AMD is not set | |
| +# CONFIG_PATA_ARTOP is not set | |
| +# CONFIG_PATA_ATIIXP is not set | |
| +# CONFIG_PATA_ATP867X is not set | |
| +# CONFIG_PATA_CMD64X is not set | |
| +# CONFIG_PATA_CYPRESS is not set | |
| +# CONFIG_PATA_EFAR is not set | |
| +# CONFIG_PATA_HPT366 is not set | |
| +# CONFIG_PATA_HPT37X is not set | |
| +# CONFIG_PATA_HPT3X2N is not set | |
| +# CONFIG_PATA_HPT3X3 is not set | |
| +# CONFIG_PATA_IT8213 is not set | |
| +# CONFIG_PATA_IT821X is not set | |
| +# CONFIG_PATA_JMICRON is not set | |
| +# CONFIG_PATA_MARVELL is not set | |
| +# CONFIG_PATA_NETCELL is not set | |
| +# CONFIG_PATA_NINJA32 is not set | |
| +# CONFIG_PATA_NS87415 is not set | |
| +# CONFIG_PATA_OLDPIIX is not set | |
| +# CONFIG_PATA_OPTIDMA is not set | |
| +# CONFIG_PATA_PDC2027X is not set | |
| +# CONFIG_PATA_PDC_OLD is not set | |
| +# CONFIG_PATA_RADISYS is not set | |
| +# CONFIG_PATA_RDC is not set | |
| +# CONFIG_PATA_SCH is not set | |
| +# CONFIG_PATA_SERVERWORKS is not set | |
| +# CONFIG_PATA_SIL680 is not set | |
| +# CONFIG_PATA_SIS is not set | |
| +# CONFIG_PATA_TOSHIBA is not set | |
| +# CONFIG_PATA_TRIFLEX is not set | |
| +# CONFIG_PATA_VIA is not set | |
| +# CONFIG_PATA_WINBOND is not set | |
| + | |
| +# | |
| +# PIO-only SFF controllers | |
| +# | |
| +# CONFIG_PATA_CMD640_PCI is not set | |
| +# CONFIG_PATA_MPIIX is not set | |
| +# CONFIG_PATA_NS87410 is not set | |
| +# CONFIG_PATA_OPTI is not set | |
| +# CONFIG_PATA_PLATFORM is not set | |
| +# CONFIG_PATA_RZ1000 is not set | |
| + | |
| +# | |
| +# Generic fallback / legacy drivers | |
| +# | |
| +# CONFIG_ATA_GENERIC is not set | |
| +# CONFIG_PATA_LEGACY is not set | |
| +CONFIG_MD=y | |
| +CONFIG_BLK_DEV_MD=y | |
| +# CONFIG_MD_AUTODETECT is not set | |
| +# CONFIG_MD_LINEAR is not set | |
| +CONFIG_MD_RAID0=y | |
| +CONFIG_MD_RAID1=y | |
| +CONFIG_MD_RAID10=y | |
| +CONFIG_MD_RAID456=y | |
| +# CONFIG_MD_MULTIPATH is not set | |
| +# CONFIG_MD_FAULTY is not set | |
| +# CONFIG_BCACHE is not set | |
| +CONFIG_BLK_DEV_DM_BUILTIN=y | |
| +CONFIG_BLK_DEV_DM=y | |
| +# CONFIG_DM_MQ_DEFAULT is not set | |
| +# CONFIG_DM_DEBUG is not set | |
| +CONFIG_DM_BUFIO=y | |
| +CONFIG_DM_BIO_PRISON=m | |
| +CONFIG_DM_PERSISTENT_DATA=m | |
| +# CONFIG_DM_DEBUG_BLOCK_STACK_TRACING is not set | |
| +CONFIG_DM_CRYPT=y | |
| +CONFIG_DM_SNAPSHOT=y | |
| +CONFIG_DM_THIN_PROVISIONING=m | |
| +# CONFIG_DM_CACHE is not set | |
| +# CONFIG_DM_ERA is not set | |
| +# CONFIG_DM_MIRROR is not set | |
| +# CONFIG_DM_RAID is not set | |
| +# CONFIG_DM_ZERO is not set | |
| +# CONFIG_DM_MULTIPATH is not set | |
| +# CONFIG_DM_DELAY is not set | |
| +# CONFIG_DM_UEVENT is not set | |
| +# CONFIG_DM_FLAKEY is not set | |
| +# CONFIG_DM_VERITY is not set | |
| +# CONFIG_DM_SWITCH is not set | |
| +# CONFIG_DM_LOG_WRITES is not set | |
| +CONFIG_TARGET_CORE=y | |
| +# CONFIG_TCM_IBLOCK is not set | |
| +CONFIG_TCM_FILEIO=y | |
| +# CONFIG_TCM_PSCSI is not set | |
| +# CONFIG_LOOPBACK_TARGET is not set | |
| +CONFIG_ISCSI_TARGET=y | |
| +# CONFIG_FUSION is not set | |
| + | |
| +# | |
| +# IEEE 1394 (FireWire) support | |
| +# | |
| +# CONFIG_FIREWIRE is not set | |
| +# CONFIG_FIREWIRE_NOSY is not set | |
| +CONFIG_NETDEVICES=y | |
| +CONFIG_NET_CORE=y | |
| +CONFIG_BONDING=y | |
| +CONFIG_DUMMY=m | |
| +# CONFIG_EQUALIZER is not set | |
| +# CONFIG_NET_FC is not set | |
| +# CONFIG_NET_TEAM is not set | |
| +CONFIG_MACVLAN=m | |
| +# CONFIG_MACVTAP is not set | |
| +CONFIG_IPVLAN=m | |
| +CONFIG_VXLAN=m | |
| +CONFIG_GENEVE=m | |
| +CONFIG_NETCONSOLE=m | |
| +# CONFIG_NETCONSOLE_DYNAMIC is not set | |
| +CONFIG_NETPOLL=y | |
| +CONFIG_NET_POLL_CONTROLLER=y | |
| +CONFIG_TUN=y | |
| +# CONFIG_TUN_VNET_CROSS_LE is not set | |
| +CONFIG_VETH=m | |
| +# CONFIG_NLMON is not set | |
| +# CONFIG_ARCNET is not set | |
| + | |
| +# | |
| +# CAIF transport drivers | |
| +# | |
| + | |
| +# | |
| +# Distributed Switch Architecture drivers | |
| +# | |
| +# CONFIG_NET_DSA_MV88E6XXX is not set | |
| +# CONFIG_NET_DSA_MV88E6XXX_NEED_PPU is not set | |
| +CONFIG_ETHERNET=y | |
| +# CONFIG_NET_VENDOR_3COM is not set | |
| +# CONFIG_NET_VENDOR_ADAPTEC is not set | |
| +# CONFIG_NET_VENDOR_AGERE is not set | |
| +# CONFIG_NET_VENDOR_ALTEON is not set | |
| +# CONFIG_ALTERA_TSE is not set | |
| +CONFIG_NET_AL_ETH=y | |
| +CONFIG_AL_ETH_ALLOC_FRAG=y | |
| +# CONFIG_AL_ETH_ALLOC_PAGE is not set | |
| +# CONFIG_AL_ETH_ALLOC_SKB is not set | |
| +# CONFIG_NET_VENDOR_AMD is not set | |
| +# CONFIG_NET_VENDOR_ARC is not set | |
| +# CONFIG_NET_VENDOR_ATHEROS is not set | |
| +# CONFIG_NET_VENDOR_AURORA is not set | |
| +# CONFIG_NET_CADENCE is not set | |
| +# CONFIG_NET_VENDOR_BROADCOM is not set | |
| +# CONFIG_NET_VENDOR_BROCADE is not set | |
| +# CONFIG_NET_VENDOR_CAVIUM is not set | |
| +# CONFIG_NET_VENDOR_CHELSIO is not set | |
| +# CONFIG_NET_VENDOR_CIRRUS is not set | |
| +# CONFIG_NET_VENDOR_CISCO is not set | |
| +# CONFIG_DM9000 is not set | |
| +# CONFIG_DNET is not set | |
| +# CONFIG_NET_VENDOR_DEC is not set | |
| +# CONFIG_NET_VENDOR_DLINK is not set | |
| +# CONFIG_NET_VENDOR_EMULEX is not set | |
| +# CONFIG_NET_VENDOR_EZCHIP is not set | |
| +# CONFIG_NET_VENDOR_EXAR is not set | |
| +# CONFIG_NET_VENDOR_FARADAY is not set | |
| +# CONFIG_NET_VENDOR_HISILICON is not set | |
| +# CONFIG_NET_VENDOR_HP is not set | |
| +# CONFIG_NET_VENDOR_INTEL is not set | |
| +# CONFIG_JME is not set | |
| +# CONFIG_NET_VENDOR_MARVELL is not set | |
| +# CONFIG_NET_VENDOR_MELLANOX is not set | |
| +# CONFIG_NET_VENDOR_MICREL is not set | |
| +# CONFIG_NET_VENDOR_MYRI is not set | |
| +# CONFIG_FEALNX is not set | |
| +# CONFIG_NET_VENDOR_NATSEMI is not set | |
| +# CONFIG_NET_VENDOR_NVIDIA is not set | |
| +# CONFIG_NET_VENDOR_OKI is not set | |
| +# CONFIG_ETHOC is not set | |
| +# CONFIG_NET_PACKET_ENGINE is not set | |
| +# CONFIG_NET_VENDOR_QLOGIC is not set | |
| +# CONFIG_NET_VENDOR_QUALCOMM is not set | |
| +# CONFIG_NET_VENDOR_REALTEK is not set | |
| +# CONFIG_NET_VENDOR_RENESAS is not set | |
| +# CONFIG_NET_VENDOR_RDC is not set | |
| +# CONFIG_NET_VENDOR_ROCKER is not set | |
| +# CONFIG_NET_VENDOR_SAMSUNG is not set | |
| +# CONFIG_NET_VENDOR_SEEQ is not set | |
| +# CONFIG_NET_VENDOR_SILAN is not set | |
| +# CONFIG_NET_VENDOR_SIS is not set | |
| +# CONFIG_SFC is not set | |
| +# CONFIG_NET_VENDOR_SMSC is not set | |
| +# CONFIG_NET_VENDOR_STMICRO is not set | |
| +# CONFIG_NET_VENDOR_SUN is not set | |
| +# CONFIG_NET_VENDOR_SYNOPSYS is not set | |
| +# CONFIG_NET_VENDOR_TEHUTI is not set | |
| +# CONFIG_NET_VENDOR_TI is not set | |
| +# CONFIG_NET_VENDOR_VIA is not set | |
| +# CONFIG_NET_VENDOR_WIZNET is not set | |
| +# CONFIG_FDDI is not set | |
| +# CONFIG_HIPPI is not set | |
| +CONFIG_PHYLIB=y | |
| + | |
| +# | |
| +# MII PHY device drivers | |
| +# | |
| +# CONFIG_AQUANTIA_PHY is not set | |
| +CONFIG_AT803X_PHY=y | |
| +# CONFIG_AMD_PHY is not set | |
| +# CONFIG_MARVELL_PHY is not set | |
| +# CONFIG_DAVICOM_PHY is not set | |
| +# CONFIG_QSEMI_PHY is not set | |
| +# CONFIG_LXT_PHY is not set | |
| +# CONFIG_CICADA_PHY is not set | |
| +# CONFIG_VITESSE_PHY is not set | |
| +# CONFIG_TERANETICS_PHY is not set | |
| +# CONFIG_SMSC_PHY is not set | |
| +# CONFIG_BROADCOM_PHY is not set | |
| +# CONFIG_BCM7XXX_PHY is not set | |
| +# CONFIG_BCM87XX_PHY is not set | |
| +# CONFIG_ICPLUS_PHY is not set | |
| +# CONFIG_REALTEK_PHY is not set | |
| +# CONFIG_NATIONAL_PHY is not set | |
| +# CONFIG_STE10XP is not set | |
| +# CONFIG_LSI_ET1011C_PHY is not set | |
| +# CONFIG_MICREL_PHY is not set | |
| +# CONFIG_DP83848_PHY is not set | |
| +# CONFIG_DP83867_PHY is not set | |
| +# CONFIG_MICROCHIP_PHY is not set | |
| +# CONFIG_FIXED_PHY is not set | |
| +# CONFIG_MDIO_BITBANG is not set | |
| +# CONFIG_MDIO_BUS_MUX_GPIO is not set | |
| +# CONFIG_MDIO_BUS_MUX_MMIOREG is not set | |
| +# CONFIG_MDIO_BCM_UNIMAC is not set | |
| +# CONFIG_PPP is not set | |
| +# CONFIG_SLIP is not set | |
| +# CONFIG_USB_NET_DRIVERS is not set | |
| +# CONFIG_WLAN is not set | |
| + | |
| +# | |
| +# Enable WiMAX (Networking options) to see the WiMAX drivers | |
| +# | |
| +# CONFIG_WAN is not set | |
| +# CONFIG_VMXNET3 is not set | |
| +# CONFIG_ISDN is not set | |
| +# CONFIG_NVM is not set | |
| + | |
| +# | |
| +# Input device support | |
| +# | |
| +CONFIG_INPUT=y | |
| +# CONFIG_INPUT_LEDS is not set | |
| +# CONFIG_INPUT_FF_MEMLESS is not set | |
| +# CONFIG_INPUT_POLLDEV is not set | |
| +# CONFIG_INPUT_SPARSEKMAP is not set | |
| +# CONFIG_INPUT_MATRIXKMAP is not set | |
| + | |
| +# | |
| +# Userland interfaces | |
| +# | |
| +# CONFIG_INPUT_MOUSEDEV is not set | |
| +# CONFIG_INPUT_JOYDEV is not set | |
| +CONFIG_INPUT_EVDEV=y | |
| +# CONFIG_INPUT_EVBUG is not set | |
| + | |
| +# | |
| +# Input Device Drivers | |
| +# | |
| +CONFIG_INPUT_KEYBOARD=y | |
| +# CONFIG_KEYBOARD_ADP5588 is not set | |
| +# CONFIG_KEYBOARD_ADP5589 is not set | |
| +# CONFIG_KEYBOARD_ATKBD is not set | |
| +# CONFIG_KEYBOARD_QT1070 is not set | |
| +# CONFIG_KEYBOARD_QT2160 is not set | |
| +# CONFIG_KEYBOARD_LKKBD is not set | |
| +CONFIG_KEYBOARD_GPIO=y | |
| +# CONFIG_KEYBOARD_GPIO_POLLED is not set | |
| +# CONFIG_KEYBOARD_TCA6416 is not set | |
| +# CONFIG_KEYBOARD_TCA8418 is not set | |
| +# CONFIG_KEYBOARD_MATRIX is not set | |
| +# CONFIG_KEYBOARD_LM8323 is not set | |
| +# CONFIG_KEYBOARD_LM8333 is not set | |
| +# CONFIG_KEYBOARD_MAX7359 is not set | |
| +# CONFIG_KEYBOARD_MCS is not set | |
| +# CONFIG_KEYBOARD_MPR121 is not set | |
| +# CONFIG_KEYBOARD_NEWTON is not set | |
| +# CONFIG_KEYBOARD_OPENCORES is not set | |
| +# CONFIG_KEYBOARD_SAMSUNG is not set | |
| +# CONFIG_KEYBOARD_STOWAWAY is not set | |
| +# CONFIG_KEYBOARD_SUNKBD is not set | |
| +# CONFIG_KEYBOARD_OMAP4 is not set | |
| +# CONFIG_KEYBOARD_XTKBD is not set | |
| +# CONFIG_KEYBOARD_CAP11XX is not set | |
| +# CONFIG_KEYBOARD_BCM is not set | |
| +# CONFIG_INPUT_MOUSE is not set | |
| +# CONFIG_INPUT_JOYSTICK is not set | |
| +# CONFIG_INPUT_TABLET is not set | |
| +# CONFIG_INPUT_TOUCHSCREEN is not set | |
| +# CONFIG_INPUT_MISC is not set | |
| + | |
| +# | |
| +# Hardware I/O ports | |
| +# | |
| +CONFIG_SERIO=y | |
| +# CONFIG_SERIO_SERPORT is not set | |
| +# CONFIG_SERIO_AMBAKMI is not set | |
| +# CONFIG_SERIO_PCIPS2 is not set | |
| +CONFIG_SERIO_LIBPS2=y | |
| +# CONFIG_SERIO_RAW is not set | |
| +# CONFIG_SERIO_ALTERA_PS2 is not set | |
| +# CONFIG_SERIO_PS2MULT is not set | |
| +# CONFIG_SERIO_ARC_PS2 is not set | |
| +# CONFIG_SERIO_APBPS2 is not set | |
| +# CONFIG_USERIO is not set | |
| +# CONFIG_GAMEPORT is not set | |
| + | |
| +# | |
| +# Character devices | |
| +# | |
| +CONFIG_TTY=y | |
| +# CONFIG_VT is not set | |
| +CONFIG_UNIX98_PTYS=y | |
| +CONFIG_DEVPTS_MULTIPLE_INSTANCES=y | |
| +# CONFIG_LEGACY_PTYS is not set | |
| +# CONFIG_SERIAL_NONSTANDARD is not set | |
| +# CONFIG_NOZOMI is not set | |
| +# CONFIG_N_GSM is not set | |
| +# CONFIG_TRACE_SINK is not set | |
| +CONFIG_DEVMEM=y | |
| +# CONFIG_DEVKMEM is not set | |
| + | |
| +# | |
| +# Serial drivers | |
| +# | |
| +CONFIG_SERIAL_EARLYCON=y | |
| +CONFIG_SERIAL_8250=y | |
| +CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y | |
| +CONFIG_SERIAL_8250_CONSOLE=y | |
| +CONFIG_SERIAL_8250_DMA=y | |
| +# CONFIG_SERIAL_8250_PCI is not set | |
| +CONFIG_SERIAL_8250_NR_UARTS=4 | |
| +CONFIG_SERIAL_8250_RUNTIME_UARTS=2 | |
| +# CONFIG_SERIAL_8250_EXTENDED is not set | |
| +CONFIG_SERIAL_8250_FSL=y | |
| +CONFIG_SERIAL_8250_DW=y | |
| +# CONFIG_SERIAL_8250_EM is not set | |
| +# CONFIG_SERIAL_8250_RT288X is not set | |
| +# CONFIG_SERIAL_8250_INGENIC is not set | |
| +# CONFIG_SERIAL_8250_MID is not set | |
| + | |
| +# | |
| +# Non-8250 serial port support | |
| +# | |
| +# CONFIG_SERIAL_AMBA_PL010 is not set | |
| +CONFIG_SERIAL_AMBA_PL011=y | |
| +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y | |
| +# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set | |
| +# CONFIG_SERIAL_UARTLITE is not set | |
| +CONFIG_SERIAL_CORE=y | |
| +CONFIG_SERIAL_CORE_CONSOLE=y | |
| +# CONFIG_SERIAL_JSM is not set | |
| +CONFIG_SERIAL_OF_PLATFORM=y | |
| +# CONFIG_SERIAL_SCCNXP is not set | |
| +# CONFIG_SERIAL_SC16IS7XX is not set | |
| +# CONFIG_SERIAL_BCM63XX is not set | |
| +# CONFIG_SERIAL_ALTERA_JTAGUART is not set | |
| +# CONFIG_SERIAL_ALTERA_UART is not set | |
| +# CONFIG_SERIAL_XILINX_PS_UART is not set | |
| +# CONFIG_SERIAL_ARC is not set | |
| +# CONFIG_SERIAL_RP2 is not set | |
| +# CONFIG_SERIAL_FSL_LPUART is not set | |
| +# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set | |
| +# CONFIG_SERIAL_ST_ASC is not set | |
| +# CONFIG_SERIAL_STM32 is not set | |
| +# CONFIG_TTY_PRINTK is not set | |
| +# CONFIG_HVC_DCC is not set | |
| +# CONFIG_IPMI_HANDLER is not set | |
| +# CONFIG_HW_RANDOM is not set | |
| +# CONFIG_R3964 is not set | |
| +# CONFIG_APPLICOM is not set | |
| +# CONFIG_RAW_DRIVER is not set | |
| +# CONFIG_TCG_TPM is not set | |
| +CONFIG_DEVPORT=y | |
| +# CONFIG_XILLYBUS is not set | |
| + | |
| +# | |
| +# I2C support | |
| +# | |
| +CONFIG_I2C=y | |
| +CONFIG_I2C_BOARDINFO=y | |
| +CONFIG_I2C_COMPAT=y | |
| +CONFIG_I2C_CHARDEV=y | |
| +# CONFIG_I2C_MUX is not set | |
| +CONFIG_I2C_HELPER_AUTO=y | |
| + | |
| +# | |
| +# I2C Hardware Bus support | |
| +# | |
| + | |
| +# | |
| +# PC SMBus host controller drivers | |
| +# | |
| +# CONFIG_I2C_ALI1535 is not set | |
| +# CONFIG_I2C_ALI1563 is not set | |
| +# CONFIG_I2C_ALI15X3 is not set | |
| +# CONFIG_I2C_AMD756 is not set | |
| +# CONFIG_I2C_AMD8111 is not set | |
| +# CONFIG_I2C_I801 is not set | |
| +# CONFIG_I2C_ISCH is not set | |
| +# CONFIG_I2C_PIIX4 is not set | |
| +# CONFIG_I2C_NFORCE2 is not set | |
| +# CONFIG_I2C_SIS5595 is not set | |
| +# CONFIG_I2C_SIS630 is not set | |
| +# CONFIG_I2C_SIS96X is not set | |
| +# CONFIG_I2C_VIA is not set | |
| +# CONFIG_I2C_VIAPRO is not set | |
| + | |
| +# | |
| +# I2C system bus drivers (mostly embedded / system-on-chip) | |
| +# | |
| +# CONFIG_I2C_CBUS_GPIO is not set | |
| +CONFIG_I2C_DESIGNWARE_CORE=y | |
| +CONFIG_I2C_DESIGNWARE_PLATFORM=y | |
| +# CONFIG_I2C_DESIGNWARE_PCI is not set | |
| +# CONFIG_I2C_EMEV2 is not set | |
| +# CONFIG_I2C_GPIO is not set | |
| +# CONFIG_I2C_NOMADIK is not set | |
| +# CONFIG_I2C_OCORES is not set | |
| +# CONFIG_I2C_PCA_PLATFORM is not set | |
| +# CONFIG_I2C_PXA_PCI is not set | |
| +# CONFIG_I2C_RK3X is not set | |
| +# CONFIG_I2C_SIMTEC is not set | |
| +# CONFIG_I2C_XILINX is not set | |
| + | |
| +# | |
| +# External I2C/SMBus adapter drivers | |
| +# | |
| +# CONFIG_I2C_DIOLAN_U2C is not set | |
| +# CONFIG_I2C_PARPORT_LIGHT is not set | |
| +# CONFIG_I2C_ROBOTFUZZ_OSIF is not set | |
| +# CONFIG_I2C_TAOS_EVM is not set | |
| +# CONFIG_I2C_TINY_USB is not set | |
| + | |
| +# | |
| +# Other I2C/SMBus bus drivers | |
| +# | |
| +# CONFIG_I2C_STUB is not set | |
| +# CONFIG_I2C_SLAVE is not set | |
| +# CONFIG_I2C_DEBUG_CORE is not set | |
| +# CONFIG_I2C_DEBUG_ALGO is not set | |
| +# CONFIG_I2C_DEBUG_BUS is not set | |
| +# CONFIG_SPI is not set | |
| +# CONFIG_SPMI is not set | |
| +# CONFIG_HSI is not set | |
| + | |
| +# | |
| +# PPS support | |
| +# | |
| +# CONFIG_PPS is not set | |
| + | |
| +# | |
| +# PPS generators support | |
| +# | |
| + | |
| +# | |
| +# PTP clock support | |
| +# | |
| +# CONFIG_PTP_1588_CLOCK is not set | |
| + | |
| +# | |
| +# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. | |
| +# | |
| +CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y | |
| +CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y | |
| +CONFIG_GPIOLIB=y | |
| +CONFIG_GPIO_DEVRES=y | |
| +CONFIG_OF_GPIO=y | |
| +CONFIG_GPIOLIB_IRQCHIP=y | |
| +# CONFIG_DEBUG_GPIO is not set | |
| +CONFIG_GPIO_SYSFS=y | |
| +CONFIG_GPIO_GENERIC=y | |
| + | |
| +# | |
| +# Memory mapped GPIO drivers | |
| +# | |
| +# CONFIG_GPIO_74XX_MMIO is not set | |
| +# CONFIG_GPIO_ALTERA is not set | |
| +# CONFIG_GPIO_DWAPB is not set | |
| +# CONFIG_GPIO_EM is not set | |
| +CONFIG_GPIO_GENERIC_PLATFORM=y | |
| +# CONFIG_GPIO_GRGPIO is not set | |
| +CONFIG_GPIO_PL061=y | |
| +# CONFIG_GPIO_SYSCON is not set | |
| +# CONFIG_GPIO_VX855 is not set | |
| +# CONFIG_GPIO_XILINX is not set | |
| +# CONFIG_GPIO_ZEVIO is not set | |
| +# CONFIG_GPIO_ZX is not set | |
| + | |
| +# | |
| +# I2C GPIO expanders | |
| +# | |
| +# CONFIG_GPIO_ADP5588 is not set | |
| +# CONFIG_GPIO_ADNP is not set | |
| +# CONFIG_GPIO_MAX7300 is not set | |
| +# CONFIG_GPIO_MAX732X is not set | |
| +CONFIG_GPIO_PCA953X=y | |
| +# CONFIG_GPIO_PCA953X_IRQ is not set | |
| +# CONFIG_GPIO_PCF857X is not set | |
| +# CONFIG_GPIO_SX150X is not set | |
| + | |
| +# | |
| +# MFD GPIO expanders | |
| +# | |
| + | |
| +# | |
| +# PCI GPIO expanders | |
| +# | |
| +# CONFIG_GPIO_AMD8111 is not set | |
| +# CONFIG_GPIO_BT8XX is not set | |
| +# CONFIG_GPIO_ML_IOH is not set | |
| +# CONFIG_GPIO_RDC321X is not set | |
| + | |
| +# | |
| +# SPI or I2C GPIO expanders | |
| +# | |
| +# CONFIG_GPIO_MCP23S08 is not set | |
| + | |
| +# | |
| +# USB GPIO expanders | |
| +# | |
| +# CONFIG_W1 is not set | |
| +CONFIG_POWER_SUPPLY=y | |
| +# CONFIG_POWER_SUPPLY_DEBUG is not set | |
| +# CONFIG_PDA_POWER is not set | |
| +# CONFIG_TEST_POWER is not set | |
| +# CONFIG_BATTERY_DS2780 is not set | |
| +# CONFIG_BATTERY_DS2781 is not set | |
| +# CONFIG_BATTERY_DS2782 is not set | |
| +# CONFIG_BATTERY_SBS is not set | |
| +# CONFIG_BATTERY_BQ27XXX is not set | |
| +# CONFIG_BATTERY_MAX17040 is not set | |
| +# CONFIG_BATTERY_MAX17042 is not set | |
| +# CONFIG_CHARGER_MAX8903 is not set | |
| +# CONFIG_CHARGER_LP8727 is not set | |
| +# CONFIG_CHARGER_GPIO is not set | |
| +# CONFIG_CHARGER_BQ2415X is not set | |
| +# CONFIG_CHARGER_BQ24190 is not set | |
| +# CONFIG_CHARGER_BQ24735 is not set | |
| +# CONFIG_CHARGER_BQ25890 is not set | |
| +# CONFIG_CHARGER_SMB347 is not set | |
| +# CONFIG_BATTERY_GAUGE_LTC2941 is not set | |
| +# CONFIG_CHARGER_RT9455 is not set | |
| +CONFIG_POWER_RESET=y | |
| +# CONFIG_POWER_RESET_BRCMSTB is not set | |
| +# CONFIG_POWER_RESET_GPIO is not set | |
| +# CONFIG_POWER_RESET_GPIO_RESTART is not set | |
| +# CONFIG_POWER_RESET_LTC2952 is not set | |
| +# CONFIG_POWER_RESET_RESTART is not set | |
| +# CONFIG_POWER_RESET_VERSATILE is not set | |
| +CONFIG_POWER_RESET_VEXPRESS=y | |
| +# CONFIG_POWER_RESET_SYSCON is not set | |
| +# CONFIG_POWER_RESET_SYSCON_POWEROFF is not set | |
| +CONFIG_POWER_RESET_ALPINE=y | |
| +# CONFIG_POWER_AVS is not set | |
| +CONFIG_HWMON=y | |
| +# CONFIG_HWMON_VID is not set | |
| +# CONFIG_HWMON_DEBUG_CHIP is not set | |
| + | |
| +# | |
| +# Native drivers | |
| +# | |
| +# CONFIG_SENSORS_AD7414 is not set | |
| +# CONFIG_SENSORS_AD7418 is not set | |
| +# CONFIG_SENSORS_ADM1021 is not set | |
| +# CONFIG_SENSORS_ADM1025 is not set | |
| +# CONFIG_SENSORS_ADM1026 is not set | |
| +# CONFIG_SENSORS_ADM1029 is not set | |
| +# CONFIG_SENSORS_ADM1031 is not set | |
| +# CONFIG_SENSORS_ADM9240 is not set | |
| +# CONFIG_SENSORS_ADT7410 is not set | |
| +# CONFIG_SENSORS_ADT7411 is not set | |
| +# CONFIG_SENSORS_ADT7462 is not set | |
| +# CONFIG_SENSORS_ADT7470 is not set | |
| +# CONFIG_SENSORS_ADT7475 is not set | |
| +# CONFIG_SENSORS_ASC7621 is not set | |
| +# CONFIG_SENSORS_ATXP1 is not set | |
| +# CONFIG_SENSORS_DS620 is not set | |
| +# CONFIG_SENSORS_DS1621 is not set | |
| +# CONFIG_SENSORS_I5K_AMB is not set | |
| +# CONFIG_SENSORS_F71805F is not set | |
| +# CONFIG_SENSORS_F71882FG is not set | |
| +# CONFIG_SENSORS_F75375S is not set | |
| +# CONFIG_SENSORS_GL518SM is not set | |
| +# CONFIG_SENSORS_GL520SM is not set | |
| +CONFIG_SENSORS_G760A=y | |
| +CONFIG_SENSORS_G762=y | |
| +# CONFIG_SENSORS_GPIO_FAN is not set | |
| +# CONFIG_SENSORS_HIH6130 is not set | |
| +# CONFIG_SENSORS_IT87 is not set | |
| +# CONFIG_SENSORS_JC42 is not set | |
| +# CONFIG_SENSORS_POWR1220 is not set | |
| +# CONFIG_SENSORS_LINEAGE is not set | |
| +# CONFIG_SENSORS_LTC2945 is not set | |
| +# CONFIG_SENSORS_LTC4151 is not set | |
| +# CONFIG_SENSORS_LTC4215 is not set | |
| +# CONFIG_SENSORS_LTC4222 is not set | |
| +# CONFIG_SENSORS_LTC4245 is not set | |
| +# CONFIG_SENSORS_LTC4260 is not set | |
| +# CONFIG_SENSORS_LTC4261 is not set | |
| +# CONFIG_SENSORS_MAX16065 is not set | |
| +# CONFIG_SENSORS_MAX1619 is not set | |
| +# CONFIG_SENSORS_MAX1668 is not set | |
| +# CONFIG_SENSORS_MAX197 is not set | |
| +# CONFIG_SENSORS_MAX6639 is not set | |
| +# CONFIG_SENSORS_MAX6642 is not set | |
| +# CONFIG_SENSORS_MAX6650 is not set | |
| +# CONFIG_SENSORS_MAX6697 is not set | |
| +# CONFIG_SENSORS_MAX31790 is not set | |
| +# CONFIG_SENSORS_HTU21 is not set | |
| +# CONFIG_SENSORS_MCP3021 is not set | |
| +# CONFIG_SENSORS_LM63 is not set | |
| +# CONFIG_SENSORS_LM73 is not set | |
| +# CONFIG_SENSORS_LM75 is not set | |
| +# CONFIG_SENSORS_LM77 is not set | |
| +# CONFIG_SENSORS_LM78 is not set | |
| +# CONFIG_SENSORS_LM80 is not set | |
| +# CONFIG_SENSORS_LM83 is not set | |
| +# CONFIG_SENSORS_LM85 is not set | |
| +# CONFIG_SENSORS_LM87 is not set | |
| +# CONFIG_SENSORS_LM90 is not set | |
| +# CONFIG_SENSORS_LM92 is not set | |
| +# CONFIG_SENSORS_LM93 is not set | |
| +# CONFIG_SENSORS_LM95234 is not set | |
| +# CONFIG_SENSORS_LM95241 is not set | |
| +# CONFIG_SENSORS_LM95245 is not set | |
| +# CONFIG_SENSORS_PC87360 is not set | |
| +# CONFIG_SENSORS_PC87427 is not set | |
| +# CONFIG_SENSORS_NTC_THERMISTOR is not set | |
| +# CONFIG_SENSORS_NCT6683 is not set | |
| +# CONFIG_SENSORS_NCT6775 is not set | |
| +# CONFIG_SENSORS_NCT7802 is not set | |
| +# CONFIG_SENSORS_NCT7904 is not set | |
| +# CONFIG_SENSORS_PCF8591 is not set | |
| +# CONFIG_PMBUS is not set | |
| +# CONFIG_SENSORS_SHT15 is not set | |
| +# CONFIG_SENSORS_SHT21 is not set | |
| +# CONFIG_SENSORS_SHTC1 is not set | |
| +# CONFIG_SENSORS_SIS5595 is not set | |
| +# CONFIG_SENSORS_DME1737 is not set | |
| +# CONFIG_SENSORS_EMC1403 is not set | |
| +# CONFIG_SENSORS_EMC2103 is not set | |
| +# CONFIG_SENSORS_EMC6W201 is not set | |
| +# CONFIG_SENSORS_SMSC47M1 is not set | |
| +# CONFIG_SENSORS_SMSC47M192 is not set | |
| +# CONFIG_SENSORS_SMSC47B397 is not set | |
| +# CONFIG_SENSORS_SCH56XX_COMMON is not set | |
| +# CONFIG_SENSORS_SMM665 is not set | |
| +# CONFIG_SENSORS_ADC128D818 is not set | |
| +# CONFIG_SENSORS_ADS1015 is not set | |
| +# CONFIG_SENSORS_ADS7828 is not set | |
| +# CONFIG_SENSORS_AMC6821 is not set | |
| +# CONFIG_SENSORS_INA209 is not set | |
| +# CONFIG_SENSORS_INA2XX is not set | |
| +# CONFIG_SENSORS_TC74 is not set | |
| +# CONFIG_SENSORS_THMC50 is not set | |
| +# CONFIG_SENSORS_TMP102 is not set | |
| +# CONFIG_SENSORS_TMP103 is not set | |
| +# CONFIG_SENSORS_TMP401 is not set | |
| +# CONFIG_SENSORS_TMP421 is not set | |
| +# CONFIG_SENSORS_VEXPRESS is not set | |
| +# CONFIG_SENSORS_VIA686A is not set | |
| +# CONFIG_SENSORS_VT1211 is not set | |
| +# CONFIG_SENSORS_VT8231 is not set | |
| +# CONFIG_SENSORS_W83781D is not set | |
| +# CONFIG_SENSORS_W83791D is not set | |
| +# CONFIG_SENSORS_W83792D is not set | |
| +# CONFIG_SENSORS_W83793 is not set | |
| +# CONFIG_SENSORS_W83795 is not set | |
| +# CONFIG_SENSORS_W83L785TS is not set | |
| +# CONFIG_SENSORS_W83L786NG is not set | |
| +# CONFIG_SENSORS_W83627HF is not set | |
| +# CONFIG_SENSORS_W83627EHF is not set | |
| +CONFIG_THERMAL=y | |
| +CONFIG_THERMAL_HWMON=y | |
| +# CONFIG_THERMAL_OF is not set | |
| +# CONFIG_THERMAL_WRITABLE_TRIPS is not set | |
| +CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y | |
| +# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set | |
| +# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set | |
| +# CONFIG_THERMAL_DEFAULT_GOV_POWER_ALLOCATOR is not set | |
| +# CONFIG_THERMAL_GOV_FAIR_SHARE is not set | |
| +CONFIG_THERMAL_GOV_STEP_WISE=y | |
| +# CONFIG_THERMAL_GOV_BANG_BANG is not set | |
| +# CONFIG_THERMAL_GOV_USER_SPACE is not set | |
| +# CONFIG_THERMAL_GOV_POWER_ALLOCATOR is not set | |
| +# CONFIG_THERMAL_EMULATION is not set | |
| +CONFIG_AL_THERMAL=y | |
| +# CONFIG_WATCHDOG is not set | |
| +CONFIG_SSB_POSSIBLE=y | |
| + | |
| +# | |
| +# Sonics Silicon Backplane | |
| +# | |
| +# CONFIG_SSB is not set | |
| +CONFIG_BCMA_POSSIBLE=y | |
| + | |
| +# | |
| +# Broadcom specific AMBA | |
| +# | |
| +# CONFIG_BCMA is not set | |
| + | |
| +# | |
| +# Multifunction device drivers | |
| +# | |
| +CONFIG_MFD_CORE=y | |
| +# CONFIG_MFD_AS3711 is not set | |
| +# CONFIG_MFD_AS3722 is not set | |
| +# CONFIG_PMIC_ADP5520 is not set | |
| +# CONFIG_MFD_AAT2870_CORE is not set | |
| +# CONFIG_MFD_ATMEL_FLEXCOM is not set | |
| +# CONFIG_MFD_ATMEL_HLCDC is not set | |
| +# CONFIG_MFD_BCM590XX is not set | |
| +# CONFIG_MFD_AXP20X is not set | |
| +# CONFIG_MFD_CROS_EC is not set | |
| +# CONFIG_MFD_ASIC3 is not set | |
| +# CONFIG_PMIC_DA903X is not set | |
| +# CONFIG_MFD_DA9052_I2C is not set | |
| +# CONFIG_MFD_DA9055 is not set | |
| +# CONFIG_MFD_DA9062 is not set | |
| +# CONFIG_MFD_DA9063 is not set | |
| +# CONFIG_MFD_DA9150 is not set | |
| +# CONFIG_MFD_DLN2 is not set | |
| +# CONFIG_MFD_MC13XXX_I2C is not set | |
| +# CONFIG_MFD_HI6421_PMIC is not set | |
| +# CONFIG_HTC_EGPIO is not set | |
| +# CONFIG_HTC_PASIC3 is not set | |
| +# CONFIG_HTC_I2CPLD is not set | |
| +# CONFIG_LPC_ICH is not set | |
| +# CONFIG_LPC_SCH is not set | |
| +# CONFIG_INTEL_SOC_PMIC is not set | |
| +# CONFIG_MFD_JANZ_CMODIO is not set | |
| +# CONFIG_MFD_KEMPLD is not set | |
| +# CONFIG_MFD_88PM800 is not set | |
| +# CONFIG_MFD_88PM805 is not set | |
| +# CONFIG_MFD_88PM860X is not set | |
| +# CONFIG_MFD_MAX14577 is not set | |
| +# CONFIG_MFD_MAX77686 is not set | |
| +# CONFIG_MFD_MAX77693 is not set | |
| +# CONFIG_MFD_MAX77843 is not set | |
| +# CONFIG_MFD_MAX8907 is not set | |
| +# CONFIG_MFD_MAX8925 is not set | |
| +# CONFIG_MFD_MAX8997 is not set | |
| +# CONFIG_MFD_MAX8998 is not set | |
| +# CONFIG_MFD_MT6397 is not set | |
| +# CONFIG_MFD_MENF21BMC is not set | |
| +# CONFIG_MFD_VIPERBOARD is not set | |
| +# CONFIG_MFD_RETU is not set | |
| +# CONFIG_MFD_PCF50633 is not set | |
| +# CONFIG_MFD_PM8921_CORE is not set | |
| +# CONFIG_MFD_RDC321X is not set | |
| +# CONFIG_MFD_RTSX_PCI is not set | |
| +# CONFIG_MFD_RT5033 is not set | |
| +# CONFIG_MFD_RTSX_USB is not set | |
| +# CONFIG_MFD_RC5T583 is not set | |
| +# CONFIG_MFD_RK808 is not set | |
| +# CONFIG_MFD_RN5T618 is not set | |
| +# CONFIG_MFD_SEC_CORE is not set | |
| +# CONFIG_MFD_SI476X_CORE is not set | |
| +# CONFIG_MFD_SM501 is not set | |
| +# CONFIG_MFD_SKY81452 is not set | |
| +# CONFIG_MFD_SMSC is not set | |
| +# CONFIG_ABX500_CORE is not set | |
| +# CONFIG_MFD_STMPE is not set | |
| +CONFIG_MFD_SYSCON=y | |
| +# CONFIG_MFD_TI_AM335X_TSCADC is not set | |
| +# CONFIG_MFD_LP3943 is not set | |
| +# CONFIG_MFD_LP8788 is not set | |
| +# CONFIG_MFD_PALMAS is not set | |
| +# CONFIG_TPS6105X is not set | |
| +# CONFIG_TPS65010 is not set | |
| +# CONFIG_TPS6507X is not set | |
| +# CONFIG_MFD_TPS65090 is not set | |
| +# CONFIG_MFD_TPS65217 is not set | |
| +# CONFIG_MFD_TPS65218 is not set | |
| +# CONFIG_MFD_TPS6586X is not set | |
| +# CONFIG_MFD_TPS65910 is not set | |
| +# CONFIG_MFD_TPS65912 is not set | |
| +# CONFIG_MFD_TPS65912_I2C is not set | |
| +# CONFIG_MFD_TPS80031 is not set | |
| +# CONFIG_TWL4030_CORE is not set | |
| +# CONFIG_TWL6040_CORE is not set | |
| +# CONFIG_MFD_WL1273_CORE is not set | |
| +# CONFIG_MFD_LM3533 is not set | |
| +# CONFIG_MFD_TC3589X is not set | |
| +# CONFIG_MFD_TMIO is not set | |
| +# CONFIG_MFD_T7L66XB is not set | |
| +# CONFIG_MFD_TC6387XB is not set | |
| +# CONFIG_MFD_TC6393XB is not set | |
| +# CONFIG_MFD_VX855 is not set | |
| +# CONFIG_MFD_ARIZONA_I2C is not set | |
| +# CONFIG_MFD_WM8400 is not set | |
| +# CONFIG_MFD_WM831X_I2C is not set | |
| +# CONFIG_MFD_WM8350_I2C is not set | |
| +# CONFIG_MFD_WM8994 is not set | |
| +CONFIG_MFD_VEXPRESS_SYSREG=y | |
| +# CONFIG_REGULATOR is not set | |
| +# CONFIG_MEDIA_SUPPORT is not set | |
| + | |
| +# | |
| +# Graphics support | |
| +# | |
| +# CONFIG_VGA_ARB is not set | |
| +# CONFIG_DRM is not set | |
| + | |
| +# | |
| +# Frame buffer Devices | |
| +# | |
| +# CONFIG_FB is not set | |
| +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set | |
| +# CONFIG_VGASTATE is not set | |
| +# CONFIG_SOUND is not set | |
| + | |
| +# | |
| +# HID support | |
| +# | |
| +CONFIG_HID=y | |
| +# CONFIG_HID_BATTERY_STRENGTH is not set | |
| +# CONFIG_HIDRAW is not set | |
| +# CONFIG_UHID is not set | |
| +# CONFIG_HID_GENERIC is not set | |
| + | |
| +# | |
| +# Special HID drivers | |
| +# | |
| +# CONFIG_HID_A4TECH is not set | |
| +# CONFIG_HID_ACRUX is not set | |
| +# CONFIG_HID_APPLE is not set | |
| +# CONFIG_HID_APPLEIR is not set | |
| +# CONFIG_HID_AUREAL is not set | |
| +# CONFIG_HID_BELKIN is not set | |
| +# CONFIG_HID_BETOP_FF is not set | |
| +# CONFIG_HID_CHERRY is not set | |
| +# CONFIG_HID_CHICONY is not set | |
| +# CONFIG_HID_CORSAIR is not set | |
| +# CONFIG_HID_CP2112 is not set | |
| +# CONFIG_HID_CYPRESS is not set | |
| +# CONFIG_HID_DRAGONRISE is not set | |
| +# CONFIG_HID_EMS_FF is not set | |
| +# CONFIG_HID_ELECOM is not set | |
| +# CONFIG_HID_ELO is not set | |
| +# CONFIG_HID_EZKEY is not set | |
| +# CONFIG_HID_GEMBIRD is not set | |
| +# CONFIG_HID_GFRM is not set | |
| +# CONFIG_HID_HOLTEK is not set | |
| +# CONFIG_HID_GT683R is not set | |
| +# CONFIG_HID_KEYTOUCH is not set | |
| +# CONFIG_HID_KYE is not set | |
| +# CONFIG_HID_UCLOGIC is not set | |
| +# CONFIG_HID_WALTOP is not set | |
| +# CONFIG_HID_GYRATION is not set | |
| +# CONFIG_HID_ICADE is not set | |
| +# CONFIG_HID_TWINHAN is not set | |
| +# CONFIG_HID_KENSINGTON is not set | |
| +# CONFIG_HID_LCPOWER is not set | |
| +# CONFIG_HID_LENOVO is not set | |
| +# CONFIG_HID_LOGITECH is not set | |
| +# CONFIG_HID_MAGICMOUSE is not set | |
| +# CONFIG_HID_MICROSOFT is not set | |
| +# CONFIG_HID_MONTEREY is not set | |
| +# CONFIG_HID_MULTITOUCH is not set | |
| +# CONFIG_HID_NTRIG is not set | |
| +# CONFIG_HID_ORTEK is not set | |
| +# CONFIG_HID_PANTHERLORD is not set | |
| +# CONFIG_HID_PENMOUNT is not set | |
| +# CONFIG_HID_PETALYNX is not set | |
| +# CONFIG_HID_PICOLCD is not set | |
| +# CONFIG_HID_PLANTRONICS is not set | |
| +# CONFIG_HID_PRIMAX is not set | |
| +# CONFIG_HID_ROCCAT is not set | |
| +# CONFIG_HID_SAITEK is not set | |
| +# CONFIG_HID_SAMSUNG is not set | |
| +# CONFIG_HID_SONY is not set | |
| +# CONFIG_HID_SPEEDLINK is not set | |
| +# CONFIG_HID_STEELSERIES is not set | |
| +# CONFIG_HID_SUNPLUS is not set | |
| +# CONFIG_HID_RMI is not set | |
| +# CONFIG_HID_GREENASIA is not set | |
| +# CONFIG_HID_SMARTJOYPLUS is not set | |
| +# CONFIG_HID_TIVO is not set | |
| +# CONFIG_HID_TOPSEED is not set | |
| +# CONFIG_HID_THINGM is not set | |
| +# CONFIG_HID_THRUSTMASTER is not set | |
| +# CONFIG_HID_WACOM is not set | |
| +# CONFIG_HID_WIIMOTE is not set | |
| +# CONFIG_HID_XINMO is not set | |
| +# CONFIG_HID_ZEROPLUS is not set | |
| +# CONFIG_HID_ZYDACRON is not set | |
| +# CONFIG_HID_SENSOR_HUB is not set | |
| + | |
| +# | |
| +# USB HID support | |
| +# | |
| +CONFIG_USB_HID=y | |
| +# CONFIG_HID_PID is not set | |
| +CONFIG_USB_HIDDEV=y | |
| + | |
| +# | |
| +# I2C HID support | |
| +# | |
| +# CONFIG_I2C_HID is not set | |
| +CONFIG_USB_OHCI_LITTLE_ENDIAN=y | |
| +CONFIG_USB_SUPPORT=y | |
| +CONFIG_USB_COMMON=y | |
| +CONFIG_USB_ARCH_HAS_HCD=y | |
| +CONFIG_USB=y | |
| +# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set | |
| + | |
| +# | |
| +# Miscellaneous USB options | |
| +# | |
| +CONFIG_USB_DEFAULT_PERSIST=y | |
| +# CONFIG_USB_DYNAMIC_MINORS is not set | |
| +# CONFIG_USB_OTG is not set | |
| +# CONFIG_USB_OTG_WHITELIST is not set | |
| +# CONFIG_USB_OTG_BLACKLIST_HUB is not set | |
| +# CONFIG_USB_ULPI_BUS is not set | |
| +# CONFIG_USB_MON is not set | |
| +# CONFIG_USB_WUSB_CBAF is not set | |
| + | |
| +# | |
| +# USB Host Controller Drivers | |
| +# | |
| +# CONFIG_USB_C67X00_HCD is not set | |
| +CONFIG_USB_XHCI_HCD=y | |
| +CONFIG_USB_XHCI_PCI=y | |
| +CONFIG_USB_XHCI_PLATFORM=y | |
| +CONFIG_USB_EHCI_HCD=y | |
| +CONFIG_USB_EHCI_ROOT_HUB_TT=y | |
| +CONFIG_USB_EHCI_TT_NEWSCHED=y | |
| +CONFIG_USB_EHCI_PCI=y | |
| +# CONFIG_USB_EHCI_HCD_PLATFORM is not set | |
| +# CONFIG_USB_OXU210HP_HCD is not set | |
| +# CONFIG_USB_ISP116X_HCD is not set | |
| +# CONFIG_USB_ISP1362_HCD is not set | |
| +# CONFIG_USB_FOTG210_HCD is not set | |
| +# CONFIG_USB_OHCI_HCD is not set | |
| +# CONFIG_USB_UHCI_HCD is not set | |
| +# CONFIG_USB_SL811_HCD is not set | |
| +# CONFIG_USB_R8A66597_HCD is not set | |
| +# CONFIG_USB_HCD_TEST_MODE is not set | |
| + | |
| +# | |
| +# USB Device Class drivers | |
| +# | |
| +CONFIG_USB_ACM=y | |
| +CONFIG_USB_PRINTER=y | |
| +# CONFIG_USB_WDM is not set | |
| +# CONFIG_USB_TMC is not set | |
| + | |
| +# | |
| +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may | |
| +# | |
| + | |
| +# | |
| +# also be needed; see USB_STORAGE Help for more info | |
| +# | |
| +CONFIG_USB_STORAGE=y | |
| +# CONFIG_USB_STORAGE_DEBUG is not set | |
| +# CONFIG_USB_STORAGE_REALTEK is not set | |
| +CONFIG_USB_STORAGE_DATAFAB=y | |
| +CONFIG_USB_STORAGE_FREECOM=y | |
| +# CONFIG_USB_STORAGE_ISD200 is not set | |
| +# CONFIG_USB_STORAGE_USBAT is not set | |
| +CONFIG_USB_STORAGE_SDDR09=y | |
| +CONFIG_USB_STORAGE_SDDR55=y | |
| +CONFIG_USB_STORAGE_JUMPSHOT=y | |
| +# CONFIG_USB_STORAGE_ALAUDA is not set | |
| +# CONFIG_USB_STORAGE_ONETOUCH is not set | |
| +# CONFIG_USB_STORAGE_KARMA is not set | |
| +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set | |
| +# CONFIG_USB_STORAGE_ENE_UB6250 is not set | |
| +# CONFIG_USB_UAS is not set | |
| + | |
| +# | |
| +# USB Imaging devices | |
| +# | |
| +# CONFIG_USB_MDC800 is not set | |
| +# CONFIG_USB_MICROTEK is not set | |
| +# CONFIG_USBIP_CORE is not set | |
| +# CONFIG_USB_MUSB_HDRC is not set | |
| +CONFIG_USB_DWC3=y | |
| +CONFIG_USB_DWC3_HOST=y | |
| + | |
| +# | |
| +# Platform Glue Driver Support | |
| +# | |
| +CONFIG_USB_DWC3_PCI=y | |
| +# CONFIG_USB_DWC2 is not set | |
| +# CONFIG_USB_CHIPIDEA is not set | |
| +# CONFIG_USB_ISP1760 is not set | |
| + | |
| +# | |
| +# USB port drivers | |
| +# | |
| +CONFIG_USB_SERIAL=m | |
| +CONFIG_USB_SERIAL_GENERIC=y | |
| +# CONFIG_USB_SERIAL_SIMPLE is not set | |
| +# CONFIG_USB_SERIAL_AIRCABLE is not set | |
| +# CONFIG_USB_SERIAL_ARK3116 is not set | |
| +# CONFIG_USB_SERIAL_BELKIN is not set | |
| +# CONFIG_USB_SERIAL_CH341 is not set | |
| +# CONFIG_USB_SERIAL_WHITEHEAT is not set | |
| +# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set | |
| +# CONFIG_USB_SERIAL_CP210X is not set | |
| +# CONFIG_USB_SERIAL_CYPRESS_M8 is not set | |
| +# CONFIG_USB_SERIAL_EMPEG is not set | |
| +CONFIG_USB_SERIAL_FTDI_SIO=m | |
| +# CONFIG_USB_SERIAL_VISOR is not set | |
| +# CONFIG_USB_SERIAL_IPAQ is not set | |
| +# CONFIG_USB_SERIAL_IR is not set | |
| +# CONFIG_USB_SERIAL_EDGEPORT is not set | |
| +# CONFIG_USB_SERIAL_EDGEPORT_TI is not set | |
| +# CONFIG_USB_SERIAL_F81232 is not set | |
| +# CONFIG_USB_SERIAL_GARMIN is not set | |
| +# CONFIG_USB_SERIAL_IPW is not set | |
| +# CONFIG_USB_SERIAL_IUU is not set | |
| +# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set | |
| +# CONFIG_USB_SERIAL_KEYSPAN is not set | |
| +# CONFIG_USB_SERIAL_KLSI is not set | |
| +# CONFIG_USB_SERIAL_KOBIL_SCT is not set | |
| +# CONFIG_USB_SERIAL_MCT_U232 is not set | |
| +# CONFIG_USB_SERIAL_METRO is not set | |
| +# CONFIG_USB_SERIAL_MOS7720 is not set | |
| +# CONFIG_USB_SERIAL_MOS7840 is not set | |
| +# CONFIG_USB_SERIAL_MXUPORT is not set | |
| +# CONFIG_USB_SERIAL_NAVMAN is not set | |
| +CONFIG_USB_SERIAL_PL2303=m | |
| +# CONFIG_USB_SERIAL_OTI6858 is not set | |
| +# CONFIG_USB_SERIAL_QCAUX is not set | |
| +# CONFIG_USB_SERIAL_QUALCOMM is not set | |
| +# CONFIG_USB_SERIAL_SPCP8X5 is not set | |
| +# CONFIG_USB_SERIAL_SAFE is not set | |
| +# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set | |
| +# CONFIG_USB_SERIAL_SYMBOL is not set | |
| +# CONFIG_USB_SERIAL_TI is not set | |
| +# CONFIG_USB_SERIAL_CYBERJACK is not set | |
| +# CONFIG_USB_SERIAL_XIRCOM is not set | |
| +# CONFIG_USB_SERIAL_OPTION is not set | |
| +# CONFIG_USB_SERIAL_OMNINET is not set | |
| +# CONFIG_USB_SERIAL_OPTICON is not set | |
| +# CONFIG_USB_SERIAL_XSENS_MT is not set | |
| +# CONFIG_USB_SERIAL_WISHBONE is not set | |
| +# CONFIG_USB_SERIAL_SSU100 is not set | |
| +# CONFIG_USB_SERIAL_QT2 is not set | |
| +# CONFIG_USB_SERIAL_DEBUG is not set | |
| + | |
| +# | |
| +# USB Miscellaneous drivers | |
| +# | |
| +# CONFIG_USB_EMI62 is not set | |
| +# CONFIG_USB_EMI26 is not set | |
| +# CONFIG_USB_ADUTUX is not set | |
| +# CONFIG_USB_SEVSEG is not set | |
| +# CONFIG_USB_RIO500 is not set | |
| +# CONFIG_USB_LEGOTOWER is not set | |
| +# CONFIG_USB_LCD is not set | |
| +# CONFIG_USB_LED is not set | |
| +# CONFIG_USB_CYPRESS_CY7C63 is not set | |
| +# CONFIG_USB_CYTHERM is not set | |
| +# CONFIG_USB_IDMOUSE is not set | |
| +# CONFIG_USB_FTDI_ELAN is not set | |
| +# CONFIG_USB_APPLEDISPLAY is not set | |
| +# CONFIG_USB_SISUSBVGA is not set | |
| +# CONFIG_USB_LD is not set | |
| +# CONFIG_USB_TRANCEVIBRATOR is not set | |
| +# CONFIG_USB_IOWARRIOR is not set | |
| +# CONFIG_USB_TEST is not set | |
| +# CONFIG_USB_EHSET_TEST_FIXTURE is not set | |
| +# CONFIG_USB_ISIGHTFW is not set | |
| +# CONFIG_USB_YUREX is not set | |
| +# CONFIG_USB_EZUSB_FX2 is not set | |
| +# CONFIG_USB_HSIC_USB3503 is not set | |
| +# CONFIG_USB_LINK_LAYER_TEST is not set | |
| + | |
| +# | |
| +# USB Physical Layer drivers | |
| +# | |
| +# CONFIG_USB_PHY is not set | |
| +# CONFIG_NOP_USB_XCEIV is not set | |
| +# CONFIG_AM335X_PHY_USB is not set | |
| +# CONFIG_USB_GPIO_VBUS is not set | |
| +# CONFIG_USB_ISP1301 is not set | |
| +# CONFIG_USB_ULPI is not set | |
| +# CONFIG_USB_GADGET is not set | |
| +# CONFIG_USB_LED_TRIG is not set | |
| +# CONFIG_UWB is not set | |
| +# CONFIG_MMC is not set | |
| +# CONFIG_MEMSTICK is not set | |
| +CONFIG_NEW_LEDS=y | |
| +CONFIG_LEDS_CLASS=y | |
| +# CONFIG_LEDS_CLASS_FLASH is not set | |
| + | |
| +# | |
| +# LED drivers | |
| +# | |
| +# CONFIG_LEDS_BCM6328 is not set | |
| +# CONFIG_LEDS_BCM6358 is not set | |
| +# CONFIG_LEDS_LM3530 is not set | |
| +# CONFIG_LEDS_LM3642 is not set | |
| +# CONFIG_LEDS_PCA9532 is not set | |
| +CONFIG_LEDS_GPIO=y | |
| +# CONFIG_LEDS_LP3944 is not set | |
| +# CONFIG_LEDS_LP5521 is not set | |
| +# CONFIG_LEDS_LP5523 is not set | |
| +# CONFIG_LEDS_LP5562 is not set | |
| +# CONFIG_LEDS_LP8501 is not set | |
| +# CONFIG_LEDS_LP8860 is not set | |
| +# CONFIG_LEDS_PCA955X is not set | |
| +# CONFIG_LEDS_PCA963X is not set | |
| +# CONFIG_LEDS_BD2802 is not set | |
| +# CONFIG_LEDS_LT3593 is not set | |
| +# CONFIG_LEDS_TCA6507 is not set | |
| +# CONFIG_LEDS_TLC591XX is not set | |
| +# CONFIG_LEDS_LM355x is not set | |
| + | |
| +# | |
| +# LED driver for blink(1) USB RGB LED is under Special HID drivers (HID_THINGM) | |
| +# | |
| +# CONFIG_LEDS_BLINKM is not set | |
| +# CONFIG_LEDS_SYSCON is not set | |
| + | |
| +# | |
| +# LED Triggers | |
| +# | |
| +CONFIG_LEDS_TRIGGERS=y | |
| +CONFIG_LEDS_TRIGGER_TIMER=y | |
| +# CONFIG_LEDS_TRIGGER_ONESHOT is not set | |
| +# CONFIG_LEDS_TRIGGER_HEARTBEAT is not set | |
| +# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set | |
| +# CONFIG_LEDS_TRIGGER_CPU is not set | |
| +CONFIG_LEDS_TRIGGER_GPIO=y | |
| +# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set | |
| + | |
| +# | |
| +# iptables trigger is under Netfilter config (LED target) | |
| +# | |
| +# CONFIG_LEDS_TRIGGER_TRANSIENT is not set | |
| +# CONFIG_LEDS_TRIGGER_CAMERA is not set | |
| +# CONFIG_ACCESSIBILITY is not set | |
| +# CONFIG_INFINIBAND is not set | |
| +CONFIG_EDAC_ATOMIC_SCRUB=y | |
| +CONFIG_EDAC_SUPPORT=y | |
| +CONFIG_EDAC=y | |
| +# CONFIG_EDAC_LEGACY_SYSFS is not set | |
| +# CONFIG_EDAC_DEBUG is not set | |
| +CONFIG_EDAC_MM_EDAC=y | |
| +CONFIG_RTC_LIB=y | |
| +CONFIG_RTC_CLASS=y | |
| +CONFIG_RTC_HCTOSYS=y | |
| +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" | |
| +CONFIG_RTC_SYSTOHC=y | |
| +CONFIG_RTC_SYSTOHC_DEVICE="rtc0" | |
| +# CONFIG_RTC_DEBUG is not set | |
| + | |
| +# | |
| +# RTC interfaces | |
| +# | |
| +CONFIG_RTC_INTF_SYSFS=y | |
| +CONFIG_RTC_INTF_PROC=y | |
| +CONFIG_RTC_INTF_DEV=y | |
| +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set | |
| +# CONFIG_RTC_DRV_TEST is not set | |
| + | |
| +# | |
| +# I2C RTC drivers | |
| +# | |
| +# CONFIG_RTC_DRV_ABB5ZES3 is not set | |
| +# CONFIG_RTC_DRV_ABX80X is not set | |
| +CONFIG_RTC_DRV_DS1307=y | |
| +# CONFIG_RTC_DRV_DS1374 is not set | |
| +# CONFIG_RTC_DRV_DS1672 is not set | |
| +# CONFIG_RTC_DRV_DS3232 is not set | |
| +# CONFIG_RTC_DRV_HYM8563 is not set | |
| +# CONFIG_RTC_DRV_MAX6900 is not set | |
| +# CONFIG_RTC_DRV_RS5C372 is not set | |
| +# CONFIG_RTC_DRV_ISL1208 is not set | |
| +# CONFIG_RTC_DRV_ISL12022 is not set | |
| +# CONFIG_RTC_DRV_ISL12057 is not set | |
| +# CONFIG_RTC_DRV_X1205 is not set | |
| +# CONFIG_RTC_DRV_PCF2127 is not set | |
| +# CONFIG_RTC_DRV_PCF8523 is not set | |
| +# CONFIG_RTC_DRV_PCF8563 is not set | |
| +# CONFIG_RTC_DRV_PCF85063 is not set | |
| +# CONFIG_RTC_DRV_PCF8583 is not set | |
| +# CONFIG_RTC_DRV_M41T80 is not set | |
| +# CONFIG_RTC_DRV_BQ32K is not set | |
| +# CONFIG_RTC_DRV_S35390A is not set | |
| +# CONFIG_RTC_DRV_FM3130 is not set | |
| +# CONFIG_RTC_DRV_RX8581 is not set | |
| +# CONFIG_RTC_DRV_RX8025 is not set | |
| +# CONFIG_RTC_DRV_EM3027 is not set | |
| +# CONFIG_RTC_DRV_RV3029C2 is not set | |
| +# CONFIG_RTC_DRV_RV8803 is not set | |
| + | |
| +# | |
| +# SPI RTC drivers | |
| +# | |
| + | |
| +# | |
| +# Platform RTC drivers | |
| +# | |
| +# CONFIG_RTC_DRV_CMOS is not set | |
| +# CONFIG_RTC_DRV_DS1286 is not set | |
| +# CONFIG_RTC_DRV_DS1511 is not set | |
| +# CONFIG_RTC_DRV_DS1553 is not set | |
| +# CONFIG_RTC_DRV_DS1685_FAMILY is not set | |
| +# CONFIG_RTC_DRV_DS1742 is not set | |
| +# CONFIG_RTC_DRV_DS2404 is not set | |
| +# CONFIG_RTC_DRV_STK17TA8 is not set | |
| +# CONFIG_RTC_DRV_M48T86 is not set | |
| +# CONFIG_RTC_DRV_M48T35 is not set | |
| +# CONFIG_RTC_DRV_M48T59 is not set | |
| +# CONFIG_RTC_DRV_MSM6242 is not set | |
| +# CONFIG_RTC_DRV_BQ4802 is not set | |
| +# CONFIG_RTC_DRV_RP5C01 is not set | |
| +# CONFIG_RTC_DRV_V3020 is not set | |
| +# CONFIG_RTC_DRV_ZYNQMP is not set | |
| + | |
| +# | |
| +# on-CPU RTC drivers | |
| +# | |
| +# CONFIG_RTC_DRV_PL030 is not set | |
| +# CONFIG_RTC_DRV_PL031 is not set | |
| +# CONFIG_RTC_DRV_SNVS is not set | |
| + | |
| +# | |
| +# HID Sensor RTC drivers | |
| +# | |
| +# CONFIG_RTC_DRV_HID_SENSOR_TIME is not set | |
| +CONFIG_DMADEVICES=y | |
| +# CONFIG_DMADEVICES_DEBUG is not set | |
| + | |
| +# | |
| +# DMA Devices | |
| +# | |
| +CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=y | |
| +CONFIG_DMA_ENGINE=y | |
| +CONFIG_DMA_OF=y | |
| +# CONFIG_AMBA_PL08X is not set | |
| +# CONFIG_FSL_EDMA is not set | |
| +# CONFIG_INTEL_IDMA64 is not set | |
| +# CONFIG_NBPFAXI_DMA is not set | |
| +# CONFIG_PL330_DMA is not set | |
| +# CONFIG_DW_DMAC is not set | |
| +# CONFIG_DW_DMAC_PCI is not set | |
| + | |
| +# | |
| +# DMA Clients | |
| +# | |
| +CONFIG_ASYNC_TX_DMA=y | |
| +# CONFIG_DMATEST is not set | |
| +CONFIG_DMA_ENGINE_RAID=y | |
| +CONFIG_AL_DMA=y | |
| +# CONFIG_AL_DMA_STATS is not set | |
| +CONFIG_AL_DMA_PCI_IOV=y | |
| +# CONFIG_AUXDISPLAY is not set | |
| +# CONFIG_UIO is not set | |
| +# CONFIG_VIRT_DRIVERS is not set | |
| + | |
| +# | |
| +# Virtio drivers | |
| +# | |
| +# CONFIG_VIRTIO_PCI is not set | |
| +# CONFIG_VIRTIO_MMIO is not set | |
| + | |
| +# | |
| +# Microsoft Hyper-V guest support | |
| +# | |
| +# CONFIG_STAGING is not set | |
| +# CONFIG_CHROME_PLATFORMS is not set | |
| +CONFIG_READYNAS_PLATFORMS=y | |
| +CONFIG_GPIO_PWR=y | |
| +CONFIG_HD44780_LCD=y | |
| +CONFIG_READYNAS_LCD=y | |
| +CONFIG_CLKDEV_LOOKUP=y | |
| +CONFIG_HAVE_CLK_PREPARE=y | |
| +CONFIG_COMMON_CLK=y | |
| + | |
| +# | |
| +# Common Clock Framework | |
| +# | |
| +# CONFIG_COMMON_CLK_SI5351 is not set | |
| +# CONFIG_COMMON_CLK_SI514 is not set | |
| +# CONFIG_COMMON_CLK_SI570 is not set | |
| +# CONFIG_COMMON_CLK_CDCE925 is not set | |
| +# CONFIG_CLK_QORIQ is not set | |
| +# CONFIG_COMMON_CLK_PXA is not set | |
| +# CONFIG_COMMON_CLK_CDCE706 is not set | |
| + | |
| +# | |
| +# Hardware Spinlock drivers | |
| +# | |
| + | |
| +# | |
| +# Clock Source drivers | |
| +# | |
| +CONFIG_CLKSRC_OF=y | |
| +CONFIG_CLKSRC_PROBE=y | |
| +CONFIG_CLKSRC_MMIO=y | |
| +CONFIG_ARM_ARCH_TIMER=y | |
| +CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y | |
| +# CONFIG_ARM_TIMER_SP804 is not set | |
| +# CONFIG_ATMEL_PIT is not set | |
| +# CONFIG_SH_TIMER_CMT is not set | |
| +# CONFIG_SH_TIMER_MTU2 is not set | |
| +# CONFIG_SH_TIMER_TMU is not set | |
| +# CONFIG_EM_TIMER_STI is not set | |
| +# CONFIG_MAILBOX is not set | |
| +# CONFIG_IOMMU_SUPPORT is not set | |
| + | |
| +# | |
| +# Remoteproc drivers | |
| +# | |
| +# CONFIG_STE_MODEM_RPROC is not set | |
| + | |
| +# | |
| +# Rpmsg drivers | |
| +# | |
| + | |
| +# | |
| +# SOC (System On Chip) specific Drivers | |
| +# | |
| +# CONFIG_SOC_BRCMSTB is not set | |
| +# CONFIG_SUNXI_SRAM is not set | |
| +# CONFIG_SOC_TI is not set | |
| +# CONFIG_PM_DEVFREQ is not set | |
| +# CONFIG_EXTCON is not set | |
| +# CONFIG_MEMORY is not set | |
| +# CONFIG_IIO is not set | |
| +# CONFIG_NTB is not set | |
| +# CONFIG_VME_BUS is not set | |
| +# CONFIG_PWM is not set | |
| +CONFIG_IRQCHIP=y | |
| +CONFIG_ARM_GIC=y | |
| +# CONFIG_IPACK_BUS is not set | |
| +# CONFIG_RESET_CONTROLLER is not set | |
| +# CONFIG_FMC is not set | |
| + | |
| +# | |
| +# PHY Subsystem | |
| +# | |
| +# CONFIG_GENERIC_PHY is not set | |
| +# CONFIG_PHY_PXA_28NM_HSIC is not set | |
| +# CONFIG_PHY_PXA_28NM_USB2 is not set | |
| +# CONFIG_BCM_KONA_USB2_PHY is not set | |
| +# CONFIG_POWERCAP is not set | |
| +# CONFIG_MCB is not set | |
| + | |
| +# | |
| +# Performance monitor support | |
| +# | |
| +CONFIG_RAS=y | |
| +# CONFIG_THUNDERBOLT is not set | |
| + | |
| +# | |
| +# Android | |
| +# | |
| +# CONFIG_ANDROID is not set | |
| +# CONFIG_LIBNVDIMM is not set | |
| +# CONFIG_NVMEM is not set | |
| +# CONFIG_STM is not set | |
| +# CONFIG_STM_DUMMY is not set | |
| +# CONFIG_STM_SOURCE_CONSOLE is not set | |
| +# CONFIG_INTEL_TH is not set | |
| + | |
| +# | |
| +# FPGA Configuration Support | |
| +# | |
| +# CONFIG_FPGA is not set | |
| + | |
| +# | |
| +# Firmware Drivers | |
| +# | |
| +# CONFIG_FIRMWARE_MEMMAP is not set | |
| + | |
| +# | |
| +# File systems | |
| +# | |
| +CONFIG_DCACHE_WORD_ACCESS=y | |
| +CONFIG_LFS_ON_32CPU=y | |
| +# CONFIG_EXT2_FS is not set | |
| +# CONFIG_EXT3_FS is not set | |
| +CONFIG_EXT4_FS=y | |
| +CONFIG_EXT4_USE_FOR_EXT2=y | |
| +CONFIG_EXT4_FS_POSIX_ACL=y | |
| +CONFIG_EXT4_FS_SECURITY=y | |
| +CONFIG_EXT4_ENCRYPTION=y | |
| +CONFIG_EXT4_FS_ENCRYPTION=y | |
| +# CONFIG_EXT4_DEBUG is not set | |
| +CONFIG_JBD2=y | |
| +# CONFIG_JBD2_DEBUG is not set | |
| +CONFIG_FS_MBCACHE=y | |
| +# CONFIG_REISERFS_FS is not set | |
| +# CONFIG_JFS_FS is not set | |
| +CONFIG_XFS_FS=m | |
| +CONFIG_XFS_QUOTA=y | |
| +CONFIG_XFS_POSIX_ACL=y | |
| +CONFIG_XFS_RT=y | |
| +# CONFIG_XFS_WARN is not set | |
| +# CONFIG_XFS_DEBUG is not set | |
| +# CONFIG_GFS2_FS is not set | |
| +# CONFIG_OCFS2_FS is not set | |
| +CONFIG_BTRFS_FS=y | |
| +CONFIG_BTRFS_FS_POSIX_ACL=y | |
| +# CONFIG_BTRFS_FS_CHECK_INTEGRITY is not set | |
| +# CONFIG_BTRFS_FS_RUN_SANITY_TESTS is not set | |
| +# CONFIG_BTRFS_DEBUG is not set | |
| +# CONFIG_BTRFS_ASSERT is not set | |
| +CONFIG_BTRFS_MDCSREPAIR=y | |
| +CONFIG_BTRFS_FIEMAP_PHYSICAL=y | |
| +# CONFIG_NILFS2_FS is not set | |
| +# CONFIG_F2FS_FS is not set | |
| +CONFIG_FS_POSIX_ACL=y | |
| +CONFIG_EXPORTFS=y | |
| +CONFIG_FILE_LOCKING=y | |
| +CONFIG_FSNOTIFY=y | |
| +CONFIG_DNOTIFY=y | |
| +CONFIG_INOTIFY_USER=y | |
| +CONFIG_FANOTIFY=y | |
| +CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y | |
| +CONFIG_QUOTA=y | |
| +CONFIG_QUOTA_NETLINK_INTERFACE=y | |
| +# CONFIG_PRINT_QUOTA_WARNING is not set | |
| +# CONFIG_QUOTA_DEBUG is not set | |
| +CONFIG_QUOTA_TREE=y | |
| +# CONFIG_QFMT_V1 is not set | |
| +CONFIG_QFMT_V2=y | |
| +CONFIG_QUOTACTL=y | |
| +CONFIG_AUTOFS4_FS=y | |
| +CONFIG_FUSE_FS=y | |
| +# CONFIG_CUSE is not set | |
| +CONFIG_OVERLAY_FS=y | |
| + | |
| +# | |
| +# Caches | |
| +# | |
| +CONFIG_FSCACHE=y | |
| +# CONFIG_FSCACHE_STATS is not set | |
| +# CONFIG_FSCACHE_HISTOGRAM is not set | |
| +# CONFIG_FSCACHE_DEBUG is not set | |
| +# CONFIG_FSCACHE_OBJECT_LIST is not set | |
| +# CONFIG_CACHEFILES is not set | |
| + | |
| +# | |
| +# CD-ROM/DVD Filesystems | |
| +# | |
| +CONFIG_ISO9660_FS=m | |
| +CONFIG_JOLIET=y | |
| +# CONFIG_ZISOFS is not set | |
| +CONFIG_UDF_FS=m | |
| +CONFIG_UDF_NLS=y | |
| + | |
| +# | |
| +# DOS/FAT/NT Filesystems | |
| +# | |
| +CONFIG_FAT_FS=y | |
| +CONFIG_MSDOS_FS=y | |
| +CONFIG_VFAT_FS=y | |
| +CONFIG_FAT_DEFAULT_CODEPAGE=437 | |
| +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" | |
| +# CONFIG_NTFS_FS is not set | |
| + | |
| +# | |
| +# Pseudo filesystems | |
| +# | |
| +CONFIG_PROC_FS=y | |
| +CONFIG_PROC_SYSCTL=y | |
| +CONFIG_PROC_PAGE_MONITOR=y | |
| +# CONFIG_PROC_CHILDREN is not set | |
| +CONFIG_KERNFS=y | |
| +CONFIG_SYSFS=y | |
| +CONFIG_TMPFS=y | |
| +CONFIG_TMPFS_POSIX_ACL=y | |
| +CONFIG_TMPFS_XATTR=y | |
| +# CONFIG_HUGETLBFS is not set | |
| +# CONFIG_HUGETLB_PAGE is not set | |
| +CONFIG_CONFIGFS_FS=y | |
| +CONFIG_MISC_FILESYSTEMS=y | |
| +# CONFIG_ADFS_FS is not set | |
| +# CONFIG_AFFS_FS is not set | |
| +# CONFIG_ECRYPT_FS is not set | |
| +# CONFIG_HFS_FS is not set | |
| +# CONFIG_HFSPLUS_FS is not set | |
| +# CONFIG_BEFS_FS is not set | |
| +# CONFIG_BFS_FS is not set | |
| +# CONFIG_EFS_FS is not set | |
| +# CONFIG_JFFS2_FS is not set | |
| +CONFIG_UBIFS_FS=y | |
| +# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set | |
| +CONFIG_UBIFS_FS_LZO=y | |
| +CONFIG_UBIFS_FS_ZLIB=y | |
| +# CONFIG_UBIFS_ATIME_SUPPORT is not set | |
| +# CONFIG_LOGFS is not set | |
| +# CONFIG_CRAMFS is not set | |
| +# CONFIG_SQUASHFS is not set | |
| +# CONFIG_VXFS_FS is not set | |
| +# CONFIG_MINIX_FS is not set | |
| +# CONFIG_OMFS_FS is not set | |
| +# CONFIG_HPFS_FS is not set | |
| +# CONFIG_QNX4FS_FS is not set | |
| +# CONFIG_QNX6FS_FS is not set | |
| +# CONFIG_ROMFS_FS is not set | |
| +# CONFIG_PSTORE is not set | |
| +# CONFIG_SYSV_FS is not set | |
| +# CONFIG_UFS_FS is not set | |
| +CONFIG_NETWORK_FILESYSTEMS=y | |
| +CONFIG_NFS_FS=y | |
| +CONFIG_NFS_V2=y | |
| +CONFIG_NFS_V3=y | |
| +CONFIG_NFS_V3_ACL=y | |
| +CONFIG_NFS_V4=y | |
| +# CONFIG_NFS_SWAP is not set | |
| +# CONFIG_NFS_V4_1 is not set | |
| +# CONFIG_NFS_FSCACHE is not set | |
| +# CONFIG_NFS_USE_LEGACY_DNS is not set | |
| +CONFIG_NFS_USE_KERNEL_DNS=y | |
| +CONFIG_NFSD=y | |
| +CONFIG_NFSD_V2_ACL=y | |
| +CONFIG_NFSD_V3=y | |
| +CONFIG_NFSD_V3_ACL=y | |
| +CONFIG_NFSD_V4=y | |
| +# CONFIG_NFSD_PNFS is not set | |
| +CONFIG_NFSD_V4_SECURITY_LABEL=y | |
| +CONFIG_GRACE_PERIOD=y | |
| +CONFIG_LOCKD=y | |
| +CONFIG_LOCKD_V4=y | |
| +CONFIG_NFS_ACL_SUPPORT=y | |
| +CONFIG_NFS_COMMON=y | |
| +CONFIG_SUNRPC=y | |
| +CONFIG_SUNRPC_GSS=y | |
| +CONFIG_RPCSEC_GSS_KRB5=y | |
| +# CONFIG_SUNRPC_DEBUG is not set | |
| +# CONFIG_CEPH_FS is not set | |
| +CONFIG_CIFS=y | |
| +# CONFIG_CIFS_STATS is not set | |
| +CONFIG_CIFS_WEAK_PW_HASH=y | |
| +CONFIG_CIFS_UPCALL=y | |
| +CONFIG_CIFS_XATTR=y | |
| +CONFIG_CIFS_POSIX=y | |
| +CONFIG_CIFS_ACL=y | |
| +CONFIG_CIFS_DEBUG=y | |
| +# CONFIG_CIFS_DEBUG2 is not set | |
| +CONFIG_CIFS_DFS_UPCALL=y | |
| +CONFIG_CIFS_SMB2=y | |
| +# CONFIG_CIFS_SMB311 is not set | |
| +# CONFIG_CIFS_FSCACHE is not set | |
| +# CONFIG_NCP_FS is not set | |
| +# CONFIG_CODA_FS is not set | |
| +# CONFIG_AFS_FS is not set | |
| +CONFIG_NLS=y | |
| +CONFIG_NLS_DEFAULT="iso8859-1" | |
| +CONFIG_NLS_CODEPAGE_437=y | |
| +# CONFIG_NLS_CODEPAGE_737 is not set | |
| +# CONFIG_NLS_CODEPAGE_775 is not set | |
| +CONFIG_NLS_CODEPAGE_850=y | |
| +# CONFIG_NLS_CODEPAGE_852 is not set | |
| +# CONFIG_NLS_CODEPAGE_855 is not set | |
| +# CONFIG_NLS_CODEPAGE_857 is not set | |
| +# CONFIG_NLS_CODEPAGE_860 is not set | |
| +# CONFIG_NLS_CODEPAGE_861 is not set | |
| +# CONFIG_NLS_CODEPAGE_862 is not set | |
| +# CONFIG_NLS_CODEPAGE_863 is not set | |
| +# CONFIG_NLS_CODEPAGE_864 is not set | |
| +# CONFIG_NLS_CODEPAGE_865 is not set | |
| +# CONFIG_NLS_CODEPAGE_866 is not set | |
| +# CONFIG_NLS_CODEPAGE_869 is not set | |
| +# CONFIG_NLS_CODEPAGE_936 is not set | |
| +# CONFIG_NLS_CODEPAGE_950 is not set | |
| +# CONFIG_NLS_CODEPAGE_932 is not set | |
| +# CONFIG_NLS_CODEPAGE_949 is not set | |
| +# CONFIG_NLS_CODEPAGE_874 is not set | |
| +# CONFIG_NLS_ISO8859_8 is not set | |
| +# CONFIG_NLS_CODEPAGE_1250 is not set | |
| +# CONFIG_NLS_CODEPAGE_1251 is not set | |
| +# CONFIG_NLS_ASCII is not set | |
| +CONFIG_NLS_ISO8859_1=y | |
| +CONFIG_NLS_ISO8859_2=y | |
| +# CONFIG_NLS_ISO8859_3 is not set | |
| +# CONFIG_NLS_ISO8859_4 is not set | |
| +# CONFIG_NLS_ISO8859_5 is not set | |
| +# CONFIG_NLS_ISO8859_6 is not set | |
| +# CONFIG_NLS_ISO8859_7 is not set | |
| +# CONFIG_NLS_ISO8859_9 is not set | |
| +# CONFIG_NLS_ISO8859_13 is not set | |
| +# CONFIG_NLS_ISO8859_14 is not set | |
| +# CONFIG_NLS_ISO8859_15 is not set | |
| +# CONFIG_NLS_KOI8_R is not set | |
| +# CONFIG_NLS_KOI8_U is not set | |
| +# CONFIG_NLS_MAC_ROMAN is not set | |
| +# CONFIG_NLS_MAC_CELTIC is not set | |
| +# CONFIG_NLS_MAC_CENTEURO is not set | |
| +# CONFIG_NLS_MAC_CROATIAN is not set | |
| +# CONFIG_NLS_MAC_CYRILLIC is not set | |
| +# CONFIG_NLS_MAC_GAELIC is not set | |
| +# CONFIG_NLS_MAC_GREEK is not set | |
| +# CONFIG_NLS_MAC_ICELAND is not set | |
| +# CONFIG_NLS_MAC_INUIT is not set | |
| +# CONFIG_NLS_MAC_ROMANIAN is not set | |
| +# CONFIG_NLS_MAC_TURKISH is not set | |
| +CONFIG_NLS_UTF8=y | |
| +# CONFIG_DLM is not set | |
| + | |
| +# | |
| +# Kernel hacking | |
| +# | |
| + | |
| +# | |
| +# printk and dmesg options | |
| +# | |
| +CONFIG_PRINTK_TIME=y | |
| +CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 | |
| +# CONFIG_BOOT_PRINTK_DELAY is not set | |
| + | |
| +# | |
| +# Compile-time checks and compiler options | |
| +# | |
| +CONFIG_DEBUG_INFO=y | |
| +CONFIG_DEBUG_INFO_REDUCED=y | |
| +# CONFIG_DEBUG_INFO_SPLIT is not set | |
| +# CONFIG_DEBUG_INFO_DWARF4 is not set | |
| +# CONFIG_GDB_SCRIPTS is not set | |
| +CONFIG_ENABLE_WARN_DEPRECATED=y | |
| +CONFIG_ENABLE_MUST_CHECK=y | |
| +CONFIG_FRAME_WARN=1024 | |
| +# CONFIG_STRIP_ASM_SYMS is not set | |
| +# CONFIG_READABLE_ASM is not set | |
| +# CONFIG_UNUSED_SYMBOLS is not set | |
| +# CONFIG_PAGE_OWNER is not set | |
| +# CONFIG_DEBUG_FS is not set | |
| +# CONFIG_HEADERS_CHECK is not set | |
| +# CONFIG_DEBUG_SECTION_MISMATCH is not set | |
| +CONFIG_SECTION_MISMATCH_WARN_ONLY=y | |
| +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set | |
| +CONFIG_MAGIC_SYSRQ=y | |
| +CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1 | |
| +CONFIG_DEBUG_KERNEL=y | |
| + | |
| +# | |
| +# Memory Debugging | |
| +# | |
| +# CONFIG_PAGE_EXTENSION is not set | |
| +# CONFIG_DEBUG_PAGEALLOC is not set | |
| +# CONFIG_DEBUG_OBJECTS is not set | |
| +# CONFIG_SLUB_DEBUG_ON is not set | |
| +# CONFIG_SLUB_STATS is not set | |
| +CONFIG_HAVE_DEBUG_KMEMLEAK=y | |
| +# CONFIG_DEBUG_KMEMLEAK is not set | |
| +# CONFIG_DEBUG_STACK_USAGE is not set | |
| +# CONFIG_DEBUG_VM is not set | |
| +# CONFIG_DEBUG_MEMORY_INIT is not set | |
| +# CONFIG_DEBUG_PER_CPU_MAPS is not set | |
| +# CONFIG_DEBUG_HIGHMEM is not set | |
| +# CONFIG_DEBUG_SHIRQ is not set | |
| + | |
| +# | |
| +# Debug Lockups and Hangs | |
| +# | |
| +CONFIG_LOCKUP_DETECTOR=y | |
| +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set | |
| +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 | |
| +# CONFIG_DETECT_HUNG_TASK is not set | |
| +CONFIG_PANIC_ON_OOPS=y | |
| +CONFIG_PANIC_ON_OOPS_VALUE=1 | |
| +CONFIG_PANIC_TIMEOUT=0 | |
| +CONFIG_SCHED_DEBUG=y | |
| +CONFIG_SCHED_INFO=y | |
| +# CONFIG_SCHEDSTATS is not set | |
| +# CONFIG_SCHED_STACK_END_CHECK is not set | |
| +# CONFIG_DEBUG_TIMEKEEPING is not set | |
| +# CONFIG_TIMER_STATS is not set | |
| + | |
| +# | |
| +# Lock Debugging (spinlocks, mutexes, etc...) | |
| +# | |
| +# CONFIG_DEBUG_RT_MUTEXES is not set | |
| +# CONFIG_DEBUG_SPINLOCK is not set | |
| +# CONFIG_DEBUG_MUTEXES is not set | |
| +# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set | |
| +# CONFIG_DEBUG_LOCK_ALLOC is not set | |
| +# CONFIG_PROVE_LOCKING is not set | |
| +# CONFIG_LOCK_STAT is not set | |
| +# CONFIG_DEBUG_ATOMIC_SLEEP is not set | |
| +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set | |
| +# CONFIG_LOCK_TORTURE_TEST is not set | |
| +CONFIG_STACKTRACE=y | |
| +# CONFIG_DEBUG_KOBJECT is not set | |
| +CONFIG_DEBUG_BUGVERBOSE=y | |
| +# CONFIG_DEBUG_LIST is not set | |
| +# CONFIG_DEBUG_PI_LIST is not set | |
| +# CONFIG_DEBUG_SG is not set | |
| +# CONFIG_DEBUG_NOTIFIERS is not set | |
| +# CONFIG_DEBUG_CREDENTIALS is not set | |
| + | |
| +# | |
| +# RCU Debugging | |
| +# | |
| +# CONFIG_PROVE_RCU is not set | |
| +# CONFIG_SPARSE_RCU_POINTER is not set | |
| +# CONFIG_TORTURE_TEST is not set | |
| +# CONFIG_RCU_TORTURE_TEST is not set | |
| +CONFIG_RCU_CPU_STALL_TIMEOUT=21 | |
| +# CONFIG_RCU_TRACE is not set | |
| +# CONFIG_RCU_EQS_DEBUG is not set | |
| +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set | |
| +# CONFIG_NOTIFIER_ERROR_INJECTION is not set | |
| +# CONFIG_FAULT_INJECTION is not set | |
| +CONFIG_HAVE_FUNCTION_TRACER=y | |
| +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y | |
| +CONFIG_HAVE_DYNAMIC_FTRACE=y | |
| +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y | |
| +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y | |
| +CONFIG_HAVE_C_RECORDMCOUNT=y | |
| +CONFIG_TRACING_SUPPORT=y | |
| +# CONFIG_FTRACE is not set | |
| + | |
| +# | |
| +# Runtime Testing | |
| +# | |
| +# CONFIG_TEST_LIST_SORT is not set | |
| +# CONFIG_BACKTRACE_SELF_TEST is not set | |
| +# CONFIG_RBTREE_TEST is not set | |
| +# CONFIG_INTERVAL_TREE_TEST is not set | |
| +# CONFIG_PERCPU_TEST is not set | |
| +# CONFIG_ATOMIC64_SELFTEST is not set | |
| +# CONFIG_ASYNC_RAID6_TEST is not set | |
| +# CONFIG_TEST_HEXDUMP is not set | |
| +# CONFIG_TEST_STRING_HELPERS is not set | |
| +# CONFIG_TEST_KSTRTOX is not set | |
| +# CONFIG_TEST_PRINTF is not set | |
| +# CONFIG_TEST_RHASHTABLE is not set | |
| +# CONFIG_DMA_API_DEBUG is not set | |
| +# CONFIG_TEST_LKM is not set | |
| +# CONFIG_TEST_USER_COPY is not set | |
| +# CONFIG_TEST_BPF is not set | |
| +# CONFIG_TEST_FIRMWARE is not set | |
| +# CONFIG_TEST_UDELAY is not set | |
| +# CONFIG_MEMTEST is not set | |
| +# CONFIG_TEST_STATIC_KEYS is not set | |
| +# CONFIG_SAMPLES is not set | |
| +CONFIG_HAVE_ARCH_KGDB=y | |
| +# CONFIG_KGDB is not set | |
| +# CONFIG_ARM_PTDUMP is not set | |
| +# CONFIG_STRICT_DEVMEM is not set | |
| +CONFIG_ARM_UNWIND=y | |
| +CONFIG_DEBUG_USER=y | |
| +# CONFIG_DEBUG_LL is not set | |
| +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" | |
| +# CONFIG_DEBUG_UART_8250 is not set | |
| +CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" | |
| +# CONFIG_PID_IN_CONTEXTIDR is not set | |
| +# CONFIG_DEBUG_SET_MODULE_RONX is not set | |
| +# CONFIG_CORESIGHT is not set | |
| + | |
| +# | |
| +# Security options | |
| +# | |
| +CONFIG_KEYS=y | |
| +# CONFIG_PERSISTENT_KEYRINGS is not set | |
| +# CONFIG_BIG_KEYS is not set | |
| +CONFIG_ENCRYPTED_KEYS=y | |
| +# CONFIG_SECURITY_DMESG_RESTRICT is not set | |
| +CONFIG_SECURITY=y | |
| +# CONFIG_SECURITYFS is not set | |
| +# CONFIG_SECURITY_NETWORK is not set | |
| +# CONFIG_SECURITY_PATH is not set | |
| +# CONFIG_SECURITY_SMACK is not set | |
| +# CONFIG_SECURITY_TOMOYO is not set | |
| +# CONFIG_SECURITY_APPARMOR is not set | |
| +# CONFIG_SECURITY_YAMA is not set | |
| +# CONFIG_INTEGRITY is not set | |
| +CONFIG_DEFAULT_SECURITY_DAC=y | |
| +CONFIG_DEFAULT_SECURITY="" | |
| +CONFIG_XOR_BLOCKS=y | |
| +CONFIG_ASYNC_CORE=y | |
| +CONFIG_ASYNC_MEMCPY=y | |
| +CONFIG_ASYNC_XOR=y | |
| +CONFIG_ASYNC_PQ=y | |
| +CONFIG_ASYNC_RAID6_RECOV=y | |
| +CONFIG_CRYPTO=y | |
| + | |
| +# | |
| +# Crypto core or helper | |
| +# | |
| +CONFIG_CRYPTO_ALGAPI=y | |
| +CONFIG_CRYPTO_ALGAPI2=y | |
| +CONFIG_CRYPTO_AEAD=y | |
| +CONFIG_CRYPTO_AEAD2=y | |
| +CONFIG_CRYPTO_BLKCIPHER=y | |
| +CONFIG_CRYPTO_BLKCIPHER2=y | |
| +CONFIG_CRYPTO_HASH=y | |
| +CONFIG_CRYPTO_HASH2=y | |
| +CONFIG_CRYPTO_RNG=y | |
| +CONFIG_CRYPTO_RNG2=y | |
| +CONFIG_CRYPTO_RNG_DEFAULT=y | |
| +CONFIG_CRYPTO_PCOMP2=y | |
| +CONFIG_CRYPTO_AKCIPHER2=y | |
| +# CONFIG_CRYPTO_RSA is not set | |
| +CONFIG_CRYPTO_MANAGER=y | |
| +CONFIG_CRYPTO_MANAGER2=y | |
| +CONFIG_CRYPTO_USER=y | |
| +CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y | |
| +CONFIG_CRYPTO_GF128MUL=y | |
| +CONFIG_CRYPTO_NULL=y | |
| +CONFIG_CRYPTO_NULL2=y | |
| +# CONFIG_CRYPTO_PCRYPT is not set | |
| +CONFIG_CRYPTO_WORKQUEUE=y | |
| +# CONFIG_CRYPTO_CRYPTD is not set | |
| +# CONFIG_CRYPTO_MCRYPTD is not set | |
| +CONFIG_CRYPTO_AUTHENC=y | |
| +# CONFIG_CRYPTO_TEST is not set | |
| + | |
| +# | |
| +# Authenticated Encryption with Associated Data | |
| +# | |
| +CONFIG_CRYPTO_CCM=y | |
| +# CONFIG_CRYPTO_GCM is not set | |
| +# CONFIG_CRYPTO_CHACHA20POLY1305 is not set | |
| +CONFIG_CRYPTO_SEQIV=y | |
| +# CONFIG_CRYPTO_ECHAINIV is not set | |
| + | |
| +# | |
| +# Block modes | |
| +# | |
| +CONFIG_CRYPTO_CBC=y | |
| +CONFIG_CRYPTO_CTR=y | |
| +CONFIG_CRYPTO_CTS=y | |
| +CONFIG_CRYPTO_ECB=y | |
| +CONFIG_CRYPTO_LRW=y | |
| +CONFIG_CRYPTO_PCBC=y | |
| +CONFIG_CRYPTO_XTS=y | |
| +CONFIG_CRYPTO_KEYWRAP=y | |
| + | |
| +# | |
| +# Hash modes | |
| +# | |
| +CONFIG_CRYPTO_CMAC=y | |
| +CONFIG_CRYPTO_HMAC=y | |
| +CONFIG_CRYPTO_XCBC=y | |
| +CONFIG_CRYPTO_VMAC=y | |
| + | |
| +# | |
| +# Digest | |
| +# | |
| +CONFIG_CRYPTO_CRC32C=y | |
| +# CONFIG_CRYPTO_CRC32 is not set | |
| +CONFIG_CRYPTO_CRCT10DIF=y | |
| +# CONFIG_CRYPTO_GHASH is not set | |
| +# CONFIG_CRYPTO_POLY1305 is not set | |
| +CONFIG_CRYPTO_MD4=y | |
| +CONFIG_CRYPTO_MD5=y | |
| +# CONFIG_CRYPTO_MICHAEL_MIC is not set | |
| +# CONFIG_CRYPTO_RMD128 is not set | |
| +# CONFIG_CRYPTO_RMD160 is not set | |
| +# CONFIG_CRYPTO_RMD256 is not set | |
| +# CONFIG_CRYPTO_RMD320 is not set | |
| +CONFIG_CRYPTO_SHA1=y | |
| +CONFIG_CRYPTO_SHA256=y | |
| +CONFIG_CRYPTO_SHA512=y | |
| +# CONFIG_CRYPTO_TGR192 is not set | |
| +# CONFIG_CRYPTO_WP512 is not set | |
| + | |
| +# | |
| +# Ciphers | |
| +# | |
| +CONFIG_CRYPTO_AES=y | |
| +# CONFIG_CRYPTO_ANUBIS is not set | |
| +CONFIG_CRYPTO_ARC4=y | |
| +CONFIG_CRYPTO_BLOWFISH=y | |
| +CONFIG_CRYPTO_BLOWFISH_COMMON=y | |
| +# CONFIG_CRYPTO_CAMELLIA is not set | |
| +# CONFIG_CRYPTO_CAST5 is not set | |
| +# CONFIG_CRYPTO_CAST6 is not set | |
| +CONFIG_CRYPTO_DES=y | |
| +# CONFIG_CRYPTO_FCRYPT is not set | |
| +# CONFIG_CRYPTO_KHAZAD is not set | |
| +# CONFIG_CRYPTO_SALSA20 is not set | |
| +# CONFIG_CRYPTO_CHACHA20 is not set | |
| +# CONFIG_CRYPTO_SEED is not set | |
| +# CONFIG_CRYPTO_SERPENT is not set | |
| +# CONFIG_CRYPTO_TEA is not set | |
| +# CONFIG_CRYPTO_TWOFISH is not set | |
| + | |
| +# | |
| +# Compression | |
| +# | |
| +CONFIG_CRYPTO_DEFLATE=y | |
| +# CONFIG_CRYPTO_ZLIB is not set | |
| +CONFIG_CRYPTO_LZO=y | |
| +# CONFIG_CRYPTO_842 is not set | |
| +# CONFIG_CRYPTO_LZ4 is not set | |
| +# CONFIG_CRYPTO_LZ4HC is not set | |
| + | |
| +# | |
| +# Random Number Generation | |
| +# | |
| +# CONFIG_CRYPTO_ANSI_CPRNG is not set | |
| +CONFIG_CRYPTO_DRBG_MENU=y | |
| +CONFIG_CRYPTO_DRBG_HMAC=y | |
| +# CONFIG_CRYPTO_DRBG_HASH is not set | |
| +# CONFIG_CRYPTO_DRBG_CTR is not set | |
| +CONFIG_CRYPTO_DRBG=y | |
| +CONFIG_CRYPTO_JITTERENTROPY=y | |
| +CONFIG_CRYPTO_USER_API=y | |
| +CONFIG_CRYPTO_USER_API_HASH=y | |
| +CONFIG_CRYPTO_USER_API_SKCIPHER=y | |
| +# CONFIG_CRYPTO_USER_API_RNG is not set | |
| +# CONFIG_CRYPTO_USER_API_AEAD is not set | |
| +CONFIG_CRYPTO_HW=y | |
| +# CONFIG_CRYPTO_DEV_HIFN_795X is not set | |
| +CONFIG_CRYPTO_DEV_AL_CRYPTO=y | |
| +CONFIG_CRYPTO_DEV_AL_CRYPTO_STATS=y | |
| +CONFIG_CRYPTO_DEV_AL_AHASH_CRC=y | |
| +# CONFIG_ASYMMETRIC_KEY_TYPE is not set | |
| + | |
| +# | |
| +# Certificates for signature checking | |
| +# | |
| +# CONFIG_SYSTEM_TRUSTED_KEYRING is not set | |
| +CONFIG_ARM_CRYPTO=y | |
| +CONFIG_CRYPTO_SHA1_ARM=y | |
| +CONFIG_CRYPTO_SHA256_ARM=y | |
| +CONFIG_CRYPTO_SHA512_ARM=y | |
| +CONFIG_CRYPTO_AES_ARM=y | |
| +# CONFIG_BINARY_PRINTF is not set | |
| + | |
| +# | |
| +# Library routines | |
| +# | |
| +CONFIG_RAID6_PQ=y | |
| +CONFIG_BITREVERSE=y | |
| +CONFIG_HAVE_ARCH_BITREVERSE=y | |
| +CONFIG_RATIONAL=y | |
| +CONFIG_GENERIC_STRNCPY_FROM_USER=y | |
| +CONFIG_GENERIC_STRNLEN_USER=y | |
| +CONFIG_GENERIC_NET_UTILS=y | |
| +CONFIG_GENERIC_PCI_IOMAP=y | |
| +CONFIG_GENERIC_IO=y | |
| +CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y | |
| +# CONFIG_CRC_CCITT is not set | |
| +CONFIG_CRC16=y | |
| +CONFIG_CRC_T10DIF=y | |
| +CONFIG_CRC_ITU_T=y | |
| +CONFIG_CRC32=y | |
| +# CONFIG_CRC32_SELFTEST is not set | |
| +CONFIG_CRC32_SLICEBY8=y | |
| +# CONFIG_CRC32_SLICEBY4 is not set | |
| +# CONFIG_CRC32_SARWATE is not set | |
| +# CONFIG_CRC32_BIT is not set | |
| +# CONFIG_CRC7 is not set | |
| +CONFIG_LIBCRC32C=y | |
| +# CONFIG_CRC8 is not set | |
| +# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set | |
| +# CONFIG_RANDOM32_SELFTEST is not set | |
| +CONFIG_ZLIB_INFLATE=y | |
| +CONFIG_ZLIB_DEFLATE=y | |
| +CONFIG_LZO_COMPRESS=y | |
| +CONFIG_LZO_DECOMPRESS=y | |
| +CONFIG_XZ_DEC=y | |
| +CONFIG_XZ_DEC_X86=y | |
| +CONFIG_XZ_DEC_POWERPC=y | |
| +CONFIG_XZ_DEC_IA64=y | |
| +CONFIG_XZ_DEC_ARM=y | |
| +CONFIG_XZ_DEC_ARMTHUMB=y | |
| +CONFIG_XZ_DEC_SPARC=y | |
| +CONFIG_XZ_DEC_BCJ=y | |
| +# CONFIG_XZ_DEC_TEST is not set | |
| +CONFIG_DECOMPRESS_GZIP=y | |
| +CONFIG_DECOMPRESS_LZMA=y | |
| +CONFIG_DECOMPRESS_XZ=y | |
| +CONFIG_GENERIC_ALLOCATOR=y | |
| +CONFIG_ASSOCIATIVE_ARRAY=y | |
| +CONFIG_HAS_IOMEM=y | |
| +CONFIG_HAS_IOPORT_MAP=y | |
| +CONFIG_HAS_DMA=y | |
| +CONFIG_CPU_RMAP=y | |
| +CONFIG_DQL=y | |
| +CONFIG_GLOB=y | |
| +# CONFIG_GLOB_SELFTEST is not set | |
| +CONFIG_NLATTR=y | |
| +CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y | |
| +# CONFIG_CORDIC is not set | |
| +# CONFIG_DDR is not set | |
| +CONFIG_LIBFDT=y | |
| +CONFIG_OID_REGISTRY=y | |
| +# CONFIG_SG_SPLIT is not set | |
| +CONFIG_ARCH_HAS_SG_CHAIN=y | |
| +# CONFIG_VIRTUALIZATION is not set | |
| diff -x .git -Naur linux-4.4.111/crypto/testmgr.c linux-4.4.111-alpine/crypto/testmgr.c | |
| --- linux-4.4.111/crypto/testmgr.c 2018-02-20 12:32:40.448080528 -0500 | |
| +++ linux-4.4.111-alpine/crypto/testmgr.c 2018-02-14 21:04:16.000000000 -0500 | |
| @@ -1689,14 +1689,20 @@ | |
| static int alg_test_crc32c(const struct alg_test_desc *desc, | |
| const char *driver, u32 type, u32 mask) | |
| { | |
| +#ifndef CONFIG_CRYPTO_DEV_AL_AHASH_CRC | |
| struct crypto_shash *tfm; | |
| u32 val; | |
| +#endif | |
| int err; | |
| err = alg_test_hash(desc, driver, type, mask); | |
| if (err) | |
| goto out; | |
| - | |
| +/** | |
| + * Removed the part of CRC self-test that assumes CRC is implemented as SHASH | |
| + * since AL crypto driver implement it as AHASH | |
| + */ | |
| +#ifndef CONFIG_CRYPTO_DEV_AL_AHASH_CRC | |
| tfm = crypto_alloc_shash(driver, type | CRYPTO_ALG_INTERNAL, mask); | |
| if (IS_ERR(tfm)) { | |
| printk(KERN_ERR "alg: crc32c: Failed to load transform for %s: " | |
| @@ -1728,7 +1734,7 @@ | |
| } while (0); | |
| crypto_free_shash(tfm); | |
| - | |
| +#endif | |
| out: | |
| return err; | |
| } | |
| diff -x .git -Naur linux-4.4.111/Documentation/devicetree/bindings/misc/hd44780-lcd.txt linux-4.4.111-alpine/Documentation/devicetree/bindings/misc/hd44780-lcd.txt | |
| --- linux-4.4.111/Documentation/devicetree/bindings/misc/hd44780-lcd.txt 1969-12-31 19:00:00.000000000 -0500 | |
| +++ linux-4.4.111-alpine/Documentation/devicetree/bindings/misc/hd44780-lcd.txt 2018-02-14 21:04:16.000000000 -0500 | |
| @@ -0,0 +1,33 @@ | |
| +Driver to drive Hitachi HD44780 based LCD displays through GPIO lines. | |
| + | |
| +This is a generic HD44780-based LCD driver not using GPIO. | |
| + | |
| +Required properties: | |
| +- compatible : should be "gpio-lcd" or "hd44780-lcd". | |
| +- lcm-bits : an array of 4 or 8 GPIO line references. The 3rd argument | |
| + (polarity or active high/low) is honored. | |
| + lcm-en, lcm-rs, lcm-rw : GPIO line references to the corresponding | |
| + HD44780 signals, EN, RS, and RW. | |
| + lcm-bl : a GPIO line reference to control LCD backlight. | |
| + locm-data-4bit : a boolean property to indicate 4-bit data mode. | |
| + | |
| +Optional properties: | |
| +- lcm-lines : the number of LCD lines (default is 2). The HD44780 does not | |
| + support more than 2 lines. | |
| +- lcm-cols : the number of LCD columns. Currently ignored. | |
| + | |
| +Example: | |
| + | |
| +gpio_lcd: gpio_lcd { | |
| + compatible = "gpio-lcd"; | |
| + lcm-data-4bit; | |
| + lcm-lines = <2>; | |
| + lcm-bits = <&gpio4 4 0>, | |
| + <&gpio4 5 0>, | |
| + <&gpio4 6 0>, | |
| + <&gpio4 7 0>; | |
| + lcm-rs = <&gpio4 3 0>; | |
| + lcm-bl = <&gpio5 0 0>; | |
| + lcm-rw = <&gpio5 1 0>; | |
| + lcm-en = <&gpio5 2 0>; | |
| +}; | |
| diff -x .git -Naur linux-4.4.111/Documentation/devicetree/bindings/misc/readynas-lcd.txt linux-4.4.111-alpine/Documentation/devicetree/bindings/misc/readynas-lcd.txt | |
| --- linux-4.4.111/Documentation/devicetree/bindings/misc/readynas-lcd.txt 1969-12-31 19:00:00.000000000 -0500 | |
| +++ linux-4.4.111-alpine/Documentation/devicetree/bindings/misc/readynas-lcd.txt 2018-02-14 21:04:16.000000000 -0500 | |
| @@ -0,0 +1,22 @@ | |
| +Driver to implement NETGEAR ReadyNAS's LCD user land API over the procfs | |
| +using the Hitachi HD44780 based LCD driver "gpio-lcd." | |
| + | |
| +This driver creates the following /proc entries: | |
| +/proc/LCD : 'echo 1 \"Hello\" > /proc/LCD' displays "Hello" on line #1. | |
| + : 'echo 2 \"World\" > /proc/LCD' displays "World" on line #2. | |
| + : 'echo 3 > /proc/LCD' turns LCD on. | |
| + : 'echo 4 > /proc/LCD' turns LCD off. | |
| + : 'echo 0 > /proc/LCD' clears LCD. | |
| +/proc/LCDstatus : a read-only entry to return LCD on/off status. | |
| +/proc/LCDinfo : a read-only entry to return LCD information | |
| + | |
| +Required properties: | |
| +- compatible : should be "readynas-lcd." | |
| +- lcd-device : a reference to the HD33780 device. | |
| + | |
| +Example: | |
| + | |
| +readynas_lcd { | |
| + compatible = "readynas-lcd"; | |
| + lcd-device = <&gpio_lcd>; | |
| +}; | |
| diff -x .git -Naur linux-4.4.111/Documentation/md-cluster.txt linux-4.4.111-alpine/Documentation/md-cluster.txt | |
| --- linux-4.4.111/Documentation/md-cluster.txt 2018-02-20 12:32:31.938047228 -0500 | |
| +++ linux-4.4.111-alpine/Documentation/md-cluster.txt 2018-02-14 21:04:16.000000000 -0500 | |
| @@ -3,7 +3,7 @@ | |
| 1. On-disk format | |
| -Separate write-intent-bitmap are used for each cluster node. | |
| +Separate write-intent-bitmaps are used for each cluster node. | |
| The bitmaps record all writes that may have been started on that node, | |
| and may not yet have finished. The on-disk layout is: | |
| @@ -14,117 +14,161 @@ | |
| | bm super[2] + bits | bm bits [2, contd] | bm super[3] + bits | | |
| | bm bits [3, contd] | | | | |
| -During "normal" functioning we assume the filesystem ensures that only one | |
| -node writes to any given block at a time, so a write | |
| -request will | |
| +During "normal" functioning we assume the filesystem ensures that only | |
| +one node writes to any given block at a time, so a write request will | |
| + | |
| - set the appropriate bit (if not already set) | |
| - commit the write to all mirrors | |
| - schedule the bit to be cleared after a timeout. | |
| -Reads are just handled normally. It is up to the filesystem to | |
| -ensure one node doesn't read from a location where another node (or the same | |
| +Reads are just handled normally. It is up to the filesystem to ensure | |
| +one node doesn't read from a location where another node (or the same | |
| node) is writing. | |
| 2. DLM Locks for management | |
| -There are two locks for managing the device: | |
| +There are three groups of locks for managing the device: | |
| 2.1 Bitmap lock resource (bm_lockres) | |
| - The bm_lockres protects individual node bitmaps. They are named in the | |
| - form bitmap001 for node 1, bitmap002 for node and so on. When a node | |
| - joins the cluster, it acquires the lock in PW mode and it stays so | |
| - during the lifetime the node is part of the cluster. The lock resource | |
| - number is based on the slot number returned by the DLM subsystem. Since | |
| - DLM starts node count from one and bitmap slots start from zero, one is | |
| - subtracted from the DLM slot number to arrive at the bitmap slot number. | |
| + The bm_lockres protects individual node bitmaps. They are named in | |
| + the form bitmap000 for node 1, bitmap001 for node 2 and so on. When a | |
| + node joins the cluster, it acquires the lock in PW mode and it stays | |
| + so during the lifetime the node is part of the cluster. The lock | |
| + resource number is based on the slot number returned by the DLM | |
| + subsystem. Since DLM starts node count from one and bitmap slots | |
| + start from zero, one is subtracted from the DLM slot number to arrive | |
| + at the bitmap slot number. | |
| + | |
| + The LVB of the bitmap lock for a particular node records the range | |
| + of sectors that are being re-synced by that node. No other | |
| + node may write to those sectors. This is used when a new nodes | |
| + joins the cluster. | |
| + | |
| +2.2 Message passing locks | |
| + | |
| + Each node has to communicate with other nodes when starting or ending | |
| + resync, and for metadata superblock updates. This communication is | |
| + managed through three locks: "token", "message", and "ack", together | |
| + with the Lock Value Block (LVB) of one of the "message" lock. | |
| + | |
| +2.3 new-device management | |
| + | |
| + A single lock: "no-new-dev" is used to co-ordinate the addition of | |
| + new devices - this must be synchronized across the array. | |
| + Normally all nodes hold a concurrent-read lock on this device. | |
| 3. Communication | |
| -Each node has to communicate with other nodes when starting or ending | |
| -resync, and metadata superblock updates. | |
| + Messages can be broadcast to all nodes, and the sender waits for all | |
| + other nodes to acknowledge the message before proceeding. Only one | |
| + message can be processed at a time. | |
| 3.1 Message Types | |
| - There are 3 types, of messages which are passed | |
| - | |
| - 3.1.1 METADATA_UPDATED: informs other nodes that the metadata has been | |
| - updated, and the node must re-read the md superblock. This is performed | |
| - synchronously. | |
| + There are six types of messages which are passed: | |
| - 3.1.2 RESYNC: informs other nodes that a resync is initiated or ended | |
| - so that each node may suspend or resume the region. | |
| + 3.1.1 METADATA_UPDATED: informs other nodes that the metadata has | |
| + been updated, and the node must re-read the md superblock. This is | |
| + performed synchronously. It is primarily used to signal device | |
| + failure. | |
| + | |
| + 3.1.2 RESYNCING: informs other nodes that a resync is initiated or | |
| + ended so that each node may suspend or resume the region. Each | |
| + RESYNCING message identifies a range of the devices that the | |
| + sending node is about to resync. This over-rides any pervious | |
| + notification from that node: only one ranged can be resynced at a | |
| + time per-node. | |
| + | |
| + 3.1.3 NEWDISK: informs other nodes that a device is being added to | |
| + the array. Message contains an identifier for that device. See | |
| + below for further details. | |
| + | |
| + 3.1.4 REMOVE: A failed or spare device is being removed from the | |
| + array. The slot-number of the device is included in the message. | |
| + | |
| + 3.1.5 RE_ADD: A failed device is being re-activated - the assumption | |
| + is that it has been determined to be working again. | |
| + | |
| + 3.1.6 BITMAP_NEEDS_SYNC: if a node is stopped locally but the bitmap | |
| + isn't clean, then another node is informed to take the ownership of | |
| + resync. | |
| 3.2 Communication mechanism | |
| The DLM LVB is used to communicate within nodes of the cluster. There | |
| are three resources used for the purpose: | |
| - 3.2.1 Token: The resource which protects the entire communication | |
| + 3.2.1 token: The resource which protects the entire communication | |
| system. The node having the token resource is allowed to | |
| communicate. | |
| - 3.2.2 Message: The lock resource which carries the data to | |
| + 3.2.2 message: The lock resource which carries the data to | |
| communicate. | |
| - 3.2.3 Ack: The resource, acquiring which means the message has been | |
| + 3.2.3 ack: The resource, acquiring which means the message has been | |
| acknowledged by all nodes in the cluster. The BAST of the resource | |
| - is used to inform the receive node that a node wants to communicate. | |
| + is used to inform the receiving node that a node wants to | |
| + communicate. | |
| The algorithm is: | |
| - 1. receive status | |
| + 1. receive status - all nodes have concurrent-reader lock on "ack". | |
| - sender receiver receiver | |
| - ACK:CR ACK:CR ACK:CR | |
| + sender receiver receiver | |
| + "ack":CR "ack":CR "ack":CR | |
| - 2. sender get EX of TOKEN | |
| - sender get EX of MESSAGE | |
| + 2. sender get EX on "token" | |
| + sender get EX on "message" | |
| sender receiver receiver | |
| - TOKEN:EX ACK:CR ACK:CR | |
| - MESSAGE:EX | |
| - ACK:CR | |
| - | |
| - Sender checks that it still needs to send a message. Messages received | |
| - or other events that happened while waiting for the TOKEN may have made | |
| - this message inappropriate or redundant. | |
| - | |
| - 3. sender write LVB. | |
| - sender down-convert MESSAGE from EX to CW | |
| - sender try to get EX of ACK | |
| - [ wait until all receiver has *processed* the MESSAGE ] | |
| + "token":EX "ack":CR "ack":CR | |
| + "message":EX | |
| + "ack":CR | |
| + | |
| + Sender checks that it still needs to send a message. Messages | |
| + received or other events that happened while waiting for the | |
| + "token" may have made this message inappropriate or redundant. | |
| + | |
| + 3. sender writes LVB. | |
| + sender down-convert "message" from EX to CW | |
| + sender try to get EX of "ack" | |
| + [ wait until all receivers have *processed* the "message" ] | |
| - [ triggered by bast of ACK ] | |
| - receiver get CR of MESSAGE | |
| + [ triggered by bast of "ack" ] | |
| + receiver get CR on "message" | |
| receiver read LVB | |
| receiver processes the message | |
| [ wait finish ] | |
| - receiver release ACK | |
| + receiver releases "ack" | |
| + receiver tries to get PR on "message" | |
| - sender receiver receiver | |
| - TOKEN:EX MESSAGE:CR MESSAGE:CR | |
| - MESSAGE:CR | |
| - ACK:EX | |
| - | |
| - 4. triggered by grant of EX on ACK (indicating all receivers have processed | |
| - message) | |
| - sender down-convert ACK from EX to CR | |
| - sender release MESSAGE | |
| - sender release TOKEN | |
| - receiver upconvert to PR of MESSAGE | |
| - receiver get CR of ACK | |
| - receiver release MESSAGE | |
| + sender receiver receiver | |
| + "token":EX "message":CR "message":CR | |
| + "message":CW | |
| + "ack":EX | |
| + | |
| + 4. triggered by grant of EX on "ack" (indicating all receivers | |
| + have processed message) | |
| + sender down-converts "ack" from EX to CR | |
| + sender releases "message" | |
| + sender releases "token" | |
| + receiver upconvert to PR on "message" | |
| + receiver get CR of "ack" | |
| + receiver release "message" | |
| sender receiver receiver | |
| - ACK:CR ACK:CR ACK:CR | |
| + "ack":CR "ack":CR "ack":CR | |
| 4. Handling Failures | |
| 4.1 Node Failure | |
| - When a node fails, the DLM informs the cluster with the slot. The node | |
| - starts a cluster recovery thread. The cluster recovery thread: | |
| + | |
| + When a node fails, the DLM informs the cluster with the slot | |
| + number. The node starts a cluster recovery thread. The cluster | |
| + recovery thread: | |
| + | |
| - acquires the bitmap<number> lock of the failed node | |
| - opens the bitmap | |
| - reads the bitmap of the failed node | |
| @@ -132,45 +176,149 @@ | |
| - cleans the bitmap of the failed node | |
| - releases bitmap<number> lock of the failed node | |
| - initiates resync of the bitmap on the current node | |
| + md_check_recovery is invoked within recover_bitmaps, | |
| + then md_check_recovery -> metadata_update_start/finish, | |
| + it will lock the communication by lock_comm. | |
| + Which means when one node is resyncing it blocks all | |
| + other nodes from writing anywhere on the array. | |
| - The resync process, is the regular md resync. However, in a clustered | |
| + The resync process is the regular md resync. However, in a clustered | |
| environment when a resync is performed, it needs to tell other nodes | |
| of the areas which are suspended. Before a resync starts, the node | |
| - send out RESYNC_START with the (lo,hi) range of the area which needs | |
| - to be suspended. Each node maintains a suspend_list, which contains | |
| - the list of ranges which are currently suspended. On receiving | |
| - RESYNC_START, the node adds the range to the suspend_list. Similarly, | |
| - when the node performing resync finishes, it send RESYNC_FINISHED | |
| - to other nodes and other nodes remove the corresponding entry from | |
| - the suspend_list. | |
| + send out RESYNCING with the (lo,hi) range of the area which needs to | |
| + be suspended. Each node maintains a suspend_list, which contains the | |
| + list of ranges which are currently suspended. On receiving RESYNCING, | |
| + the node adds the range to the suspend_list. Similarly, when the node | |
| + performing resync finishes, it sends RESYNCING with an empty range to | |
| + other nodes and other nodes remove the corresponding entry from the | |
| + suspend_list. | |
| - A helper function, should_suspend() can be used to check if a particular | |
| - I/O range should be suspended or not. | |
| + A helper function, ->area_resyncing() can be used to check if a | |
| + particular I/O range should be suspended or not. | |
| 4.2 Device Failure | |
| + | |
| Device failures are handled and communicated with the metadata update | |
| - routine. | |
| + routine. When a node detects a device failure it does not allow | |
| + any further writes to that device until the failure has been | |
| + acknowledged by all other nodes. | |
| 5. Adding a new Device | |
| -For adding a new device, it is necessary that all nodes "see" the new device | |
| -to be added. For this, the following algorithm is used: | |
| + | |
| + For adding a new device, it is necessary that all nodes "see" the new | |
| + device to be added. For this, the following algorithm is used: | |
| 1. Node 1 issues mdadm --manage /dev/mdX --add /dev/sdYY which issues | |
| - ioctl(ADD_NEW_DISC with disc.state set to MD_DISK_CLUSTER_ADD) | |
| - 2. Node 1 sends NEWDISK with uuid and slot number | |
| + ioctl(ADD_NEW_DISK with disc.state set to MD_DISK_CLUSTER_ADD) | |
| + 2. Node 1 sends a NEWDISK message with uuid and slot number | |
| 3. Other nodes issue kobject_uevent_env with uuid and slot number | |
| (Steps 4,5 could be a udev rule) | |
| 4. In userspace, the node searches for the disk, perhaps | |
| using blkid -t SUB_UUID="" | |
| - 5. Other nodes issue either of the following depending on whether the disk | |
| - was found: | |
| + 5. Other nodes issue either of the following depending on whether | |
| + the disk was found: | |
| ioctl(ADD_NEW_DISK with disc.state set to MD_DISK_CANDIDATE and | |
| - disc.number set to slot number) | |
| + disc.number set to slot number) | |
| ioctl(CLUSTERED_DISK_NACK) | |
| - 6. Other nodes drop lock on no-new-devs (CR) if device is found | |
| - 7. Node 1 attempts EX lock on no-new-devs | |
| - 8. If node 1 gets the lock, it sends METADATA_UPDATED after unmarking the disk | |
| - as SpareLocal | |
| - 9. If not (get no-new-dev lock), it fails the operation and sends METADATA_UPDATED | |
| - 10. Other nodes get the information whether a disk is added or not | |
| - by the following METADATA_UPDATED. | |
| + 6. Other nodes drop lock on "no-new-devs" (CR) if device is found | |
| + 7. Node 1 attempts EX lock on "no-new-dev" | |
| + 8. If node 1 gets the lock, it sends METADATA_UPDATED after | |
| + unmarking the disk as SpareLocal | |
| + 9. If not (get "no-new-dev" lock), it fails the operation and sends | |
| + METADATA_UPDATED. | |
| + 10. Other nodes get the information whether a disk is added or not | |
| + by the following METADATA_UPDATED. | |
| + | |
| +6. Module interface. | |
| + | |
| + There are 17 call-backs which the md core can make to the cluster | |
| + module. Understanding these can give a good overview of the whole | |
| + process. | |
| + | |
| +6.1 join(nodes) and leave() | |
| + | |
| + These are called when an array is started with a clustered bitmap, | |
| + and when the array is stopped. join() ensures the cluster is | |
| + available and initializes the various resources. | |
| + Only the first 'nodes' nodes in the cluster can use the array. | |
| + | |
| +6.2 slot_number() | |
| + | |
| + Reports the slot number advised by the cluster infrastructure. | |
| + Range is from 0 to nodes-1. | |
| + | |
| +6.3 resync_info_update() | |
| + | |
| + This updates the resync range that is stored in the bitmap lock. | |
| + The starting point is updated as the resync progresses. The | |
| + end point is always the end of the array. | |
| + It does *not* send a RESYNCING message. | |
| + | |
| +6.4 resync_start(), resync_finish() | |
| + | |
| + These are called when resync/recovery/reshape starts or stops. | |
| + They update the resyncing range in the bitmap lock and also | |
| + send a RESYNCING message. resync_start reports the whole | |
| + array as resyncing, resync_finish reports none of it. | |
| + | |
| + resync_finish() also sends a BITMAP_NEEDS_SYNC message which | |
| + allows some other node to take over. | |
| + | |
| +6.5 metadata_update_start(), metadata_update_finish(), | |
| + metadata_update_cancel(). | |
| + | |
| + metadata_update_start is used to get exclusive access to | |
| + the metadata. If a change is still needed once that access is | |
| + gained, metadata_update_finish() will send a METADATA_UPDATE | |
| + message to all other nodes, otherwise metadata_update_cancel() | |
| + can be used to release the lock. | |
| + | |
| +6.6 area_resyncing() | |
| + | |
| + This combines two elements of functionality. | |
| + | |
| + Firstly, it will check if any node is currently resyncing | |
| + anything in a given range of sectors. If any resync is found, | |
| + then the caller will avoid writing or read-balancing in that | |
| + range. | |
| + | |
| + Secondly, while node recovery is happening it reports that | |
| + all areas are resyncing for READ requests. This avoids races | |
| + between the cluster-filesystem and the cluster-RAID handling | |
| + a node failure. | |
| + | |
| +6.7 add_new_disk_start(), add_new_disk_finish(), new_disk_ack() | |
| + | |
| + These are used to manage the new-disk protocol described above. | |
| + When a new device is added, add_new_disk_start() is called before | |
| + it is bound to the array and, if that succeeds, add_new_disk_finish() | |
| + is called the device is fully added. | |
| + | |
| + When a device is added in acknowledgement to a previous | |
| + request, or when the device is declared "unavailable", | |
| + new_disk_ack() is called. | |
| + | |
| +6.8 remove_disk() | |
| + | |
| + This is called when a spare or failed device is removed from | |
| + the array. It causes a REMOVE message to be send to other nodes. | |
| + | |
| +6.9 gather_bitmaps() | |
| + | |
| + This sends a RE_ADD message to all other nodes and then | |
| + gathers bitmap information from all bitmaps. This combined | |
| + bitmap is then used to recovery the re-added device. | |
| + | |
| +6.10 lock_all_bitmaps() and unlock_all_bitmaps() | |
| + | |
| + These are called when change bitmap to none. If a node plans | |
| + to clear the cluster raid's bitmap, it need to make sure no other | |
| + nodes are using the raid which is achieved by lock all bitmap | |
| + locks within the cluster, and also those locks are unlocked | |
| + accordingly. | |
| + | |
| +7. Unsupported features | |
| + | |
| +There are somethings which are not supported by cluster MD yet. | |
| + | |
| +- update size and change array_sectors. | |
| diff -x .git -Naur linux-4.4.111/drivers/acpi/acpica/evgpe.c linux-4.4.111-alpine/drivers/acpi/acpica/evgpe.c | |
| --- linux-4.4.111/drivers/acpi/acpica/evgpe.c 2018-02-20 12:32:40.578081036 -0500 | |
| +++ linux-4.4.111-alpine/drivers/acpi/acpica/evgpe.c 2018-02-14 21:04:16.000000000 -0500 | |
| @@ -677,6 +677,11 @@ | |
| return (AE_OK); | |
| } | |
| +extern bool readynas_ignore_acpi_event(u32); | |
| +#define READYNAS_IGNORE_ACPI(d, e, n) \ | |
| + do { if (readynas_ignore_acpi_event(n)) \ | |
| + return_UINT32(ACPI_INTERRUPT_HANDLED); \ | |
| + } while (0) | |
| /******************************************************************************* | |
| * | |
| @@ -703,7 +708,7 @@ | |
| u32 return_value; | |
| ACPI_FUNCTION_TRACE(ev_gpe_dispatch); | |
| - | |
| + READYNAS_IGNORE_ACPI(gpe_device, gpe_event_info, gpe_number); | |
| /* | |
| * Always disable the GPE so that it does not keep firing before | |
| * any asynchronous activity completes (either from the execution | |
| diff -x .git -Naur linux-4.4.111/drivers/ata/ahci_alpine.c linux-4.4.111-alpine/drivers/ata/ahci_alpine.c | |
| --- linux-4.4.111/drivers/ata/ahci_alpine.c 1969-12-31 19:00:00.000000000 -0500 | |
| +++ linux-4.4.111-alpine/drivers/ata/ahci_alpine.c 2018-02-14 21:04:17.000000000 -0500 | |
| @@ -0,0 +1,133 @@ | |
| +/* | |
| + * ahci.c - AHCI SATA support | |
| + * | |
| + * Maintained by: Tejun Heo <tj@kernel.org> | |
| + * Please ALWAYS copy linux-ide@vger.kernel.org | |
| + * on emails. | |
| + * | |
| + * Copyright 2004-2005 Red Hat, Inc. | |
| + * | |
| + * | |
| + * This program is free software; you can redistribute it and/or modify | |
| + * it under the terms of the GNU General Public License as published by | |
| + * the Free Software Foundation; either version 2, or (at your option) | |
| + * any later version. | |
| + * | |
| + * This program is distributed in the hope that it will be useful, | |
| + * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| + * GNU General Public License for more details. | |
| + * | |
| + * You should have received a copy of the GNU General Public License | |
| + * along with this program; see the file COPYING. If not, write to | |
| + * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
| + * | |
| + * | |
| + * libata documentation is available via 'make {ps|pdf}docs', | |
| + * as Documentation/DocBook/libata.* | |
| + * | |
| + * AHCI hardware documentation: | |
| + * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf | |
| + * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf | |
| + * | |
| + */ | |
| +#include <linux/kernel.h> | |
| +#include <linux/module.h> | |
| +#include <linux/pci.h> | |
| +#include <linux/blkdev.h> | |
| +#include <linux/delay.h> | |
| +#include <linux/interrupt.h> | |
| +#include <linux/dma-mapping.h> | |
| +#include <linux/device.h> | |
| +#include <linux/dmi.h> | |
| +#include <linux/gfp.h> | |
| +#include <scsi/scsi_host.h> | |
| +#include <scsi/scsi_cmnd.h> | |
| +#include <linux/libata.h> | |
| +#include "ahci.h" | |
| +#include "ahci_alpine.h" | |
| + | |
| +#include <soc/alpine/al_hal_iofic.h> | |
| +#include <soc/alpine/al_hal_iofic_regs.h> | |
| + | |
| +#define al_ahci_iofic_base(base) ((base) + 0x2000) | |
| + | |
| +struct alpine_host_priv { | |
| + /* for msix interrupts */ | |
| + unsigned int msix_vecs; | |
| + struct msix_entry msix_entries[]; | |
| +}; | |
| + | |
| +void ahci_port_intr(struct ata_port *ap); | |
| + | |
| +int al_init_msix_interrupts(struct pci_dev *pdev, unsigned int n_ports, | |
| + struct ahci_host_priv *hpriv) | |
| +{ | |
| + int i, rc; | |
| + void __iomem *iofic_base = al_ahci_iofic_base(hpriv->mmio); | |
| + struct alpine_host_priv *al_data; | |
| + | |
| + hpriv->plat_data = NULL; | |
| + | |
| + al_data = kzalloc( | |
| + sizeof(unsigned int) + n_ports * sizeof(struct msix_entry), GFP_KERNEL); | |
| + | |
| + if (!al_data) | |
| + return -ENOMEM; | |
| + | |
| + al_data->msix_vecs = n_ports; | |
| + | |
| + for (i = 0; i < n_ports; i++) { | |
| + /* entries 0-2 are in group A */ | |
| + al_data->msix_entries[i].entry = 3 + i; | |
| + al_data->msix_entries[i].vector = 0; | |
| + } | |
| + | |
| + rc = pci_enable_msix_exact(pdev, al_data->msix_entries, n_ports); | |
| + | |
| + if (rc) { | |
| + dev_info(&pdev->dev,"failed to enable MSIX, vectors %d rc %d\n", | |
| + n_ports, rc); | |
| + kfree(al_data); | |
| + return -EPERM; | |
| + } | |
| + | |
| + /* we use only group B */ | |
| + al_iofic_config(iofic_base, 1 /*GROUP_B*/, | |
| + INT_CONTROL_GRP_SET_ON_POSEDGE | | |
| + INT_CONTROL_GRP_AUTO_CLEAR | | |
| + INT_CONTROL_GRP_AUTO_MASK | | |
| + INT_CONTROL_GRP_CLEAR_ON_READ); | |
| + | |
| + al_iofic_moder_res_config(iofic_base, 1, 15); | |
| + | |
| + al_iofic_unmask(iofic_base, 1, (1 << n_ports) - 1); | |
| + | |
| + hpriv->plat_data = al_data; | |
| + | |
| + return n_ports; | |
| +} | |
| +EXPORT_SYMBOL(al_init_msix_interrupts); | |
| + | |
| +void alpine_clean_cause(struct ata_port *ap_this) | |
| +{ | |
| + struct ata_host *host = ap_this->host; | |
| + struct ahci_host_priv *hpriv = host->private_data; | |
| + void __iomem *iofic_base = al_ahci_iofic_base(hpriv->mmio); | |
| + | |
| + /* clean host cause */ | |
| + writel(1 << ap_this->port_no, hpriv->mmio + HOST_IRQ_STAT); | |
| + | |
| + /* unmask the interrupt in the iofic (auto-masked) */ | |
| + al_iofic_unmask(iofic_base, 1, 1 << ap_this->port_no); | |
| +} | |
| +EXPORT_SYMBOL(alpine_clean_cause); | |
| + | |
| +int al_port_irq(struct ata_host *host, int port) | |
| +{ | |
| + struct ahci_host_priv *hpriv = host->private_data; | |
| + struct alpine_host_priv *al_priv = hpriv->plat_data; | |
| + | |
| + return al_priv->msix_entries[port].vector; | |
| +} | |
| +EXPORT_SYMBOL(al_port_irq); | |
| diff -x .git -Naur linux-4.4.111/drivers/ata/ahci_alpine.h linux-4.4.111-alpine/drivers/ata/ahci_alpine.h | |
| --- linux-4.4.111/drivers/ata/ahci_alpine.h 1969-12-31 19:00:00.000000000 -0500 | |
| +++ linux-4.4.111-alpine/drivers/ata/ahci_alpine.h 2018-02-14 21:04:17.000000000 -0500 | |
| @@ -0,0 +1,26 @@ | |
| +#ifndef _AHCI_ALPINE_H | |
| +#define _AHCI_ALPINE_H | |
| + | |
| +#ifdef CONFIG_AHCI_ALPINE | |
| + | |
| +extern int al_init_msix_interrupts(struct pci_dev *pdev, | |
| + unsigned int n_ports, struct ahci_host_priv *hpriv); | |
| + | |
| +extern void alpine_clean_cause(struct ata_port *ap_this); | |
| + | |
| +extern int al_port_irq(struct ata_host *host, int port); | |
| +#else | |
| + | |
| +static inline int al_init_msix_interrupts(struct pci_dev *pdev, | |
| + unsigned int n_ports, struct ahci_host_priv *hpriv) | |
| +{ return 0; } | |
| + | |
| +static inline void alpine_clean_cause(struct ata_port *ap_this) | |
| +{}; | |
| + | |
| +static inline int al_port_irq(struct ata_host *host, int port) | |
| +{ return -EINVAL; }; | |
| + | |
| +#endif | |
| + | |
| +#endif /* _AHCI_ALPINE_H */ | |
| diff -x .git -Naur linux-4.4.111/drivers/ata/ahci.c linux-4.4.111-alpine/drivers/ata/ahci.c | |
| --- linux-4.4.111/drivers/ata/ahci.c 2018-02-20 12:32:40.808081936 -0500 | |
| +++ linux-4.4.111-alpine/drivers/ata/ahci.c 2018-02-14 21:04:17.000000000 -0500 | |
| @@ -31,7 +31,6 @@ | |
| * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf | |
| * | |
| */ | |
| - | |
| #include <linux/kernel.h> | |
| #include <linux/module.h> | |
| #include <linux/pci.h> | |
| @@ -47,6 +46,7 @@ | |
| #include <scsi/scsi_cmnd.h> | |
| #include <linux/libata.h> | |
| #include "ahci.h" | |
| +#include "ahci_alpine.h" | |
| #define DRV_NAME "ahci" | |
| #define DRV_VERSION "3.0" | |
| @@ -68,6 +68,7 @@ | |
| board_ahci_yes_fbs, | |
| /* board IDs for specific chipsets in alphabetical order */ | |
| + board_ahci_alpine, | |
| board_ahci_avn, | |
| board_ahci_mcp65, | |
| board_ahci_mcp77, | |
| @@ -161,6 +162,13 @@ | |
| .port_ops = &ahci_ops, | |
| }, | |
| /* by chipsets */ | |
| + [board_ahci_alpine] = { | |
| + AHCI_HFLAGS (AHCI_HFLAG_NO_PMP | AHCI_HFLAG_AL_MSIX | AHCI_HFLAG_MULTI_MSI), | |
| + .flags = AHCI_FLAG_COMMON | ATA_FLAG_SW_ACTIVITY, | |
| + .pio_mask = ATA_PIO4, | |
| + .udma_mask = ATA_UDMA6, | |
| + .port_ops = &ahci_ops, | |
| + }, | |
| [board_ahci_avn] = { | |
| .flags = AHCI_FLAG_COMMON, | |
| .pio_mask = ATA_PIO4, | |
| @@ -400,6 +408,10 @@ | |
| { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */ | |
| { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */ | |
| +#ifdef CONFIG_AHCI_ALPINE | |
| + /* Annapurna Labs */ | |
| + { PCI_VDEVICE(ANNAPURNA_LABS, 0x0031), board_ahci_alpine }, /* 0031 */ | |
| +#endif | |
| /* AMD */ | |
| { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */ | |
| { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */ | |
| @@ -1346,6 +1358,14 @@ | |
| if (hpriv->flags & AHCI_HFLAG_NO_MSI) | |
| return -ENODEV; | |
| + pr_debug("al pdev->vendor: %d anpa: %d\n", pdev->vendor, PCI_VENDOR_ID_ANNAPURNA_LABS); | |
| + if (pdev->vendor == PCI_VENDOR_ID_ANNAPURNA_LABS) { | |
| + nvec = al_init_msix_interrupts(pdev, n_ports, hpriv); | |
| + pr_debug("init msix interrupts returned: %d\n", nvec); | |
| + if (nvec > 0) | |
| + return nvec; | |
| + } | |
| + | |
| nvec = pci_msix_vec_count(pdev); | |
| if (nvec < 0) | |
| return nvec; | |
| @@ -1424,6 +1444,7 @@ | |
| return nvec; | |
| } | |
| + | |
| static int ahci_init_interrupts(struct pci_dev *pdev, unsigned int n_ports, | |
| struct ahci_host_priv *hpriv) | |
| { | |
| diff -x .git -Naur linux-4.4.111/drivers/ata/ahci.h linux-4.4.111-alpine/drivers/ata/ahci.h | |
| --- linux-4.4.111/drivers/ata/ahci.h 2018-02-20 12:32:40.818081975 -0500 | |
| +++ linux-4.4.111-alpine/drivers/ata/ahci.h 2018-02-14 21:04:17.000000000 -0500 | |
| @@ -181,8 +181,6 @@ | |
| PORT_CMD_ALPE = (1 << 26), /* Aggressive Link PM enable */ | |
| PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */ | |
| PORT_CMD_FBSCP = (1 << 22), /* FBS Capable Port */ | |
| - PORT_CMD_ESP = (1 << 21), /* External Sata Port */ | |
| - PORT_CMD_HPCP = (1 << 18), /* HotPlug Capable Port */ | |
| PORT_CMD_PMP = (1 << 17), /* PMP attached */ | |
| PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */ | |
| PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */ | |
| @@ -242,6 +240,7 @@ | |
| AHCI_HFLAG_NO_FBS = (1 << 18), /* no FBS */ | |
| AHCI_HFLAG_EDGE_IRQ = (1 << 19), /* HOST_IRQ_STAT behaves as | |
| Edge Triggered */ | |
| + AHCI_HFLAG_AL_MSIX = (1 << 20), /* alpine msix */ | |
| /* ap->flags bits */ | |
| diff -x .git -Naur linux-4.4.111/drivers/ata/Kconfig linux-4.4.111-alpine/drivers/ata/Kconfig | |
| --- linux-4.4.111/drivers/ata/Kconfig 2018-02-20 12:32:40.788081858 -0500 | |
| +++ linux-4.4.111-alpine/drivers/ata/Kconfig 2018-02-14 21:04:17.000000000 -0500 | |
| @@ -151,6 +151,15 @@ | |
| If unsure, say N. | |
| +config AHCI_ALPINE | |
| + bool "Annapurna labs Alpine AHCI SATA support" | |
| + depends on ARCH_ALPINE | |
| + help | |
| + This option enables support for the Alpine SoC's | |
| + onboard AHCI SATA. | |
| + | |
| + If unsure, say N. | |
| + | |
| config AHCI_SUNXI | |
| tristate "Allwinner sunxi AHCI SATA support" | |
| depends on ARCH_SUNXI | |
| diff -x .git -Naur linux-4.4.111/drivers/ata/libahci.c linux-4.4.111-alpine/drivers/ata/libahci.c | |
| --- linux-4.4.111/drivers/ata/libahci.c 2018-02-20 12:32:40.848082093 -0500 | |
| +++ linux-4.4.111-alpine/drivers/ata/libahci.c 2018-02-14 21:04:17.000000000 -0500 | |
| @@ -31,9 +31,9 @@ | |
| * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf | |
| * | |
| */ | |
| - | |
| #include <linux/kernel.h> | |
| #include <linux/gfp.h> | |
| +#include <linux/pci.h> | |
| #include <linux/module.h> | |
| #include <linux/blkdev.h> | |
| #include <linux/delay.h> | |
| @@ -43,9 +43,13 @@ | |
| #include <scsi/scsi_host.h> | |
| #include <scsi/scsi_cmnd.h> | |
| #include <linux/libata.h> | |
| +#include <linux/gpio.h> | |
| #include "ahci.h" | |
| +#include "ahci_alpine.h" | |
| #include "libata.h" | |
| +#define RN20X_ACT_LED_GPIO 474 | |
| + | |
| static int ahci_skip_host_reset; | |
| int ahci_ignore_sss; | |
| EXPORT_SYMBOL_GPL(ahci_ignore_sss); | |
| @@ -496,8 +500,8 @@ | |
| } | |
| } | |
| - /* fabricate port_map from cap.nr_ports for < AHCI 1.3 */ | |
| - if (!port_map && vers < 0x10300) { | |
| + /* fabricate port_map from cap.nr_ports */ | |
| + if (!port_map) { | |
| port_map = (1 << ahci_nr_ports(cap)) - 1; | |
| dev_warn(dev, "forcing PORTS_IMPL to 0x%x\n", port_map); | |
| @@ -577,6 +581,7 @@ | |
| return -EINVAL; | |
| } | |
| +static void do_marvell_9170_recover(struct ata_port *ap, int reset); | |
| void ahci_start_engine(struct ata_port *ap) | |
| { | |
| void __iomem *port_mmio = ahci_port_base(ap); | |
| @@ -587,6 +592,7 @@ | |
| tmp |= PORT_CMD_START; | |
| writel(tmp, port_mmio + PORT_CMD); | |
| readl(port_mmio + PORT_CMD); /* flush */ | |
| + do_marvell_9170_recover(ap, 0); | |
| } | |
| EXPORT_SYMBOL_GPL(ahci_start_engine); | |
| @@ -950,9 +956,8 @@ | |
| emp->saved_activity = emp->activity = 0; | |
| setup_timer(&emp->timer, ahci_sw_activity_blink, (unsigned long)link); | |
| - /* check our blink policy and set flag for link if it's enabled */ | |
| - if (emp->blink_policy) | |
| - link->flags |= ATA_LFLAG_SW_ACTIVITY; | |
| + /* our default blink policy is to enable */ | |
| + link->flags |= ATA_LFLAG_SW_ACTIVITY; | |
| } | |
| int ahci_reset_em(struct ata_host *host) | |
| @@ -973,12 +978,9 @@ | |
| static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state, | |
| ssize_t size) | |
| { | |
| - struct ahci_host_priv *hpriv = ap->host->private_data; | |
| struct ahci_port_priv *pp = ap->private_data; | |
| - void __iomem *mmio = hpriv->mmio; | |
| - u32 em_ctl; | |
| - u32 message[] = {0, 0}; | |
| unsigned long flags; | |
| + int led_val = 0; | |
| int pmp; | |
| struct ahci_em_priv *emp; | |
| @@ -991,37 +993,12 @@ | |
| spin_lock_irqsave(ap->lock, flags); | |
| - /* | |
| - * if we are still busy transmitting a previous message, | |
| - * do not allow | |
| - */ | |
| - em_ctl = readl(mmio + HOST_EM_CTL); | |
| - if (em_ctl & EM_CTL_TM) { | |
| - spin_unlock_irqrestore(ap->lock, flags); | |
| - return -EBUSY; | |
| - } | |
| - | |
| - if (hpriv->em_msg_type & EM_MSG_TYPE_LED) { | |
| - /* | |
| - * create message header - this is all zero except for | |
| - * the message size, which is 4 bytes. | |
| - */ | |
| - message[0] |= (4 << 8); | |
| - | |
| - /* ignore 0:4 of byte zero, fill in port info yourself */ | |
| - message[1] = ((state & ~EM_MSG_LED_HBA_PORT) | ap->port_no); | |
| + if (state & EM_MSG_LED_VALUE_ON) | |
| + led_val = 1; | |
| - /* write message to EM_LOC */ | |
| - writel(message[0], mmio + hpriv->em_loc); | |
| - writel(message[1], mmio + hpriv->em_loc+4); | |
| + gpio_set_value(RN20X_ACT_LED_GPIO, led_val); | |
| - /* | |
| - * tell hardware to transmit the message | |
| - */ | |
| - writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL); | |
| - } | |
| - | |
| - /* save off new led state for port/slot */ | |
| + /* save new led state */ | |
| emp->led_state = state; | |
| spin_unlock_irqrestore(ap->lock, flags); | |
| @@ -1118,7 +1095,6 @@ | |
| int port_no, void __iomem *mmio, | |
| void __iomem *port_mmio) | |
| { | |
| - struct ahci_host_priv *hpriv = ap->host->private_data; | |
| const char *emsg = NULL; | |
| int rc; | |
| u32 tmp; | |
| @@ -1140,11 +1116,6 @@ | |
| writel(tmp, port_mmio + PORT_IRQ_STAT); | |
| writel(1 << port_no, mmio + HOST_IRQ_STAT); | |
| - | |
| - /* mark esata ports */ | |
| - tmp = readl(port_mmio + PORT_CMD); | |
| - if ((tmp & PORT_CMD_ESP) && (hpriv->cap & HOST_CAP_SXS)) | |
| - ap->pflags |= ATA_PFLAG_EXTERNAL; | |
| } | |
| void ahci_init_controller(struct ata_host *host) | |
| @@ -1449,6 +1420,173 @@ | |
| return rc; | |
| } | |
| +/* | |
| + * Special chip reset/recover for RN3130/3138 Marvell SATA called in | |
| + * ahci_hardreset(). | |
| + */ | |
| +#include <linux/gpio.h> | |
| +#include <linux/pci.h> | |
| +#include "../platform/readynas/readynas-io.h" | |
| + | |
| +static void marvell_9170_save_pci_dev(struct pci_dev *pdev, void __iomem *mmio, | |
| + u32 pci[][4], u32 dev[][4], int idx) | |
| +{ | |
| + int i; | |
| + | |
| + for (i = 0; pci[i][0] != 0xffffffff; i++) { | |
| + if (!pci[i][3]) | |
| + pci_read_config_dword(pdev, pci[i][0], &pci[i][idx]); | |
| + pr_info("%s: pci[%x]=%x\n", __func__, pci[i][0], pci[i][idx]); | |
| + } | |
| + for (i = 0; dev[i][0] != 0xffffffff; i++) { | |
| + if (!dev[i][3]) | |
| + dev[i][idx] = readl(mmio + dev[i][0]); | |
| + pr_info("%s: dev[%x]=%x\n", __func__, dev[i][0], dev[i][idx]); | |
| + } | |
| +} | |
| + | |
| +static void marvell_9170_restore_pci_dev(struct pci_dev *pdev, | |
| + void __iomem *mmio, | |
| + u32 pci[][4], u32 dev[][4], int idx) | |
| +{ | |
| + int i; | |
| + | |
| + for (i = 0; pci[i][0] != 0xffffffff; i++) { | |
| + pr_err("%s: pci[%x]=%x\n", __func__, pci[i][0], pci[i][idx]); | |
| + pci_write_config_dword(pdev, pci[i][0], pci[i][idx]); | |
| + } | |
| + for (i = 0; dev[i][0] != 0xffffffff; i++) { | |
| + pr_err("%s: dev[%x]=%x\n", __func__, dev[i][0], dev[i][idx]); | |
| + writel(dev[i][idx], mmio + dev[i][0]); | |
| + } | |
| +} | |
| + | |
| +static void (*marvell_9170_recover)(struct ata_port *ap, int reset); | |
| +static void do_marvell_9170_recover(struct ata_port *ap, int reset) | |
| +{ | |
| +#ifdef CONFIG_X86_64 | |
| + struct ata_host *host = ap->host; | |
| + struct pci_dev *pdev = to_pci_dev(host->dev); | |
| + struct ahci_host_priv *hpriv = host->private_data; | |
| + void __iomem *mmio = hpriv->mmio; | |
| + | |
| + static u32 __pci[][4] = { | |
| + {0x04,}, {0x0c,}, | |
| + {0x10,}, {0x14,}, {0x18,}, {0x1c,}, {0x20,}, {0x24,}, {0x30,}, | |
| + {0x3c,}, {0x44,}, {0x50,}, | |
| + {0x54,}, | |
| + {0x58,}, {0x78,}, {0x80,}, {0xa0,}, | |
| + {0xffffffff,} | |
| + }; | |
| + static u32 __dev[][4] = { | |
| + {0x004, 0x80000002, 0x80000002, 1}, | |
| + {0x100,}, {0x104,}, {0x108,}, {0x10c,}, | |
| + {0x110, 0xffffffff, 0xffffffff, 1}, /* PORT_IRQ_STAT */ | |
| + {0x114, 0x7840007f, 0x7840007f, 1}, /* PORT_IRQ_MASK */ | |
| + {0x118, 0x710011, 0x710011, 1}, | |
| + {0x180,}, {0x184,}, {0x188,}, {0x18c,}, | |
| + {0x190, 0xffffffff, 0xffffffff, 1}, /* PORT_IRQ_STAT */ | |
| + {0x194, 0x7840007f, 0x7840007f, 1}, /* PORT_IRQ_MASK */ | |
| + {0x198, 0x710011, 0x710011, 1}, | |
| + {0xffffffff,} | |
| + }; | |
| + | |
| + static struct gpio_chip *gc; | |
| + static struct gpio_desc *gd; | |
| + static unsigned long prev_jiffies, base_jiffies; | |
| + static void __iomem *mmio2, *mmio4; | |
| + static struct pci_dev *pdev2, *pdev4; | |
| + | |
| + unsigned long now = jiffies; | |
| + | |
| + if (!base_jiffies) | |
| + base_jiffies = now; | |
| + if (pdev->vendor != PCI_VENDOR_ID_MARVELL_EXT || | |
| + pdev->device != 0x9170) { | |
| + pr_info("%s: ignoring PCI device (%04x:%04x) at PCI#%d\n", | |
| + __func__, | |
| + pdev->vendor, pdev->device, pdev->bus->number); | |
| + return; | |
| + } | |
| + if (!readynas_io_compatible("rn3130") && | |
| + !readynas_io_compatible("rn3138")) { | |
| + pr_info("%s: not right model\n", __func__); | |
| + return; | |
| + } | |
| + if (pdev->bus->number == 2) { | |
| + mmio2 = mmio; | |
| + pdev2 = pdev; | |
| + } else if (pdev->bus->number == 4) { | |
| + mmio4 = mmio; | |
| + pdev4 = pdev; | |
| + } | |
| + | |
| + if (!reset) {/* Update to-be-restored register value copies. */ | |
| + marvell_9170_recover = do_marvell_9170_recover; | |
| + pr_info("%s: start_engine() called for PCI#%d port %d\n", | |
| + __func__, pdev->bus->number, ap->port_no); | |
| + if (pdev2) { | |
| + pr_info("%s: saving PCI#2 and DEV\n", __func__); | |
| + marvell_9170_save_pci_dev(pdev2, mmio2, | |
| + __pci, __dev, 1); | |
| + } | |
| + if (pdev4) { | |
| + pr_info("%s: saving PCI#4 and DEV\n", __func__); | |
| + marvell_9170_save_pci_dev(pdev4, mmio4, | |
| + __pci, __dev, 2); | |
| + } | |
| + return; | |
| + } | |
| + | |
| + /* Assert GPIO signal to reset chip and restore registers only for | |
| + * internal (PCI#2) SATA. | |
| + */ | |
| + if (pdev->bus->number != 2) | |
| + return; | |
| + | |
| + if (time_before(now, base_jiffies + HZ * 20)) { | |
| + prev_jiffies = now; | |
| + pr_info("%s: still booting\n", __func__); | |
| + return; | |
| + } | |
| + if (time_before(now, prev_jiffies + HZ * 30)) { | |
| + prev_jiffies = now; | |
| + pr_info("%s: too short since last\n", __func__); | |
| + return; | |
| + } | |
| + prev_jiffies = now; | |
| + if (!gc) { | |
| + gc = rn_gpiochip_find_by_label("gpio_it87"); | |
| + if (IS_ERR_OR_NULL(gc)) { | |
| + pr_err("%s: cannot find gpio_it87\n", __func__); | |
| + return; | |
| + } | |
| + } | |
| + if (!gd) { | |
| + gd = gpiochip_get_desc(gc, 11); | |
| + if (IS_ERR_OR_NULL(gd)) { | |
| + pr_err("%s: cannot get gpio_it87 port 11\n", __func__); | |
| + return; | |
| + } | |
| + } | |
| + pr_err("%s: hardreset() called for PCI#%d port %d\n", | |
| + __func__, pdev->bus->number, ap->port_no); | |
| + gpiod_direction_output(gd, 0); | |
| + mdelay(50); | |
| + gpiod_direction_input(gd); | |
| + msleep(500); | |
| + if (pdev2) { | |
| + pr_err("%s: restoring PCI#2 and DEV\n", __func__); | |
| + marvell_9170_restore_pci_dev(pdev2, mmio2, __pci, __dev, 1); | |
| + } | |
| + if (pdev4) { | |
| + pr_err("%s: restoring PCI#4 and DEV\n", __func__); | |
| + marvell_9170_restore_pci_dev(pdev4, mmio4, __pci, __dev, 2); | |
| + } | |
| + msleep(500); | |
| +#endif /* CONFIG_X86_64 */ | |
| +} | |
| + | |
| static int ahci_hardreset(struct ata_link *link, unsigned int *class, | |
| unsigned long deadline) | |
| { | |
| @@ -1463,6 +1601,8 @@ | |
| DPRINTK("ENTER\n"); | |
| + if (marvell_9170_recover) | |
| + marvell_9170_recover(ap, 1); | |
| ahci_stop_engine(ap); | |
| /* clear D2H reception area to properly wait for D2H FIS */ | |
| @@ -1810,6 +1950,9 @@ | |
| struct ahci_port_priv *pp = ap->private_data; | |
| void __iomem *port_mmio = ahci_port_base(ap); | |
| u32 status; | |
| +#ifdef CONFIG_AHCI_ALPINE | |
| + struct ata_host *host = ap->host; | |
| +#endif | |
| status = atomic_xchg(&pp->intr_status, 0); | |
| if (!status) | |
| @@ -1819,6 +1962,12 @@ | |
| ahci_handle_port_interrupt(ap, port_mmio, status); | |
| spin_unlock_bh(ap->lock); | |
| +#ifdef CONFIG_AHCI_ALPINE | |
| + spin_lock(&host->lock); | |
| + alpine_clean_cause(ap); | |
| + spin_unlock(&host->lock); | |
| +#endif | |
| + | |
| return IRQ_HANDLED; | |
| } | |
| @@ -1947,6 +2096,38 @@ | |
| return IRQ_RETVAL(rc); | |
| } | |
| +#ifdef CONFIG_AHCI_ALPINE | |
| + | |
| +/* 1 on not anapurna, 0 on success, <0 on error */ | |
| +static int al_ahci_request_irq(struct ata_host *host, int port) | |
| +{ | |
| + int port_irq; | |
| + struct ahci_port_priv *pp = host->ports[port]->private_data; | |
| + struct ahci_host_priv *hpriv = host->private_data; | |
| + | |
| + if (!(hpriv->flags & AHCI_HFLAG_AL_MSIX)) { | |
| + pr_debug("al_ahci_request_irq no msix\n"); | |
| + return 1; | |
| + } | |
| + port_irq = al_port_irq(host,port); | |
| + pr_debug("al_ahci_request_irq port: %d\n", port); | |
| + if (port_irq < 0) | |
| + return port_irq; | |
| + | |
| + return devm_request_threaded_irq(host->dev, port_irq, | |
| + ahci_multi_irqs_intr, | |
| + ahci_port_thread_fn, 0, | |
| + pp->irq_desc, host->ports[port]); | |
| +} | |
| + | |
| +#else /* CONFIG_AHCI_ALPINE */ | |
| + | |
| +static int al_ahci_request_irq(struct ata_host *host, int port) | |
| +{ | |
| + return 1; | |
| +} | |
| +#endif /* CONFIG_AHCI_ALPINE */ | |
| + | |
| unsigned int ahci_qc_issue(struct ata_queued_cmd *qc) | |
| { | |
| struct ata_port *ap = qc->ap; | |
| @@ -2484,6 +2665,7 @@ | |
| { | |
| int i, rc; | |
| + pr_debug("ahci_host_activate_multi_irqs\n"); | |
| rc = ata_host_start(host); | |
| if (rc) | |
| return rc; | |
| @@ -2500,7 +2682,10 @@ | |
| continue; | |
| } | |
| - rc = devm_request_threaded_irq(host->dev, irq + i, | |
| + rc = al_ahci_request_irq(host, i); | |
| + pr_debug("al_ahci_request_irq returned: %d\n",rc); | |
| + if (rc >0) | |
| + rc = devm_request_threaded_irq(host->dev, irq + i, | |
| ahci_multi_irqs_intr, | |
| ahci_port_thread_fn, 0, | |
| pp->irq_desc, host->ports[i]); | |
| diff -x .git -Naur linux-4.4.111/drivers/ata/libata-scsi.c linux-4.4.111-alpine/drivers/ata/libata-scsi.c | |
| --- linux-4.4.111/drivers/ata/libata-scsi.c 2018-02-20 12:32:40.978082602 -0500 | |
| +++ linux-4.4.111-alpine/drivers/ata/libata-scsi.c 2018-02-14 21:04:17.000000000 -0500 | |
| @@ -2012,11 +2012,8 @@ | |
| VPRINTK("ENTER\n"); | |
| - /* set scsi removable (RMB) bit per ata bit, or if the | |
| - * AHCI port says it's external (Hotplug-capable, eSATA). | |
| - */ | |
| - if (ata_id_removable(args->id) || | |
| - (args->dev->link->ap->pflags & ATA_PFLAG_EXTERNAL)) | |
| + /* set scsi removable (RMB) bit per ata bit */ | |
| + if (ata_id_removable(args->id)) | |
| hdr[1] |= (1 << 7); | |
| if (args->dev->class == ATA_DEV_ZAC) { | |
| diff -x .git -Naur linux-4.4.111/drivers/ata/libata-transport.c linux-4.4.111-alpine/drivers/ata/libata-transport.c | |
| --- linux-4.4.111/drivers/ata/libata-transport.c 2018-02-20 12:32:40.978082602 -0500 | |
| +++ linux-4.4.111-alpine/drivers/ata/libata-transport.c 2018-02-14 21:04:17.000000000 -0500 | |
| @@ -39,7 +39,7 @@ | |
| #define ATA_PORT_ATTRS 3 | |
| #define ATA_LINK_ATTRS 3 | |
| -#define ATA_DEV_ATTRS 9 | |
| +#define ATA_DEV_ATTRS 10 | |
| struct scsi_transport_template; | |
| struct scsi_transport_template *ata_scsi_transport_template; | |
| @@ -581,6 +581,58 @@ | |
| static DEVICE_ATTR(trim, S_IRUGO, show_ata_dev_trim, NULL); | |
| +static unsigned int | |
| +sata_pmp_gscr_write(struct ata_link *link, int reg, u32 val) | |
| +{ | |
| + struct ata_port *ap = link->ap; | |
| + struct ata_device *pmp_dev = ap->link.device; | |
| + struct ata_taskfile tf; | |
| + unsigned int ret; | |
| + | |
| + if (ap->nr_active_links) | |
| + return ATA_DEFER_PORT; | |
| + | |
| + ata_tf_init(pmp_dev, &tf); | |
| + tf.command = ATA_CMD_PMP_WRITE; | |
| + tf.protocol = ATA_PROT_NODATA; | |
| + tf.flags |= ATA_TFLAG_ISADDR | ATA_TFLAG_DEVICE | ATA_TFLAG_LBA48; | |
| + tf.feature = reg; | |
| + tf.device = link->pmp; | |
| + tf.nsect = val & 0xff; | |
| + tf.lbal = (val >> 8) & 0xff; | |
| + tf.lbam = (val >> 16) & 0xff; | |
| + tf.lbah = (val >> 24) & 0xff; | |
| + | |
| + ata_eh_acquire(ap); | |
| + ret = ata_exec_internal(pmp_dev, &tf, NULL, DMA_NONE, NULL, 0, | |
| + SATA_PMP_RW_TIMEOUT); | |
| + ata_eh_release(ap); | |
| + | |
| + return ret; | |
| +} | |
| + | |
| +static ssize_t | |
| +set_ata_dev_gpio(struct device *dev, struct device_attribute *attr, | |
| + const char *buf, size_t count) | |
| +{ | |
| + struct ata_device *ata_dev = transport_class_to_dev(dev); | |
| + u32 val = simple_strtol(buf, NULL, 16); | |
| + unsigned int ret; | |
| + | |
| + if (ata_dev->class != ATA_DEV_PMP) | |
| + return 0; | |
| + ret = sata_pmp_gscr_write(ata_dev->link, 130, val); | |
| + if (ret) { | |
| + if (ret == ATA_DEFER_PORT) | |
| + return -EBUSY; | |
| + else | |
| + return -EINVAL; | |
| + } | |
| + return count; | |
| +} | |
| + | |
| +static DEVICE_ATTR(gpio, S_IWUSR, NULL, set_ata_dev_gpio); | |
| + | |
| static DECLARE_TRANSPORT_CLASS(ata_dev_class, | |
| "ata_device", NULL, NULL, NULL); | |
| @@ -699,6 +751,9 @@ | |
| #define SETUP_DEV_ATTRIBUTE(field) \ | |
| SETUP_TEMPLATE(dev_attrs, field, S_IRUGO, 1) | |
| +#define SETUP_GPIO_ATTRIBUTE(field) \ | |
| + SETUP_TEMPLATE(dev_attrs, field, S_IWUSR, 1) | |
| + | |
| /** | |
| * ata_attach_transport -- instantiate ATA transport template | |
| */ | |
| @@ -754,6 +809,7 @@ | |
| SETUP_DEV_ATTRIBUTE(id); | |
| SETUP_DEV_ATTRIBUTE(gscr); | |
| SETUP_DEV_ATTRIBUTE(trim); | |
| + SETUP_GPIO_ATTRIBUTE(gpio); | |
| BUG_ON(count > ATA_DEV_ATTRS); | |
| i->dev_attrs[count] = NULL; | |
| diff -x .git -Naur linux-4.4.111/drivers/ata/Makefile linux-4.4.111-alpine/drivers/ata/Makefile | |
| --- linux-4.4.111/drivers/ata/Makefile 2018-02-20 12:32:40.788081858 -0500 | |
| +++ linux-4.4.111-alpine/drivers/ata/Makefile 2018-02-14 21:04:17.000000000 -0500 | |
| @@ -10,6 +10,7 @@ | |
| obj-$(CONFIG_SATA_SIL24) += sata_sil24.o | |
| obj-$(CONFIG_SATA_DWC) += sata_dwc_460ex.o | |
| obj-$(CONFIG_SATA_HIGHBANK) += sata_highbank.o libahci.o | |
| +obj-$(CONFIG_AHCI_ALPINE) += ahci_alpine.o libahci.o libahci_platform.o | |
| obj-$(CONFIG_AHCI_BRCMSTB) += ahci_brcmstb.o libahci.o libahci_platform.o | |
| obj-$(CONFIG_AHCI_CEVA) += ahci_ceva.o libahci.o libahci_platform.o | |
| obj-$(CONFIG_AHCI_DA850) += ahci_da850.o libahci.o libahci_platform.o | |
| diff -x .git -Naur linux-4.4.111/drivers/clk/mvebu/common.c linux-4.4.111-alpine/drivers/clk/mvebu/common.c | |
| --- linux-4.4.111/drivers/clk/mvebu/common.c 2018-02-20 12:32:41.498084637 -0500 | |
| +++ linux-4.4.111-alpine/drivers/clk/mvebu/common.c 2018-02-14 21:04:16.000000000 -0500 | |
| @@ -62,6 +62,8 @@ | |
| goto out; | |
| } | |
| + sscg_reg = readl(sscg_map + 0x3EC) & 0xFF; | |
| + system_clk -= (0x2F - sscg_reg) * 25000000; | |
| sscg_reg = readl(sscg_map); | |
| high_bound = SSCG_CONF_HIGH(sscg_reg); | |
| low_bound = SSCG_CONF_LOW(sscg_reg); | |
| diff -x .git -Naur linux-4.4.111/drivers/crypto/al/al_crypto_alg.c linux-4.4.111-alpine/drivers/crypto/al/al_crypto_alg.c | |
| --- linux-4.4.111/drivers/crypto/al/al_crypto_alg.c 1969-12-31 19:00:00.000000000 -0500 | |
| +++ linux-4.4.111-alpine/drivers/crypto/al/al_crypto_alg.c 2018-02-14 21:04:16.000000000 -0500 | |
| @@ -0,0 +1,811 @@ | |
| +/* | |
| + * drivers/crypto/al_crypto_alg.c | |
| + * | |
| + * Annapurna Labs Crypto driver - ablckcipher algorithms | |
| + * | |
| + * Copyright (C) 2012 Annapurna Labs Ltd. | |
| + * | |
| + * Algorithm registration code and chained scatter/gather lists | |
| + * handling based on caam driver. | |
| + * | |
| + * This program is free software; you can redistribute it and/or modify | |
| + * it under the terms of the GNU General Public License as published by | |
| + * the Free Software Foundation; either version 2 of the License, or | |
| + * (at your option) any later version. | |
| + * | |
| + * This program is distributed in the hope that it will be useful, | |
| + * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| + * GNU General Public License for more details. | |
| + * | |
| + * You should have received a copy of the GNU General Public License | |
| + * along with this program; if not, write to the Free Software | |
| + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
| + */ | |
| + | |
| + | |
| +/* | |
| +#ifndef DEBUG | |
| +#define DEBUG | |
| +#endif | |
| +*/ | |
| + | |
| +#include "linux/export.h" | |
| +#include "linux/crypto.h" | |
| +#include <linux/rtnetlink.h> | |
| +#include <linux/random.h> | |
| +#include <crypto/algapi.h> | |
| +#include <crypto/aes.h> | |
| +#include <crypto/des.h> | |
| +#include <linux/scatterlist.h> | |
| +#include <crypto/internal/skcipher.h> | |
| +#include <crypto/sha.h> | |
| +#include <crypto/hash.h> | |
| +#include <crypto/authenc.h> | |
| + | |
| +#include <soc/alpine/al_hal_ssm_crypto.h> | |
| + | |
| +#include "al_crypto.h" | |
| + | |
| +#define AL_CRYPTO_CRA_PRIORITY 300 | |
| + | |
| + | |
| + | |
| + | |
| +static int ablkcipher_setkey_des(struct crypto_ablkcipher *ablkcipher, | |
| + const u8 *key, unsigned int keylen); | |
| + | |
| +static int ablkcipher_setkey_aes(struct crypto_ablkcipher *ablkcipher, | |
| + const u8 *key, unsigned int keylen); | |
| + | |
| +static int ablkcipher_encrypt(struct ablkcipher_request *req); | |
| + | |
| +static int ablkcipher_decrypt(struct ablkcipher_request *req); | |
| + | |
| +struct al_crypto_ablkcipher_req_ctx { | |
| + enum al_crypto_dir dir; | |
| +}; | |
| + | |
| +struct al_crypto_alg_template { | |
| + char name[CRYPTO_MAX_ALG_NAME]; | |
| + char driver_name[CRYPTO_MAX_ALG_NAME]; | |
| + unsigned int blocksize; | |
| + uint32_t type; | |
| + union { | |
| + struct ablkcipher_alg ablkcipher; | |
| + struct blkcipher_alg blkcipher; | |
| + struct cipher_alg cipher; | |
| + struct compress_alg compress; | |
| + } template_u; | |
| + enum al_crypto_sa_enc_type enc_type; | |
| + enum al_crypto_sa_op sa_op; | |
| + enum al_crypto_sa_auth_type auth_type; | |
| + enum al_crypto_sa_sha2_mode sha2_mode; | |
| + char sw_hash_name[CRYPTO_MAX_ALG_NAME]; | |
| + unsigned int sw_hash_interm_offset; | |
| + unsigned int sw_hash_interm_size; | |
| +}; | |
| + | |
| +static struct al_crypto_alg_template driver_algs[] = { | |
| + { | |
| + .name = "cbc(aes)", | |
| + .driver_name = "cbc-aes-al", | |
| + .blocksize = AES_BLOCK_SIZE, | |
| + .type = CRYPTO_ALG_TYPE_ABLKCIPHER, | |
| + .template_u.ablkcipher = { | |
| + .setkey = ablkcipher_setkey_aes, | |
| + .encrypt = ablkcipher_encrypt, | |
| + .decrypt = ablkcipher_decrypt, | |
| + .geniv = "eseqiv", | |
| + .min_keysize = AES_MIN_KEY_SIZE, | |
| + .max_keysize = AES_MAX_KEY_SIZE, | |
| + .ivsize = AES_BLOCK_SIZE, | |
| + }, | |
| + .enc_type = AL_CRYPT_AES_CBC, | |
| + .sa_op = AL_CRYPT_ENC_ONLY, | |
| + }, | |
| + { | |
| + .name = "ecb(aes)", | |
| + .driver_name = "ecb-aes-al", | |
| + .blocksize = AES_BLOCK_SIZE, | |
| + .type = CRYPTO_ALG_TYPE_ABLKCIPHER, | |
| + .template_u.ablkcipher = { | |
| + .setkey = ablkcipher_setkey_aes, | |
| + .encrypt = ablkcipher_encrypt, | |
| + .decrypt = ablkcipher_decrypt, | |
| + .min_keysize = AES_MIN_KEY_SIZE, | |
| + .max_keysize = AES_MAX_KEY_SIZE, | |
| + .ivsize = AES_BLOCK_SIZE, | |
| + }, | |
| + .enc_type = AL_CRYPT_AES_ECB, | |
| + .sa_op = AL_CRYPT_ENC_ONLY, | |
| + }, | |
| + { | |
| + .name = "ctr(aes)", | |
| + .driver_name = "ctr-aes-al", | |
| + .blocksize = AES_BLOCK_SIZE, | |
| + .type = CRYPTO_ALG_TYPE_ABLKCIPHER, | |
| + .template_u.ablkcipher = { | |
| + .setkey = ablkcipher_setkey_aes, | |
| + .encrypt = ablkcipher_encrypt, | |
| + .decrypt = ablkcipher_decrypt, | |
| + .geniv = "eseqiv", | |
| + .min_keysize = AES_MIN_KEY_SIZE, | |
| + .max_keysize = AES_MAX_KEY_SIZE, | |
| + .ivsize = AES_BLOCK_SIZE, | |
| + }, | |
| + .enc_type = AL_CRYPT_AES_CTR, | |
| + .sa_op = AL_CRYPT_ENC_ONLY, | |
| + }, | |
| + { | |
| + .name = "cbc(des)", | |
| + .driver_name = "cbc-des-al", | |
| + .blocksize = DES_BLOCK_SIZE, | |
| + .type = CRYPTO_ALG_TYPE_ABLKCIPHER, | |
| + .template_u.ablkcipher = { | |
| + .setkey = ablkcipher_setkey_des, | |
| + .encrypt = ablkcipher_encrypt, | |
| + .decrypt = ablkcipher_decrypt, | |
| + .geniv = "eseqiv", | |
| + .min_keysize = DES_KEY_SIZE, | |
| + .max_keysize = DES_KEY_SIZE, | |
| + .ivsize = DES_BLOCK_SIZE, | |
| + }, | |
| + .enc_type = AL_CRYPT_DES_CBC, | |
| + .sa_op = AL_CRYPT_ENC_ONLY, | |
| + }, | |
| + { | |
| + .name = "ecb(des)", | |
| + .driver_name = "ecb-des-al", | |
| + .blocksize = DES_BLOCK_SIZE, | |
| + .type = CRYPTO_ALG_TYPE_ABLKCIPHER, | |
| + .template_u.ablkcipher = { | |
| + .setkey = ablkcipher_setkey_des, | |
| + .encrypt = ablkcipher_encrypt, | |
| + .decrypt = ablkcipher_decrypt, | |
| + .min_keysize = DES_KEY_SIZE, | |
| + .max_keysize = DES_KEY_SIZE, | |
| + .ivsize = 0, | |
| + }, | |
| + .enc_type = AL_CRYPT_DES_ECB, | |
| + .sa_op = AL_CRYPT_ENC_ONLY, | |
| + }, | |
| + { | |
| + .name = "ecb(des3_ede)", | |
| + .driver_name = "ecb-des3-ede-al", | |
| + .blocksize = DES3_EDE_KEY_SIZE, | |
| + .type = CRYPTO_ALG_TYPE_ABLKCIPHER, | |
| + .template_u.ablkcipher = { | |
| + .setkey = ablkcipher_setkey_des, | |
| + .encrypt = ablkcipher_encrypt, | |
| + .decrypt = ablkcipher_decrypt, | |
| + .min_keysize = DES3_EDE_KEY_SIZE, | |
| + .max_keysize = DES3_EDE_KEY_SIZE, | |
| + .ivsize = 0, | |
| + }, | |
| + .enc_type = AL_CRYPT_TRIPDES_ECB, | |
| + .sa_op = AL_CRYPT_ENC_ONLY, | |
| + }, | |
| + { | |
| + .name = "cbc(des3_ede)", | |
| + .driver_name = "cbc-des3-ede-al", | |
| + .blocksize = DES_BLOCK_SIZE, | |
| + .type = CRYPTO_ALG_TYPE_ABLKCIPHER, | |
| + .template_u.ablkcipher = { | |
| + .setkey = ablkcipher_setkey_des, | |
| + .encrypt = ablkcipher_encrypt, | |
| + .decrypt = ablkcipher_decrypt, | |
| + .geniv = "eseqiv", | |
| + .min_keysize = DES3_EDE_KEY_SIZE, | |
| + .max_keysize = DES3_EDE_KEY_SIZE, | |
| + .ivsize = DES_BLOCK_SIZE, | |
| + }, | |
| + .enc_type = AL_CRYPT_TRIPDES_CBC, | |
| + .sa_op = AL_CRYPT_ENC_ONLY, | |
| + }, | |
| +}; | |
| + | |
| +struct al_crypto_alg { | |
| + struct list_head entry; | |
| + struct al_crypto_device *device; | |
| + enum al_crypto_sa_enc_type enc_type; | |
| + enum al_crypto_sa_op sa_op; | |
| + enum al_crypto_sa_auth_type auth_type; | |
| + enum al_crypto_sa_sha2_mode sha2_mode; | |
| + char sw_hash_name[CRYPTO_MAX_ALG_NAME]; | |
| + unsigned int sw_hash_interm_offset; | |
| + unsigned int sw_hash_interm_size; | |
| + struct crypto_alg crypto_alg; | |
| +}; | |
| + | |
| +/****************************************************************************** | |
| + *****************************************************************************/ | |
| +static int al_crypto_cra_init(struct crypto_tfm *tfm) | |
| +{ | |
| + struct crypto_alg *alg = tfm->__crt_alg; | |
| + struct al_crypto_alg *al_crypto_alg = | |
| + container_of(alg, struct al_crypto_alg, crypto_alg); | |
| + struct al_crypto_ctx *ctx = crypto_tfm_ctx(tfm); | |
| + struct al_crypto_device *device = al_crypto_alg->device; | |
| + int chan_idx = atomic_inc_return(&device->tfm_count) % | |
| + (device->num_channels - device->crc_channels); | |
| + | |
| + dev_dbg(&device->pdev->dev, "%s\n", __func__); | |
| + | |
| + memset(ctx, 0, sizeof(struct al_crypto_ctx)); | |
| + memset(&ctx->sa, 0, sizeof(struct al_crypto_sa)); | |
| + | |
| + ctx->chan = device->channels[chan_idx]; | |
| + | |
| + ctx->sa.enc_type = al_crypto_alg->enc_type; | |
| + ctx->sa.sa_op = al_crypto_alg->sa_op; | |
| + ctx->hw_sa = dma_alloc_coherent(&device->pdev->dev, | |
| + sizeof(struct al_crypto_hw_sa), | |
| + &ctx->hw_sa_dma_addr, | |
| + GFP_KERNEL); | |
| + | |
| + return 0; | |
| +} | |
| + | |
| +/****************************************************************************** | |
| + *****************************************************************************/ | |
| +static int al_crypto_cra_init_ablkcipher(struct crypto_tfm *tfm) | |
| +{ | |
| + struct al_crypto_ctx *ctx = crypto_tfm_ctx(tfm); | |
| + | |
| + al_crypto_cra_init(tfm); | |
| + | |
| + tfm->crt_ablkcipher.reqsize = | |
| + sizeof(struct al_crypto_ablkcipher_req_ctx); | |
| + | |
| + AL_CRYPTO_STATS_LOCK(&ctx->chan->stats_gen_lock); | |
| + AL_CRYPTO_STATS_INC(ctx->chan->stats_gen.ablkcipher_tfms, 1); | |
| + AL_CRYPTO_STATS_UNLOCK(&ctx->chan->stats_gen_lock); | |
| + | |
| + return 0; | |
| +} | |
| + | |
| +/****************************************************************************** | |
| + *****************************************************************************/ | |
| +static void al_crypto_cra_exit(struct crypto_tfm *tfm) | |
| +{ | |
| + struct crypto_alg *alg = tfm->__crt_alg; | |
| + struct al_crypto_alg *al_crypto_alg = | |
| + container_of(alg, struct al_crypto_alg, crypto_alg); | |
| + struct al_crypto_ctx *ctx = crypto_tfm_ctx(tfm); | |
| + struct al_crypto_device *device = al_crypto_alg->device; | |
| + | |
| + dev_dbg(&device->pdev->dev, "%s\n", __func__); | |
| + | |
| + /* LRU list access has to be protected */ | |
| + spin_lock_bh(&ctx->chan->prep_lock); | |
| + if (ctx->cache_state.cached) | |
| + al_crypto_cache_remove_lru(ctx->chan, &ctx->cache_state); | |
| + spin_unlock_bh(&ctx->chan->prep_lock); | |
| + | |
| + if (ctx->hw_sa_dma_addr) | |
| + dma_free_coherent(&device->pdev->dev, | |
| + sizeof(struct al_crypto_hw_sa), | |
| + ctx->hw_sa, | |
| + ctx->hw_sa_dma_addr); | |
| + | |
| + return; | |
| +} | |
| + | |
| +/****************************************************************************** | |
| + *****************************************************************************/ | |
| +static void al_crypto_cra_exit_ablkcipher(struct crypto_tfm *tfm) | |
| +{ | |
| + struct al_crypto_ctx *ctx = crypto_tfm_ctx(tfm); | |
| + | |
| + al_crypto_cra_exit(tfm); | |
| + | |
| + AL_CRYPTO_STATS_LOCK(&ctx->chan->stats_gen_lock); | |
| + AL_CRYPTO_STATS_DEC(ctx->chan->stats_gen.ablkcipher_tfms, 1); | |
| + AL_CRYPTO_STATS_UNLOCK(&ctx->chan->stats_gen_lock); | |
| +} | |
| + | |
| +/****************************************************************************** | |
| + *****************************************************************************/ | |
| +static int ablkcipher_setkey_des(struct crypto_ablkcipher *ablkcipher, | |
| + const u8 *key, unsigned int keylen) | |
| +{ | |
| + u32 tmp[DES_EXPKEY_WORDS]; | |
| + struct al_crypto_ctx *ctx = crypto_ablkcipher_ctx(ablkcipher); | |
| + u32 *flags = &ablkcipher->base.crt_flags; | |
| + int ret; | |
| + | |
| + dev_dbg(to_dev(ctx->chan), "%s\n", __func__); | |
| + | |
| + if ((ctx->sa.enc_type == AL_CRYPT_TRIPDES_CBC) || | |
| + (ctx->sa.enc_type == AL_CRYPT_TRIPDES_ECB)) { | |
| + ctx->sa.tripdes_m = AL_CRYPT_TRIPDES_EDE; | |
| + if (keylen != DES3_EDE_KEY_SIZE) | |
| + return -EINVAL; | |
| + | |
| + } else { | |
| + ctx->sa.tripdes_m = 0; | |
| + if (keylen != DES_KEY_SIZE) | |
| + return -EINVAL; | |
| + | |
| + /* check for weak keys. */ | |
| + /* Weak keys are keys that cause the encryption mode of DES | |
| + * to act identically to the decryption mode of DES */ | |
| + ret = des_ekey(tmp, key); | |
| + if (unlikely(ret == 0) && (*flags & CRYPTO_TFM_REQ_WEAK_KEY)) { | |
| + *flags |= CRYPTO_TFM_RES_WEAK_KEY; | |
| + return -EINVAL; | |
| + } | |
| + } | |
| + | |
| + /* TODO: optimize HAL to hold ptrs to save this memcpy */ | |
| + /* copy the key to the sa */ | |
| + memcpy(&ctx->sa.enc_key, key, keylen); | |
| + | |
| + al_crypto_hw_sa_init(&ctx->sa, ctx->hw_sa); | |
| + | |
| + /* mark the sa as not cached, will update in next xaction */ | |
| + spin_lock_bh(&ctx->chan->prep_lock); | |
| + if (ctx->cache_state.cached) | |
| + al_crypto_cache_remove_lru(ctx->chan, &ctx->cache_state); | |
| + spin_unlock_bh(&ctx->chan->prep_lock); | |
| + | |
| + return 0; | |
| +} | |
| + | |
| +/****************************************************************************** | |
| + *****************************************************************************/ | |
| +static int ablkcipher_setkey_aes(struct crypto_ablkcipher *ablkcipher, | |
| + const u8 *key, unsigned int keylen) | |
| +{ | |
| + struct al_crypto_ctx *ctx = crypto_ablkcipher_ctx(ablkcipher); | |
| + | |
| + dev_dbg(to_dev(ctx->chan), "%s\n", __func__); | |
| + | |
| + switch (keylen) { | |
| + case 16: /* 128 bit */ | |
| + ctx->sa.aes_ksize = AL_CRYPT_AES_128; | |
| + break; | |
| + case 24: /* 192 bit */ | |
| + ctx->sa.aes_ksize = AL_CRYPT_AES_192; | |
| + break; | |
| + case 32: /* 256 bit */ | |
| + ctx->sa.aes_ksize = AL_CRYPT_AES_256; | |
| + break; | |
| + default: /* Invalid key size */ | |
| + return -EINVAL; | |
| + break; | |
| + } | |
| + | |
| + /* As for now we don't support GCM or CCM modes */ | |
| + if ((ctx->sa.enc_type == AL_CRYPT_AES_GCM) || | |
| + (ctx->sa.enc_type == AL_CRYPT_AES_CCM)) { | |
| + BUG(); | |
| + } | |
| + | |
| + /* TODO: optimize HAL to hold ptrs to save this memcpy */ | |
| + /* copy the key to the sa */ | |
| + memcpy(&ctx->sa.enc_key, key, keylen); | |
| + | |
| + /* Sets the counter increment to 128 bit to be aligned with the | |
| + * linux implementation. We know it contradicts the NIST spec. | |
| + * If and when the linux will be aligned with the spec we should fix it | |
| + * too. | |
| + * This variable is relevant only for CTR, GCM and CCM modes*/ | |
| + ctx->sa.cntr_size = AL_CRYPT_CNTR_128_BIT; | |
| + | |
| + al_crypto_hw_sa_init(&ctx->sa, ctx->hw_sa); | |
| + | |
| + /* mark the sa as not cached, will update in next xaction */ | |
| + spin_lock_bh(&ctx->chan->prep_lock); | |
| + if (ctx->cache_state.cached) | |
| + al_crypto_cache_remove_lru(ctx->chan, &ctx->cache_state); | |
| + spin_unlock_bh(&ctx->chan->prep_lock); | |
| + | |
| + return 0; | |
| +} | |
| + | |
| + | |
| +/****************************************************************************** | |
| + *****************************************************************************/ | |
| +/* DMA unmap buffers for ablkcipher request | |
| + */ | |
| +static inline void al_crypto_dma_unmap_ablkcipher(struct al_crypto_chan *chan, | |
| + struct ablkcipher_request *req, | |
| + int src_nents, int dst_nents, | |
| + struct al_crypto_sw_desc *desc) | |
| +{ | |
| + | |
| + if (likely(req->src == req->dst)) { | |
| + dma_unmap_sg(to_dev(chan), req->src, src_nents, | |
| + DMA_BIDIRECTIONAL); | |
| + } else { | |
| + dma_unmap_sg(to_dev(chan), req->src, src_nents, | |
| + DMA_TO_DEVICE); | |
| + dma_unmap_sg(to_dev(chan), req->dst, dst_nents, | |
| + DMA_FROM_DEVICE); | |
| + } | |
| + | |
| + if (desc && desc->hal_xaction.enc_iv_in.len) | |
| + dma_unmap_single(to_dev(chan), | |
| + desc->hal_xaction.enc_iv_in.addr, | |
| + desc->hal_xaction.enc_iv_in.len, | |
| + DMA_TO_DEVICE); | |
| +} | |
| + | |
| +/****************************************************************************** | |
| + *****************************************************************************/ | |
| +/* Cleanup single ablkcipher request - invoked from cleanup tasklet (interrupt | |
| + * handler) | |
| + */ | |
| +void al_crypto_cleanup_single_ablkcipher( | |
| + struct al_crypto_chan *chan, | |
| + struct al_crypto_sw_desc *desc, | |
| + uint32_t comp_status) | |
| +{ | |
| + struct ablkcipher_request *req = | |
| + (struct ablkcipher_request *)desc->req; | |
| + | |
| + al_crypto_dma_unmap_ablkcipher(chan, req, desc->src_nents, | |
| + desc->dst_nents, desc); | |
| + | |
| + req->base.complete(&req->base, 0); | |
| +} | |
| + | |
| +/****************************************************************************** | |
| + *****************************************************************************/ | |
| +static inline void ablkcipher_update_stats( | |
| + struct al_crypto_transaction *xaction, | |
| + struct al_crypto_chan *chan) | |
| +{ | |
| + if (xaction->dir == AL_CRYPT_ENCRYPT) { | |
| + AL_CRYPTO_STATS_INC(chan->stats_prep.ablkcipher_encrypt_reqs, | |
| + 1); | |
| + AL_CRYPTO_STATS_INC(chan->stats_prep.ablkcipher_encrypt_bytes, | |
| + xaction->enc_in_len); | |
| + } else { | |
| + AL_CRYPTO_STATS_INC(chan->stats_prep.ablkcipher_decrypt_reqs, | |
| + 1); | |
| + AL_CRYPTO_STATS_INC(chan->stats_prep.ablkcipher_decrypt_bytes, | |
| + xaction->enc_in_len); | |
| + } | |
| + | |
| + if (xaction->enc_in_len <= 512) | |
| + AL_CRYPTO_STATS_INC( | |
| + chan->stats_prep.ablkcipher_reqs_le512, 1); | |
| + else if ((xaction->enc_in_len > 512) && (xaction->enc_in_len <= 2048)) | |
| + AL_CRYPTO_STATS_INC( | |
| + chan->stats_prep.ablkcipher_reqs_512_2048, 1); | |
| + else if ((xaction->enc_in_len > 2048) && (xaction->enc_in_len <= 4096)) | |
| + AL_CRYPTO_STATS_INC( | |
| + chan->stats_prep.ablkcipher_reqs_2048_4096, 1); | |
| + else | |
| + AL_CRYPTO_STATS_INC( | |
| + chan->stats_prep.ablkcipher_reqs_gt4096, 1); | |
| +} | |
| + | |
| +/****************************************************************************** | |
| + *****************************************************************************/ | |
| +static inline void ablkcipher_prepare_xaction_buffers( | |
| + struct ablkcipher_request *req, | |
| + struct al_crypto_sw_desc *desc) | |
| +{ | |
| + int i; | |
| + int src_idx, dst_idx; | |
| + struct al_crypto_transaction *xaction = &desc->hal_xaction; | |
| + | |
| + src_idx = 0; | |
| + dst_idx = 0; | |
| + | |
| + sg_map_to_xaction_buffers(req->src, desc->src_bufs, req->nbytes, | |
| + &src_idx); | |
| + if (likely(req->src == req->dst)) { | |
| + for (i = 0; i < src_idx; i++) | |
| + desc->dst_bufs[i] = desc->src_bufs[i]; | |
| + dst_idx = src_idx; | |
| + } else | |
| + sg_map_to_xaction_buffers(req->dst, desc->dst_bufs, | |
| + req->nbytes, &dst_idx); | |
| + | |
| + xaction->src_size = xaction->enc_in_len = req->nbytes; | |
| + xaction->src.bufs = &desc->src_bufs[0]; | |
| + xaction->src.num = src_idx; | |
| + xaction->dst.bufs = &desc->dst_bufs[0]; | |
| + xaction->dst.num = dst_idx; | |
| +} | |
| + | |
| +/****************************************************************************** | |
| + *****************************************************************************/ | |
| +/* Prepare crypto transaction to be processed by HAL and submit to HAL | |
| + * Grabs and releases producer lock for relevant sw ring | |
| + */ | |
| +static int ablkcipher_do_crypt(struct ablkcipher_request *req, bool lock) | |
| +{ | |
| + int idx, rc; | |
| + struct crypto_ablkcipher *ablkcipher = crypto_ablkcipher_reqtfm(req); | |
| + struct al_crypto_ctx *ctx = crypto_ablkcipher_ctx(ablkcipher); | |
| + struct al_crypto_ablkcipher_req_ctx *rctx = ablkcipher_request_ctx(req); | |
| + enum al_crypto_dir dir = rctx->dir; | |
| + struct al_crypto_chan *chan = ctx->chan; | |
| + struct al_crypto_transaction *xaction; | |
| + int src_nents = 0, dst_nents = 0; | |
| + int ivsize = crypto_ablkcipher_ivsize(ablkcipher); | |
| + struct al_crypto_sw_desc *desc; | |
| + | |
| + src_nents = sg_count(req->src, req->nbytes); | |
| + | |
| + if (req->dst != req->src) | |
| + dst_nents = sg_count(req->dst, req->nbytes); | |
| + else | |
| + dst_nents = src_nents; | |
| + | |
| + /* Currently supported max sg chain length is | |
| + * AL_CRYPTO_OP_MAX_DATA_BUFS(12) which is minimum of descriptors left | |
| + * for data in a transaction: | |
| + * tx: 31(supported by HW) - 1(metadata) - 1(sa_in) - | |
| + * 1(enc_iv_in|auth_iv_in) - 1(auth_sign_in) = 27 | |
| + * rx: 31(supported by HW) - 1(sa_out) - 1(enc_iv_out|auth_iv_out) - | |
| + * 1(next_enc_iv_out) - 1(auth_sign_out) = 27 | |
| + */ | |
| + BUG_ON((src_nents > AL_CRYPTO_OP_MAX_BUFS) || | |
| + (dst_nents > AL_CRYPTO_OP_MAX_BUFS)); | |
| + | |
| + if (likely(req->src == req->dst)) { | |
| + dma_map_sg(to_dev(chan), req->src, src_nents, | |
| + DMA_BIDIRECTIONAL); | |
| + } else { | |
| + dma_map_sg(to_dev(chan), req->src, src_nents, | |
| + DMA_TO_DEVICE); | |
| + dma_map_sg(to_dev(chan), req->dst, dst_nents, | |
| + DMA_FROM_DEVICE); | |
| + } | |
| + | |
| + if (likely(lock)) | |
| + spin_lock_bh(&chan->prep_lock); | |
| + | |
| + if (likely(al_crypto_get_sw_desc(chan, 1) == 0)) | |
| + idx = chan->head; | |
| + else { | |
| + rc = ablkcipher_enqueue_request(&chan->sw_queue, req); | |
| + | |
| + al_crypto_dma_unmap_ablkcipher(chan, req, src_nents, dst_nents, | |
| + NULL); | |
| + | |
| + if (likely(lock)) | |
| + spin_unlock_bh(&chan->prep_lock); | |
| + | |
| + dev_dbg( | |
| + to_dev(chan), | |
| + "%s: al_crypto_get_sw_desc failed!\n", | |
| + __func__); | |
| + | |
| + return rc; | |
| + } | |
| + | |
| + chan->sw_desc_num_locked = 1; | |
| + chan->tx_desc_produced = 0; | |
| + | |
| + desc = al_crypto_get_ring_ent(chan, idx); | |
| + desc->req = (void *)req; | |
| + desc->req_type = AL_CRYPTO_REQ_ABLKCIPHER; | |
| + desc->src_nents = src_nents; | |
| + desc->dst_nents = dst_nents; | |
| + | |
| + /* prepare hal transaction */ | |
| + xaction = &desc->hal_xaction; | |
| + memset(xaction, 0, sizeof(struct al_crypto_transaction)); | |
| + xaction->dir = dir; | |
| + | |
| + ablkcipher_prepare_xaction_buffers(req, desc); | |
| + | |
| + if ((ctx->sa.enc_type != AL_CRYPT_AES_ECB) && | |
| + (ctx->sa.enc_type != AL_CRYPT_DES_ECB) && | |
| + (ctx->sa.enc_type != AL_CRYPT_TRIPDES_ECB)) { | |
| + xaction->enc_iv_in.addr = dma_map_single(to_dev(chan), | |
| + req->info, ivsize, DMA_TO_DEVICE); | |
| + xaction->enc_iv_in.len = ivsize; | |
| + } | |
| + | |
| + if (!ctx->cache_state.cached) { | |
| + xaction->sa_indx = al_crypto_cache_replace_lru(chan, | |
| + &ctx->cache_state, NULL); | |
| + xaction->sa_in.addr = ctx->hw_sa_dma_addr; | |
| + xaction->sa_in.len = sizeof(struct al_crypto_hw_sa); | |
| + } else { | |
| + al_crypto_cache_update_lru(chan, &ctx->cache_state); | |
| + xaction->sa_indx = ctx->cache_state.idx; | |
| + } | |
| + | |
| + xaction->flags = AL_SSM_INTERRUPT; | |
| + | |
| + ablkcipher_update_stats(xaction, chan); | |
| + | |
| + /* send crypto transaction to engine */ | |
| + rc = al_crypto_dma_prepare(chan->hal_crypto, chan->idx, | |
| + &desc->hal_xaction); | |
| + if (unlikely(rc != 0)) { | |
| + dev_err(to_dev(chan), | |
| + "al_crypto_dma_prepare failed!\n"); | |
| + | |
| + al_crypto_dma_unmap_ablkcipher(chan, req, src_nents, dst_nents, | |
| + desc); | |
| + | |
| + if (likely(lock)) | |
| + spin_unlock_bh(&chan->prep_lock); | |
| + return rc; | |
| + } | |
| + | |
| + chan->tx_desc_produced += desc->hal_xaction.tx_descs_count; | |
| + | |
| + al_crypto_tx_submit(chan); | |
| + | |
| + if (likely(lock)) | |
| + spin_unlock_bh(&chan->prep_lock); | |
| + | |
| + return -EINPROGRESS; | |
| +} | |
| + | |
| +/****************************************************************************** | |
| + *****************************************************************************/ | |
| +int ablkcipher_process_queue(struct al_crypto_chan *chan) | |
| +{ | |
| + struct crypto_async_request *async_req, *backlog; | |
| + struct ablkcipher_request *req; | |
| + int err = 0; | |
| + | |
| + spin_lock_bh(&chan->prep_lock); | |
| + | |
| + while (al_crypto_ring_space(chan) > 0) { | |
| + backlog = crypto_get_backlog(&chan->sw_queue); | |
| + async_req = crypto_dequeue_request(&chan->sw_queue); | |
| + | |
| + if (!async_req) | |
| + break; | |
| + | |
| + if (backlog) | |
| + backlog->complete(backlog, -EINPROGRESS); | |
| + | |
| + req = container_of(async_req, struct ablkcipher_request, base); | |
| + | |
| + err = ablkcipher_do_crypt(req, false); | |
| + if (err != -EINPROGRESS) | |
| + break; | |
| + } | |
| + | |
| + spin_unlock_bh(&chan->prep_lock); | |
| + | |
| + return err; | |
| +} | |
| + | |
| +/****************************************************************************** | |
| + *****************************************************************************/ | |
| +static int ablkcipher_encrypt(struct ablkcipher_request *req) | |
| +{ | |
| + struct crypto_ablkcipher *ablkcipher = crypto_ablkcipher_reqtfm(req); | |
| + struct al_crypto_ctx *ctx = crypto_ablkcipher_ctx(ablkcipher); | |
| + struct al_crypto_ablkcipher_req_ctx *rctx = ablkcipher_request_ctx(req); | |
| + struct al_crypto_chan *chan = ctx->chan; | |
| + | |
| + dev_dbg(to_dev(chan), "ablkcipher_encrypt %p\n", req); | |
| + | |
| + rctx->dir = AL_CRYPT_ENCRYPT; | |
| + return ablkcipher_do_crypt(req, true); | |
| +} | |
| + | |
| +/****************************************************************************** | |
| + *****************************************************************************/ | |
| +static int ablkcipher_decrypt(struct ablkcipher_request *req) | |
| +{ | |
| + struct crypto_ablkcipher *ablkcipher = crypto_ablkcipher_reqtfm(req); | |
| + struct al_crypto_ctx *ctx = crypto_ablkcipher_ctx(ablkcipher); | |
| + struct al_crypto_ablkcipher_req_ctx *rctx = ablkcipher_request_ctx(req); | |
| + struct al_crypto_chan *chan = ctx->chan; | |
| + | |
| + dev_dbg(to_dev(chan), "ablkcipher_decrypt %p\n", req); | |
| + | |
| + rctx->dir = AL_CRYPT_DECRYPT; | |
| + return ablkcipher_do_crypt(req, true); | |
| +} | |
| + | |
| +/****************************************************************************** | |
| + *****************************************************************************/ | |
| +static struct al_crypto_alg *al_crypto_alg_alloc( | |
| + struct al_crypto_device *device, | |
| + struct al_crypto_alg_template *template) | |
| +{ | |
| + struct al_crypto_alg *t_alg; | |
| + struct crypto_alg *alg; | |
| + | |
| + t_alg = kzalloc(sizeof(struct al_crypto_alg), GFP_KERNEL); | |
| + if (!t_alg) { | |
| + dev_err(&device->pdev->dev, "failed to allocate t_alg\n"); | |
| + return ERR_PTR(-ENOMEM); | |
| + } | |
| + | |
| + alg = &t_alg->crypto_alg; | |
| + | |
| + snprintf(alg->cra_name, CRYPTO_MAX_ALG_NAME, "%s", template->name); | |
| + snprintf(alg->cra_driver_name, CRYPTO_MAX_ALG_NAME, "%s", | |
| + template->driver_name); | |
| + alg->cra_module = THIS_MODULE; | |
| + alg->cra_priority = AL_CRYPTO_CRA_PRIORITY; | |
| + alg->cra_blocksize = template->blocksize; | |
| + alg->cra_alignmask = 0; | |
| + alg->cra_ctxsize = sizeof(struct al_crypto_ctx); | |
| + alg->cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_KERN_DRIVER_ONLY | | |
| + template->type; | |
| + | |
| + switch (template->type) { | |
| + case CRYPTO_ALG_TYPE_ABLKCIPHER: | |
| + alg->cra_init = al_crypto_cra_init_ablkcipher; | |
| + alg->cra_exit = al_crypto_cra_exit_ablkcipher; | |
| + alg->cra_type = &crypto_ablkcipher_type; | |
| + alg->cra_ablkcipher = template->template_u.ablkcipher; | |
| + break; | |
| + } | |
| + | |
| + t_alg->enc_type = template->enc_type; | |
| + t_alg->auth_type = template->auth_type; | |
| + t_alg->sha2_mode = template->sha2_mode; | |
| + t_alg->sa_op = template->sa_op; | |
| + t_alg->device = device; | |
| + | |
| + return t_alg; | |
| +} | |
| + | |
| +/****************************************************************************** | |
| + *****************************************************************************/ | |
| +int al_crypto_alg_init(struct al_crypto_device *device) | |
| +{ | |
| + int i; | |
| + int err = 0; | |
| + | |
| + INIT_LIST_HEAD(&device->alg_list); | |
| + | |
| + atomic_set(&device->tfm_count, -1); | |
| + | |
| + /* register crypto algorithms the device supports */ | |
| + for (i = 0; i < ARRAY_SIZE(driver_algs); i++) { | |
| + struct al_crypto_alg *t_alg; | |
| + | |
| + t_alg = al_crypto_alg_alloc(device, &driver_algs[i]); | |
| + if (IS_ERR(t_alg)) { | |
| + err = PTR_ERR(t_alg); | |
| + dev_warn(&device->pdev->dev, | |
| + "%s alg allocation failed\n", | |
| + driver_algs[i].driver_name); | |
| + continue; | |
| + } | |
| + | |
| + err = crypto_register_alg(&t_alg->crypto_alg); | |
| + if (err) { | |
| + dev_warn(&device->pdev->dev, | |
| + "%s alg registration failed\n", | |
| + t_alg->crypto_alg.cra_driver_name); | |
| + kfree(t_alg); | |
| + } else | |
| + list_add_tail(&t_alg->entry, &device->alg_list); | |
| + } | |
| + | |
| + if (!list_empty(&device->alg_list)) | |
| + dev_info(&device->pdev->dev, | |
| + "algorithms registered in /proc/crypto\n"); | |
| + | |
| + return err; | |
| +} | |
| + | |
| +/****************************************************************************** | |
| + *****************************************************************************/ | |
| +void al_crypto_alg_terminate(struct al_crypto_device *device) | |
| +{ | |
| + struct al_crypto_alg *t_alg, *n; | |
| + | |
| + if (!device->alg_list.next) | |
| + return; | |
| + | |
| + list_for_each_entry_safe(t_alg, n, &device->alg_list, entry) { | |
| + crypto_unregister_alg(&t_alg->crypto_alg); | |
| + list_del(&t_alg->entry); | |
| + kfree(t_alg); | |
| + } | |
| +} | |
| diff -x .git -Naur linux-4.4.111/drivers/crypto/al/al_crypto_core.c linux-4.4.111-alpine/drivers/crypto/al/al_crypto_core.c | |
| --- linux-4.4.111/drivers/crypto/al/al_crypto_core.c 1969-12-31 19:00:00.000000000 -0500 | |
| +++ linux-4.4.111-alpine/drivers/crypto/al/al_crypto_core.c 2018-02-14 21:04:16.000000000 -0500 | |
| @@ -0,0 +1,1411 @@ | |
| +/* | |
| + * drivers/crypto/al_crypto_core.c | |
| + * | |
| + * Annapurna Labs Crypto driver - core | |
| + * | |
| + * Copyright (C) 2012 Annapurna Labs Ltd. | |
| + * | |
| + * This program is free software; you can redistribute it and/or modify | |
| + * it under the terms of the GNU General Public License as published by | |
| + * the Free Software Foundation; either version 2 of the License, or | |
| + * (at your option) any later version. | |
| + * | |
| + * This program is distributed in the hope that it will be useful, | |
| + * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| + * GNU General Public License for more details. | |
| + * | |
| + * You should have received a copy of the GNU General Public License | |
| + * along with this program; if not, write to the Free Software | |
| + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
| + */ | |
| + | |
| +/* | |
| +#ifndef DEBUG | |
| +#define DEBUG | |
| +#endif | |
| +*/ | |
| + | |
| +#include <linux/init.h> | |
| +#include <linux/module.h> | |
| +#include <linux/slab.h> | |
| +#include <linux/dma-mapping.h> | |
| + | |
| +#include <soc/alpine/al_hal_ssm_crypto.h> | |
| +#include <soc/alpine/al_hal_udma_iofic.h> | |
| +#include <soc/alpine/al_hal_udma_config.h> | |
| + | |
| +#include "al_crypto.h" | |
| +#include "al_crypto_module_params.h" | |
| + | |
| +static void al_crypto_free_chan_resources( | |
| + struct al_crypto_chan *chan); | |
| + | |
| +static int al_crypto_alloc_chan_resources( | |
| + struct al_crypto_chan *chan); | |
| + | |
| +static void al_crypto_free_channels( | |
| + struct al_crypto_device *device); | |
| + | |
| +static int al_crypto_alloc_channels( | |
| + struct al_crypto_device *device); | |
| + | |
| +static int al_crypto_setup_interrupts( | |
| + struct al_crypto_device *device); | |
| + | |
| +static irqreturn_t al_crypto_do_interrupt_msix( | |
| + int irq, | |
| + void *data); | |
| + | |
| +static irqreturn_t al_crypto_do_interrupt_group_d( | |
| + int irq, | |
| + void *data); | |
| + | |
| +static irqreturn_t al_crypto_do_interrupt_msix_rx( | |
| + int irq, | |
| + void *data); | |
| + | |
| +static irqreturn_t al_crypto_do_interrupt_legacy( | |
| + int irq, | |
| + void *data); | |
| + | |
| +static int al_crypto_init_channels( | |
| + struct al_crypto_device *device, | |
| + int max_channels); | |
| + | |
| +static void al_crypto_init_channel( | |
| + struct al_crypto_device *device, | |
| + struct al_crypto_chan *chan, | |
| + int idx); | |
| + | |
| +static struct al_crypto_sw_desc **al_crypto_alloc_sw_ring( | |
| + struct al_crypto_chan *chan, | |
| + int order, | |
| + gfp_t flags); | |
| + | |
| +static void al_crypto_free_sw_ring( | |
| + struct al_crypto_sw_desc **ring, | |
| + struct al_crypto_chan *chan, | |
| + int size); | |
| + | |
| +static struct al_crypto_sw_desc *al_crypto_alloc_ring_ent( | |
| + struct al_crypto_chan *chan, | |
| + gfp_t flags); | |
| + | |
| +static void al_crypto_free_ring_ent( | |
| + struct al_crypto_sw_desc *desc, | |
| + struct al_crypto_chan *chan); | |
| + | |
| +static int al_crypto_iofic_config(struct al_crypto_device *device, | |
| + bool single_msix); | |
| + | |
| +static void al_crypto_cleanup_tasklet( | |
| + unsigned long data); | |
| + | |
| +static void al_crypto_cleanup_tasklet_msix_rx( | |
| + unsigned long data); | |
| + | |
| +static void al_crypto_cleanup_tasklet_legacy( | |
| + unsigned long data); | |
| + | |
| +static void al_crypto_unmask_interrupts(struct al_crypto_device *device, | |
| + bool single_interrupt); | |
| + | |
| +static void al_crypto_group_d_errors_handler(struct al_crypto_device *device); | |
| +/****************************************************************************** | |
| + *****************************************************************************/ | |
| +int al_crypto_core_init( | |
| + struct al_crypto_device *device, | |
| + void __iomem *iobase_udma, | |
| + void __iomem *iobase_app) | |
| +{ | |
| + int32_t rc; | |
| + int err; | |
| + int max_channels; | |
| + int crc_channels; | |
| + | |
| + dev_dbg( | |
| + &device->pdev->dev, | |
| + "%s(%p, %p)\n", | |
| + __func__, | |
| + device, | |
| + iobase_udma); | |
| + | |
| + device->cache = kmem_cache_create( | |
| + "al_crypto", | |
| + sizeof(struct al_crypto_sw_desc), | |
| + 0, | |
| + SLAB_HWCACHE_ALIGN, | |
| + NULL); | |
| + if (!device->cache) | |
| + return -ENOMEM; | |
| + | |
| + max_channels = device->max_channels; | |
| + crc_channels = device->crc_channels; | |
| + | |
| + if ((crc_channels > max_channels) || (max_channels > DMA_MAX_Q)) { | |
| + dev_err(&device->pdev->dev, "invalid number of channels\n"); | |
| + err = -EINVAL; | |
| + goto done; | |
| + } | |
| + | |
| + device->udma_regs_base = iobase_udma; | |
| + /* The crypto regs exists only for the PF. | |
| + * The VF uses the same configs/ error reporting as the PF */ | |
| + device->crypto_regs_base = iobase_app ? iobase_app + | |
| + AL_CRYPTO_APP_REGS_BASE_OFFSET(device->rev_id) | |
| + : NULL; | |
| + | |
| + device->ssm_dma_params.udma_regs_base = device->udma_regs_base; | |
| + | |
| + device->ssm_dma_params.name = | |
| + kmalloc(strlen(dev_name(&device->pdev->dev)) + 1, GFP_KERNEL); | |
| + if (device->ssm_dma_params.name == NULL) { | |
| + dev_err(&device->pdev->dev, "kmalloc failed\n"); | |
| + err = -ENOMEM; | |
| + goto done; | |
| + } | |
| + | |
| + strcpy(device->ssm_dma_params.name, dev_name(&device->pdev->dev)); | |
| + | |
| + device->ssm_dma_params.num_of_queues = max_channels; | |
| + | |
| + err = al_ssm_dma_init(&device->hal_crypto, | |
| + &device->ssm_dma_params); | |
| + if (err) { | |
| + dev_err(&device->pdev->dev, "al_crypto_dma_init failed\n"); | |
| + goto err_no_chan; | |
| + } | |
| + | |
| + /* enumerate and initialize channels (queues) */ | |
| + al_crypto_init_channels(device, max_channels); | |
| + | |
| + err = al_crypto_alloc_channels(device); | |
| + if (err) { | |
| + dev_err(&device->pdev->dev, | |
| + "failed to alloc channel resources\n"); | |
| + goto err_no_irq; | |
| + } | |
| + | |
| + /* enable Crypto DMA engine */ | |
| + rc = al_ssm_dma_state_set(&device->hal_crypto, UDMA_NORMAL); | |
| + | |
| + err = al_crypto_setup_interrupts(device); | |
| + | |
| + if (err) { | |
| + dev_err(&device->pdev->dev, "failed to setup interrupts\n"); | |
| + goto err_no_irq; | |
| + } | |
| + | |
| + goto done; | |
| + | |
| +err_no_irq: | |
| + al_crypto_free_channels(device); | |
| +err_no_chan: | |
| + kfree(device->ssm_dma_params.name); | |
| +done: | |
| + return err; | |
| +} | |
| + | |
| +/****************************************************************************** | |
| + *****************************************************************************/ | |
| +int al_crypto_core_terminate( | |
| + struct al_crypto_device *device) | |
| +{ | |
| + int status = 0; | |
| + | |
| + dev_dbg( | |
| + &device->pdev->dev, | |
| + "%s(%p)\n", | |
| + __func__, | |
| + device); | |
| + | |
| + al_crypto_free_channels(device); | |
| + | |
| + kfree(device->ssm_dma_params.name); | |
| + | |
| + kmem_cache_destroy(device->cache); | |
| + | |
| + return status; | |
| +} | |
| + | |
| +/****************************************************************************** | |
| + *****************************************************************************/ | |
| +static int al_crypto_init_channels( | |
| + struct al_crypto_device *device, | |
| + int max_channels) | |
| +{ | |
| + int i; | |
| + struct al_crypto_chan *chan; | |
| + | |
| + for (i = 0; i < max_channels; i++) { | |
| + chan = kzalloc(sizeof(struct al_crypto_chan), GFP_KERNEL); | |
| + if (!chan) | |
| + break; | |
| + | |
| + al_crypto_init_channel(device, chan, i); | |
| + } | |
| + device->num_channels = i; | |
| + return i; | |
| +} | |
| + | |
| +/****************************************************************************** | |
| + *****************************************************************************/ | |
| +static void al_crypto_init_channel(struct al_crypto_device *device, | |
| + struct al_crypto_chan *chan, int idx) | |
| +{ | |
| + unsigned long data = (unsigned long)chan; | |
| + | |
| + dev_dbg( | |
| + &device->pdev->dev, | |
| + "%s(%p, %p, %d)\n", | |
| + __func__, | |
| + device, | |
| + chan, | |
| + idx); | |
| + | |
| + chan->device = device; | |
| + chan->idx = idx; | |
| + chan->hal_crypto = &device->hal_crypto; | |
| + | |
| + AL_CRYPTO_STATS_INIT_LOCK(&chan->stats_gen_lock); | |
| + spin_lock_init(&chan->prep_lock); | |
| + spin_lock_init(&chan->cleanup_lock); | |
| + | |
| + device->channels[idx] = chan; | |
| + | |
| + INIT_LIST_HEAD(&chan->cache_lru_list); | |
| + chan->cache_lru_count = 0; | |
| + | |
| + tasklet_init(&chan->cleanup_task, al_crypto_cleanup_tasklet, data); | |
| + | |
| + crypto_init_queue(&chan->sw_queue, 1); | |
| +} | |
| + | |
| +/****************************************************************************** | |
| + *****************************************************************************/ | |
| +static void al_crypto_unmask_interrupts(struct al_crypto_device *device, | |
| + bool single_interrupt) | |
| +{ | |
| + /* enable group D summary */ | |
| + u32 group_a_mask = AL_INT_GROUP_A_GROUP_D_SUM; | |
| + u32 group_b_mask = (1 << device->num_channels) - 1; /* bit per Rx q*/ | |
| + u32 group_d_mask = AL_INT_GROUP_D_ALL; | |
| + | |
| + struct unit_regs __iomem *regs_base = | |
| + (struct unit_regs __iomem *)device->udma_regs_base; | |
| + | |
| + if (single_interrupt) | |
| + group_a_mask |= AL_INT_GROUP_A_GROUP_B_SUM; | |
| + | |
| + al_udma_iofic_unmask(regs_base, AL_UDMA_IOFIC_LEVEL_PRIMARY, AL_INT_GROUP_A, group_a_mask); | |
| + al_udma_iofic_unmask(regs_base, AL_UDMA_IOFIC_LEVEL_PRIMARY, AL_INT_GROUP_B, group_b_mask); | |
| + al_udma_iofic_unmask(regs_base, AL_UDMA_IOFIC_LEVEL_PRIMARY, AL_INT_GROUP_D, group_d_mask); | |
| +} | |
| + | |
| +/****************************************************************************** | |
| + *****************************************************************************/ | |
| +static void al_crypto_config_crypto_app_interrupts | |
| + (struct al_crypto_device *device) | |
| +{ | |
| + if (!device->crypto_regs_base) | |
| + return; | |
| + | |
| + al_iofic_clear_cause( | |
| + device->crypto_regs_base + AL_CRYPTO_APP_IOFIC_OFFSET, | |
| + AL_INT_GROUP_A, | |
| + AL_CRYPTO_APP_INT_A_ALL); | |
| + | |
| + al_iofic_unmask( | |
| + device->crypto_regs_base + AL_CRYPTO_APP_IOFIC_OFFSET, | |
| + AL_INT_GROUP_A, | |
| + AL_CRYPTO_APP_INT_A_ALL); | |
| + | |
| + al_iofic_config( | |
| + device->crypto_regs_base + AL_CRYPTO_APP_IOFIC_OFFSET, | |
| + AL_INT_GROUP_A, | |
| + INT_CONTROL_GRP_CLEAR_ON_READ | | |
| + INT_CONTROL_GRP_MASK_MSI_X); | |
| + | |
| + /* Clear the interrupt reg */ | |
| + al_iofic_read_cause( | |
| + device->crypto_regs_base + AL_CRYPTO_APP_IOFIC_OFFSET, | |
| + AL_INT_GROUP_A); | |
| +} | |
| + | |
| +/****************************************************************************** | |
| + *****************************************************************************/ | |
| +static int al_crypto_iofic_config(struct al_crypto_device *device, | |
| + bool single_msix) | |
| +{ | |
| + enum al_iofic_mode iofic_mode; | |
| + int int_moderation_group; | |
| + | |
| + if (single_msix) { | |
| + iofic_mode = AL_IOFIC_MODE_MSIX_PER_GROUP; | |
| + int_moderation_group = AL_INT_GROUP_A; | |
| + } else { | |
| + iofic_mode = AL_IOFIC_MODE_MSIX_PER_Q; | |
| + int_moderation_group = AL_INT_GROUP_B; | |
| + } | |
| + | |
| + if (al_udma_iofic_config( | |
| + (struct unit_regs *)device->udma_regs_base, | |
| + iofic_mode, 0x480, 0x480, 0x1E0, 0x1E0)) { | |
| + | |
| + dev_err(&device->pdev->dev, "al_udma_iofic_config failed!.\n"); | |
| + return -EIO; | |
| + } | |
| + | |
| + al_iofic_moder_res_config( | |
| + &((struct unit_regs *)(device->udma_regs_base))->gen. | |
| + interrupt_regs.main_iofic, | |
| + int_moderation_group, 15); | |
| + | |
| + al_crypto_config_crypto_app_interrupts(device); | |
| + al_crypto_unmask_interrupts(device, single_msix); | |
| + | |
| + return 0; | |
| +} | |
| + | |
| +/****************************************************************************** | |
| + *****************************************************************************/ | |
| +static int al_crypto_setup_interrupts(struct al_crypto_device *device) | |
| +{ | |
| + struct al_crypto_chan *chan; | |
| + struct pci_dev *pdev = device->pdev; | |
| + struct device *dev = &pdev->dev; | |
| + struct msix_entry *msix; | |
| + int i, msixcnt; | |
| + unsigned int cpu; | |
| + int err = -EINVAL; | |
| + int devm_alloc_num = 0; | |
| + | |
| + if (al_crypto_get_use_single_msix()) | |
| + goto msix_single_vector; | |
| + | |
| + /* The number of MSI-X vectors should equal the number of channels + 1 | |
| + * for group D */ | |
| + msixcnt = device->num_channels + 1; | |
| + | |
| + for (i = 0; i < device->num_channels; i++) | |
| + device->msix_entries[i].entry = | |
| + AL_INT_MSIX_RX_COMPLETION_START + i; | |
| + | |
| + device->msix_entries[device->num_channels].entry = | |
| + AL_INT_MSIX_GROUP_A_SUM_D_IDX; | |
| + | |
| + err = pci_enable_msix(pdev, device->msix_entries, msixcnt); | |
| + | |
| + if (err < 0) { | |
| + dev_err(dev, "pci_enable_msix failed! using intx instead.\n"); | |
| + goto intx; | |
| + } | |
| + | |
| + if (err > 0) { | |
| + dev_err(dev, "pci_enable_msix failed! msix_single_vector.\n"); | |
| + goto msix_single_vector; | |
| + } | |
| + | |
| + for (i = 0; i < device->num_channels; i++) { | |
| + msix = &device->msix_entries[i]; | |
| + | |
| + chan = device->channels[i]; | |
| + | |
| + dev_dbg(dev, "%s: requesting irq %d\n", __func__, msix->vector); | |
| + | |
| + snprintf(device->irq_tbl[i].name, AL_CRYPTO_IRQNAME_SIZE, | |
| + "al-crypto-comp-%d@pci:%s", i, | |
| + pci_name(pdev)); | |
| + | |
| + err = devm_request_irq( | |
| + dev, | |
| + msix->vector, | |
| + al_crypto_do_interrupt_msix, | |
| + 0, | |
| + device->irq_tbl[i].name, | |
| + chan); | |
| + | |
| + if (err) { | |
| + dev_err(dev, "devm_request_irq failed!.\n"); | |
| + goto err_free_devm; | |
| + } | |
| + | |
| + devm_alloc_num++; | |
| + | |
| + cpu = cpumask_next((i % num_online_cpus() - 1), cpu_online_mask); | |
| + cpumask_set_cpu(cpu, &chan->affinity_hint_mask); | |
| + | |
| + irq_set_affinity_hint(msix->vector, &chan->affinity_hint_mask); | |
| + } | |
| + | |
| + snprintf(device->irq_tbl[device->num_channels].name, | |
| + AL_CRYPTO_IRQNAME_SIZE, | |
| + "al-crypto-interrupt-group-d@pci:%s", | |
| + pci_name(pdev)); | |
| + | |
| + err = devm_request_irq( | |
| + dev, | |
| + device->msix_entries[device->num_channels].vector, | |
| + al_crypto_do_interrupt_group_d, | |
| + 0, | |
| + device->irq_tbl[device->num_channels].name, | |
| + device); | |
| + | |
| + if (err) { | |
| + dev_err(dev, "devm_request_irq failed!.\n"); | |
| + goto err_free_devm; | |
| + } | |
| + | |
| + err = al_crypto_iofic_config(device, false); | |
| + if (err) | |
| + return err; | |
| + | |
| + goto done; | |
| + | |
| +msix_single_vector: | |
| + msix = &device->msix_entries[0]; | |
| + | |
| + msix->entry = 0; | |
| + | |
| + tasklet_init(&device->cleanup_task, | |
| + al_crypto_cleanup_tasklet_msix_rx, | |
| + (unsigned long)device); | |
| + | |
| + err = pci_enable_msix(pdev, device->msix_entries, 1); | |
| + | |
| + if (err) { | |
| + pci_disable_msix(pdev); | |
| + goto intx; | |
| + } | |
| + | |
| + snprintf(device->irq_tbl[0].name, AL_CRYPTO_IRQNAME_SIZE, | |
| + "al-crypto-msix-all@pci:%s", pci_name(pdev)); | |
| + | |
| + err = devm_request_irq( | |
| + dev, | |
| + msix->vector, | |
| + al_crypto_do_interrupt_msix_rx, | |
| + 0, | |
| + device->irq_tbl[0].name, | |
| + device); | |
| + | |
| + if (err) { | |
| + dev_err(dev, "devm_request_irq failed!.\n"); | |
| + pci_disable_msix(pdev); | |
| + goto intx; | |
| + } | |
| + | |
| + devm_alloc_num = 1; | |
| + | |
| + err = al_crypto_iofic_config(device, true); | |
| + if (err) | |
| + return err; | |
| + goto done; | |
| + | |
| +intx: | |
| + tasklet_init(&device->cleanup_task, | |
| + al_crypto_cleanup_tasklet_legacy, | |
| + (unsigned long)device); | |
| + | |
| + snprintf(device->irq_tbl[0].name, AL_CRYPTO_IRQNAME_SIZE, | |
| + "al-crypto-intx-all@pci:%s", pci_name(pdev)); | |
| + | |
| + err = devm_request_irq(dev, pdev->irq, al_crypto_do_interrupt_legacy, | |
| + IRQF_SHARED, device->irq_tbl[0].name, device); | |
| + if (err) | |
| + goto err_no_irq; | |
| + | |
| + if (al_udma_iofic_config( | |
| + (struct unit_regs *)device->udma_regs_base, | |
| + AL_IOFIC_MODE_LEGACY, 0x480, 0x480, 0x1E0, 0x1E0)) { | |
| + dev_err(dev, "al_udma_iofic_config failed!.\n"); | |
| + return -EIO; | |
| + } | |
| + | |
| + al_crypto_config_crypto_app_interrupts(device); | |
| + al_crypto_unmask_interrupts(device, true); | |
| + | |
| +done: | |
| + device->num_irq_used = devm_alloc_num; | |
| + return 0; | |
| + | |
| +err_free_devm: | |
| + | |
| + for (i = 0; i < devm_alloc_num; i++) { | |
| + msix = &device->msix_entries[i]; | |
| + chan = device->channels[i]; | |
| + irq_set_affinity_hint(msix->vector, NULL); | |
| + devm_free_irq(dev, msix->vector, chan); | |
| + return -EIO; | |
| + } | |
| + | |
| +err_no_irq: | |
| + /* Disable all interrupt generation */ | |
| + | |
| + dev_err(dev, "no usable interrupts\n"); | |
| + return err; | |
| +} | |
| + | |
| +/****************************************************************************** | |
| + *****************************************************************************/ | |
| +/* Free tx and rx descriptor rings for all channels | |
| + */ | |
| +static void al_crypto_free_channels(struct al_crypto_device *device) | |
| +{ | |
| + int i; | |
| + | |
| + for (i = 0; i < device->num_channels; i++) { | |
| + al_crypto_free_chan_resources(device->channels[i]); | |
| + al_crypto_free_channel(device->channels[i]); | |
| + } | |
| + | |
| + for (i = 0; i < device->num_irq_used; i++) | |
| + irq_set_affinity_hint(device->msix_entries[i].vector, NULL); | |
| +} | |
| + | |
| +/****************************************************************************** | |
| + *****************************************************************************/ | |
| +/* Allocate/initialize tx and rx descriptor rings for all channels | |
| + */ | |
| +static int al_crypto_alloc_channels(struct al_crypto_device *device) | |
| +{ | |
| + int i, j; | |
| + int err = -EINVAL; | |
| + | |
| + for (i = 0; i < device->num_channels; i++) { | |
| + err = al_crypto_alloc_chan_resources(device->channels[i]); | |
| + | |
| + if (err < 0) { | |
| + dev_err( | |
| + &device->pdev->dev, | |
| + "failed to alloc resources for channel %d\n", | |
| + i); | |
| + | |
| + for (j = 0; j < i; j++) { | |
| + al_crypto_free_chan_resources( | |
| + device->channels[j]); | |
| + } | |
| + return err; | |
| + } | |
| + } | |
| + | |
| + return 0; | |
| +} | |
| + | |
| +/****************************************************************************** | |
| + *****************************************************************************/ | |
| +static inline bool al_crypto_is_crypt_auth_chan(struct al_crypto_chan *chan) | |
| +{ | |
| + struct al_crypto_device *device = chan->device; | |
| + return (chan->idx < device->num_channels - device->crc_channels); | |
| +} | |
| + | |
| +/****************************************************************************** | |
| + *****************************************************************************/ | |
| +/* Allocate/initialize tx and rx descriptor rings for one channel | |
| + */ | |
| +static int al_crypto_alloc_chan_resources(struct al_crypto_chan *chan) | |
| +{ | |
| + struct al_crypto_device *device = chan->device; | |
| + struct device *dev = to_dev(chan); | |
| + struct al_crypto_sw_desc **sw_ring; | |
| + struct al_udma_q_params tx_params; | |
| + struct al_udma_q_params rx_params; | |
| + struct al_udma_m2s_pkt_len_conf conf; | |
| + struct al_udma *crypto_udma; | |
| + | |
| + int rc = 0; | |
| + int tx_descs_order; | |
| + int rx_descs_order; | |
| + int ring_alloc_order; | |
| + | |
| + dev_dbg(dev, "al_crypto_alloc_chan_resources: channel %d\n", | |
| + chan->idx); | |
| + | |
| + /* have we already been set up? */ | |
| + if (chan->sw_ring) | |
| + return 1 << chan->alloc_order; | |
| + | |
| + tx_descs_order = al_crypto_get_tx_descs_order(); | |
| + rx_descs_order = al_crypto_get_rx_descs_order(); | |
| + ring_alloc_order = al_crypto_get_ring_alloc_order(); | |
| + | |
| + chan->tx_descs_num = 1 << tx_descs_order; | |
| + chan->rx_descs_num = 1 << rx_descs_order; | |
| + | |
| + /* allocate coherent memory for Tx submission descriptors */ | |
| + chan->tx_dma_desc_virt = dma_alloc_coherent(dev, | |
| + chan->tx_descs_num * | |
| + sizeof(union al_udma_desc), | |
| + &chan->tx_dma_desc, | |
| + GFP_KERNEL); | |
| + if (chan->tx_dma_desc_virt == NULL) { | |
| + dev_err(dev, "failed to allocate %u bytes of coherent memory for Tx submission descriptors\n", | |
| + (unsigned int) | |
| + (chan->tx_descs_num * sizeof(union al_udma_desc))); | |
| + return -ENOMEM; | |
| + } | |
| + dev_dbg(dev, "allocted tx descriptor ring: virt 0x%p phys 0x%llx\n", | |
| + chan->tx_dma_desc_virt, (u64)chan->tx_dma_desc); | |
| + | |
| + /* allocate coherent memory for Rx submission descriptors */ | |
| + chan->rx_dma_desc_virt = dma_alloc_coherent(dev, | |
| + chan->rx_descs_num * | |
| + sizeof(union al_udma_desc), | |
| + &chan->rx_dma_desc, | |
| + GFP_KERNEL); | |
| + if (chan->rx_dma_desc_virt == NULL) { | |
| + dev_err(dev, "failed to allocate %u bytes of coherent memory for Rx submission descriptors\n", | |
| + (unsigned int) | |
| + (chan->rx_descs_num * sizeof(union al_udma_desc))); | |
| + | |
| + al_crypto_free_chan_resources(chan); | |
| + return -ENOMEM; | |
| + } | |
| + dev_dbg(dev, "allocted rx descriptor ring: virt 0x%p phys 0x%llx\n", | |
| + chan->rx_dma_desc_virt, (u64)chan->rx_dma_desc); | |
| + | |
| + /* allocate coherent memory for Rx completion descriptors */ | |
| + chan->rx_dma_cdesc_virt = dma_alloc_coherent(dev, | |
| + chan->rx_descs_num * | |
| + AL_CRYPTO_RX_CDESC_SIZE, | |
| + &chan->rx_dma_cdesc, | |
| + GFP_KERNEL); | |
| + if (chan->rx_dma_cdesc_virt == NULL) { | |
| + dev_err(dev, "failed to allocate %d bytes of coherent memory for Rx completion descriptors\n", | |
| + chan->rx_descs_num * AL_CRYPTO_RX_CDESC_SIZE); | |
| + | |
| + al_crypto_free_chan_resources(chan); | |
| + return -ENOMEM; | |
| + } | |
| + | |
| + /* clear the Rx completion descriptors to avoid false positive */ | |
| + memset( | |
| + chan->rx_dma_cdesc_virt, | |
| + 0, | |
| + chan->rx_descs_num * AL_CRYPTO_RX_CDESC_SIZE); | |
| + | |
| + dev_dbg( | |
| + dev, | |
| + "allocted rx completion desc ring: virt 0x%p phys 0x%llx\n", | |
| + chan->rx_dma_cdesc_virt, (u64)chan->rx_dma_cdesc); | |
| + | |
| + rc = al_ssm_dma_handle_get( | |
| + &device->hal_crypto, | |
| + UDMA_TX, | |
| + &crypto_udma); | |
| + if (rc) { | |
| + dev_err(to_dev(chan), "al_crypto_dma_handle_get failed\n"); | |
| + al_crypto_free_chan_resources(chan); | |
| + return rc; | |
| + } | |
| + | |
| + conf.encode_64k_as_zero = true; | |
| + conf.max_pkt_size = 0xfffff; | |
| + al_udma_m2s_packet_size_cfg_set(crypto_udma, &conf); | |
| + | |
| + tx_params.size = chan->tx_descs_num; | |
| + tx_params.desc_base = chan->tx_dma_desc_virt; | |
| + tx_params.desc_phy_base = chan->tx_dma_desc; | |
| + tx_params.cdesc_base = NULL; /* don't use Tx completion ring */ | |
| + tx_params.cdesc_phy_base = 0; | |
| + tx_params.cdesc_size = AL_CRYPTO_TX_CDESC_SIZE; /* size is needed */ | |
| + | |
| + rx_params.size = chan->rx_descs_num; | |
| + rx_params.desc_base = chan->rx_dma_desc_virt; | |
| + rx_params.desc_phy_base = chan->rx_dma_desc; | |
| + rx_params.cdesc_base = chan->rx_dma_cdesc_virt; | |
| + rx_params.cdesc_phy_base = chan->rx_dma_cdesc; | |
| + rx_params.cdesc_size = AL_CRYPTO_RX_CDESC_SIZE; | |
| + | |
| + /* alloc sw descriptors */ | |
| + if (ring_alloc_order < AL_CRYPTO_SW_RING_MIN_ORDER) { | |
| + dev_err( | |
| + dev, | |
| + "%s: ring_alloc_order = %d < %d!\n", | |
| + __func__, | |
| + ring_alloc_order, | |
| + AL_CRYPTO_SW_RING_MIN_ORDER); | |
| + | |
| + al_crypto_free_chan_resources(chan); | |
| + return -EINVAL; | |
| + } else if (ring_alloc_order > AL_CRYPTO_SW_RING_MAX_ORDER) { | |
| + dev_err( | |
| + dev, | |
| + "%s: ring_alloc_order = %d > %d!\n", | |
| + __func__, | |
| + ring_alloc_order, | |
| + AL_CRYPTO_SW_RING_MAX_ORDER); | |
| + | |
| + al_crypto_free_chan_resources(chan); | |
| + return -EINVAL; | |
| + } else if (ring_alloc_order > rx_descs_order) { | |
| + dev_warn( | |
| + dev, | |
| + "%s: ring_alloc_order > rx_descs_order (%d>%d)!\n", | |
| + __func__, | |
| + ring_alloc_order, | |
| + rx_descs_order); | |
| + | |
| + } | |
| + | |
| + sw_ring = al_crypto_alloc_sw_ring(chan, ring_alloc_order, GFP_KERNEL); | |
| + if (!sw_ring) { | |
| + dev_err( | |
| + dev, | |
| + "%s: sw ring alloc failed! ring_alloc_order = %d\n", | |
| + __func__, | |
| + ring_alloc_order); | |
| + | |
| + al_crypto_free_chan_resources(chan); | |
| + return -ENOMEM; | |
| + } | |
| + | |
| + spin_lock_bh(&chan->cleanup_lock); | |
| + spin_lock_bh(&chan->prep_lock); | |
| + chan->sw_ring = sw_ring; | |
| + chan->head = 0; | |
| + chan->tail = 0; | |
| + chan->alloc_order = ring_alloc_order; | |
| + chan->type = al_crypto_is_crypt_auth_chan(chan) ? | |
| + AL_CRYPT_AUTH_Q : AL_MEM_CRC_MEMCPY_Q; | |
| + | |
| + chan->cache_entries_num = al_crypto_is_crypt_auth_chan(chan) ? | |
| + (CACHED_SAD_SIZE / (device->num_channels - | |
| + device->crc_channels)) : | |
| + (CRC_IV_CACHE_SIZE / device->crc_channels); | |
| + | |
| + rc = al_ssm_dma_q_init(&device->hal_crypto, chan->idx, | |
| + &tx_params, &rx_params, chan->type); | |
| + if (rc) { | |
| + dev_err(dev, "failed to initialize hal q %d. rc %d\n", | |
| + chan->idx, rc); | |
| + | |
| + spin_unlock_bh(&chan->prep_lock); | |
| + spin_unlock_bh(&chan->cleanup_lock); | |
| + al_crypto_free_chan_resources(chan); | |
| + return -ENOMEM; | |
| + } | |
| + | |
| + spin_unlock_bh(&chan->prep_lock); | |
| + spin_unlock_bh(&chan->cleanup_lock); | |
| + | |
| + /* should we return less ?*/ | |
| + return 1 << chan->alloc_order; | |
| +} | |
| + | |
| +/****************************************************************************** | |
| + *****************************************************************************/ | |
| +/* Free tx and rx descriptor rings for one channel | |
| + */ | |
| +static void al_crypto_free_chan_resources(struct al_crypto_chan *chan) | |
| +{ | |
| + struct device *dev = to_dev(chan); | |
| + | |
| + dev_dbg(dev, "%s: %p\n", __func__, chan); | |
| + | |
| + tasklet_disable(&chan->cleanup_task); | |
| + | |
| + al_crypto_cleanup_fn(chan, 0); | |
| + | |
| + spin_lock_bh(&chan->cleanup_lock); | |
| + | |
| + al_crypto_free_sw_ring(chan->sw_ring, chan , 1 << chan->alloc_order); | |
| + | |
| + if (chan->tx_dma_desc_virt != NULL) { | |
| + dma_free_coherent( | |
| + dev, | |
| + chan->tx_descs_num * sizeof(union al_udma_desc), | |
| + chan->tx_dma_desc_virt, chan->tx_dma_desc); | |
| + chan->tx_dma_desc_virt = NULL; | |
| + } | |
| + | |
| + if (chan->rx_dma_desc_virt != NULL) { | |
| + dma_free_coherent( | |
| + dev, | |
| + chan->rx_descs_num * sizeof(union al_udma_desc), | |
| + chan->rx_dma_desc_virt, | |
| + chan->rx_dma_desc); | |
| + chan->rx_dma_desc_virt = NULL; | |
| + } | |
| + | |
| + if (chan->rx_dma_cdesc_virt != NULL) { | |
| + dma_free_coherent(dev, chan->rx_descs_num * | |
| + AL_CRYPTO_RX_CDESC_SIZE, | |
| + chan->rx_dma_cdesc_virt, chan->rx_dma_cdesc); | |
| + chan->rx_dma_desc_virt = NULL; | |
| + } | |
| + | |
| + spin_unlock_bh(&chan->cleanup_lock); | |
| + | |
| + return; | |
| +} | |
| + | |
| +/****************************************************************************** | |
| + *****************************************************************************/ | |
| +/* Alloc sw descriptors ring | |
| + */ | |
| +static struct al_crypto_sw_desc **al_crypto_alloc_sw_ring( | |
| + struct al_crypto_chan *chan, | |
| + int order, | |
| + gfp_t flags) | |
| +{ | |
| + struct al_crypto_sw_desc **ring; | |
| + int descs = 1 << order; | |
| + int i; | |
| + | |
| + /* allocate the array to hold the software ring */ | |
| + ring = kcalloc(descs, sizeof(*ring), flags); | |
| + if (!ring) | |
| + return NULL; | |
| + for (i = 0; i < descs; i++) { | |
| + ring[i] = al_crypto_alloc_ring_ent(chan, flags); | |
| + if (!ring[i]) { | |
| + al_crypto_free_sw_ring(ring, chan , i); | |
| + return NULL; | |
| + } | |
| + /* set_desc_id(ring[i], i); */ | |
| + } | |
| + | |
| + return ring; | |
| +} | |
| + | |
| +/****************************************************************************** | |
| + *****************************************************************************/ | |
| +/* Free sw descriptors ring | |
| +*/ | |
| +static void al_crypto_free_sw_ring( | |
| + struct al_crypto_sw_desc **ring, | |
| + struct al_crypto_chan *chan, | |
| + int size) | |
| +{ | |
| + int i; | |
| + | |
| + for (i = 0; i < size; i++) | |
| + al_crypto_free_ring_ent(ring[i], chan); | |
| + | |
| + kfree(ring); | |
| +} | |
| + | |
| +/****************************************************************************** | |
| + *****************************************************************************/ | |
| +/* Alloc sw descriptor | |
| + */ | |
| +static struct al_crypto_sw_desc *al_crypto_alloc_ring_ent( | |
| + struct al_crypto_chan *chan, | |
| + gfp_t flags) | |
| +{ | |
| + struct al_crypto_sw_desc *desc; | |
| + | |
| + desc = kmem_cache_zalloc(chan->device->cache, flags); | |
| + if (!desc) | |
| + return NULL; | |
| + | |
| + return desc; | |
| +} | |
| + | |
| +/****************************************************************************** | |
| + *****************************************************************************/ | |
| +/* Free sw descriptor | |
| + */ | |
| +static void al_crypto_free_ring_ent( | |
| + struct al_crypto_sw_desc *desc, | |
| + struct al_crypto_chan *chan) | |
| +{ | |
| + kmem_cache_free(chan->device->cache, desc); | |
| +} | |
| + | |
| +/****************************************************************************** | |
| + *****************************************************************************/ | |
| +/* Get sw desc | |
| + */ | |
| +int al_crypto_get_sw_desc(struct al_crypto_chan *chan, int num) | |
| +{ | |
| + if (likely(al_crypto_ring_space(chan) >= num)) { | |
| + dev_dbg(to_dev(chan), "%s: (%x:%x)\n", | |
| + __func__, chan->head, chan->tail); | |
| + return 0; | |
| + } | |
| + | |
| + return -ENOMEM; | |
| +} | |
| + | |
| +/****************************************************************************** | |
| + *****************************************************************************/ | |
| +/* Handler used for vector-per-channel interrupt mode | |
| + */ | |
| +static irqreturn_t al_crypto_do_interrupt_msix(int irq, void *data) | |
| +{ | |
| + struct al_crypto_chan *chan = data; | |
| + | |
| + pr_debug("%s(%d, %p)\n", __func__, irq, data); | |
| + | |
| + tasklet_schedule(&chan->cleanup_task); | |
| + | |
| + return IRQ_HANDLED; | |
| +} | |
| + | |
| +/****************************************************************************** | |
| + *****************************************************************************/ | |
| +/* Handler for interrupt group d | |
| + */ | |
| +static irqreturn_t al_crypto_do_interrupt_group_d(int irq, void *data) | |
| +{ | |
| + struct al_crypto_device *device = data; | |
| + | |
| + pr_debug("%s(%d, %p)\n", __func__, irq, device); | |
| + | |
| + al_crypto_group_d_errors_handler(device); | |
| + | |
| + return IRQ_HANDLED; | |
| +} | |
| + | |
| +/****************************************************************************** | |
| + *****************************************************************************/ | |
| +/* Handler used for vector-per-group interrupt mode | |
| + */ | |
| +static irqreturn_t al_crypto_do_interrupt_msix_rx(int irq, void *data) | |
| +{ | |
| + struct al_crypto_device *device = data; | |
| + | |
| + pr_debug("%s(%d, %p)\n", __func__, irq, data); | |
| + | |
| + tasklet_schedule(&device->cleanup_task); | |
| + | |
| + return IRQ_HANDLED; | |
| +} | |
| + | |
| +/****************************************************************************** | |
| + *****************************************************************************/ | |
| +/* Handler used for legacy interrupt mode | |
| + */ | |
| +static irqreturn_t al_crypto_do_interrupt_legacy(int irq, void *data) | |
| +{ | |
| + struct al_crypto_device *device = data; | |
| + | |
| + pr_debug("%s(%d, %p)\n", __func__, irq, data); | |
| + | |
| + al_udma_iofic_mask( | |
| + (struct unit_regs *)device->udma_regs_base, | |
| + AL_UDMA_IOFIC_LEVEL_PRIMARY, | |
| + AL_INT_GROUP_A, | |
| + AL_INT_GROUP_A_GROUP_B_SUM | | |
| + AL_INT_GROUP_A_GROUP_D_SUM); | |
| + | |
| + tasklet_schedule(&device->cleanup_task); | |
| + | |
| + return IRQ_HANDLED; | |
| +} | |
| + | |
| +/****************************************************************************** | |
| + *****************************************************************************/ | |
| +int al_crypto_cleanup_fn(struct al_crypto_chan *chan, int from_tasklet) | |
| +{ | |
| + struct al_crypto_sw_desc *desc; | |
| + uint32_t comp_status; | |
| + u16 active; | |
| + int idx, i, rc; | |
| + | |
| + spin_lock_bh(&chan->cleanup_lock); | |
| + idx = chan->tail; | |
| + | |
| + dev_dbg(to_dev(chan), "%s: head: %#x tail: %#x\n", | |
| + __func__, chan->head, chan->tail); | |
| + | |
| + active = al_crypto_ring_active(chan); | |
| + | |
| + AL_CRYPTO_STATS_SET(chan->stats_comp.max_active_descs, | |
| + (active > chan->stats_comp.max_active_descs) ? | |
| + active : | |
| + chan->stats_comp.max_active_descs); | |
| + | |
| + for (i = 0; i < active; i++) { | |
| + rc = al_crypto_dma_completion(chan->hal_crypto, chan->idx, | |
| + &comp_status); | |
| + | |
| + /* if no completed transaction found -> exit */ | |
| + if (rc == 0) { | |
| + dev_dbg(to_dev(chan), "%s: No completion\n", | |
| + __func__); | |
| + | |
| + break; | |
| + } | |
| + | |
| + dev_dbg( | |
| + to_dev(chan), | |
| + "%s: completion status: %u\n", | |
| + __func__, | |
| + comp_status); | |
| + | |
| + /* This will instruct the CPU to make sure the index is up to | |
| + date before reading the new item */ | |
| + smp_read_barrier_depends(); | |
| + | |
| + desc = al_crypto_get_ring_ent(chan, idx + i); | |
| + | |
| + if (desc->req_type == AL_CRYPTO_REQ_ABLKCIPHER) | |
| + al_crypto_cleanup_single_ablkcipher( | |
| + chan, desc, comp_status); | |
| + else if (desc->req_type == AL_CRYPTO_REQ_AHASH) | |
| + al_crypto_cleanup_single_ahash( | |
| + chan, desc, comp_status); | |
| + else if (desc->req_type == AL_CRYPTO_REQ_CRC) | |
| + al_crypto_cleanup_single_crc( | |
| + chan, desc, comp_status); | |
| + else { | |
| + dev_err(to_dev(chan), | |
| + "alg type %d is not supported\n", | |
| + desc->req_type); | |
| + | |
| + BUG(); | |
| + } | |
| + } | |
| + | |
| + /* This will make sure the CPU has finished reading the item | |
| + before it writes the new tail pointer, which will erase the item */ | |
| + smp_mb(); /* finish all descriptor reads before incrementing tail */ | |
| + | |
| + chan->tail = idx + i; | |
| + | |
| + /* Keep track of redundant interrupts - interrupts that doesn't | |
| + yield completions */ | |
| + if (unlikely(from_tasklet && (!i))) | |
| + AL_CRYPTO_STATS_INC(chan->stats_comp.redundant_int_cnt, 1); | |
| + | |
| + spin_unlock_bh(&chan->cleanup_lock); | |
| + | |
| + /* Currently only ablkcipher reqs can be backlogged */ | |
| + if (i && chan->sw_queue.qlen) | |
| + ablkcipher_process_queue(chan); | |
| + | |
| + return i; | |
| +}; | |
| + | |
| +/****************************************************************************** | |
| + *****************************************************************************/ | |
| +static void al_crypto_group_d_errors_handler(struct al_crypto_device *device) | |
| +{ | |
| + u32 read_cause_group_d, read_cause_crypto_reg_a; | |
| + | |
| + read_cause_group_d = al_udma_iofic_read_cause(device->udma_regs_base, | |
| + AL_UDMA_IOFIC_LEVEL_PRIMARY, | |
| + AL_INT_GROUP_D); | |
| + | |
| + dev_err(&device->pdev->dev, | |
| + "got error - %08x from group D\n", | |
| + read_cause_group_d); | |
| + | |
| + | |
| + if (read_cause_group_d & AL_INT_GROUP_D_APP_EXT_INT) { | |
| + read_cause_crypto_reg_a = | |
| + al_iofic_read_cause( | |
| + device->crypto_regs_base + | |
| + AL_CRYPTO_APP_IOFIC_OFFSET, | |
| + AL_INT_GROUP_A); | |
| + | |
| + al_iofic_unmask( | |
| + device->crypto_regs_base + AL_CRYPTO_APP_IOFIC_OFFSET, | |
| + AL_INT_GROUP_A, | |
| + AL_CRYPTO_APP_INT_A_ALL); | |
| + | |
| + al_udma_iofic_unmask( | |
| + (struct unit_regs *)device->udma_regs_base, | |
| + AL_UDMA_IOFIC_LEVEL_PRIMARY, | |
| + AL_INT_GROUP_A, | |
| + AL_INT_GROUP_A_GROUP_D_SUM); | |
| + | |
| + dev_err(&device->pdev->dev, | |
| + "got error - %08x from APP group A\n", | |
| + read_cause_crypto_reg_a); | |
| + } | |
| +} | |
| + | |
| +/****************************************************************************** | |
| + *****************************************************************************/ | |
| +static void al_crypto_cleanup_tasklet(unsigned long data) | |
| +{ | |
| + struct al_crypto_chan *chan = (struct al_crypto_chan *)data; | |
| + int num_completed; | |
| + | |
| + num_completed = al_crypto_cleanup_fn(chan, 1); | |
| + | |
| + if (unlikely(num_completed < 0)) | |
| + dev_err( | |
| + to_dev(chan), | |
| + "al_crypto_cleanup_fn failed\n"); | |
| + | |
| + al_udma_iofic_unmask( | |
| + (struct unit_regs *)chan->device->udma_regs_base, | |
| + AL_UDMA_IOFIC_LEVEL_PRIMARY, | |
| + AL_INT_GROUP_B, | |
| + 1 << chan->idx); | |
| +} | |
| + | |
| +/****************************************************************************** | |
| + *****************************************************************************/ | |
| +static inline void al_crypto_cleanup_q_group_fn( | |
| + struct al_crypto_device *device, | |
| + int group) | |
| +{ | |
| + int num_completed; | |
| + unsigned int status; | |
| + int i; | |
| + | |
| + status = al_udma_iofic_read_cause( | |
| + (struct unit_regs *)device->udma_regs_base, | |
| + AL_UDMA_IOFIC_LEVEL_PRIMARY, | |
| + group); | |
| + | |
| + for (i = 0; i < device->num_channels; i++) { | |
| + if (status & AL_BIT(i)) { | |
| + num_completed = al_crypto_cleanup_fn( | |
| + device->channels[i], 1); | |
| + | |
| + if (unlikely(num_completed < 0)) | |
| + dev_err(to_dev(device->channels[i]), | |
| + "al_crypto_cleanup_fn failed\n"); | |
| + } | |
| + } | |
| +} | |
| + | |
| +/****************************************************************************** | |
| + *****************************************************************************/ | |
| +static void al_crypto_cleanup_tasklet_msix_rx(unsigned long data) | |
| +{ | |
| + struct al_crypto_device *device = (struct al_crypto_device *)data; | |
| + unsigned int status; | |
| + | |
| + status = al_udma_iofic_read_cause( | |
| + (struct unit_regs *)device->udma_regs_base, | |
| + AL_UDMA_IOFIC_LEVEL_PRIMARY, | |
| + AL_INT_GROUP_D); | |
| + | |
| + if (unlikely(status)) | |
| + al_crypto_group_d_errors_handler(device); | |
| + | |
| + al_crypto_cleanup_q_group_fn(device, AL_INT_GROUP_B); | |
| + | |
| + al_udma_iofic_unmask( | |
| + (struct unit_regs *)device->udma_regs_base, | |
| + AL_UDMA_IOFIC_LEVEL_PRIMARY, | |
| + AL_INT_GROUP_A, | |
| + AL_INT_GROUP_A_GROUP_B_SUM); | |
| +} | |
| + | |
| +/****************************************************************************** | |
| + *****************************************************************************/ | |
| +static void al_crypto_cleanup_tasklet_legacy(unsigned long data) | |
| +{ | |
| + struct al_crypto_device *device = (struct al_crypto_device *)data; | |
| + unsigned int status; | |
| + | |
| + status = al_udma_iofic_read_cause( | |
| + (struct unit_regs *)device->udma_regs_base, | |
| + AL_UDMA_IOFIC_LEVEL_PRIMARY, | |
| + AL_INT_GROUP_A); | |
| + | |
| + if (unlikely(status & AL_INT_GROUP_A_GROUP_D_SUM)) | |
| + al_crypto_group_d_errors_handler(device); | |
| + else if (status & AL_INT_GROUP_A_GROUP_B_SUM) | |
| + al_crypto_cleanup_q_group_fn(device, AL_INT_GROUP_B); | |
| + | |
| + al_udma_iofic_unmask( | |
| + (struct unit_regs *)device->udma_regs_base, | |
| + AL_UDMA_IOFIC_LEVEL_PRIMARY, | |
| + AL_INT_GROUP_A, | |
| + AL_INT_GROUP_A_GROUP_B_SUM); | |
| +} | |
| + | |
| +/****************************************************************************** | |
| + *****************************************************************************/ | |
| +/* Update the LRU list according to the currently accessed entry | |
| + */ | |
| +void al_crypto_cache_update_lru(struct al_crypto_chan *chan, | |
| + struct al_crypto_cache_state *ctx) | |
| +{ | |
| + struct list_head *ptr; | |
| + struct al_crypto_cache_lru_entry *lru_entry = NULL; | |
| + uint32_t list_idx = 0; | |
| + | |
| + /* skip update if cache not yet populated */ | |
| + if (unlikely(chan->cache_lru_count <= 1)) | |
| + return; | |
| + | |
| + list_for_each(ptr, &chan->cache_lru_list) { | |
| + lru_entry = list_entry(ptr, | |
| + struct al_crypto_cache_lru_entry, | |
| + list); | |
| + if (lru_entry->ctx == ctx) | |
| + break; | |
| + list_idx++; | |
| + } | |
| + | |
| + /* The entry has to be in the list */ | |
| + BUG_ON(lru_entry->ctx != ctx); | |
| + | |
| + /* move to tail only if needed */ | |
| + if (list_idx != (chan->cache_lru_count - 1)) | |
| + list_move_tail(ptr, &chan->cache_lru_list); | |
| +} | |
| + | |
| +/****************************************************************************** | |
| + *****************************************************************************/ | |
| +/* Translate cache entry index in ring[0..3] to global index: [0..15] in sa | |
| + * sa cache, [0..7] in crc iv cache | |
| + */ | |
| +static inline uint32_t | |
| +al_crypto_ring_cache_idx(struct al_crypto_chan *chan, int cache_idx) | |
| +{ | |
| + struct al_crypto_device *device = chan->device; | |
| + int chan_idx = chan->idx; | |
| + | |
| + if (chan->idx >= (device->num_channels - device->crc_channels)) | |
| + chan_idx = chan->idx - | |
| + (device->num_channels - device->crc_channels); | |
| + | |
| + return (chan_idx * chan->cache_entries_num) + cache_idx; | |
| +} | |
| + | |
| +/****************************************************************************** | |
| + *****************************************************************************/ | |
| +/* Replace least recently used cache entry with current entry | |
| + */ | |
| +uint32_t al_crypto_cache_replace_lru(struct al_crypto_chan *chan, | |
| + struct al_crypto_cache_state *ctx, | |
| + struct al_crypto_cache_state **old_ctx) | |
| +{ | |
| + struct al_crypto_cache_lru_entry *lru_entry = NULL; | |
| + | |
| + if (chan->cache_lru_count < chan->cache_entries_num) { | |
| + /* find a free entry */ | |
| + int i; | |
| + for (i = 0; i < chan->cache_entries_num; i++) { | |
| + lru_entry = &chan->cache_lru_entries[i]; | |
| + if (lru_entry->ctx && lru_entry->ctx->cached) | |
| + continue; | |
| + else | |
| + break; | |
| + } | |
| + | |
| + BUG_ON(!lru_entry); | |
| + BUG_ON(i >= chan->cache_entries_num); | |
| + | |
| + lru_entry->cache_idx = | |
| + al_crypto_ring_cache_idx(chan, i); | |
| + lru_entry->ctx = ctx; | |
| + | |
| + list_add_tail(&lru_entry->list, | |
| + &chan->cache_lru_list); | |
| + chan->cache_lru_count++; | |
| + if (old_ctx) | |
| + *old_ctx = NULL; | |
| + } else { | |
| + AL_CRYPTO_STATS_INC(chan->stats_prep.cache_misses, 1); | |
| + lru_entry = list_first_entry(&chan->cache_lru_list, | |
| + struct al_crypto_cache_lru_entry, | |
| + list); | |
| + /* Invalidate old ctx */ | |
| + lru_entry->ctx->cached = false; | |
| + /* Return old ctx if needed */ | |
| + if (old_ctx) | |
| + *old_ctx = lru_entry->ctx; | |
| + /* Connect new ctx */ | |
| + lru_entry->ctx = ctx; | |
| + /* Move current entry to end of LRU list */ | |
| + list_rotate_left(&chan->cache_lru_list); | |
| + } | |
| + | |
| + ctx->cached = true; | |
| + ctx->idx = lru_entry->cache_idx; | |
| + return lru_entry->cache_idx; | |
| +} | |
| + | |
| +/****************************************************************************** | |
| + *****************************************************************************/ | |
| +/* Remove the entry from LRU list | |
| + */ | |
| +void al_crypto_cache_remove_lru(struct al_crypto_chan *chan, | |
| + struct al_crypto_cache_state *ctx) | |
| +{ | |
| + struct list_head *ptr; | |
| + struct al_crypto_cache_lru_entry *lru_entry = NULL; | |
| + uint32_t list_idx = 0; | |
| + | |
| + /* lru list is empty */ | |
| + if (chan->cache_lru_count == 0) | |
| + return; | |
| + | |
| + list_for_each(ptr, &chan->cache_lru_list) { | |
| + lru_entry = list_entry(ptr, | |
| + struct al_crypto_cache_lru_entry, | |
| + list); | |
| + if (lru_entry->ctx == ctx) | |
| + break; | |
| + list_idx++; | |
| + } | |
| + | |
| + /* The entry has to be in the list */ | |
| + BUG_ON(lru_entry->ctx != ctx); | |
| + | |
| + list_del(ptr); | |
| + lru_entry->ctx = NULL; | |
| + chan->cache_lru_count--; | |
| + ctx->cached = false; | |
| +} | |
| + | |
| +/****************************************************************************** | |
| + *****************************************************************************/ | |
| +/* Move ring tail to process prepared descriptors | |
| + */ | |
| +void al_crypto_tx_submit(struct al_crypto_chan *chan) | |
| +{ | |
| + dev_dbg( | |
| + to_dev(chan), | |
| + "%s: %p\n", | |
| + __func__, | |
| + chan); | |
| + | |
| + /* according to Documentation/circular-buffers.txt we should have */ | |
| + /* smp_wmb before intcrementing the head, however, the */ | |
| + /* al_crypto_dma_action contains writel() which implies dmb on ARM */ | |
| + /* so this smp_wmb() can be omitted on ARM platforms */ | |
| + /*smp_wmb();*/ /* commit the item before incrementing the head */ | |
| + chan->head += chan->sw_desc_num_locked; | |
| + /* in our case the consumer (interrupt handler) will be waken up by */ | |
| + /* the hw, so we send the transaction to the hw after incrementing */ | |
| + /* the head */ | |
| + | |
| + al_crypto_dma_action( | |
| + chan->hal_crypto, | |
| + chan->idx, | |
| + chan->tx_desc_produced); | |
| +} | |
| + | |
| +/****************************************************************************** | |
| + *****************************************************************************/ | |
| +/* Set interrupt moderation interval, each tick ~= 1.5usecs | |
| + */ | |
| +void al_crypto_set_int_moderation(struct al_crypto_device *device, int interval) | |
| +{ | |
| + int i; | |
| + | |
| + for (i = 0; i < device->num_channels; i++) | |
| + al_iofic_msix_moder_interval_config( | |
| + &((struct unit_regs *)(device->udma_regs_base))->gen. | |
| + interrupt_regs.main_iofic, | |
| + AL_INT_GROUP_B, | |
| + i, | |
| + interval); | |
| + | |
| + device->int_moderation = interval; | |
| +} | |
| + | |
| +/****************************************************************************** | |
| + *****************************************************************************/ | |
| +/* Get interrupt moderation interval | |
| + */ | |
| +int al_crypto_get_int_moderation(struct al_crypto_device *device) | |
| +{ | |
| + return device->int_moderation; | |
| +} | |
| diff -x .git -Naur linux-4.4.111/drivers/crypto/al/al_crypto_crc.c linux-4.4.111-alpine/drivers/crypto/al/al_crypto_crc.c | |
| --- linux-4.4.111/drivers/crypto/al/al_crypto_crc.c 1969-12-31 19:00:00.000000000 -0500 | |
| +++ linux-4.4.111-alpine/drivers/crypto/al/al_crypto_crc.c 2018-02-14 21:04:16.000000000 -0500 | |
| @@ -0,0 +1,622 @@ | |
| +/* | |
| + * drivers/crypto/al_crypto_crc.c | |
| + * | |
| + * Annapurna Labs Crypto driver - crc/checksum algorithms | |
| + * | |
| + * Copyright (C) 2013 Annapurna Labs Ltd. | |
| + * | |
| + * Algorithm registration code and chained scatter/gather lists | |
| + * handling based on caam driver. | |
| + * | |
| + * This program is free software; you can redistribute it and/or modify | |
| + * it under the terms of the GNU General Public License as published by | |
| + * the Free Software Foundation; either version 2 of the License, or | |
| + * (at your option) any later version. | |
| + * | |
| + * This program is distributed in the hope that it will be useful, | |
| + * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| + * GNU General Public License for more details. | |
| + * | |
| + * You should have received a copy of the GNU General Public License | |
| + * along with this program; if not, write to the Free Software | |
| + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
| + */ | |
| + | |
| +#include "linux/export.h" | |
| +#include "linux/crypto.h" | |
| +#include <crypto/algapi.h> | |
| +#include <linux/scatterlist.h> | |
| +#include <crypto/hash.h> | |
| +#include <crypto/internal/hash.h> | |
| +#include <linux/unaligned/access_ok.h> | |
| + | |
| +#include <soc/alpine/al_hal_ssm_crypto.h> | |
| +#include <soc/alpine/al_hal_ssm_crc_memcpy.h> | |
| + | |
| +#include "al_crypto.h" | |
| + | |
| +#define AL_CRYPTO_CRA_PRIORITY 300 | |
| + | |
| +static int crc_init(struct ahash_request *req); | |
| + | |
| +static int crc_update(struct ahash_request *req); | |
| + | |
| +static int crc_final(struct ahash_request *req); | |
| + | |
| +static int crc_finup(struct ahash_request *req); | |
| + | |
| +static int crc_digest(struct ahash_request *req); | |
| + | |
| +static int crc_export(struct ahash_request *req, void *out); | |
| + | |
| +static int crc_import(struct ahash_request *req, const void *in); | |
| + | |
| +static int crc_setkey(struct crypto_ahash *ahash, | |
| + const u8 *key, unsigned int keylen); | |
| + | |
| +struct al_crc_req_ctx { | |
| + /* Make sure the following field isn't share the same cache line | |
| + * with other fields. | |
| + * This field is DMAed */ | |
| + uint32_t result ____cacheline_aligned; | |
| + bool last ____cacheline_aligned; | |
| + struct al_crypto_cache_state cache_state; | |
| + dma_addr_t crc_dma_addr; | |
| +}; | |
| + | |
| +struct al_crc_ctx { | |
| + struct al_crypto_chan *chan; | |
| + enum al_crc_checksum_type crcsum_type; | |
| + uint32_t key; | |
| +}; | |
| + | |
| +struct al_crc_template { | |
| + char name[CRYPTO_MAX_ALG_NAME]; | |
| + char driver_name[CRYPTO_MAX_ALG_NAME]; | |
| + unsigned int blocksize; | |
| + struct ahash_alg template_ahash; | |
| + enum al_crc_checksum_type crcsum_type; | |
| +}; | |
| + | |
| +static struct al_crc_template driver_crc[] = { | |
| + { | |
| + .name = "crc32c", | |
| + .driver_name = "crc32c-al", | |
| + .blocksize = CHKSUM_BLOCK_SIZE, | |
| + .template_ahash = { | |
| + .init = crc_init, | |
| + .update = crc_update, | |
| + .final = crc_final, | |
| + .finup = crc_finup, | |
| + .digest = crc_digest, | |
| + .export = crc_export, | |
| + .import = crc_import, | |
| + .setkey = crc_setkey, | |
| + .halg = { | |
| + .digestsize = CHKSUM_DIGEST_SIZE, | |
| + .statesize = sizeof(struct al_crc_ctx), | |
| + }, | |
| + }, | |
| + .crcsum_type = AL_CRC_CHECKSUM_CRC32C, | |
| + }, | |
| +}; | |
| + | |
| +struct al_crc { | |
| + struct list_head entry; | |
| + struct al_crypto_device *device; | |
| + enum al_crc_checksum_type crcsum_type; | |
| + struct ahash_alg ahash_alg; | |
| +}; | |
| + | |
| +/****************************************************************************** | |
| + *****************************************************************************/ | |
| +static int al_crc_cra_init(struct crypto_tfm *tfm) | |
| +{ | |
| + struct crypto_alg *base = tfm->__crt_alg; | |
| + struct hash_alg_common *halg = | |
| + container_of(base, struct hash_alg_common, base); | |
| + struct ahash_alg *alg = | |
| + container_of(halg, struct ahash_alg, halg); | |
| + struct al_crc *al_crc = | |
| + container_of(alg, struct al_crc, ahash_alg); | |
| + struct al_crc_ctx *ctx = crypto_tfm_ctx(tfm); | |
| + struct al_crypto_device *device = al_crc->device; | |
| + int chan_idx = (atomic_inc_return(&device->crc_tfm_count) % | |
| + device->crc_channels) + | |
| + (device->num_channels - device->crc_channels); | |
| + | |
| + ctx->chan = device->channels[chan_idx]; | |
| + | |
| + ctx->crcsum_type = al_crc->crcsum_type; | |
| + | |
| + ctx->key = 0; | |
| + | |
| + crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm), | |
| + sizeof(struct al_crc_req_ctx)); | |
| + | |
| + AL_CRYPTO_STATS_LOCK(&ctx->chan->stats_gen_lock); | |
| + AL_CRYPTO_STATS_INC(ctx->chan->stats_gen.crc_tfms, 1); | |
| + AL_CRYPTO_STATS_UNLOCK(&ctx->chan->stats_gen_lock); | |
| + | |
| + return 0; | |
| +} | |
| + | |
| +/****************************************************************************** | |
| + *****************************************************************************/ | |
| +static void al_crc_cra_exit(struct crypto_tfm *tfm) | |
| +{ | |
| + struct al_crc_ctx *ctx = crypto_tfm_ctx(tfm); | |
| + | |
| + AL_CRYPTO_STATS_LOCK(&ctx->chan->stats_gen_lock); | |
| + AL_CRYPTO_STATS_DEC(ctx->chan->stats_gen.crc_tfms, 1); | |
| + AL_CRYPTO_STATS_UNLOCK(&ctx->chan->stats_gen_lock); | |
| + | |
| + return; | |
| +} | |
| + | |
| +/****************************************************************************** | |
| + *****************************************************************************/ | |
| +/* DMA unmap buffers for crc request | |
| + */ | |
| +static inline void al_crypto_dma_unmap_crc( | |
| + struct al_crypto_chan *chan, | |
| + struct al_crypto_sw_desc *desc) | |
| +{ | |
| + struct ahash_request *req = | |
| + (struct ahash_request *)desc->req; | |
| + struct al_crc_req_ctx *req_ctx = | |
| + ahash_request_ctx(req); | |
| + struct crypto_ahash *ahash = crypto_ahash_reqtfm(req); | |
| + unsigned int digestsize = crypto_ahash_digestsize(ahash); | |
| + | |
| + if (desc->src_nents) | |
| + dma_unmap_sg(to_dev(chan), | |
| + req->src, | |
| + desc->src_nents, | |
| + DMA_TO_DEVICE); | |
| + | |
| + if (req_ctx->last) { | |
| + dma_unmap_single(to_dev(chan), | |
| + req_ctx->crc_dma_addr, | |
| + digestsize, | |
| + DMA_BIDIRECTIONAL); | |
| + put_unaligned_le32(req_ctx->result, req->result); | |
| + } | |
| +} | |
| + | |
| +/****************************************************************************** | |
| + *****************************************************************************/ | |
| +/* Cleanup single crc request - invoked from cleanup tasklet (interrupt | |
| + * handler) | |
| + */ | |
| +void al_crypto_cleanup_single_crc( | |
| + struct al_crypto_chan *chan, | |
| + struct al_crypto_sw_desc *desc, | |
| + uint32_t comp_status) | |
| +{ | |
| + struct ahash_request *req = | |
| + (struct ahash_request *)desc->req; | |
| + struct crypto_ahash *ahash = crypto_ahash_reqtfm(req); | |
| + struct al_crc_ctx *ctx = crypto_ahash_ctx(ahash); | |
| + struct al_crc_req_ctx *req_ctx = ahash_request_ctx(req); | |
| + | |
| + al_crypto_dma_unmap_crc(chan, desc); | |
| + | |
| + /* LRU list access has to be protected */ | |
| + if (req_ctx->last) { | |
| + spin_lock(&ctx->chan->prep_lock); | |
| + if (req_ctx->cache_state.cached) | |
| + al_crypto_cache_remove_lru(chan, &req_ctx->cache_state); | |
| + spin_unlock(&ctx->chan->prep_lock); | |
| + } | |
| + | |
| + req->base.complete(&req->base, 0); | |
| +} | |
| + | |
| +/****************************************************************************** | |
| + *****************************************************************************/ | |
| +static int crc_init(struct ahash_request *req) | |
| +{ | |
| + struct crypto_ahash *ahash = crypto_ahash_reqtfm(req); | |
| + struct al_crc_ctx *ctx = crypto_ahash_ctx(ahash); | |
| + struct al_crc_req_ctx *req_ctx = ahash_request_ctx(req); | |
| + struct al_crypto_chan *chan = ctx->chan; | |
| + unsigned int digestsize = crypto_ahash_digestsize(ahash); | |
| + | |
| + req_ctx->last = false; | |
| + req_ctx->cache_state.cached = false; | |
| + | |
| + put_unaligned_le32(ctx->key, &req_ctx->result); | |
| + | |
| + req_ctx->crc_dma_addr = dma_map_single(to_dev(chan), | |
| + &req_ctx->result, | |
| + digestsize, | |
| + DMA_BIDIRECTIONAL); | |
| + | |
| + return 0; | |
| +} | |
| + | |
| +/****************************************************************************** | |
| + *****************************************************************************/ | |
| +static inline void crc_req_prepare_xaction_buffers(struct ahash_request *req, | |
| + struct al_crypto_sw_desc *desc, | |
| + int nbytes, | |
| + int src_nents, | |
| + int *src_idx) | |
| +{ | |
| + struct al_crc_transaction *xaction; | |
| + | |
| + xaction = &desc->hal_crc_xaction; | |
| + *src_idx = 0; | |
| + | |
| + if (src_nents) | |
| + sg_map_to_xaction_buffers(req->src, desc->src_bufs, nbytes, | |
| + src_idx); | |
| +} | |
| + | |
| +/****************************************************************************** | |
| + *****************************************************************************/ | |
| +static inline void crc_update_stats(int nbytes, | |
| + struct al_crypto_chan *chan) | |
| +{ | |
| + AL_CRYPTO_STATS_INC(chan->stats_prep.crc_reqs, 1); | |
| + AL_CRYPTO_STATS_INC(chan->stats_prep.crc_bytes, nbytes); | |
| + | |
| + if (nbytes <= 512) | |
| + AL_CRYPTO_STATS_INC(chan->stats_prep.crc_reqs_le512, 1); | |
| + else if ((nbytes > 512) && (nbytes <= 2048)) | |
| + AL_CRYPTO_STATS_INC(chan->stats_prep.crc_reqs_512_2048, 1); | |
| + else if ((nbytes > 2048) && (nbytes <= 4096)) | |
| + AL_CRYPTO_STATS_INC(chan->stats_prep.crc_reqs_2048_4096, 1); | |
| + else | |
| + AL_CRYPTO_STATS_INC(chan->stats_prep.crc_reqs_gt4096, 1); | |
| +} | |
| + | |
| +/****************************************************************************** | |
| + *****************************************************************************/ | |
| +static inline void crc_req_prepare_xaction(struct ahash_request *req, | |
| + int nbytes, | |
| + struct al_crypto_sw_desc *desc, | |
| + int src_nents) | |
| +{ | |
| + struct crypto_ahash *ahash = crypto_ahash_reqtfm(req); | |
| + struct al_crc_ctx *ctx = crypto_ahash_ctx(ahash); | |
| + struct al_crc_req_ctx *req_ctx = ahash_request_ctx(req); | |
| + struct al_crypto_chan *chan = ctx->chan; | |
| + struct al_crc_transaction *xaction; | |
| + unsigned int digestsize = crypto_ahash_digestsize(ahash); | |
| + int src_idx; | |
| + | |
| + /* prepare hal transaction */ | |
| + xaction = &desc->hal_crc_xaction; | |
| + memset(xaction, 0, sizeof(struct al_crc_transaction)); | |
| + xaction->crcsum_type = ctx->crcsum_type; | |
| + xaction->xor_valid = AL_TRUE; | |
| + xaction->in_xor = ~0; | |
| + xaction->res_xor = ~0; | |
| + | |
| + /* if the entry is not cached, take stored iv */ | |
| + if (!(req_ctx->cache_state.cached)) { | |
| + xaction->crc_iv_in.addr = req_ctx->crc_dma_addr; | |
| + xaction->crc_iv_in.len = digestsize; | |
| + } | |
| + | |
| + /* both store in cache and output intermediate result */ | |
| + /* cached result will be used unless it will be replaced */ | |
| + xaction->crc_out.addr = req_ctx->crc_dma_addr; | |
| + xaction->crc_out.len = digestsize; | |
| + | |
| + if (likely(!req_ctx->last)) { | |
| + xaction->st_crc_out = AL_TRUE; | |
| + | |
| + if (!req_ctx->cache_state.cached) { | |
| + xaction->cached_crc_indx = al_crypto_cache_replace_lru( | |
| + chan, &req_ctx->cache_state, | |
| + NULL); | |
| + xaction->flags = AL_SSM_BARRIER; | |
| + } else { | |
| + al_crypto_cache_update_lru(chan, &req_ctx->cache_state); | |
| + xaction->cached_crc_indx = req_ctx->cache_state.idx; | |
| + } | |
| + } | |
| + | |
| + crc_req_prepare_xaction_buffers(req, desc, nbytes, src_nents, | |
| + &src_idx); | |
| + | |
| + xaction->src.bufs = &desc->src_bufs[0]; | |
| + xaction->src.num = src_idx; | |
| + | |
| + dev_dbg(to_dev(chan), | |
| + "%s: req_ctx->cache_state.cached=%d\n", | |
| + __func__, req_ctx->cache_state.cached); | |
| + | |
| + xaction->flags = AL_SSM_INTERRUPT; | |
| + | |
| + crc_update_stats(nbytes, chan); | |
| +} | |
| + | |
| +/****************************************************************************** | |
| + *****************************************************************************/ | |
| +/* Main CRC processing function that handles update/final/finup and digest | |
| + * | |
| + * Implementation is based on the assumption that the caller waits for | |
| + * completion of every operation before issuing the next operation | |
| + */ | |
| +static int crc_process_req(struct ahash_request *req, unsigned int nbytes) | |
| +{ | |
| + struct crypto_ahash *ahash = crypto_ahash_reqtfm(req); | |
| + struct al_crc_ctx *ctx = crypto_ahash_ctx(ahash); | |
| + struct al_crc_req_ctx *req_ctx = ahash_request_ctx(req); | |
| + struct al_crypto_chan *chan = ctx->chan; | |
| + unsigned int digestsize = crypto_ahash_digestsize(ahash); | |
| + | |
| + int idx; | |
| + int src_nents = 0; | |
| + struct al_crypto_sw_desc *desc; | |
| + int rc = 0; | |
| + | |
| + dev_dbg(to_dev(chan), | |
| + "%s: nbytes=%d, last=%d\n", | |
| + __func__, nbytes, req_ctx->last); | |
| + | |
| + if (nbytes) { | |
| + src_nents = sg_count(req->src, nbytes); | |
| + | |
| + dev_dbg(to_dev(chan), "%s: src_nents=%d\n", __func__, | |
| + src_nents); | |
| + | |
| + dma_map_sg(to_dev(chan), req->src, src_nents, | |
| + DMA_TO_DEVICE); | |
| + | |
| + spin_lock_bh(&chan->prep_lock); | |
| + if (likely(al_crypto_get_sw_desc(chan, 1) == 0)) | |
| + idx = chan->head; | |
| + else { | |
| + spin_unlock_bh(&chan->prep_lock); | |
| + dev_err( | |
| + to_dev(chan), | |
| + "%s: al_crypto_get_sw_desc failed!\n", | |
| + __func__); | |
| + | |
| + if (src_nents) | |
| + dma_unmap_sg(to_dev(chan), req->src, src_nents, | |
| + DMA_TO_DEVICE); | |
| + | |
| + return -ENOSPC; | |
| + } | |
| + | |
| + chan->sw_desc_num_locked = 1; | |
| + chan->tx_desc_produced = 0; | |
| + | |
| + desc = al_crypto_get_ring_ent(chan, idx); | |
| + desc->req = (void *)req; | |
| + desc->req_type = AL_CRYPTO_REQ_CRC; | |
| + desc->src_nents = src_nents; | |
| + | |
| + crc_req_prepare_xaction(req, nbytes, desc, src_nents); | |
| + | |
| + /* send crypto transaction to engine */ | |
| + rc = al_crc_csum_prepare(chan->hal_crypto, chan->idx, | |
| + &desc->hal_crc_xaction); | |
| + if (unlikely(rc != 0)) { | |
| + dev_err(to_dev(chan), | |
| + "al_crypto_dma_prepare failed!\n"); | |
| + | |
| + al_crypto_dma_unmap_crc(chan, desc); | |
| + | |
| + spin_unlock_bh(&chan->prep_lock); | |
| + return rc; | |
| + } | |
| + | |
| + chan->tx_desc_produced += desc->hal_crc_xaction.tx_descs_count; | |
| + | |
| + al_crypto_tx_submit(chan); | |
| + | |
| + spin_unlock_bh(&chan->prep_lock); | |
| + | |
| + return -EINPROGRESS; | |
| + } else if (likely(req_ctx->last)) { | |
| + dma_unmap_single(to_dev(chan), req_ctx->crc_dma_addr, | |
| + digestsize, DMA_BIDIRECTIONAL); | |
| + put_unaligned_le32(req_ctx->result, req->result); | |
| + | |
| + spin_lock_bh(&ctx->chan->prep_lock); | |
| + if (req_ctx->cache_state.cached) | |
| + al_crypto_cache |
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