gf180mcuD/gf180mcu_fd_sc_mcu7t5v0/APU
Metric | Before | After | Delta |
---|---|---|---|
clock__skew__worst_setup | 0.2601 | 0.2327 | -0.0275 (-10.5582%) ❗ |
design__instance__area | 107602 | 109714 | 2112 (+1.9628%) ❗ |
design__max_cap_violation__count | 15 | 19 | 4 (+26.6667%) ❗ |
ir__drop__avg | 0.0000 | 0.0000 | 0.0000 (+9.7368%) ❗ |
power__internal__total | 0.0090 | 0.0100 | 0.0009 (+10.0740%) ❗ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (+1.0770%) ❗ |
power__switching__total | 0.0048 | 0.0054 | 0.0005 (+11.2306%) ❗ |
power__total | 0.0139 | 0.0153 | 0.0015 (+10.4765%) ❗ |
clock__skew__worst_setup__corner:max_ff_n40C_5v50 | 0.2704 | 0.2454 | -0.0250 (-9.2358%) ❗ |
design__max_cap_violation__count__corner:max_ff_n40C_5v50 | 13 | 15 | 2 (+15.3846%) ❗ |
clock__skew__worst_setup__corner:max_ss_125C_4v50 | 0.7330 | 0.6537 | -0.0793 (-10.8141%) ❗ |
design__max_cap_violation__count__corner:max_ss_125C_4v50 | 15 | 19 | 4 (+26.6667%) ❗ |
clock__skew__worst_setup__corner:max_tt_025C_5v00 | 0.4134 | 0.3716 | -0.0418 (-10.1115%) ❗ |
design__max_cap_violation__count__corner:max_tt_025C_5v00 | 13 | 17 | 4 (+30.7692%) ❗ |
clock__skew__worst_setup__corner:min_ff_n40C_5v50 | 0.2601 | 0.2327 | -0.0275 (-10.5582%) ❗ |
design__max_cap_violation__count__corner:min_ff_n40C_5v50 | 6 | 10 | 4 (+66.6667%) ❗ |
clock__skew__worst_setup__corner:min_ss_125C_4v50 | 0.7087 | 0.6266 | -0.0822 (-11.5916%) ❗ |
design__max_cap_violation__count__corner:min_ss_125C_4v50 | 7 | 12 | 5 (+71.4286%) ❗ |
clock__skew__worst_setup__corner:min_tt_025C_5v00 | 0.3987 | 0.3544 | -0.0443 (-11.1165%) ❗ |
design__max_cap_violation__count__corner:min_tt_025C_5v00 | 7 | 11 | 4 (+57.1429%) ❗ |
clock__skew__worst_setup__corner:nom_ff_n40C_5v50 | 0.2648 | 0.2384 | -0.0263 (-9.9467%) ❗ |
design__max_cap_violation__count__corner:nom_ff_n40C_5v50 | 10 | 13 | 3 (+30.0000%) ❗ |
clock__skew__worst_setup__corner:nom_ss_125C_4v50 | 0.7198 | 0.6389 | -0.0809 (-11.2345%) ❗ |
design__max_cap_violation__count__corner:nom_ss_125C_4v50 | 10 | 13 | 3 (+30.0000%) ❗ |
clock__skew__worst_setup__corner:nom_tt_025C_5v00 | 0.4053 | 0.3622 | -0.0431 (-10.6265%) ❗ |
design__max_cap_violation__count__corner:nom_tt_025C_5v00 | 10 | 13 | 3 (+30.0000%) ❗ |
clock__skew__worst_hold | 0.7330 | 0.6537 | -0.0793 (-10.8141%) ⭕ |
ir__drop__worst | 0.0002 | 0.0002 | -0.0000 (-9.4675%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_5v50 | 0.2704 | 0.2454 | -0.0250 (-9.2358%) ⭕ |
clock__skew__worst_hold__corner:max_ss_125C_4v50 | 0.7330 | 0.6537 | -0.0793 (-10.8141%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_5v00 | 0.4134 | 0.3716 | -0.0418 (-10.1115%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_5v50 | 0.2601 | 0.2327 | -0.0275 (-10.5582%) ⭕ |
clock__skew__worst_hold__corner:min_ss_125C_4v50 | 0.7087 | 0.6266 | -0.0822 (-11.5916%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_5v00 | 0.3987 | 0.3544 | -0.0443 (-11.1165%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_5v50 | 0.2648 | 0.2384 | -0.0263 (-9.9467%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_125C_4v50 | 0.7198 | 0.6389 | -0.0809 (-11.2345%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_5v00 | 0.4053 | 0.3622 | -0.0431 (-10.6265%) ⭕ |
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
design__core__area | 284217 | 284217 | 0 (0.0000%) ⭕ |
design__die__area | 308622 | 308622 | 0 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 140 | 140 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
ir__voltage__worst | 5 | 5 | 0 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_5v50 | 140 | 140 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_125C_4v50 | 140 | 140 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_5v00 | 140 | 140 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_5v50 | 140 | 140 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_125C_4v50 | 140 | 140 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_5v00 | 140 | 140 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_5v50 | 140 | 140 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_125C_4v50 | 140 | 140 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_5v00 | 140 | 140 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
gf180mcuD/gf180mcu_fd_sc_mcu7t5v0/blink
Metric | Before | After | Delta |
---|---|---|---|
clock__skew__worst_hold | -0.0036 | -0.0018 | 0.0018 (-49.8596%) ❗ |
design__instance__area | 4151.1200 | 4168.6800 | 17.5600 (+0.4230%) ❗ |
ir__drop__avg | 0.0003 | 0.0003 | 0.0000 (+3.5433%) ❗ |
ir__drop__worst | 0.0006 | 0.0007 | 0.0000 (+6.4669%) ❗ |
power__internal__total | 0.0028 | 0.0028 | 0.0001 (+2.0107%) ❗ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (+0.7890%) ❗ |
power__switching__total | 0.0006 | 0.0006 | 0.0000 (+2.5397%) ❗ |
power__total | 0.0033 | 0.0034 | 0.0001 (+2.0990%) ❗ |
clock__skew__worst_hold__corner:max_ff_n40C_5v50 | -0.0042 | -0.0023 | 0.0019 (-44.3353%) ❗ |
clock__skew__worst_hold__corner:max_ss_125C_4v50 | -0.0083 | -0.0029 | 0.0054 (-64.8428%) ❗ |
clock__skew__worst_hold__corner:max_tt_025C_5v00 | -0.0055 | -0.0025 | 0.0029 (-53.8715%) ❗ |
clock__skew__worst_hold__corner:min_ff_n40C_5v50 | -0.0036 | -0.0018 | 0.0018 (-49.8596%) ❗ |
clock__skew__worst_hold__corner:min_ss_125C_4v50 | -0.0072 | -0.0021 | 0.0051 (-70.9530%) ❗ |
clock__skew__worst_hold__corner:min_tt_025C_5v00 | -0.0047 | -0.0019 | 0.0028 (-59.7320%) ❗ |
clock__skew__worst_hold__corner:nom_ff_n40C_5v50 | -0.0038 | -0.0020 | 0.0018 (-46.9595%) ❗ |
clock__skew__worst_hold__corner:nom_ss_125C_4v50 | -0.0077 | -0.0025 | 0.0053 (-67.8027%) ❗ |
clock__skew__worst_hold__corner:nom_tt_025C_5v00 | -0.0051 | -0.0022 | 0.0029 (-56.6851%) ❗ |
clock__skew__worst_setup | -0.0083 | -0.0029 | 0.0054 (-64.8428%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_5v50 | -0.0042 | -0.0023 | 0.0019 (-44.3353%) ⭕ |
clock__skew__worst_setup__corner:max_ss_125C_4v50 | -0.0083 | -0.0029 | 0.0054 (-64.8428%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_5v00 | -0.0055 | -0.0025 | 0.0029 (-53.8715%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_5v50 | -0.0036 | -0.0018 | 0.0018 (-49.8596%) ⭕ |
clock__skew__worst_setup__corner:min_ss_125C_4v50 | -0.0072 | -0.0021 | 0.0051 (-70.9530%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_5v00 | -0.0047 | -0.0019 | 0.0028 (-59.7320%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_5v50 | -0.0038 | -0.0020 | 0.0018 (-46.9595%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_125C_4v50 | -0.0077 | -0.0025 | 0.0053 (-67.8027%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_5v00 | -0.0051 | -0.0022 | 0.0029 (-56.6851%) ⭕ |
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
design__core__area | 6146.5600 | 6146.5600 | 0.0000 (0.0000%) ⭕ |
design__die__area | 10108.6000 | 10108.6000 | 0.0000 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
ir__voltage__worst | 5 | 5 | 0 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_5v50 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_125C_4v50 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_5v00 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_5v50 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_125C_4v50 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_5v00 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_5v50 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_125C_4v50 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_5v00 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
gf180mcuD/gf180mcu_fd_sc_mcu7t5v0/cell_inverter
Metric | Before | After | Delta |
---|---|---|---|
design__instance__area | 8.7808 | 8.7808 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
gf180mcuD/gf180mcu_fd_sc_mcu7t5v0/inverter
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
design__core__area | 570.7520 | 570.7520 | 0.0000 (0.0000%) ⭕ |
design__die__area | 2500 | 2500 | 0 (0.0000%) ⭕ |
design__instance__area | 57.0752 | 57.0752 | 0.0000 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
gf180mcuD/gf180mcu_fd_sc_mcu7t5v0/latch_bad
Metric | Before | After | Delta |
---|---|---|---|
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
gf180mcuD/gf180mcu_fd_sc_mcu7t5v0/latch_good
Metric | Before | After | Delta |
---|---|---|---|
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
gf180mcuD/gf180mcu_fd_sc_mcu7t5v0/spm
Metric | Before | After | Delta |
---|---|---|---|
clock__skew__worst_hold | -0.0086 | -0.0059 | 0.0027 (-31.6391%) ❗ |
design__instance__area | 11621.4000 | 11709.2000 | 87.8000 (+0.7555%) ❗ |
ir__drop__avg | 0.0004 | 0.0004 | 0.0000 (+1.5000%) ❗ |
ir__drop__worst | 0.0010 | 0.0011 | 0.0000 (+4.8544%) ❗ |
power__internal__total | 0.0071 | 0.0072 | 0.0001 (+0.9535%) ❗ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (+0.2823%) ❗ |
power__switching__total | 0.0021 | 0.0022 | 0.0001 (+3.2202%) ❗ |
power__total | 0.0092 | 0.0094 | 0.0001 (+1.4667%) ❗ |
clock__skew__worst_hold__corner:max_ff_n40C_5v50 | -0.0097 | -0.0076 | 0.0022 (-22.2781%) ❗ |
clock__skew__worst_hold__corner:max_ss_125C_4v50 | -0.0262 | -0.0199 | 0.0063 (-24.1248%) ❗ |
clock__skew__worst_hold__corner:max_tt_025C_5v00 | -0.0148 | -0.0114 | 0.0034 (-23.0474%) ❗ |
clock__skew__worst_hold__corner:min_ff_n40C_5v50 | -0.0086 | -0.0059 | 0.0027 (-31.6391%) ❗ |
clock__skew__worst_hold__corner:min_ss_125C_4v50 | -0.0231 | -0.0153 | 0.0078 (-33.8523%) ❗ |
clock__skew__worst_hold__corner:min_tt_025C_5v00 | -0.0131 | -0.0088 | 0.0043 (-32.6035%) ❗ |
clock__skew__worst_hold__corner:nom_ff_n40C_5v50 | -0.0091 | -0.0066 | 0.0025 (-26.9982%) ❗ |
clock__skew__worst_hold__corner:nom_ss_125C_4v50 | -0.0245 | -0.0174 | 0.0071 (-29.0282%) ❗ |
clock__skew__worst_hold__corner:nom_tt_025C_5v00 | -0.0139 | -0.0100 | 0.0039 (-27.8651%) ❗ |
clock__skew__worst_setup | -0.0262 | -0.0199 | 0.0063 (-24.1248%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_5v50 | -0.0097 | -0.0076 | 0.0022 (-22.2781%) ⭕ |
clock__skew__worst_setup__corner:max_ss_125C_4v50 | -0.0262 | -0.0199 | 0.0063 (-24.1248%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_5v00 | -0.0148 | -0.0114 | 0.0034 (-23.0474%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_5v50 | -0.0086 | -0.0059 | 0.0027 (-31.6391%) ⭕ |
clock__skew__worst_setup__corner:min_ss_125C_4v50 | -0.0231 | -0.0153 | 0.0078 (-33.8523%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_5v00 | -0.0131 | -0.0088 | 0.0043 (-32.6035%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_5v50 | -0.0091 | -0.0066 | 0.0025 (-26.9982%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_125C_4v50 | -0.0245 | -0.0174 | 0.0071 (-29.0282%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_5v00 | -0.0139 | -0.0100 | 0.0039 (-27.8651%) ⭕ |
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
design__core__area | 21280.3000 | 21280.3000 | 0.0000 (0.0000%) ⭕ |
design__die__area | 28670.3000 | 28670.3000 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
ir__voltage__worst | 5 | 5 | 0 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_5v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_5v50 | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_125C_4v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_125C_4v50 | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_5v00 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_5v00 | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_5v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_5v50 | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_125C_4v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_125C_4v50 | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_5v00 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_5v00 | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_5v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_5v50 | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_125C_4v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_125C_4v50 | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_5v00 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_5v00 | 9 | 9 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
gf180mcuD/gf180mcu_fd_sc_mcu7t5v0/usb
Metric | Before | After | Delta |
---|---|---|---|
design__instance__area | 31501.1000 | 31891.9000 | 390.8000 (+1.2406%) ❗ |
design__max_fanout_violation__count | 12 | 14 | 2 (+16.6667%) ❗ |
ir__drop__avg | 0.0003 | 0.0003 | 0.0000 (+6.2500%) ❗ |
ir__drop__worst | 0.0006 | 0.0006 | 0.0000 (+0.9772%) ❗ |
power__internal__total | 0.0156 | 0.0164 | 0.0008 (+5.2978%) ❗ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (+1.0323%) ❗ |
power__switching__total | 0.0054 | 0.0061 | 0.0006 (+11.7430%) ❗ |
power__total | 0.0210 | 0.0225 | 0.0015 (+6.9620%) ❗ |
clock__skew__worst_hold__corner:max_ff_n40C_5v50 | -0.0428 | -0.0200 | 0.0228 (-53.3354%) ❗ |
design__max_fanout_violation__count__corner:max_ff_n40C_5v50 | 12 | 14 | 2 (+16.6667%) ❗ |
clock__skew__worst_setup__corner:max_ss_125C_4v50 | 0.1113 | 0.0463 | -0.0650 (-58.4259%) ❗ |
design__max_fanout_violation__count__corner:max_ss_125C_4v50 | 12 | 14 | 2 (+16.6667%) ❗ |
clock__skew__worst_setup__corner:max_tt_025C_5v00 | 0.0642 | 0.0284 | -0.0358 (-55.8062%) ❗ |
design__max_fanout_violation__count__corner:max_tt_025C_5v00 | 12 | 14 | 2 (+16.6667%) ❗ |
clock__skew__worst_setup__corner:min_ff_n40C_5v50 | 0.0396 | 0.0153 | -0.0243 (-61.3296%) ❗ |
design__max_fanout_violation__count__corner:min_ff_n40C_5v50 | 12 | 14 | 2 (+16.6667%) ❗ |
clock__skew__worst_setup__corner:min_ss_125C_4v50 | 0.1040 | 0.0356 | -0.0685 (-65.7952%) ❗ |
design__max_fanout_violation__count__corner:min_ss_125C_4v50 | 12 | 14 | 2 (+16.6667%) ❗ |
clock__skew__worst_setup__corner:min_tt_025C_5v00 | 0.0597 | 0.0219 | -0.0379 (-63.3670%) ❗ |
design__max_fanout_violation__count__corner:min_tt_025C_5v00 | 12 | 14 | 2 (+16.6667%) ❗ |
clock__skew__worst_hold__corner:nom_ff_n40C_5v50 | -0.0409 | 0.0174 | 0.0583 (-142.5968%) ❗ |
design__max_fanout_violation__count__corner:nom_ff_n40C_5v50 | 12 | 14 | 2 (+16.6667%) ❗ |
clock__skew__worst_setup__corner:nom_ss_125C_4v50 | 0.1071 | 0.0405 | -0.0665 (-62.1464%) ❗ |
design__max_fanout_violation__count__corner:nom_ss_125C_4v50 | 12 | 14 | 2 (+16.6667%) ❗ |
clock__skew__worst_setup__corner:nom_tt_025C_5v00 | 0.0616 | 0.0249 | -0.0367 (-59.5987%) ❗ |
design__max_fanout_violation__count__corner:nom_tt_025C_5v00 | 12 | 14 | 2 (+16.6667%) ❗ |
clock__skew__worst_hold | 0.1113 | 0.0463 | -0.0650 (-58.4259%) ⭕ |
clock__skew__worst_setup | -0.0428 | -0.0200 | 0.0228 (-53.3354%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_5v50 | -0.0428 | -0.0200 | 0.0228 (-53.3354%) ⭕ |
clock__skew__worst_hold__corner:max_ss_125C_4v50 | 0.1113 | 0.0463 | -0.0650 (-58.4259%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_5v00 | 0.0642 | 0.0284 | -0.0358 (-55.8062%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_5v50 | 0.0396 | 0.0153 | -0.0243 (-61.3296%) ⭕ |
clock__skew__worst_hold__corner:min_ss_125C_4v50 | 0.1040 | 0.0356 | -0.0685 (-65.7952%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_5v00 | 0.0597 | 0.0219 | -0.0379 (-63.3670%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_5v50 | -0.0409 | 0.0174 | 0.0583 (-142.5968%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_125C_4v50 | 0.1071 | 0.0405 | -0.0665 (-62.1464%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_5v00 | 0.0616 | 0.0249 | -0.0367 (-59.5987%) ⭕ |
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
design__core__area | 59885.1000 | 59885.1000 | 0.0000 (0.0000%) ⭕ |
design__die__area | 72420.7000 | 72420.7000 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
ir__voltage__worst | 5 | 5 | 0 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_5v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_125C_4v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_5v00 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_5v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_125C_4v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_5v00 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_5v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_125C_4v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_5v00 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
gf180mcuD/gf180mcu_fd_sc_mcu7t5v0/usb_cdc_core
Metric | Before | After | Delta |
---|---|---|---|
timing__hold__tns | 0.0000 | -0.0121 | -0.0121 |
timing__hold__wns | 0.0000 | -0.0121 | -0.0121 |
timing__hold_vio__count | 0 | 1 | 1 |
timing__setup__tns | -140.5281 | -107.6689 | 32.8591 (-23.3826%) |
timing__setup__wns | -3.0528 | -2.6659 | 0.3869 (-12.6723%) |
timing__setup_r2r_vio__count | 307 | 232 | -75 (-24.4300%) |
timing__setup_vio__count | 340 | 265 | -75 (-22.0588%) |
timing__hold__tns__corner:max_ss_125C_4v50 | 0.0000 | -0.0121 | -0.0121 |
timing__hold__wns__corner:max_ss_125C_4v50 | 0.0000 | -0.0121 | -0.0121 |
timing__hold_vio__count__corner:max_ss_125C_4v50 | 0 | 1 | 1 |
timing__setup__tns__corner:max_ss_125C_4v50 | -140.5281 | -107.6689 | 32.8591 (-23.3826%) |
timing__setup__wns__corner:max_ss_125C_4v50 | -3.0528 | -2.6659 | 0.3869 (-12.6723%) |
timing__setup_r2r_vio__count__corner:max_ss_125C_4v50 | 118 | 99 | -19 (-16.1017%) |
timing__setup_vio__count__corner:max_ss_125C_4v50 | 129 | 110 | -19 (-14.7287%) |
timing__setup__tns__corner:min_ss_125C_4v50 | -103.8446 | -81.4578 | 22.3868 (-21.5580%) |
timing__setup__wns__corner:min_ss_125C_4v50 | -2.7181 | -2.4068 | 0.3113 (-11.4533%) |
timing__setup_r2r_vio__count__corner:min_ss_125C_4v50 | 81 | 60 | -21 (-25.9259%) |
timing__setup_vio__count__corner:min_ss_125C_4v50 | 92 | 71 | -21 (-22.8261%) |
timing__setup__tns__corner:nom_ss_125C_4v50 | -119.3090 | -91.8569 | 27.4521 (-23.0092%) |
timing__setup__wns__corner:nom_ss_125C_4v50 | -2.8715 | -2.5239 | 0.3476 (-12.1039%) |
timing__setup_r2r_vio__count__corner:nom_ss_125C_4v50 | 108 | 73 | -35 (-32.4074%) |
timing__setup_vio__count__corner:nom_ss_125C_4v50 | 119 | 84 | -35 (-29.4118%) |
clock__skew__worst_hold | 0.5254 | 0.5376 | 0.0123 (+2.3324%) ❗ |
design__instance__area | 73679.7000 | 75115.4000 | 1435.7000 (+1.9486%) ❗ |
design__max_cap_violation__count | 6 | 9 | 3 (+50.0000%) ❗ |
ir__drop__avg | 0.0004 | 0.0004 | 0.0000 (+8.6735%) ❗ |
ir__drop__worst | 0.0014 | 0.0016 | 0.0002 (+16.5468%) ❗ |
power__internal__total | 0.0556 | 0.0597 | 0.0041 (+7.3815%) ❗ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (+1.5692%) ❗ |
power__switching__total | 0.0206 | 0.0229 | 0.0022 (+10.8102%) ❗ |
power__total | 0.0762 | 0.0826 | 0.0063 (+8.3102%) ❗ |
clock__skew__worst_hold__corner:max_ff_n40C_5v50 | 0.1929 | 0.1996 | 0.0067 (+3.4818%) ❗ |
design__max_cap_violation__count__corner:max_ff_n40C_5v50 | 6 | 9 | 3 (+50.0000%) ❗ |
clock__skew__worst_hold__corner:max_ss_125C_4v50 | 0.5254 | 0.5376 | 0.0123 (+2.3324%) ❗ |
design__max_cap_violation__count__corner:max_ss_125C_4v50 | 6 | 9 | 3 (+50.0000%) ❗ |
clock__skew__worst_hold__corner:max_tt_025C_5v00 | 0.2953 | 0.3037 | 0.0084 (+2.8368%) ❗ |
design__max_cap_violation__count__corner:max_tt_025C_5v00 | 6 | 9 | 3 (+50.0000%) ❗ |
clock__skew__worst_hold__corner:min_ff_n40C_5v50 | 0.1867 | 0.1931 | 0.0065 (+3.4576%) ❗ |
design__max_cap_violation__count__corner:min_ff_n40C_5v50 | 6 | 9 | 3 (+50.0000%) ❗ |
clock__skew__worst_hold__corner:min_ss_125C_4v50 | 0.5114 | 0.5240 | 0.0126 (+2.4548%) ❗ |
design__max_cap_violation__count__corner:min_ss_125C_4v50 | 6 | 9 | 3 (+50.0000%) ❗ |
clock__skew__worst_hold__corner:min_tt_025C_5v00 | 0.2867 | 0.2950 | 0.0083 (+2.8911%) ❗ |
design__max_cap_violation__count__corner:min_tt_025C_5v00 | 6 | 9 | 3 (+50.0000%) ❗ |
clock__skew__worst_hold__corner:nom_ff_n40C_5v50 | 0.1895 | 0.1961 | 0.0066 (+3.4725%) ❗ |
design__max_cap_violation__count__corner:nom_ff_n40C_5v50 | 6 | 9 | 3 (+50.0000%) ❗ |
clock__skew__worst_hold__corner:nom_ss_125C_4v50 | 0.5178 | 0.5302 | 0.0124 (+2.3994%) ❗ |
design__max_cap_violation__count__corner:nom_ss_125C_4v50 | 6 | 9 | 3 (+50.0000%) ❗ |
clock__skew__worst_hold__corner:nom_tt_025C_5v00 | 0.2907 | 0.2990 | 0.0083 (+2.8675%) ❗ |
design__max_cap_violation__count__corner:nom_tt_025C_5v00 | 6 | 9 | 3 (+50.0000%) ❗ |
clock__skew__worst_setup | 0.1867 | 0.1931 | 0.0065 (+3.4576%) ⭕ |
design__max_fanout_violation__count | 83 | 81 | -2 (-2.4096%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_5v50 | 0.1929 | 0.1996 | 0.0067 (+3.4818%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_5v50 | 83 | 81 | -2 (-2.4096%) ⭕ |
clock__skew__worst_setup__corner:max_ss_125C_4v50 | 0.5254 | 0.5376 | 0.0123 (+2.3324%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_125C_4v50 | 83 | 81 | -2 (-2.4096%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_5v00 | 0.2953 | 0.3037 | 0.0084 (+2.8368%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_5v00 | 83 | 81 | -2 (-2.4096%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_5v50 | 0.1867 | 0.1931 | 0.0065 (+3.4576%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_5v50 | 83 | 81 | -2 (-2.4096%) ⭕ |
clock__skew__worst_setup__corner:min_ss_125C_4v50 | 0.5114 | 0.5240 | 0.0126 (+2.4548%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_125C_4v50 | 83 | 81 | -2 (-2.4096%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_5v00 | 0.2867 | 0.2950 | 0.0083 (+2.8911%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_5v00 | 83 | 81 | -2 (-2.4096%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_5v50 | 0.1895 | 0.1961 | 0.0066 (+3.4725%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_5v50 | 83 | 81 | -2 (-2.4096%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_125C_4v50 | 0.5178 | 0.5302 | 0.0124 (+2.3994%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_125C_4v50 | 83 | 81 | -2 (-2.4096%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_5v00 | 0.2907 | 0.2990 | 0.0083 (+2.8675%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_5v00 | 83 | 81 | -2 (-2.4096%) ⭕ |
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
design__core__area | 157640 | 157640 | 0 (0.0000%) ⭕ |
design__die__area | 177207 | 177207 | 0 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
ir__voltage__worst | 5 | 5 | 0 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
gf180mcuD/gf180mcu_fd_sc_mcu7t5v0/wbqspiflash
Metric | Before | After | Delta |
---|---|---|---|
timing__setup__tns | -402.0797 | -404.1298 | -2.0501 (+0.5099%) |
timing__setup__wns | -3.8000 | -3.6249 | 0.1751 (-4.6077%) |
timing__setup__tns__corner:max_ss_125C_4v50 | -402.0797 | -404.1298 | -2.0501 (+0.5099%) |
timing__setup__wns__corner:max_ss_125C_4v50 | -3.8000 | -3.6249 | 0.1751 (-4.6077%) |
timing__setup__tns__corner:min_ss_125C_4v50 | -325.1684 | -318.2667 | 6.9017 (-2.1225%) |
timing__setup__wns__corner:min_ss_125C_4v50 | -2.9963 | -2.8119 | 0.1844 (-6.1541%) |
timing__setup__tns__corner:nom_ss_125C_4v50 | -359.7891 | -357.1103 | 2.6788 (-0.7446%) |
timing__setup__wns__corner:nom_ss_125C_4v50 | -3.3667 | -3.1743 | 0.1924 (-5.7141%) |
clock__skew__worst_hold | -0.1847 | -0.1821 | 0.0026 (-1.4167%) ❗ |
clock__skew__worst_setup | -0.5212 | -0.5233 | -0.0021 (+0.4006%) ❗ |
design__instance__area | 67873 | 68769 | 896 (+1.3201%) ❗ |
ir__drop__avg | 0.0025 | 0.0025 | 0.0001 (+2.8340%) ❗ |
ir__drop__worst | 0.0104 | 0.0120 | 0.0016 (+15.3846%) ❗ |
power__internal__total | 0.1169 | 0.1187 | 0.0018 (+1.5723%) ❗ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (+0.5410%) ❗ |
power__switching__total | 0.0861 | 0.0879 | 0.0019 (+2.1609%) ❗ |
power__total | 0.2030 | 0.2067 | 0.0037 (+1.8219%) ❗ |
clock__skew__worst_setup__corner:max_ff_n40C_5v50 | -0.1879 | -0.1894 | -0.0015 (+0.8235%) ❗ |
clock__skew__worst_setup__corner:max_ss_125C_4v50 | -0.5212 | -0.5233 | -0.0021 (+0.4006%) ❗ |
clock__skew__worst_setup__corner:max_tt_025C_5v00 | -0.2907 | -0.2925 | -0.0018 (+0.6320%) ❗ |
clock__skew__worst_hold__corner:min_ff_n40C_5v50 | -0.1847 | -0.1821 | 0.0026 (-1.4167%) ❗ |
clock__skew__worst_hold__corner:min_ss_125C_4v50 | -0.5128 | -0.5049 | 0.0079 (-1.5415%) ❗ |
clock__skew__worst_hold__corner:min_tt_025C_5v00 | -0.2861 | -0.2818 | 0.0044 (-1.5218%) ❗ |
clock__skew__worst_hold__corner:nom_ff_n40C_5v50 | -0.1862 | -0.1855 | 0.0007 (-0.3942%) ❗ |
clock__skew__worst_hold__corner:nom_ss_125C_4v50 | -0.5172 | -0.5133 | 0.0038 (-0.7398%) ❗ |
clock__skew__worst_hold__corner:nom_tt_025C_5v00 | -0.2883 | -0.2867 | 0.0016 (-0.5619%) ❗ |
clock__skew__worst_hold__corner:max_ff_n40C_5v50 | -0.1879 | -0.1894 | -0.0015 (+0.8235%) ⭕ |
clock__skew__worst_hold__corner:max_ss_125C_4v50 | -0.5212 | -0.5233 | -0.0021 (+0.4006%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_5v00 | -0.2907 | -0.2925 | -0.0018 (+0.6320%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_5v50 | -0.1847 | -0.1821 | 0.0026 (-1.4167%) ⭕ |
clock__skew__worst_setup__corner:min_ss_125C_4v50 | -0.5128 | -0.5049 | 0.0079 (-1.5415%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_5v00 | -0.2861 | -0.2818 | 0.0044 (-1.5218%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_5v50 | -0.1862 | -0.1855 | 0.0007 (-0.3942%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_125C_4v50 | -0.5172 | -0.5133 | 0.0038 (-0.7398%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_5v00 | -0.2883 | -0.2867 | 0.0016 (-0.5619%) ⭕ |
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
design__core__area | 94345.3000 | 94345.3000 | 0.0000 (0.0000%) ⭕ |
design__die__area | 109560 | 109560 | 0 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
ir__voltage__worst | 4.9900 | 4.9900 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 448 | 448 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 451 | 451 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_5v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_125C_4v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_125C_4v50 | 150 | 150 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_125C_4v50 | 151 | 151 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_5v00 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_5v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_125C_4v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_125C_4v50 | 149 | 149 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_125C_4v50 | 150 | 150 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_5v00 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_5v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_125C_4v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_125C_4v50 | 149 | 149 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_125C_4v50 | 150 | 150 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_5v00 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
gf180mcuD/gf180mcu_fd_sc_mcu7t5v0/zipdiv
Metric | Before | After | Delta |
---|---|---|---|
timing__setup__tns | -228.6117 | -227.2777 | 1.3340 (-0.5835%) |
timing__setup__wns | -5.0252 | -4.8488 | 0.1764 (-3.5100%) |
timing__setup__tns__corner:max_ss_125C_4v50 | -228.6117 | -227.2777 | 1.3340 (-0.5835%) |
timing__setup__wns__corner:max_ss_125C_4v50 | -5.0252 | -4.8488 | 0.1764 (-3.5100%) |
timing__setup__tns__corner:min_ss_125C_4v50 | -208.5530 | -208.3596 | 0.1934 (-0.0927%) |
timing__setup__wns__corner:min_ss_125C_4v50 | -4.4685 | -4.3687 | 0.0998 (-2.2339%) |
timing__setup__tns__corner:nom_ss_125C_4v50 | -217.3473 | -216.9541 | 0.3932 (-0.1809%) |
timing__setup__wns__corner:nom_ss_125C_4v50 | -4.7209 | -4.5875 | 0.1333 (-2.8241%) |
clock__skew__worst_setup | 0.0398 | 0.0208 | -0.0191 (-47.8543%) ❗ |
design__instance__area | 35841.0000 | 36192.3000 | 351.3000 (+0.9802%) ❗ |
design__max_fanout_violation__count | 5 | 7 | 2 (+40.0000%) ❗ |
ir__drop__avg | 0.0004 | 0.0004 | 0.0000 (+6.6116%) ❗ |
ir__drop__worst | 0.0015 | 0.0015 | 0.0000 (+0.6579%) ❗ |
power__internal__total | 0.0197 | 0.0205 | 0.0009 (+4.3277%) ❗ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (+0.5324%) ❗ |
power__switching__total | 0.0103 | 0.0111 | 0.0008 (+7.4185%) ❗ |
power__total | 0.0300 | 0.0316 | 0.0016 (+5.3924%) ❗ |
clock__skew__worst_setup__corner:max_ff_n40C_5v50 | 0.0442 | 0.0267 | -0.0175 (-39.5562%) ❗ |
design__max_fanout_violation__count__corner:max_ff_n40C_5v50 | 5 | 7 | 2 (+40.0000%) ❗ |
clock__skew__worst_setup__corner:max_ss_125C_4v50 | 0.1158 | 0.0654 | -0.0505 (-43.5754%) ❗ |
design__max_fanout_violation__count__corner:max_ss_125C_4v50 | 5 | 7 | 2 (+40.0000%) ❗ |
clock__skew__worst_setup__corner:max_tt_025C_5v00 | 0.0665 | 0.0386 | -0.0279 (-42.0123%) ❗ |
design__max_fanout_violation__count__corner:max_tt_025C_5v00 | 5 | 7 | 2 (+40.0000%) ❗ |
clock__skew__worst_setup__corner:min_ff_n40C_5v50 | 0.0398 | 0.0208 | -0.0191 (-47.8543%) ❗ |
design__max_fanout_violation__count__corner:min_ff_n40C_5v50 | 5 | 7 | 2 (+40.0000%) ❗ |
clock__skew__worst_setup__corner:min_ss_125C_4v50 | 0.1055 | 0.0523 | -0.0532 (-50.3938%) ❗ |
design__max_fanout_violation__count__corner:min_ss_125C_4v50 | 5 | 7 | 2 (+40.0000%) ❗ |
clock__skew__worst_setup__corner:min_tt_025C_5v00 | 0.0602 | 0.0308 | -0.0294 (-48.8160%) ❗ |
design__max_fanout_violation__count__corner:min_tt_025C_5v00 | 5 | 7 | 2 (+40.0000%) ❗ |
clock__skew__worst_setup__corner:nom_ff_n40C_5v50 | 0.0418 | 0.0234 | -0.0184 (-44.0467%) ❗ |
design__max_fanout_violation__count__corner:nom_ff_n40C_5v50 | 5 | 7 | 2 (+40.0000%) ❗ |
clock__skew__worst_setup__corner:nom_ss_125C_4v50 | 0.1103 | 0.0583 | -0.0520 (-47.1417%) ❗ |
design__max_fanout_violation__count__corner:nom_ss_125C_4v50 | 5 | 7 | 2 (+40.0000%) ❗ |
clock__skew__worst_setup__corner:nom_tt_025C_5v00 | 0.0631 | 0.0344 | -0.0288 (-45.5632%) ❗ |
design__max_fanout_violation__count__corner:nom_tt_025C_5v00 | 5 | 7 | 2 (+40.0000%) ❗ |
clock__skew__worst_hold | 0.1158 | 0.0654 | -0.0505 (-43.5754%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_5v50 | 0.0442 | 0.0267 | -0.0175 (-39.5562%) ⭕ |
clock__skew__worst_hold__corner:max_ss_125C_4v50 | 0.1158 | 0.0654 | -0.0505 (-43.5754%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_5v00 | 0.0665 | 0.0386 | -0.0279 (-42.0123%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_5v50 | 0.0398 | 0.0208 | -0.0191 (-47.8543%) ⭕ |
clock__skew__worst_hold__corner:min_ss_125C_4v50 | 0.1055 | 0.0523 | -0.0532 (-50.3938%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_5v00 | 0.0602 | 0.0308 | -0.0294 (-48.8160%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_5v50 | 0.0418 | 0.0234 | -0.0184 (-44.0467%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_125C_4v50 | 0.1103 | 0.0583 | -0.0520 (-47.1417%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_5v00 | 0.0631 | 0.0344 | -0.0288 (-45.5632%) ⭕ |
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
design__core__area | 73310.9000 | 73310.9000 | 0.0000 (0.0000%) ⭕ |
design__die__area | 86150 | 86150 | 0 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
ir__voltage__worst | 5 | 5 | 0 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 186 | 186 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 186 | 186 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_5v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_125C_4v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_125C_4v50 | 63 | 63 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_125C_4v50 | 63 | 63 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_5v00 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_5v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_125C_4v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_125C_4v50 | 61 | 61 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_125C_4v50 | 61 | 61 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_5v00 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_5v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_5v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_125C_4v50 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_125C_4v50 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_125C_4v50 | 62 | 62 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_125C_4v50 | 62 | 62 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_5v00 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_5v00 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/APU
Metric | Before | After | Delta |
---|---|---|---|
clock__skew__worst_setup | 0.1158 | -0.1152 | -0.2310 (-199.5568%) ❗ |
design__instance__area | 32891.5000 | 33422.1000 | 530.6000 (+1.6132%) ❗ |
design__max_fanout_violation__count | 35 | 49 | 14 (+40.0000%) ❗ |
design__max_slew_violation__count | 18 | 21 | 3 (+16.6667%) ❗ |
ir__drop__avg | 0.0001 | 0.0001 | 0.0000 (+9.4070%) ❗ |
ir__drop__worst | 0.0004 | 0.0005 | 0.0001 (+21.8750%) ❗ |
power__internal__total | 0.0021 | 0.0023 | 0.0002 (+9.5682%) ❗ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (+3.1746%) ❗ |
power__switching__total | 0.0012 | 0.0013 | 0.0001 (+11.1916%) ❗ |
power__total | 0.0033 | 0.0036 | 0.0003 (+10.1389%) ❗ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.1207 | 0.1206 | -0.0001 (-0.0762%) ❗ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 35 | 49 | 14 (+40.0000%) ❗ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.3104 | 0.3101 | -0.0004 (-0.1140%) ❗ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 35 | 49 | 14 (+40.0000%) ❗ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 18 | 21 | 3 (+16.6667%) ❗ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.1788 | 0.1765 | -0.0024 (-1.3220%) ❗ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 35 | 49 | 14 (+40.0000%) ❗ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.1158 | -0.1152 | -0.2310 (-199.5568%) ❗ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 35 | 49 | 14 (+40.0000%) ❗ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | 0.2973 | 0.2974 | 0.0001 (+0.0363%) ❗ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 35 | 49 | 14 (+40.0000%) ❗ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 11 | 15 | 4 (+36.3636%) ❗ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.1711 | 0.1687 | -0.0024 (-1.3804%) ❗ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 35 | 49 | 14 (+40.0000%) ❗ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.1181 | 0.1175 | -0.0006 (-0.5149%) ❗ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 35 | 49 | 14 (+40.0000%) ❗ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.3032 | 0.3030 | -0.0002 (-0.0805%) ❗ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 35 | 49 | 14 (+40.0000%) ❗ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.1748 | 0.1723 | -0.0025 (-1.4056%) ❗ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 35 | 49 | 14 (+40.0000%) ❗ |
antenna__violating__nets | 2 | 0 | -2 (-100.0000%) ⭕ |
antenna__violating__pins | 2 | 0 | -2 (-100.0000%) ⭕ |
clock__skew__worst_hold | 0.3104 | 0.3101 | -0.0004 (-0.1140%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | 0.1207 | 0.1206 | -0.0001 (-0.0762%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | 0.3104 | 0.3101 | -0.0004 (-0.1140%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | 0.1788 | 0.1765 | -0.0024 (-1.3220%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | 0.1158 | -0.1152 | -0.2310 (-199.5568%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.2973 | 0.2974 | 0.0001 (+0.0363%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | 0.1711 | 0.1687 | -0.0024 (-1.3804%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | 0.1181 | 0.1175 | -0.0006 (-0.5149%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | 0.3032 | 0.3030 | -0.0002 (-0.0805%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | 0.1748 | 0.1723 | -0.0025 (-1.4056%) ⭕ |
design__core__area | 83157.3000 | 83157.3000 | 0.0000 (0.0000%) ⭕ |
design__die__area | 92941.4000 | 92941.4000 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 18 | 18 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/EF_GPIO
Metric | Before | After | Delta |
---|---|---|---|
clock__skew__worst_hold | -0.0024 | -0.0011 | 0.0013 (-55.0943%) ❗ |
design__instance__area | 1345.0400 | 1358.8000 | 13.7600 (+1.0230%) ❗ |
ir__drop__avg | 0.0000 | 0.0000 | 0.0000 (+3.7736%) ❗ |
power__internal__total | 0.0002 | 0.0002 | 0.0000 (+4.8065%) ❗ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (+1.5524%) ❗ |
power__switching__total | 0.0001 | 0.0001 | 0.0000 (+1.6490%) ❗ |
power__total | 0.0003 | 0.0003 | 0.0000 (+3.8506%) ❗ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.0028 | -0.0021 | 0.0007 (-24.3594%) ❗ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.0060 | -0.0033 | 0.0027 (-44.9403%) ❗ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.0035 | -0.0023 | 0.0012 (-33.1430%) ❗ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.0024 | -0.0011 | 0.0013 (-55.0943%) ❗ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | -0.0054 | -0.0018 | 0.0036 (-66.6171%) ❗ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | -0.0030 | -0.0012 | 0.0018 (-59.6261%) ❗ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.0025 | -0.0014 | 0.0011 (-44.1024%) ❗ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -0.0056 | -0.0024 | 0.0032 (-57.5545%) ❗ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -0.0032 | -0.0016 | 0.0016 (-49.0732%) ❗ |
clock__skew__worst_setup | -0.0060 | -0.0033 | 0.0027 (-44.9403%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | -0.0028 | -0.0021 | 0.0007 (-24.3594%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | -0.0060 | -0.0033 | 0.0027 (-44.9403%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | -0.0035 | -0.0023 | 0.0012 (-33.1430%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | -0.0024 | -0.0011 | 0.0013 (-55.0943%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | -0.0054 | -0.0018 | 0.0036 (-66.6171%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | -0.0030 | -0.0012 | 0.0018 (-59.6261%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | -0.0025 | -0.0014 | 0.0011 (-44.1024%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | -0.0056 | -0.0024 | 0.0032 (-57.5545%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | -0.0032 | -0.0016 | 0.0016 (-49.0732%) ⭕ |
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
design__core__area | 1670.3500 | 1670.3500 | 0.0000 (0.0000%) ⭕ |
design__die__area | 2700.3500 | 2700.3500 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
ir__drop__worst | 0.0001 | 0.0001 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/EF_PSRAM_CTRL_V2
Metric | Before | After | Delta |
---|---|---|---|
timing__setup__tns | -0.0692 | -0.0798 | -0.0106 (+15.2987%) |
timing__setup__wns | -0.0692 | -0.0798 | -0.0106 (+15.2987%) |
timing__setup__tns__corner:max_ss_100C_1v60 | -0.0692 | -0.0798 | -0.0106 (+15.2987%) |
timing__setup__wns__corner:max_ss_100C_1v60 | -0.0692 | -0.0798 | -0.0106 (+15.2987%) |
timing__setup__tns__corner:nom_ss_100C_1v60 | -0.0025 | -0.0096 | -0.0070 (+276.4544%) |
timing__setup__wns__corner:nom_ss_100C_1v60 | -0.0025 | -0.0096 | -0.0070 (+276.4544%) |
clock__skew__worst_hold | -0.0133 | -0.0039 | 0.0095 (-71.0666%) ❗ |
design__instance__area | 5614.1300 | 5660.4300 | 46.3000 (+0.8247%) ❗ |
design__max_fanout_violation__count | 2 | 3 | 1 (+50.0000%) ❗ |
ir__drop__avg | 0.0003 | 0.0003 | 0.0000 (+1.9934%) ❗ |
ir__drop__worst | 0.0009 | 0.0009 | 0.0000 (+0.4479%) ❗ |
power__internal__total | 0.0008 | 0.0009 | 0.0000 (+3.2584%) ❗ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (+1.7555%) ❗ |
power__switching__total | 0.0009 | 0.0009 | 0.0000 (+1.0881%) ❗ |
power__total | 0.0018 | 0.0018 | 0.0000 (+2.1327%) ❗ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.0153 | -0.0058 | 0.0095 (-62.1126%) ❗ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 2 | 3 | 1 (+50.0000%) ❗ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.0304 | -0.0092 | 0.0211 (-69.6138%) ❗ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 2 | 3 | 1 (+50.0000%) ❗ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.0190 | -0.0068 | 0.0122 (-64.0662%) ❗ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 2 | 3 | 1 (+50.0000%) ❗ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.0133 | -0.0039 | 0.0095 (-71.0666%) ❗ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 2 | 3 | 1 (+50.0000%) ❗ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | -0.0275 | -0.0068 | 0.0208 (-75.4378%) ❗ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 2 | 3 | 1 (+50.0000%) ❗ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | -0.0170 | -0.0047 | 0.0123 (-72.2556%) ❗ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 2 | 3 | 1 (+50.0000%) ❗ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.0139 | -0.0045 | 0.0094 (-67.4980%) ❗ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 2 | 3 | 1 (+50.0000%) ❗ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -0.0287 | -0.0080 | 0.0207 (-72.2834%) ❗ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 2 | 3 | 1 (+50.0000%) ❗ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -0.0176 | -0.0055 | 0.0121 (-68.8621%) ❗ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 2 | 3 | 1 (+50.0000%) ❗ |
clock__skew__worst_setup | -0.0304 | -0.0092 | 0.0211 (-69.6138%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | -0.0153 | -0.0058 | 0.0095 (-62.1126%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | -0.0304 | -0.0092 | 0.0211 (-69.6138%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | -0.0190 | -0.0068 | 0.0122 (-64.0662%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | -0.0133 | -0.0039 | 0.0095 (-71.0666%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | -0.0275 | -0.0068 | 0.0208 (-75.4378%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | -0.0170 | -0.0047 | 0.0123 (-72.2556%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | -0.0139 | -0.0045 | 0.0094 (-67.4980%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | -0.0287 | -0.0080 | 0.0207 (-72.2834%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | -0.0176 | -0.0055 | 0.0121 (-68.8621%) ⭕ |
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
design__core__area | 8051.4700 | 8051.4700 | 0.0000 (0.0000%) ⭕ |
design__die__area | 11313.5000 | 11313.5000 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 1 | 1 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/EF_TCC32
Metric | Before | After | Delta |
---|---|---|---|
clock__skew__worst_setup | -0.0230 | -0.0260 | -0.0031 (+13.4271%) ❗ |
design__instance__area | 9206.3300 | 9387.7500 | 181.4200 (+1.9706%) ❗ |
design__max_fanout_violation__count | 1 | 2 | 1 (+100.0000%) ❗ |
ir__drop__avg | 0.0003 | 0.0004 | 0.0000 (+10.5263%) ❗ |
ir__drop__worst | 0.0009 | 0.0012 | 0.0003 (+29.5681%) ❗ |
power__internal__total | 0.0012 | 0.0013 | 0.0002 (+14.2258%) ❗ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (+4.0610%) ❗ |
power__switching__total | 0.0009 | 0.0009 | 0.0000 (+5.5902%) ❗ |
power__total | 0.0020 | 0.0023 | 0.0002 (+10.5116%) ❗ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.0188 | -0.0123 | 0.0065 (-34.4044%) ❗ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 1 | 2 | 1 (+100.0000%) ❗ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.0365 | -0.0260 | -0.0626 (-171.2968%) ❗ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 1 | 2 | 1 (+100.0000%) ❗ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.0230 | -0.0161 | 0.0068 (-29.7896%) ❗ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 1 | 2 | 1 (+100.0000%) ❗ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.0166 | -0.0087 | -0.0253 (-152.6370%) ❗ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 1 | 2 | 1 (+100.0000%) ❗ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.0346 | -0.0205 | -0.0551 (-159.0927%) ❗ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 1 | 2 | 1 (+100.0000%) ❗ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.0217 | -0.0117 | -0.0334 (-153.7388%) ❗ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 1 | 2 | 1 (+100.0000%) ❗ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.0169 | -0.0102 | -0.0271 (-160.4316%) ❗ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 1 | 2 | 1 (+100.0000%) ❗ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.0358 | -0.0229 | -0.0587 (-163.9778%) ❗ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 1 | 2 | 1 (+100.0000%) ❗ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.0222 | -0.0136 | -0.0357 (-161.2750%) ❗ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 1 | 2 | 1 (+100.0000%) ❗ |
clock__skew__worst_hold | 0.0365 | -0.0087 | -0.0452 (-123.8523%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | -0.0188 | -0.0123 | 0.0065 (-34.4044%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | 0.0365 | -0.0260 | -0.0626 (-171.2968%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | -0.0230 | -0.0161 | 0.0068 (-29.7896%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | 0.0166 | -0.0087 | -0.0253 (-152.6370%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | 0.0346 | -0.0205 | -0.0551 (-159.0927%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | 0.0217 | -0.0117 | -0.0334 (-153.7388%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | 0.0169 | -0.0102 | -0.0271 (-160.4316%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | 0.0358 | -0.0229 | -0.0587 (-163.9778%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | 0.0222 | -0.0136 | -0.0357 (-161.2750%) ⭕ |
antenna__violating__nets | 1 | 1 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 1 | 1 | 0 (0.0000%) ⭕ |
design__core__area | 11369.7000 | 11369.7000 | 0.0000 (0.0000%) ⭕ |
design__die__area | 15327.4000 | 15327.4000 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/EF_UART
Metric | Before | After | Delta |
---|---|---|---|
clock__skew__worst_hold | -0.0369 | -0.0258 | 0.0110 (-29.8967%) ❗ |
design__instance__area | 19431.1000 | 19716.4000 | 285.3000 (+1.4683%) ❗ |
design__max_fanout_violation__count | 19 | 23 | 4 (+21.0526%) ❗ |
ir__drop__avg | 0.0007 | 0.0008 | 0.0001 (+7.9023%) ❗ |
ir__drop__worst | 0.0022 | 0.0023 | 0.0000 (+1.8018%) ❗ |
power__internal__total | 0.0031 | 0.0032 | 0.0001 (+4.4074%) ❗ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (+2.3515%) ❗ |
power__switching__total | 0.0016 | 0.0018 | 0.0002 (+14.4965%) ❗ |
power__total | 0.0047 | 0.0050 | 0.0004 (+7.8566%) ❗ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.0413 | -0.0353 | 0.0060 (-14.5303%) ❗ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 19 | 23 | 4 (+21.0526%) ❗ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.0782 | -0.0616 | 0.0165 (-21.1476%) ❗ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 19 | 23 | 4 (+21.0526%) ❗ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.0542 | -0.0450 | 0.0092 (-17.0464%) ❗ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 19 | 23 | 4 (+21.0526%) ❗ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.0369 | -0.0258 | 0.0110 (-29.8967%) ❗ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 19 | 23 | 4 (+21.0526%) ❗ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | -0.0718 | -0.0463 | 0.0255 (-35.5288%) ❗ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 19 | 23 | 4 (+21.0526%) ❗ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | -0.0491 | -0.0337 | 0.0155 (-31.4868%) ❗ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 19 | 23 | 4 (+21.0526%) ❗ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.0382 | -0.0288 | 0.0093 (-24.3913%) ❗ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 19 | 23 | 4 (+21.0526%) ❗ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -0.0734 | -0.0514 | 0.0220 (-29.9677%) ❗ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 19 | 23 | 4 (+21.0526%) ❗ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -0.0504 | -0.0370 | 0.0134 (-26.5818%) ❗ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 19 | 23 | 4 (+21.0526%) ❗ |
clock__skew__worst_setup | -0.0782 | -0.0616 | 0.0165 (-21.1476%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | -0.0413 | -0.0353 | 0.0060 (-14.5303%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | -0.0782 | -0.0616 | 0.0165 (-21.1476%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | -0.0542 | -0.0450 | 0.0092 (-17.0464%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | -0.0369 | -0.0258 | 0.0110 (-29.8967%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | -0.0718 | -0.0463 | 0.0255 (-35.5288%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | -0.0491 | -0.0337 | 0.0155 (-31.4868%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | -0.0382 | -0.0288 | 0.0093 (-24.3913%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | -0.0734 | -0.0514 | 0.0220 (-29.9677%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | -0.0504 | -0.0370 | 0.0134 (-26.5818%) ⭕ |
antenna__violating__nets | 6 | 6 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 6 | 6 | 0 (0.0000%) ⭕ |
design__core__area | 22502.8000 | 22502.8000 | 0.0000 (0.0000%) ⭕ |
design__die__area | 27887 | 27887 | 0 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/MS_CLK_RST
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | -0.7534 | -0.7534 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | -2.6779 | -2.6779 | 0.0000 (0.0000%) ⭕ |
design__core__area | 9240.1100 | 9240.1100 | 0.0000 (0.0000%) ⭕ |
design__die__area | 12880.8000 | 12880.8000 | 0.0000 (0.0000%) ⭕ |
design__instance__area | 5172.4600 | 5172.4600 | 0.0000 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 4 | 4 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 132 | 132 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
ir__drop__worst | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0001 | 0.0001 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0001 | 0.0001 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.7567 | -0.7567 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | -0.7503 | -0.7503 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 4 | 4 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | -2.6829 | -2.6829 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | -2.6779 | -2.6779 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 4 | 4 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 132 | 132 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | -1.4421 | -1.4421 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | -1.4393 | -1.4393 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 4 | 4 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.7534 | -0.7534 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | -0.7471 | -0.7471 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 4 | 4 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | -2.6568 | -2.6568 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | -2.6518 | -2.6518 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 4 | 4 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 132 | 132 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | -1.4334 | -1.4334 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | -1.4306 | -1.4306 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 4 | 4 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.7584 | -0.7584 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | -0.7520 | -0.7520 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 4 | 4 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -2.6738 | -2.6738 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | -2.6688 | -2.6688 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 4 | 4 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 132 | 132 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -1.4413 | -1.4413 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | -1.4385 | -1.4385 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 4 | 4 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/MS_DMAC_AHBL
Metric | Before | After | Delta |
---|---|---|---|
timing__setup__tns | -78.8002 | -81.6305 | -2.8303 (+3.5918%) |
timing__setup__wns | -4.0219 | -4.0084 | 0.0135 (-0.3362%) |
timing__setup_vio__count | 87 | 92 | 5 (+5.7471%) |
timing__setup__tns__corner:max_ss_100C_1v60 | -78.8002 | -81.6305 | -2.8303 (+3.5918%) |
timing__setup__wns__corner:max_ss_100C_1v60 | -4.0219 | -4.0084 | 0.0135 (-0.3362%) |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 30 | 32 | 2 (+6.6667%) |
timing__setup__tns__corner:min_ss_100C_1v60 | -69.3421 | -71.8556 | -2.5134 (+3.6247%) |
timing__setup__wns__corner:min_ss_100C_1v60 | -3.6361 | -3.6499 | -0.0138 (+0.3788%) |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 28 | 30 | 2 (+7.1429%) |
timing__setup__tns__corner:nom_ss_100C_1v60 | -73.9476 | -76.5412 | -2.5936 (+3.5073%) |
timing__setup__wns__corner:nom_ss_100C_1v60 | -3.8266 | -3.8246 | 0.0020 (-0.0521%) |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 29 | 30 | 1 (+3.4483%) |
clock__skew__worst_hold | 1.8314 | 1.8998 | 0.0683 (+3.7314%) ❗ |
clock__skew__worst_setup | 1.0806 | 0.9905 | -0.0901 (-8.3359%) ❗ |
design__instance__area | 15117.0000 | 15442.3000 | 325.3000 (+2.1519%) ❗ |
design__max_fanout_violation__count | 8 | 11 | 3 (+37.5000%) ❗ |
design__max_slew_violation__count | 0 | 5 | 5 ❗ |
ir__drop__avg | 0.0003 | 0.0003 | 0.0000 (+13.6808%) ❗ |
ir__drop__worst | 0.0011 | 0.0012 | 0.0001 (+13.2075%) ❗ |
power__internal__total | 0.0012 | 0.0013 | 0.0001 (+6.8516%) ❗ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (+3.3684%) ❗ |
power__switching__total | 0.0005 | 0.0006 | 0.0001 (+19.9480%) ❗ |
power__total | 0.0018 | 0.0020 | 0.0002 (+10.7684%) ❗ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | 0.6047 | 0.6248 | 0.0200 (+3.3118%) ❗ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 1.1144 | 1.0366 | -0.0778 (-6.9810%) ❗ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 8 | 11 | 3 (+37.5000%) ❗ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | 1.8314 | 1.8998 | 0.0683 (+3.7314%) ❗ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | 3.4108 | 3.1347 | -0.2761 (-8.0947%) ❗ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 8 | 11 | 3 (+37.5000%) ❗ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 0 | 5 | 5 ❗ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | 0.9451 | 0.9849 | 0.0397 (+4.2031%) ❗ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | 1.7390 | 1.6195 | -0.1195 (-6.8707%) ❗ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 8 | 11 | 3 (+37.5000%) ❗ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | 0.5804 | 0.6028 | 0.0224 (+3.8633%) ❗ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 1.0806 | 0.9905 | -0.0901 (-8.3359%) ❗ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 8 | 11 | 3 (+37.5000%) ❗ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | 1.7678 | 1.8272 | 0.0594 (+3.3580%) ❗ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 3.3194 | 3.0107 | -0.3087 (-9.2998%) ❗ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 8 | 11 | 3 (+37.5000%) ❗ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | 0.9090 | 0.9426 | 0.0336 (+3.6996%) ❗ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 1.6860 | 1.5454 | -0.1406 (-8.3380%) ❗ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 8 | 11 | 3 (+37.5000%) ❗ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | 0.5924 | 0.6169 | 0.0245 (+4.1329%) ❗ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 1.0973 | 1.0176 | -0.0798 (-7.2717%) ❗ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 8 | 11 | 3 (+37.5000%) ❗ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | 1.7999 | 1.8640 | 0.0642 (+3.5656%) ❗ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 3.3673 | 3.0796 | -0.2878 (-8.5457%) ❗ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 8 | 11 | 3 (+37.5000%) ❗ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | 0.9270 | 0.9641 | 0.0371 (+4.0003%) ❗ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 1.7121 | 1.5874 | -0.1247 (-7.2814%) ❗ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 8 | 11 | 3 (+37.5000%) ❗ |
antenna__violating__nets | 1 | 0 | -1 (-100.0000%) ⭕ |
antenna__violating__pins | 1 | 0 | -1 (-100.0000%) ⭕ |
design__core__area | 19398.6000 | 19398.6000 | 0.0000 (0.0000%) ⭕ |
design__die__area | 24435.4000 | 24435.4000 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/MS_SPI_XIP_CACHE
Metric | Before | After | Delta |
---|---|---|---|
timing__hold__tns | -3.1612 | -3.6390 | -0.4779 (+15.1174%) |
timing__hold__wns | -0.2464 | -0.2293 | 0.0171 (-6.9354%) |
timing__hold_vio__count | 61 | 62 | 1 (+1.6393%) |
timing__setup__tns | -60.3515 | -68.6819 | -8.3304 (+13.8031%) |
timing__setup__wns | -2.3449 | -2.5638 | -0.2189 (+9.3347%) |
timing__hold__tns__corner:max_ss_100C_1v60 | -3.1612 | -3.6390 | -0.4779 (+15.1174%) |
timing__hold__wns__corner:max_ss_100C_1v60 | -0.2464 | -0.2293 | 0.0171 (-6.9354%) |
timing__setup__tns__corner:max_ss_100C_1v60 | -60.3515 | -68.6819 | -8.3304 (+13.8031%) |
timing__setup__wns__corner:max_ss_100C_1v60 | -2.3449 | -2.5638 | -0.2189 (+9.3347%) |
timing__hold__tns__corner:min_ss_100C_1v60 | -0.2911 | -0.5274 | -0.2363 (+81.1854%) |
timing__hold__wns__corner:min_ss_100C_1v60 | -0.0845 | -0.0603 | 0.0242 (-28.6666%) |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 17 | 18 | 1 (+5.8824%) |
timing__setup__tns__corner:min_ss_100C_1v60 | -37.6669 | -41.9287 | -4.2618 (+11.3145%) |
timing__setup__wns__corner:min_ss_100C_1v60 | -1.6112 | -1.7608 | -0.1496 (+9.2860%) |
timing__hold__tns__corner:nom_ss_100C_1v60 | -1.5911 | -1.8472 | -0.2561 (+16.0987%) |
timing__hold__wns__corner:nom_ss_100C_1v60 | -0.1613 | -0.1375 | 0.0237 (-14.7219%) |
timing__setup__tns__corner:nom_ss_100C_1v60 | -49.1027 | -55.4686 | -6.3659 (+12.9644%) |
timing__setup__wns__corner:nom_ss_100C_1v60 | -1.9970 | -2.1821 | -0.1851 (+9.2706%) |
antenna__violating__nets | 31 | 58 | 27 (+87.0968%) ❗ |
antenna__violating__pins | 35 | 78 | 43 (+122.8571%) ❗ |
clock__skew__worst_setup | 0.1032 | 0.0684 | -0.0348 (-33.6860%) ❗ |
design__instance__area | 147501 | 149284 | 1783 (+1.2088%) ❗ |
design__max_cap_violation__count | 21 | 43 | 22 (+104.7619%) ❗ |
design__max_fanout_violation__count | 196 | 221 | 25 (+12.7551%) ❗ |
design__max_slew_violation__count | 266 | 439 | 173 (+65.0376%) ❗ |
ir__drop__avg | 0.0003 | 0.0003 | 0.0000 (+10.1045%) ❗ |
ir__drop__worst | 0.0016 | 0.0020 | 0.0003 (+20.1220%) ❗ |
power__internal__total | 0.0149 | 0.0160 | 0.0011 (+7.4869%) ❗ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (+2.2513%) ❗ |
power__switching__total | 0.0066 | 0.0076 | 0.0010 (+15.2540%) ❗ |
power__total | 0.0215 | 0.0236 | 0.0021 (+9.8773%) ❗ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.1158 | 0.0852 | -0.0306 (-26.4331%) ❗ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 21 | 28 | 7 (+33.3333%) ❗ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 196 | 221 | 25 (+12.7551%) ❗ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 49 | 49 ❗ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.2704 | 0.1786 | -0.0918 (-33.9567%) ❗ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 21 | 43 | 22 (+104.7619%) ❗ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 196 | 221 | 25 (+12.7551%) ❗ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 266 | 439 | 173 (+65.0376%) ❗ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.1657 | 0.1170 | -0.0486 (-29.3579%) ❗ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 21 | 28 | 7 (+33.3333%) ❗ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 196 | 221 | 25 (+12.7551%) ❗ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 28 | 140 | 112 (+400.0000%) ❗ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.1032 | 0.0684 | -0.0348 (-33.6860%) ❗ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 2 | 7 | 5 (+250.0000%) ❗ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 196 | 221 | 25 (+12.7551%) ❗ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 17 | 17 ❗ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.2409 | 0.1472 | -0.0937 (-38.9001%) ❗ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 2 | 13 | 11 (+550.0000%) ❗ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 196 | 221 | 25 (+12.7551%) ❗ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 193 | 338 | 145 (+75.1295%) ❗ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.1455 | 0.0952 | -0.0502 (-34.5293%) ❗ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 2 | 7 | 5 (+250.0000%) ❗ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 196 | 221 | 25 (+12.7551%) ❗ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 58 | 58 ❗ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.1093 | 0.0772 | -0.0321 (-29.3547%) ❗ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 12 | 20 | 8 (+66.6667%) ❗ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 196 | 221 | 25 (+12.7551%) ❗ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 43 | 43 ❗ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.2545 | 0.1637 | -0.0908 (-35.6797%) ❗ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 12 | 33 | 21 (+175.0000%) ❗ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 196 | 221 | 25 (+12.7551%) ❗ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 224 | 374 | 150 (+66.9643%) ❗ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.1558 | 0.1073 | -0.0485 (-31.1266%) ❗ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 12 | 20 | 8 (+66.6667%) ❗ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 196 | 221 | 25 (+12.7551%) ❗ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 77 | 77 ❗ |
clock__skew__worst_hold | 0.2704 | 0.1786 | -0.0918 (-33.9567%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | 0.1158 | 0.0852 | -0.0306 (-26.4331%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | 0.2704 | 0.1786 | -0.0918 (-33.9567%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | 0.1657 | 0.1170 | -0.0486 (-29.3579%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | 0.1032 | 0.0684 | -0.0348 (-33.6860%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | 0.2409 | 0.1472 | -0.0937 (-38.9001%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | 0.1455 | 0.0952 | -0.0502 (-34.5293%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | 0.1093 | 0.0772 | -0.0321 (-29.3547%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | 0.2545 | 0.1637 | -0.0908 (-35.6797%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | 0.1558 | 0.1073 | -0.0485 (-31.1266%) ⭕ |
design__core__area | 207279 | 207279 | 0 (0.0000%) ⭕ |
design__die__area | 223714 | 223714 | 0 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 96 | 96 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 26 | 26 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 32 | 32 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 32 | 32 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 18 | 18 | 0 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 32 | 32 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/aes_upw_new
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | -3.1920 | -3.1920 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | 0.1992 | 0.1992 | 0.0000 (0.0000%) ⭕ |
design__core__area | 10174000 | 10174000 | 0 (0.0000%) ⭕ |
design__die__area | 10278400 | 10278400 | 0 (0.0000%) ⭕ |
design__instance__area | 656000 | 656000 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0 | 0 | 0 (0.0000%) ⭕ |
ir__drop__worst | 0 | 0 | 0 (0.0000%) ⭕ |
ir__voltage__worst | 0 | 0 | 0 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0094 | 0.0094 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0033 | 0.0033 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0128 | 0.0128 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -3.2127 | -3.2127 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.2206 | 0.2206 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | -3.5492 | -3.5492 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.5638 | 0.5638 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | -3.3170 | -3.3170 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.3268 | 0.3268 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -3.1920 | -3.1920 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.1992 | 0.1992 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | -3.5017 | -3.5017 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.5147 | 0.5147 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | -3.2863 | -3.2863 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.2956 | 0.2956 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -3.2007 | -3.2007 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.2085 | 0.2085 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -3.5238 | -3.5238 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.5379 | 0.5379 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -3.2998 | -3.2998 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.3097 | 0.3097 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/aes_upw_old
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | -3.1920 | -3.1920 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | 0.1992 | 0.1992 | 0.0000 (0.0000%) ⭕ |
design__core__area | 10174000 | 10174000 | 0 (0.0000%) ⭕ |
design__die__area | 10278400 | 10278400 | 0 (0.0000%) ⭕ |
design__instance__area | 656000 | 656000 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0 | 0 | 0 (0.0000%) ⭕ |
ir__drop__worst | 0 | 0 | 0 (0.0000%) ⭕ |
ir__voltage__worst | 0 | 0 | 0 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0094 | 0.0094 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0033 | 0.0033 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0128 | 0.0128 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -3.2127 | -3.2127 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.2206 | 0.2206 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | -3.5492 | -3.5492 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.5638 | 0.5638 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | -3.3170 | -3.3170 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.3268 | 0.3268 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -3.1920 | -3.1920 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.1992 | 0.1992 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | -3.5017 | -3.5017 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.5147 | 0.5147 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | -3.2863 | -3.2863 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.2956 | 0.2956 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -3.2007 | -3.2007 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.2085 | 0.2085 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -3.5238 | -3.5238 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.5379 | 0.5379 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -3.2998 | -3.2998 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.3097 | 0.3097 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 987 | 987 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/blink
Metric | Before | After | Delta |
---|---|---|---|
clock__skew__worst_setup | 0.0033 | 0.0021 | -0.0011 (-34.7082%) ❗ |
design__instance__area | 1393.8400 | 1401.3400 | 7.5000 (+0.5381%) ❗ |
ir__drop__avg | 0.0001 | 0.0001 | 0.0000 (+2.9297%) ❗ |
power__internal__total | 0.0002 | 0.0002 | 0.0000 (+2.7687%) ❗ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (+0.6494%) ❗ |
power__switching__total | 0.0000 | 0.0000 | 0.0000 (+2.3338%) ❗ |
power__total | 0.0002 | 0.0002 | 0.0000 (+2.6902%) ❗ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.0047 | 0.0032 | -0.0014 (-30.8237%) ❗ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.0086 | 0.0057 | -0.0029 (-33.6399%) ❗ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.0056 | 0.0038 | -0.0018 (-31.5619%) ❗ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.0033 | 0.0021 | -0.0011 (-34.7082%) ❗ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.0068 | 0.0041 | -0.0028 (-40.2920%) ❗ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.0041 | 0.0026 | -0.0015 (-36.2860%) ❗ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.0038 | 0.0026 | -0.0012 (-31.7528%) ❗ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.0075 | 0.0048 | -0.0028 (-36.8191%) ❗ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.0046 | 0.0031 | -0.0015 (-33.2180%) ❗ |
clock__skew__worst_hold | 0.0086 | 0.0057 | -0.0029 (-33.6399%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | 0.0047 | 0.0032 | -0.0014 (-30.8237%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | 0.0086 | 0.0057 | -0.0029 (-33.6399%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | 0.0056 | 0.0038 | -0.0018 (-31.5619%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | 0.0033 | 0.0021 | -0.0011 (-34.7082%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | 0.0068 | 0.0041 | -0.0028 (-40.2920%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | 0.0041 | 0.0026 | -0.0015 (-36.2860%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | 0.0038 | 0.0026 | -0.0012 (-31.7528%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | 0.0075 | 0.0048 | -0.0028 (-36.8191%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | 0.0046 | 0.0031 | -0.0015 (-33.2180%) ⭕ |
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
design__core__area | 2387.2900 | 2387.2900 | 0.0000 (0.0000%) ⭕ |
design__die__area | 4273.3200 | 4273.3200 | 0.0000 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
ir__drop__worst | 0.0002 | 0.0002 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 2 | 2 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/caravel_upw
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
design__core__area | 10174000 | 10174000 | 0 (0.0000%) ⭕ |
design__die__area | 10278400 | 10278400 | 0 (0.0000%) ⭕ |
design__instance__area | 1080000 | 1080000 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 365 | 365 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 1098 | 1098 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0 | 0 | 0 (0.0000%) ⭕ |
ir__drop__worst | 0 | 0 | 0 (0.0000%) ⭕ |
ir__voltage__worst | 0 | 0 | 0 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 240 | 240 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 365 | 365 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 1089 | 1089 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 365 | 365 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 1098 | 1098 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 365 | 365 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 1095 | 1095 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 360 | 360 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 1074 | 1074 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 360 | 360 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 1098 | 1098 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 360 | 360 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 1095 | 1095 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 363 | 363 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 1083 | 1083 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 363 | 363 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 1098 | 1098 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 363 | 363 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 1095 | 1095 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/cell_inverter
Metric | Before | After | Delta |
---|---|---|---|
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/dual_spm
Metric | Before | After | Delta |
---|---|---|---|
clock__skew__worst_setup | 0.0064 | -0.0046 | -0.0110 (-172.4745%) ❗ |
power__internal__total | 0.0018 | 0.0018 | 0.0001 (+2.8649%) ❗ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (+0.8120%) ❗ |
power__switching__total | 0.0007 | 0.0007 | 0.0000 (+1.5952%) ❗ |
power__total | 0.0025 | 0.0025 | 0.0001 (+2.5035%) ❗ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.0073 | 0.0034 | -0.0039 (-53.6605%) ❗ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.0134 | 0.0052 | -0.0082 (-61.1007%) ❗ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.0096 | 0.0042 | -0.0055 (-56.7346%) ❗ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.0064 | 0.0024 | -0.0039 (-61.6968%) ❗ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.0120 | -0.0041 | -0.0161 (-134.3341%) ❗ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.0084 | -0.0030 | -0.0114 (-135.6211%) ❗ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.0067 | 0.0027 | -0.0039 (-59.0473%) ❗ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.0125 | -0.0046 | -0.0171 (-136.9780%) ❗ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.0088 | -0.0034 | -0.0122 (-138.1863%) ❗ |
clock__skew__worst_hold | 0.0134 | 0.0052 | -0.0082 (-61.1007%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | 0.0073 | 0.0034 | -0.0039 (-53.6605%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | 0.0134 | 0.0052 | -0.0082 (-61.1007%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | 0.0096 | 0.0042 | -0.0055 (-56.7346%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | 0.0064 | 0.0024 | -0.0039 (-61.6968%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | 0.0120 | -0.0041 | -0.0161 (-134.3341%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | 0.0084 | -0.0030 | -0.0114 (-135.6211%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | 0.0067 | 0.0027 | -0.0039 (-59.0473%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | 0.0125 | -0.0046 | -0.0171 (-136.9780%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | 0.0088 | -0.0034 | -0.0122 (-138.1863%) ⭕ |
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
design__core__area | 232536 | 232536 | 0 (0.0000%) ⭕ |
design__die__area | 250000 | 250000 | 0 (0.0000%) ⭕ |
design__instance__area | 22889.8000 | 22889.8000 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/gcd
Metric | Before | After | Delta |
---|---|---|---|
clock__skew__worst_setup | 0.0072 | 0.0038 | -0.0033 (-46.7719%) ❗ |
design__instance__area | 4514.3300 | 4524.3400 | 10.0100 (+0.2217%) ❗ |
ir__drop__avg | 0.0000 | 0.0000 | 0.0000 (+1.5464%) ❗ |
power__internal__total | 0.0004 | 0.0004 | 0.0000 (+2.3374%) ❗ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (+0.4155%) ❗ |
power__switching__total | 0.0004 | 0.0004 | 0.0000 (+0.5447%) ❗ |
power__total | 0.0008 | 0.0008 | 0.0000 (+1.4799%) ❗ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.0084 | 0.0050 | -0.0034 (-40.1509%) ❗ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.0175 | 0.0088 | -0.0087 (-49.6379%) ❗ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.0108 | 0.0063 | -0.0045 (-41.7898%) ❗ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.0072 | 0.0038 | -0.0033 (-46.7719%) ❗ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.0164 | 0.0078 | -0.0087 (-52.7597%) ❗ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.0094 | 0.0048 | -0.0045 (-48.3744%) ❗ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.0074 | 0.0041 | -0.0034 (-45.2812%) ❗ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.0163 | 0.0076 | -0.0087 (-53.4580%) ❗ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.0097 | 0.0052 | -0.0046 (-46.8432%) ❗ |
clock__skew__worst_hold | 0.0175 | 0.0088 | -0.0087 (-49.6379%) ⭕ |
ir__drop__worst | 0.0001 | 0.0001 | -0.0000 (-0.4762%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | 0.0084 | 0.0050 | -0.0034 (-40.1509%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | 0.0175 | 0.0088 | -0.0087 (-49.6379%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | 0.0108 | 0.0063 | -0.0045 (-41.7898%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | 0.0072 | 0.0038 | -0.0033 (-46.7719%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | 0.0164 | 0.0078 | -0.0087 (-52.7597%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | 0.0094 | 0.0048 | -0.0045 (-48.3744%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | 0.0074 | 0.0041 | -0.0034 (-45.2812%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | 0.0163 | 0.0076 | -0.0087 (-53.4580%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | 0.0097 | 0.0052 | -0.0046 (-46.8432%) ⭕ |
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
design__core__area | 67039.3000 | 67039.3000 | 0.0000 (0.0000%) ⭕ |
design__die__area | 78425.2000 | 78425.2000 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/inverter
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
design__core__area | 1051.0100 | 1051.0100 | 0.0000 (0.0000%) ⭕ |
design__die__area | 2500 | 2500 | 0 (0.0000%) ⭕ |
design__instance__area | 18.7680 | 18.7680 | 0.0000 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/io_placer
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
design__core__area | 12273800 | 12273800 | 0 (0.0000%) ⭕ |
design__die__area | 12390400 | 12390400 | 0 (0.0000%) ⭕ |
design__instance__area | 1080000 | 1080000 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 363 | 363 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 1092 | 1092 | 0 (0.0000%) ⭕ |
ir__drop__avg | 0 | 0 | 0 (0.0000%) ⭕ |
ir__drop__worst | 0 | 0 | 0 (0.0000%) ⭕ |
ir__voltage__worst | 0 | 0 | 0 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 240 | 240 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 363 | 363 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 1089 | 1089 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 363 | 363 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 1092 | 1092 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 363 | 363 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 1089 | 1089 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 363 | 363 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 1089 | 1089 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 363 | 363 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 1092 | 1092 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 363 | 363 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 1089 | 1089 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 363 | 363 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 1089 | 1089 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 363 | 363 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 1092 | 1092 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 363 | 363 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 1089 | 1089 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/latch_bad
Metric | Before | After | Delta |
---|---|---|---|
design__instance__area | 15.0144 | 15.0144 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/latch_good
Metric | Before | After | Delta |
---|---|---|---|
design__instance__area | 15.0144 | 15.0144 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/manual_macro_placement_test
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__nets | 1 | 1 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 1 | 1 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
design__core__area | 80146.9000 | 80146.9000 | 0.0000 (0.0000%) ⭕ |
design__die__area | 90000 | 90000 | 0 (0.0000%) ⭕ |
design__instance__area | 23540.6000 | 23540.6000 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 32 | 32 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
power__internal__total | 0.0001 | 0.0001 | 0.0000 (0.0000%) ⭕ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__switching__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
power__total | 0.0002 | 0.0002 | 0.0000 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 32 | 32 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 32 | 32 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 32 | 32 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 32 | 32 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 32 | 32 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 32 | 32 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 32 | 32 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 32 | 32 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 32 | 32 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/s44
Metric | Before | After | Delta |
---|---|---|---|
clock__skew__worst_hold | -0.0053 | -0.0018 | 0.0035 (-66.4342%) ❗ |
design__instance__area | 2583.7300 | 2626.2700 | 42.5400 (+1.6465%) ❗ |
ir__drop__avg | 0.0000 | 0.0000 | 0.0000 (+8.5234%) ❗ |
ir__drop__worst | 0.0001 | 0.0001 | 0.0000 (+5.9322%) ❗ |
power__internal__total | 0.0001 | 0.0001 | 0.0000 (+11.3419%) ❗ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (+2.2121%) ❗ |
power__switching__total | 0.0000 | 0.0000 | 0.0000 (+5.4939%) ❗ |
power__total | 0.0001 | 0.0002 | 0.0000 (+9.8660%) ❗ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.0060 | -0.0025 | 0.0035 (-58.5338%) ❗ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.0111 | -0.0039 | 0.0072 (-65.0005%) ❗ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.0080 | -0.0032 | 0.0048 (-60.1072%) ❗ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.0053 | -0.0018 | 0.0035 (-66.4342%) ❗ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | -0.0099 | -0.0028 | 0.0071 (-72.1146%) ❗ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | -0.0072 | -0.0023 | 0.0049 (-67.8397%) ❗ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.0055 | -0.0020 | 0.0035 (-64.0160%) ❗ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -0.0103 | -0.0031 | 0.0071 (-69.4937%) ❗ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -0.0074 | -0.0026 | 0.0048 (-65.1564%) ❗ |
clock__skew__worst_setup | -0.0111 | -0.0039 | 0.0072 (-65.0005%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | -0.0060 | -0.0025 | 0.0035 (-58.5338%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | -0.0111 | -0.0039 | 0.0072 (-65.0005%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | -0.0080 | -0.0032 | 0.0048 (-60.1072%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | -0.0053 | -0.0018 | 0.0035 (-66.4342%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | -0.0099 | -0.0028 | 0.0071 (-72.1146%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | -0.0072 | -0.0023 | 0.0049 (-67.8397%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | -0.0055 | -0.0020 | 0.0035 (-64.0160%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | -0.0103 | -0.0031 | 0.0071 (-69.4937%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | -0.0074 | -0.0026 | 0.0048 (-65.1564%) ⭕ |
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
design__core__area | 33280.7000 | 33280.7000 | 0.0000 (0.0000%) ⭕ |
design__die__area | 39709.7000 | 39709.7000 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/spm
Metric | Before | After | Delta |
---|---|---|---|
design__instance__area | 3584.6900 | 3686.0400 | 101.3500 (+2.8273%) ❗ |
ir__drop__avg | 0.0002 | 0.0002 | 0.0000 (+8.4967%) ❗ |
ir__drop__worst | 0.0008 | 0.0009 | 0.0001 (+12.6984%) ❗ |
power__internal__total | 0.0008 | 0.0009 | 0.0001 (+11.1964%) ❗ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (+5.9084%) ❗ |
power__switching__total | 0.0004 | 0.0004 | 0.0000 (+3.5103%) ❗ |
power__total | 0.0011 | 0.0012 | 0.0001 (+8.7998%) ❗ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.0134 | -0.0110 | 0.0024 (-17.8308%) ❗ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.0206 | -0.0153 | 0.0052 (-25.5203%) ❗ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.0161 | -0.0120 | 0.0041 (-25.4354%) ❗ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.0091 | 0.0065 | -0.0026 (-28.3344%) ❗ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.0172 | 0.0101 | -0.0071 (-41.3898%) ❗ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.0115 | 0.0075 | -0.0041 (-35.2033%) ❗ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.0103 | 0.0079 | -0.0024 (-23.3126%) ❗ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.0179 | 0.0118 | -0.0061 (-33.8474%) ❗ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.0128 | 0.0088 | -0.0040 (-31.3504%) ❗ |
clock__skew__worst_hold | 0.0179 | 0.0118 | -0.0061 (-33.8474%) ⭕ |
clock__skew__worst_setup | -0.0206 | -0.0153 | 0.0052 (-25.5203%) ⭕ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | -0.0134 | -0.0110 | 0.0024 (-17.8308%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | -0.0206 | -0.0153 | 0.0052 (-25.5203%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | -0.0161 | -0.0120 | 0.0041 (-25.4354%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | 0.0091 | 0.0065 | -0.0026 (-28.3344%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | 0.0172 | 0.0101 | -0.0071 (-41.3898%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | 0.0115 | 0.0075 | -0.0041 (-35.2033%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | 0.0103 | 0.0079 | -0.0024 (-23.3126%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | 0.0179 | 0.0118 | -0.0061 (-33.8474%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | 0.0128 | 0.0088 | -0.0040 (-31.3504%) ⭕ |
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
design__core__area | 8051.4700 | 8051.4700 | 0.0000 (0.0000%) ⭕ |
design__die__area | 11317.8000 | 11317.8000 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/test_sram_macro
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__pins | 11 | 13 | 2 (+18.1818%) ❗ |
clock__skew__worst_setup | -0.4389 | -0.4404 | -0.0015 (+0.3381%) ❗ |
design__instance__area | 395673 | 395731 | 58 (+0.0147%) ❗ |
design__max_slew_violation__count | 214 | 222 | 8 (+3.7383%) ❗ |
ir__drop__avg | 0.0000 | 0.0000 | 0.0000 (+5.3763%) ❗ |
power__internal__total | 0.0018 | 0.0018 | 0.0000 (+1.1159%) ❗ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (+0.0004%) ❗ |
power__switching__total | 0.0002 | 0.0002 | 0.0000 (+1.0299%) ❗ |
power__total | 0.0020 | 0.0021 | 0.0000 (+1.0857%) ❗ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | -0.1389 | -0.1396 | -0.0007 (+0.5200%) ❗ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 38 | 46 | 8 (+21.0526%) ❗ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | -0.4389 | -0.4404 | -0.0015 (+0.3381%) ❗ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 214 | 222 | 8 (+3.7383%) ❗ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | -0.2588 | -0.2600 | -0.0012 (+0.4644%) ❗ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 137 | 144 | 7 (+5.1095%) ❗ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | -0.1487 | -0.1492 | -0.0005 (+0.3247%) ❗ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | -0.3890 | -0.3902 | -0.0012 (+0.3144%) ❗ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 170 | 179 | 9 (+5.2941%) ❗ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | -0.2436 | -0.2444 | -0.0008 (+0.3206%) ❗ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 82 | 83 | 1 (+1.2195%) ❗ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | -0.1466 | -0.1472 | -0.0006 (+0.3887%) ❗ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | -0.4181 | -0.4194 | -0.0013 (+0.3100%) ❗ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | -0.2564 | -0.2574 | -0.0010 (+0.3861%) ❗ |
clock__skew__worst_hold | -0.1389 | -0.1396 | -0.0007 (+0.5200%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.1389 | -0.1396 | -0.0007 (+0.5200%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 15 | 13 | -2 (-13.3333%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.4389 | -0.4404 | -0.0015 (+0.3381%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.2588 | -0.2600 | -0.0012 (+0.4644%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 15 | 13 | -2 (-13.3333%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.1487 | -0.1492 | -0.0005 (+0.3247%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 24 | 23 | -1 (-4.1667%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | -0.3890 | -0.3902 | -0.0012 (+0.3144%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | -0.2436 | -0.2444 | -0.0008 (+0.3206%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.1466 | -0.1472 | -0.0006 (+0.3887%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 13 | 12 | -1 (-7.6923%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 27 | 26 | -1 (-3.7037%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -0.4181 | -0.4194 | -0.0013 (+0.3100%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 14 | 13 | -1 (-7.1429%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 197 | 192 | -5 (-2.5381%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -0.2564 | -0.2574 | -0.0010 (+0.3861%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 13 | 12 | -1 (-7.6923%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 124 | 117 | -7 (-5.6452%) ⭕ |
antenna__violating__nets | 11 | 11 | 0 (0.0000%) ⭕ |
design__core__area | 906252 | 906252 | 0 (0.0000%) ⭕ |
design__die__area | 937500 | 937500 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 18 | 18 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 5 | 5 | 0 (0.0000%) ⭕ |
ir__drop__worst | 0.0002 | 0.0002 | 0.0000 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 5666674 | 5666674 | 0 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 5 | 5 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 18 | 18 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 5 | 5 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 5 | 5 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 11 | 11 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 5 | 5 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 11 | 11 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 5 | 5 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 11 | 11 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 5 | 5 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 5 | 5 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 5 | 5 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 5 | 5 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/usb
Metric | Before | After | Delta |
---|---|---|---|
clock__skew__worst_setup | 0.0238 | 0.0053 | -0.0185 (-77.8900%) ❗ |
design__instance__area | 11873.9000 | 11985.2000 | 111.3000 (+0.9373%) ❗ |
ir__drop__avg | 0.0003 | 0.0003 | 0.0000 (+7.9681%) ❗ |
ir__drop__worst | 0.0009 | 0.0010 | 0.0000 (+5.3879%) ❗ |
power__internal__total | 0.0010 | 0.0010 | 0.0000 (+4.0805%) ❗ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (+1.6277%) ❗ |
power__switching__total | 0.0004 | 0.0004 | 0.0000 (+12.1503%) ❗ |
power__total | 0.0014 | 0.0015 | 0.0001 (+6.4131%) ❗ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.0244 | 0.0082 | -0.0162 (-66.4730%) ❗ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.0495 | 0.0115 | -0.0380 (-76.7555%) ❗ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.0315 | 0.0091 | -0.0224 (-71.1250%) ❗ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.0238 | 0.0053 | -0.0185 (-77.8900%) ❗ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.0500 | 0.0086 | -0.0414 (-82.7347%) ❗ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.0312 | 0.0059 | -0.0253 (-81.0171%) ❗ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.0241 | 0.0062 | -0.0179 (-74.2716%) ❗ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.0504 | 0.0100 | -0.0404 (-80.0738%) ❗ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.0317 | 0.0069 | -0.0248 (-78.1429%) ❗ |
clock__skew__worst_hold | 0.0504 | 0.0115 | -0.0389 (-77.1853%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | 0.0244 | 0.0082 | -0.0162 (-66.4730%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | 0.0495 | 0.0115 | -0.0380 (-76.7555%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | 0.0315 | 0.0091 | -0.0224 (-71.1250%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | 0.0238 | 0.0053 | -0.0185 (-77.8900%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | 0.0500 | 0.0086 | -0.0414 (-82.7347%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | 0.0312 | 0.0059 | -0.0253 (-81.0171%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | 0.0241 | 0.0062 | -0.0179 (-74.2716%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | 0.0504 | 0.0100 | -0.0404 (-80.0738%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | 0.0317 | 0.0069 | -0.0248 (-78.1429%) ⭕ |
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
design__core__area | 24891.4000 | 24891.4000 | 0.0000 (0.0000%) ⭕ |
design__die__area | 30400.6000 | 30400.6000 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 19 | 19 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 4 | 4 | 0 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 19 | 19 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 19 | 19 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 4 | 4 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 19 | 19 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 19 | 19 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 19 | 19 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 4 | 4 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 19 | 19 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 19 | 19 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 19 | 19 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 4 | 4 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 19 | 19 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/usb_cdc_core
Metric | Before | After | Delta |
---|---|---|---|
clock__skew__worst_hold | 0.0519 | 0.0635 | 0.0117 (+22.4727%) ❗ |
design__instance__area | 22429.0000 | 23010.8000 | 581.8000 (+2.5940%) ❗ |
design__max_fanout_violation__count | 25 | 34 | 9 (+36.0000%) ❗ |
ir__drop__avg | 0.0001 | 0.0001 | 0.0000 (+17.2524%) ❗ |
ir__drop__worst | 0.0003 | 0.0004 | 0.0000 (+12.6935%) ❗ |
power__internal__total | 0.0015 | 0.0018 | 0.0003 (+18.7069%) ❗ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (+4.7744%) ❗ |
power__switching__total | 0.0006 | 0.0007 | 0.0001 (+14.6863%) ❗ |
power__total | 0.0021 | 0.0024 | 0.0004 (+17.5451%) ❗ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.0401 | 0.0300 | -0.0101 (-25.0943%) ❗ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 25 | 34 | 9 (+36.0000%) ❗ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.0825 | 0.0635 | 0.1460 (-176.9912%) ❗ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 25 | 34 | 9 (+36.0000%) ❗ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.0519 | 0.0384 | -0.0135 (-25.9691%) ❗ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 25 | 34 | 9 (+36.0000%) ❗ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.0344 | 0.0261 | 0.0604 (-175.8082%) ❗ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 25 | 34 | 9 (+36.0000%) ❗ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | -0.0746 | 0.0556 | 0.1303 (-174.5702%) ❗ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 25 | 34 | 9 (+36.0000%) ❗ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | -0.0454 | 0.0333 | 0.0788 (-173.3492%) ❗ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 25 | 34 | 9 (+36.0000%) ❗ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.0363 | 0.0284 | -0.0079 (-21.7810%) ❗ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 25 | 34 | 9 (+36.0000%) ❗ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -0.0789 | 0.0606 | 0.1396 (-176.8028%) ❗ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 25 | 34 | 9 (+36.0000%) ❗ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -0.0476 | 0.0365 | 0.0842 (-176.6354%) ❗ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 25 | 34 | 9 (+36.0000%) ❗ |
clock__skew__worst_setup | -0.0825 | 0.0261 | 0.1085 (-131.5848%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | 0.0401 | 0.0300 | -0.0101 (-25.0943%) ⭕ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | -0.0825 | 0.0635 | 0.1460 (-176.9912%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | 0.0519 | 0.0384 | -0.0135 (-25.9691%) ⭕ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | -0.0344 | 0.0261 | 0.0604 (-175.8082%) ⭕ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | -0.0746 | 0.0556 | 0.1303 (-174.5702%) ⭕ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | -0.0454 | 0.0333 | 0.0788 (-173.3492%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | 0.0363 | 0.0284 | -0.0079 (-21.7810%) ⭕ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | -0.0789 | 0.0606 | 0.1396 (-176.8028%) ⭕ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | -0.0476 | 0.0365 | 0.0842 (-176.6354%) ⭕ |
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
design__core__area | 62620.1000 | 62620.1000 | 0.0000 (0.0000%) ⭕ |
design__die__area | 71190.9000 | 71190.9000 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 2 | 2 | 0 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 2 | 2 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 2 | 2 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 2 | 2 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/user_proj_timer
Metric | Before | After | Delta |
---|---|---|---|
clock__skew__worst_setup | 0.0069 | 0.0040 | -0.0030 (-42.6222%) ❗ |
design__instance__area | 17802.1000 | 17855.9000 | 53.8000 (+0.3022%) ❗ |
ir__drop__avg | 0.0000 | 0.0000 | 0.0000 (+5.9072%) ❗ |
ir__drop__worst | 0.0001 | 0.0001 | 0.0000 (+2.8708%) ❗ |
power__internal__total | 0.0002 | 0.0002 | 0.0000 (+5.3245%) ❗ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (+0.2213%) ❗ |
power__switching__total | 0.0001 | 0.0001 | 0.0000 (+5.9249%) ❗ |
power__total | 0.0003 | 0.0003 | 0.0000 (+5.4627%) ❗ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.0085 | 0.0066 | -0.0019 (-21.7949%) ❗ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.0170 | 0.0099 | -0.0071 (-41.7401%) ❗ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.0102 | 0.0073 | -0.0028 (-27.6158%) ❗ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.0069 | 0.0040 | -0.0030 (-42.6222%) ❗ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 2 | 3 | 1 (+50.0000%) ❗ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.0145 | 0.0069 | -0.0077 (-52.6131%) ❗ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 39 | 69 | 30 (+76.9231%) ❗ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.0083 | 0.0045 | -0.0038 (-45.6064%) ❗ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.0074 | 0.0048 | -0.0025 (-34.3788%) ❗ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.0154 | 0.0079 | -0.0075 (-48.4949%) ❗ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.0089 | 0.0055 | -0.0034 (-38.4104%) ❗ |
clock__skew__worst_hold | 0.0170 | 0.0099 | -0.0071 (-41.7401%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | 0.0085 | 0.0066 | -0.0019 (-21.7949%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | 0.0170 | 0.0099 | -0.0071 (-41.7401%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | 0.0102 | 0.0073 | -0.0028 (-27.6158%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | 0.0069 | 0.0040 | -0.0030 (-42.6222%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | 0.0145 | 0.0069 | -0.0077 (-52.6131%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | 0.0083 | 0.0045 | -0.0038 (-45.6064%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | 0.0074 | 0.0048 | -0.0025 (-34.3788%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | 0.0154 | 0.0079 | -0.0075 (-48.4949%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 105 | 93 | -12 (-11.4286%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | 0.0089 | 0.0055 | -0.0034 (-38.4104%) ⭕ |
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
design__core__area | 655604 | 655604 | 0 (0.0000%) ⭕ |
design__die__area | 700000 | 700000 | 0 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 3 | 3 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 5 | 5 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 105 | 105 | 0 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 3 | 3 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 5 | 5 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 3 | 3 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 5 | 5 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 105 | 105 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 3 | 3 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 5 | 5 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 5 | 5 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 3 | 3 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 5 | 5 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 3 | 3 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 5 | 5 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 3 | 3 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 5 | 5 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 3 | 3 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 5 | 5 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 3 | 3 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 5 | 5 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/wbqspiflash
Metric | Before | After | Delta |
---|---|---|---|
antenna__violating__pins | 2 | 3 | 1 (+50.0000%) ❗ |
clock__skew__worst_hold | -0.1319 | 0.2192 | 0.3511 (-266.1502%) ❗ |
clock__skew__worst_setup | -0.3574 | -0.3772 | -0.0199 (+5.5615%) ❗ |
design__instance__area | 27580.2000 | 27737.9000 | 157.7000 (+0.5718%) ❗ |
design__max_fanout_violation__count | 37 | 39 | 2 (+5.4054%) ❗ |
design__max_slew_violation__count | 26 | 35 | 9 (+34.6154%) ❗ |
ir__drop__avg | 0.0002 | 0.0002 | 0.0000 (+2.9557%) ❗ |
ir__drop__worst | 0.0012 | 0.0014 | 0.0002 (+18.1034%) ❗ |
power__internal__total | 0.0030 | 0.0030 | 0.0001 (+1.7750%) ❗ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (+1.0870%) ❗ |
power__switching__total | 0.0029 | 0.0029 | 0.0001 (+1.9646%) ❗ |
power__total | 0.0059 | 0.0060 | 0.0001 (+1.8681%) ❗ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.1393 | 0.1522 | 0.2914 (-209.2489%) ❗ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 37 | 39 | 2 (+5.4054%) ❗ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | -0.3574 | -0.3772 | -0.0199 (+5.5615%) ❗ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 37 | 39 | 2 (+5.4054%) ❗ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 26 | 35 | 9 (+34.6154%) ❗ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.2055 | 0.2192 | 0.4246 (-206.6877%) ❗ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 37 | 39 | 2 (+5.4054%) ❗ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | -0.1319 | -0.1386 | -0.0067 (+5.0840%) ❗ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 37 | 39 | 2 (+5.4054%) ❗ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | -0.3379 | -0.3525 | -0.0145 (+4.2994%) ❗ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 37 | 39 | 2 (+5.4054%) ❗ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | -0.1939 | -0.2031 | -0.0092 (+4.7363%) ❗ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 37 | 39 | 2 (+5.4054%) ❗ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.1355 | 0.1440 | 0.2795 (-206.2209%) ❗ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 37 | 39 | 2 (+5.4054%) ❗ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | -0.3467 | -0.3631 | -0.0164 (+4.7288%) ❗ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 37 | 39 | 2 (+5.4054%) ❗ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | -0.1994 | -0.2100 | -0.0106 (+5.3316%) ❗ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 37 | 39 | 2 (+5.4054%) ❗ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | -0.1393 | 0.1522 | 0.2914 (-209.2489%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.3574 | -0.3772 | -0.0199 (+5.5615%) ⭕ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | -0.2055 | 0.2192 | 0.4246 (-206.6877%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.1319 | -0.1386 | -0.0067 (+5.0840%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | -0.3379 | -0.3525 | -0.0145 (+4.2994%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 9 | 5 | -4 (-44.4444%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | -0.1939 | -0.2031 | -0.0092 (+4.7363%) ⭕ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | -0.1355 | 0.1440 | 0.2795 (-206.2209%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -0.3467 | -0.3631 | -0.0164 (+4.7288%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 19 | 14 | -5 (-26.3158%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -0.1994 | -0.2100 | -0.0106 (+5.3316%) ⭕ |
antenna__violating__nets | 2 | 2 | 0 (0.0000%) ⭕ |
design__core__area | 74571.5000 | 74571.5000 | 0.0000 (0.0000%) ⭕ |
design__die__area | 84643.5000 | 84643.5000 | 0.0000 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/xtea
Metric | Before | After | Delta |
---|---|---|---|
clock__skew__worst_setup | 0.0265 | 0.0123 | -0.0142 (-53.6190%) ❗ |
design__instance__area | 24751.2000 | 24902.6000 | 151.4000 (+0.6117%) ❗ |
design__max_fanout_violation__count | 16 | 17 | 1 (+6.2500%) ❗ |
ir__drop__avg | 0.0002 | 0.0002 | 0.0000 (+0.4115%) ❗ |
ir__drop__worst | 0.0008 | 0.0008 | 0.0000 (+0.7874%) ❗ |
power__internal__total | 0.0031 | 0.0032 | 0.0000 (+1.0460%) ❗ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (+1.1141%) ❗ |
power__switching__total | 0.0039 | 0.0039 | 0.0000 (+0.5497%) ❗ |
power__total | 0.0070 | 0.0071 | 0.0001 (+0.7705%) ❗ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.0287 | 0.0154 | -0.0133 (-46.2914%) ❗ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 16 | 17 | 1 (+6.2500%) ❗ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.0610 | 0.0303 | -0.0307 (-50.3582%) ❗ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 16 | 17 | 1 (+6.2500%) ❗ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.0376 | 0.0203 | -0.0174 (-46.1373%) ❗ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 16 | 17 | 1 (+6.2500%) ❗ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.0265 | 0.0123 | -0.0142 (-53.6190%) ❗ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 16 | 17 | 1 (+6.2500%) ❗ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.0574 | 0.0241 | -0.0334 (-58.1089%) ❗ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 16 | 17 | 1 (+6.2500%) ❗ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.0351 | 0.0162 | -0.0189 (-53.8424%) ❗ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 16 | 17 | 1 (+6.2500%) ❗ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.0273 | 0.0135 | -0.0138 (-50.4773%) ❗ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 16 | 17 | 1 (+6.2500%) ❗ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.0595 | 0.0266 | -0.0328 (-55.2114%) ❗ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 16 | 17 | 1 (+6.2500%) ❗ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 12 | 16 | 4 (+33.3333%) ❗ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.0366 | 0.0179 | -0.0187 (-51.1494%) ❗ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 16 | 17 | 1 (+6.2500%) ❗ |
clock__skew__worst_hold | 0.0610 | 0.0303 | -0.0307 (-50.3582%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | 0.0287 | 0.0154 | -0.0133 (-46.2914%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | 0.0610 | 0.0303 | -0.0307 (-50.3582%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | 0.0376 | 0.0203 | -0.0174 (-46.1373%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | 0.0265 | 0.0123 | -0.0142 (-53.6190%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | 0.0574 | 0.0241 | -0.0334 (-58.1089%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | 0.0351 | 0.0162 | -0.0189 (-53.8424%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | 0.0273 | 0.0135 | -0.0138 (-50.4773%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | 0.0595 | 0.0266 | -0.0328 (-55.2114%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | 0.0366 | 0.0179 | -0.0187 (-51.1494%) ⭕ |
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
design__core__area | 52235.1000 | 52235.1000 | 0.0000 (0.0000%) ⭕ |
design__die__area | 60033 | 60033 | 0 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count | 22 | 22 | 0 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 22 | 22 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 6 | 6 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/zipdiv
Metric | Before | After | Delta |
---|---|---|---|
clock__skew__worst_setup | 0.0341 | 0.0099 | -0.0242 (-71.0839%) ❗ |
design__instance__area | 13127.6000 | 13257.7000 | 130.1000 (+0.9910%) ❗ |
design__max_slew_violation__count | 0 | 4 | 4 ❗ |
ir__drop__avg | 0.0001 | 0.0001 | 0.0000 (+6.4171%) ❗ |
ir__drop__worst | 0.0003 | 0.0003 | 0.0000 (+7.6642%) ❗ |
power__internal__total | 0.0006 | 0.0007 | 0.0000 (+7.7916%) ❗ |
power__leakage__total | 0.0000 | 0.0000 | 0.0000 (+1.5574%) ❗ |
power__switching__total | 0.0004 | 0.0004 | 0.0000 (+9.2806%) ❗ |
power__total | 0.0010 | 0.0011 | 0.0001 (+8.3770%) ❗ |
clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.0391 | 0.0140 | -0.0251 (-64.1887%) ❗ |
clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.0753 | 0.0218 | -0.0535 (-71.0870%) ❗ |
design__max_slew_violation__count__corner:max_ss_100C_1v60 | 0 | 4 | 4 ❗ |
clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.0502 | 0.0172 | -0.0330 (-65.6739%) ❗ |
clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.0341 | 0.0099 | -0.0242 (-71.0839%) ❗ |
clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.0680 | 0.0162 | -0.0518 (-76.1660%) ❗ |
clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.0445 | 0.0124 | -0.0321 (-72.2106%) ❗ |
clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.0358 | 0.0114 | -0.0244 (-68.1759%) ❗ |
clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.0708 | 0.0185 | -0.0522 (-73.8027%) ❗ |
clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.0466 | 0.0142 | -0.0323 (-69.4265%) ❗ |
clock__skew__worst_hold | 0.0753 | 0.0218 | -0.0535 (-71.0870%) ⭕ |
clock__skew__worst_hold__corner:max_ff_n40C_1v95 | 0.0391 | 0.0140 | -0.0251 (-64.1887%) ⭕ |
clock__skew__worst_hold__corner:max_ss_100C_1v60 | 0.0753 | 0.0218 | -0.0535 (-71.0870%) ⭕ |
clock__skew__worst_hold__corner:max_tt_025C_1v80 | 0.0502 | 0.0172 | -0.0330 (-65.6739%) ⭕ |
clock__skew__worst_hold__corner:min_ff_n40C_1v95 | 0.0341 | 0.0099 | -0.0242 (-71.0839%) ⭕ |
clock__skew__worst_hold__corner:min_ss_100C_1v60 | 0.0680 | 0.0162 | -0.0518 (-76.1660%) ⭕ |
clock__skew__worst_hold__corner:min_tt_025C_1v80 | 0.0445 | 0.0124 | -0.0321 (-72.2106%) ⭕ |
clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | 0.0358 | 0.0114 | -0.0244 (-68.1759%) ⭕ |
clock__skew__worst_hold__corner:nom_ss_100C_1v60 | 0.0708 | 0.0185 | -0.0522 (-73.8027%) ⭕ |
clock__skew__worst_hold__corner:nom_tt_025C_1v80 | 0.0466 | 0.0142 | -0.0323 (-69.4265%) ⭕ |
antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
design__core__area | 29796.1000 | 29796.1000 | 0.0000 (0.0000%) ⭕ |
design__die__area | 36193 | 36193 | 0 (0.0000%) ⭕ |
design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count | 15 | 15 | 0 (0.0000%) ⭕ |
ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 15 | 15 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 15 | 15 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 15 | 15 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:max_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 15 | 15 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 15 | 15 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 15 | 15 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:min_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 15 | 15 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ff_n40C_1v95 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 15 | 15 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_ss_100C_1v60 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 15 | 15 | 0 (0.0000%) ⭕ |
design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold__tns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold__wns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup__tns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup__wns__corner:nom_tt_025C_1v80 | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |