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@donn
Created October 12, 2019 12:13
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RiscBEE ALU in Chisel
/*
The RiscBEE ALU in Chisel
I rewrote the ALU for github.io/donn/RiscBEE in Chisel in the initial research phase for Phi…
I uh. Wasn't a fan.
Scala
--
This is free and unencumbered software released into the public domain.
Anyone is free to copy, modify, publish, use, compile, sell, or
distribute this software, either in source code form or as a compiled
binary, for any purpose, commercial or non-commercial, and by any
means.
In jurisdictions that recognize copyright laws, the author or authors
of this software dedicate any and all copyright interest in the
software to the public domain. We make this dedication for the benefit
of the public at large and to the detriment of our heirs and
successors. We intend this dedication to be an overt act of
relinquishment in perpetuity of all present and future rights to this
software under copyright law.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR
OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
OTHER DEALINGS IN THE SOFTWARE.
For more information, please refer to <http://unlicense.org/>
*/
package riscbee
import chisel3._
import chisel3.util._
class ALU extends Module {
val io = IO(new Bundle {
val A = Input(UInt(32.W))
val B = Input(UInt(32.W))
val switch = Input(Bool(1.W))
val operation = Input(UInt(3.W))
val O = Output(UInt(32.W))
val Z = Output(UInt(1.W))
val N = Output(UInt(1.W))
val C = Output(UInt(1.W))
val V = Output(UInt(1.W))
})
//create an array of FullAdders
val add = Wire(Vec(32, UInt()))
val sll = Wire(Vec(32, UInt()))
val shift = Wire(Vec(32, UInt()))
val slt = Wire(Vec(32, UInt()))
val sltu = Wire(Vec(32, UInt()))
val lxor = Wire(Vec(32, UInt()))
val srl = Wire(Vec(32, UInt()))
val lor = Wire(Vec(32, UInt()))
val land = Wire(Vec(32, UInt()))
val c = Wire(Vec(1, UInt())
val v = Wire(Vec(1, UInt())
val signedA = Wire(Vec(32, SInt())
val signedB = Wire(Vec(32, SInt())
signedA := io.A
signedB := io.B
Cat(c, add) := switch ? io.A -& io.B : io.A +& io.B
v := c ^ (add(31) ^ io.A(31) ^ io.B(31)
sll := io.A << io.B(5, 0)
slt := (signedA < signedB) ? 1.U : 0.U
sltu := (io.A < io.B) ? 1.U: 0.U
lxor := io.A ^ io.B
srl = switch ? signedA >> signedB(5, 0) : io.A >> io.B(5, 0)
lor = io.A | io.B
land = io.A & io.B
io,O := MuxLookup(operation, add, Array(1.U -> sll, 2.U -> slt, 3.U -> sltu, 4.U -> lxor, 5.U -> srl, 6.U -> lor, 7.U -> land))
Cat(io.C, io.V) := (operation === 0.U) ? Cat(c, v): (0.U)
io.Z := (io.O === 0.U) ? 1.U : 0.U
io.N := O(31)
}
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