donn/Icarus Verilog Tutorial.md

## Icarus Verilog Tutorial.md

      
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              Icarus Verilog Tutorial.md
            
          
    Icarus Verilog Tutorial

Installation

Windows

Download and install this:
http://bleyer.org/icarus/iverilog-v11-20190809-x64_setup.exe
(This comes with both IcarusVerilog and GTKWave.)
Make sure to check the option to add the executable to path.
macOS

Download and install the Homebrew package manager:
/usr/bin/ruby -e "$(curl -fsSL https://raw.githubusercontent.com/Homebrew/install/master/install)"
(This will not work on macOS 10.15 Catalina, if you're on Catalina visit https://brew.sh)
Then install the following software:
brew install icarus-verilog
brew cask install scansion

When running Scansion for the first time, you will need to go to your Applications folder, secondary/right click it, then press Open. This is because of macOS's security features.
Linux

Use your package manager, on Ubuntu for example:
sudo apt-get install -y iverilog gtkwave
Running

Create a new folder. This will become the project folder.
After creating your module and testbench, you run the commands like this
iverilog -o <filename>.vvp <testbench-name>.v
vvp <filename>.vvp

# If you are on Windows/Linux…
gtkwave <dumpfile>.vcd

# If you are on macOS…
open -a Scansion <dumpfile>.vcd
The example files

iverilog -o inverter.vvp inverter_tb.v
vvp inverter.vvp

# If you are on Windows/Linux…
gtkwave signals.vcd

# If you are on macOS…
open -a Scansion signals.vcd

  
## inverter.v
// Simple inverter
module inverter(
    input[31:0] a,
    output[31:0] b
);
    assign b = ~a;
endmodule

## inverter_tb.v
`include "inverter.v" // Not needed on Cloud V

module inverter_tb;
    reg[31:0] a;
    wire[31:0] b;

    inverter uut(
        .a(a),
        .b(b)
    );

    initial begin
        a = 0;
        // Not needed on Cloud V:
        $dumpfile("signals.vcd"); // Name of the signal dump file
        $dumpvars(0, inverter_tb); // Signals to dump
        #3000;  // Simulation time
        $finish();  // Don't forget this or the simulation will run forever and fill up your hard drive.
    end

endmodule
	// Simple inverter
	module inverter(
	input[31:0] a,
	output[31:0] b
	);
	assign b = ~a;
	endmodule
	`include "inverter.v" // Not needed on Cloud V

	module inverter_tb;
	reg[31:0] a;
	wire[31:0] b;

	inverter uut(
	.a(a),
	.b(b)
	);

	initial begin
	a = 0;
	// Not needed on Cloud V:
	$dumpfile("signals.vcd"); // Name of the signal dump file
	$dumpvars(0, inverter_tb); // Signals to dump
	#3000; // Simulation time
	$finish(); // Don't forget this or the simulation will run forever and fill up your hard drive.
	end

	endmodule