Created
June 1, 2021 04:40
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qemu-system-i386 -bios emb.bin -s -S -no-reboot -no-shutdown \ | |
-d int -trace 'pci*' -vga none -device secondary-vga \ | |
-chardev stdio,id=debug-out \ | |
-device isa-debugcon,chardev=debug-out \ | |
-trace 'vga*' -trace 'pci*' | |
Checking 0:0:0 | |
pci_cfg_read i440FX 00:0 @0xc -> 0x0 | |
pci_cfg_read i440FX 00:0 @0x8 -> 0x6000002 | |
pci_cfg_read i440FX 00:0 @0x8 -> 0x6000002 | |
pci_cfg_read i440FX 00:0 @0x8 -> 0x6000002 | |
class=6 subclass=0 Bridge/Host | |
bar_ofs 16 | |
pci_cfg_read i440FX 00:0 @0x10 -> 0x0 | |
pci_cfg_write i440FX 00:0 @0x10 <- 0xfffffff0 | |
pci_cfg_read i440FX 00:0 @0x10 -> 0x0 | |
pci_cfg_write i440FX 00:0 @0x10 <- 0x0 | |
pci_cfg_write i440FX 00:0 @0x14 <- 0x0 | |
bar_ofs 20 | |
pci_cfg_read i440FX 00:0 @0x14 -> 0x0 | |
pci_cfg_write i440FX 00:0 @0x14 <- 0xfffffff0 | |
pci_cfg_read i440FX 00:0 @0x14 -> 0x0 | |
pci_cfg_write i440FX 00:0 @0x14 <- 0x0 | |
pci_cfg_write i440FX 00:0 @0x18 <- 0x0 | |
bar_ofs 24 | |
pci_cfg_read i440FX 00:0 @0x18 -> 0x0 | |
pci_cfg_write i440FX 00:0 @0x18 <- 0xfffffff0 | |
pci_cfg_read i440FX 00:0 @0x18 -> 0x0 | |
pci_cfg_write i440FX 00:0 @0x18 <- 0x0 | |
pci_cfg_write i440FX 00:0 @0x1c <- 0x0 | |
bar_ofs 28 | |
pci_cfg_read i440FX 00:0 @0x1c -> 0x0 | |
pci_cfg_write i440FX 00:0 @0x1c <- 0xfffffff0 | |
pci_cfg_read i440FX 00:0 @0x1c -> 0x0 | |
pci_cfg_write i440FX 00:0 @0x1c <- 0x0 | |
pci_cfg_write i440FX 00:0 @0x20 <- 0x0 | |
bar_ofs 32 | |
pci_cfg_read i440FX 00:0 @0x20 -> 0x0 | |
pci_cfg_write i440FX 00:0 @0x20 <- 0xfffffff0 | |
pci_cfg_read i440FX 00:0 @0x20 -> 0x0 | |
pci_cfg_write i440FX 00:0 @0x20 <- 0x0 | |
pci_cfg_write i440FX 00:0 @0x24 <- 0x0 | |
Checking 0:1:0 | |
pci_cfg_read PIIX3 01:0 @0xc -> 0x800000 | |
pci_cfg_read PIIX3 01:0 @0x8 -> 0x6010000 | |
pci_cfg_read PIIX3 01:0 @0x8 -> 0x6010000 | |
pci_cfg_read PIIX3 01:0 @0x8 -> 0x6010000 | |
class=6 subclass=1 Bridge/ISA | |
bar_ofs 16 | |
pci_cfg_read PIIX3 01:0 @0x10 -> 0x0 | |
pci_cfg_write PIIX3 01:0 @0x10 <- 0xfffffff0 | |
pci_cfg_read PIIX3 01:0 @0x10 -> 0x0 | |
pci_cfg_write PIIX3 01:0 @0x10 <- 0x0 | |
pci_cfg_write PIIX3 01:0 @0x14 <- 0x0 | |
bar_ofs 20 | |
pci_cfg_read PIIX3 01:0 @0x14 -> 0x0 | |
pci_cfg_write PIIX3 01:0 @0x14 <- 0xfffffff0 | |
pci_cfg_read PIIX3 01:0 @0x14 -> 0x0 | |
pci_cfg_write PIIX3 01:0 @0x14 <- 0x0 | |
pci_cfg_write PIIX3 01:0 @0x18 <- 0x0 | |
bar_ofs 24 | |
pci_cfg_read PIIX3 01:0 @0x18 -> 0x0 | |
pci_cfg_write PIIX3 01:0 @0x18 <- 0xfffffff0 | |
pci_cfg_read PIIX3 01:0 @0x18 -> 0x0 | |
pci_cfg_write PIIX3 01:0 @0x18 <- 0x0 | |
pci_cfg_write PIIX3 01:0 @0x1c <- 0x0 | |
bar_ofs 28 | |
pci_cfg_read PIIX3 01:0 @0x1c -> 0x0 | |
pci_cfg_write PIIX3 01:0 @0x1c <- 0xfffffff0 | |
pci_cfg_read PIIX3 01:0 @0x1c -> 0x0 | |
pci_cfg_write PIIX3 01:0 @0x1c <- 0x0 | |
pci_cfg_write PIIX3 01:0 @0x20 <- 0x0 | |
bar_ofs 32 | |
pci_cfg_read PIIX3 01:0 @0x20 -> 0x0 | |
pci_cfg_write PIIX3 01:0 @0x20 <- 0xfffffff0 | |
pci_cfg_read PIIX3 01:0 @0x20 -> 0x0 | |
pci_cfg_write PIIX3 01:0 @0x20 <- 0x0 | |
pci_cfg_write PIIX3 01:0 @0x24 <- 0x0 | |
Checking 0:1:1 | |
pci_cfg_read piix3-ide 01:1 @0xc -> 0x0 | |
pci_cfg_read piix3-ide 01:1 @0x8 -> 0x1018000 | |
pci_cfg_read piix3-ide 01:1 @0x8 -> 0x1018000 | |
pci_cfg_read piix3-ide 01:1 @0x8 -> 0x1018000 | |
class=1 subclass=1 Storage/IDE | |
bar_ofs 16 | |
pci_cfg_read piix3-ide 01:1 @0x10 -> 0x0 | |
pci_cfg_write piix3-ide 01:1 @0x10 <- 0xfffffff0 | |
pci_cfg_read piix3-ide 01:1 @0x10 -> 0x0 | |
pci_cfg_write piix3-ide 01:1 @0x10 <- 0x0 | |
pci_cfg_write piix3-ide 01:1 @0x14 <- 0x0 | |
bar_ofs 20 | |
pci_cfg_read piix3-ide 01:1 @0x14 -> 0x0 | |
pci_cfg_write piix3-ide 01:1 @0x14 <- 0xfffffff0 | |
pci_cfg_read piix3-ide 01:1 @0x14 -> 0x0 | |
pci_cfg_write piix3-ide 01:1 @0x14 <- 0x0 | |
pci_cfg_write piix3-ide 01:1 @0x18 <- 0x0 | |
bar_ofs 24 | |
pci_cfg_read piix3-ide 01:1 @0x18 -> 0x0 | |
pci_cfg_write piix3-ide 01:1 @0x18 <- 0xfffffff0 | |
pci_cfg_read piix3-ide 01:1 @0x18 -> 0x0 | |
pci_cfg_write piix3-ide 01:1 @0x18 <- 0x0 | |
pci_cfg_write piix3-ide 01:1 @0x1c <- 0x0 | |
bar_ofs 28 | |
pci_cfg_read piix3-ide 01:1 @0x1c -> 0x0 | |
pci_cfg_write piix3-ide 01:1 @0x1c <- 0xfffffff0 | |
pci_cfg_read piix3-ide 01:1 @0x1c -> 0x0 | |
pci_cfg_write piix3-ide 01:1 @0x1c <- 0x0 | |
pci_cfg_write piix3-ide 01:1 @0x20 <- 0x0 | |
bar_ofs 32 | |
pci_cfg_read piix3-ide 01:1 @0x20 -> 0x1 | |
pci_cfg_write piix3-ide 01:1 @0x20 <- 0xfffffff0 | |
pci_cfg_read piix3-ide 01:1 @0x20 -> 0xfffffff1 | |
pci_cfg_write piix3-ide 01:1 @0x20 <- 0xeff0 | |
pci_cfg_read piix3-ide 01:1 @0x4 -> 0x2800000 | |
pci_cfg_read piix3-ide 01:1 @0x4 -> 0x2800000 | |
pci_cfg_write piix3-ide 01:1 @0x4 <- 0x2800001 | |
pci_update_mappings_add d=0x557d795cc390 00:01.1 4,0xeff0+0x10 | |
Checking 0:1:2 | |
Checking 0:2:0 | |
pci_cfg_read e1000 02:0 @0xc -> 0x0 | |
pci_cfg_read e1000 02:0 @0x8 -> 0x2000003 | |
pci_cfg_read e1000 02:0 @0x8 -> 0x2000003 | |
pci_cfg_read e1000 02:0 @0x8 -> 0x2000003 | |
class=2 subclass=0 Network/Ethernet | |
bar_ofs 16 | |
pci_cfg_read e1000 02:0 @0x10 -> 0x0 | |
pci_cfg_write e1000 02:0 @0x10 <- 0xfffffff0 | |
pci_cfg_read e1000 02:0 @0x10 -> 0xfffe0000 | |
pci_cfg_write e1000 02:0 @0x10 <- 0xeffe0000 | |
pci_cfg_read e1000 02:0 @0x4 -> 0x0 | |
pci_cfg_read e1000 02:0 @0x4 -> 0x0 | |
pci_cfg_write e1000 02:0 @0x4 <- 0x2 | |
pci_update_mappings_add d=0x557d795d8520 00:02.0 0,0xeffe0000+0x20000 | |
bar_ofs 20 | |
pci_cfg_read e1000 02:0 @0x14 -> 0x1 | |
pci_cfg_write e1000 02:0 @0x14 <- 0xfffffff0 | |
pci_cfg_read e1000 02:0 @0x14 -> 0xffffffc1 | |
pci_cfg_write e1000 02:0 @0x14 <- 0xef80 | |
pci_cfg_read e1000 02:0 @0x4 -> 0x2 | |
pci_cfg_read e1000 02:0 @0x4 -> 0x2 | |
pci_cfg_write e1000 02:0 @0x4 <- 0x3 | |
pci_update_mappings_add d=0x557d795d8520 00:02.0 1,0xef80+0x40 | |
bar_ofs 24 | |
pci_cfg_read e1000 02:0 @0x18 -> 0x0 | |
pci_cfg_write e1000 02:0 @0x18 <- 0xfffffff0 | |
pci_cfg_read e1000 02:0 @0x18 -> 0x0 | |
pci_cfg_write e1000 02:0 @0x18 <- 0x0 | |
pci_cfg_write e1000 02:0 @0x1c <- 0x0 | |
bar_ofs 28 | |
pci_cfg_read e1000 02:0 @0x1c -> 0x0 | |
pci_cfg_write e1000 02:0 @0x1c <- 0xfffffff0 | |
pci_cfg_read e1000 02:0 @0x1c -> 0x0 | |
pci_cfg_write e1000 02:0 @0x1c <- 0x0 | |
pci_cfg_write e1000 02:0 @0x20 <- 0x0 | |
bar_ofs 32 | |
pci_cfg_read e1000 02:0 @0x20 -> 0x0 | |
pci_cfg_write e1000 02:0 @0x20 <- 0xfffffff0 | |
pci_cfg_read e1000 02:0 @0x20 -> 0x0 | |
pci_cfg_write e1000 02:0 @0x20 <- 0x0 | |
pci_cfg_write e1000 02:0 @0x24 <- 0x0 | |
Checking 0:3:0 | |
pci_cfg_read secondary-vga 03:0 @0xc -> 0x0 | |
pci_cfg_read secondary-vga 03:0 @0x8 -> 0x3800002 | |
pci_cfg_read secondary-vga 03:0 @0x8 -> 0x3800002 | |
pci_cfg_read secondary-vga 03:0 @0x8 -> 0x3800002 | |
class=3 subclass=80 Display/Other | |
bar_ofs 16 | |
pci_cfg_read secondary-vga 03:0 @0x10 -> 0x8 | |
pci_cfg_write secondary-vga 03:0 @0x10 <- 0xfffffff0 | |
pci_cfg_read secondary-vga 03:0 @0x10 -> 0xff000008 | |
pci_cfg_write secondary-vga 03:0 @0x10 <- 0xee000000 | |
pci_cfg_read secondary-vga 03:0 @0x4 -> 0x0 | |
pci_cfg_read secondary-vga 03:0 @0x4 -> 0x0 | |
pci_cfg_write secondary-vga 03:0 @0x4 <- 0x2 | |
pci_update_mappings_add d=0x557d7988a420 00:03.0 0,0xee000000+0x1000000 | |
bar_ofs 20 | |
pci_cfg_read secondary-vga 03:0 @0x14 -> 0x0 | |
pci_cfg_write secondary-vga 03:0 @0x14 <- 0xfffffff0 | |
pci_cfg_read secondary-vga 03:0 @0x14 -> 0x0 | |
pci_cfg_write secondary-vga 03:0 @0x14 <- 0x0 | |
pci_cfg_write secondary-vga 03:0 @0x18 <- 0x0 | |
bar_ofs 24 | |
pci_cfg_read secondary-vga 03:0 @0x18 -> 0x0 | |
pci_cfg_write secondary-vga 03:0 @0x18 <- 0xfffffff0 | |
pci_cfg_read secondary-vga 03:0 @0x18 -> 0xfffff000 | |
pci_cfg_write secondary-vga 03:0 @0x18 <- 0xedfff000 | |
pci_update_mappings_add d=0x557d7988a420 00:03.0 2,0xedfff000+0x1000 | |
pci_cfg_read secondary-vga 03:0 @0x4 -> 0x2 | |
pci_cfg_read secondary-vga 03:0 @0x4 -> 0x2 | |
pci_cfg_write secondary-vga 03:0 @0x4 <- 0x2 | |
bar_ofs 28 | |
pci_cfg_read secondary-vga 03:0 @0x1c -> 0x0 | |
pci_cfg_write secondary-vga 03:0 @0x1c <- 0xfffffff0 | |
pci_cfg_read secondary-vga 03:0 @0x1c -> 0x0 | |
pci_cfg_write secondary-vga 03:0 @0x1c <- 0x0 | |
pci_cfg_write secondary-vga 03:0 @0x20 <- 0x0 | |
bar_ofs 32 | |
pci_cfg_read secondary-vga 03:0 @0x20 -> 0x0 | |
pci_cfg_write secondary-vga 03:0 @0x20 <- 0xfffffff0 | |
pci_cfg_read secondary-vga 03:0 @0x20 -> 0x0 | |
pci_cfg_write secondary-vga 03:0 @0x20 <- 0x0 | |
pci_cfg_write secondary-vga 03:0 @0x24 <- 0x0 | |
pci_cfg_read secondary-vga 03:0 @0x18 -> 0xedfff000 | |
Using dispi MMIO at edfff000 | |
xres=0 yres=0 bpp=0 enable=0 bank=0 vw=0 vh=0 xo=0 yo=0 | |
xres=1024 yres=768 bpp=32 enable=65 bank=0 vw=1024 vh=768 xo=0 yo=0 | |
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