pll.py

class PLL(Elaboratable):
	def elaborate(self, platform):
		m = Module()	
		m.submodules.pll = Instance(
			'SB_PLL40_2_PAD',
			i_PACKAGEPIN = platform.request('clk24_576').i,
			i_RESETB = Const(1),
			i_BYPASS = Const(0),

			o_PLLOUTGLOBALA = self.clk24_576,
			o_PLLOUTGLOBALB = self.clk36_864,

			p_FEEDBACK_PATH = 'SIMPLE',
			p_PLLOUT_SELECT_PORTB = 'GENCLK',

			p_DIVR = 0,
			p_DIVF = 23,
			p_DIVQ = 4,
			p_FILTER_RANGE = 2
		)

		platform.add_clock_constraint(self.clk24_576, 24.576e6)
		platform.add_clock_constraint(self.clk36_864, 36.864e6)
		return m