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dramforever/clkgen.txt

Last active July 13, 2022 18:30
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(Partially) undocumented JH7100 registers found in headers
Raw
clkgen.txt
Register: clk_cpundbus_root_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x0
31 24 16 8 0
| | | | |
[------<>------------------------]
'-------------------------- [25:24] (rw) clk_cpundbus_root_src
Register: clk_dla_root_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x4
31 24 16 8 0
| | | | |
[------<>------------------------]
'-------------------------- [25:24] (rw) clk_dla_root_src
Register: clk_dsp_root_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x8
31 24 16 8 0
| | | | |
[------<>------------------------]
'-------------------------- [25:24] (rw) clk_dsp_root_src
Register: clk_gmacusb_root_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0xc
31 24 16 8 0
| | | | |
[------<>------------------------]
'-------------------------- [25:24] (rw) clk_gmacusb_root_src
Register: clk_perh0_root_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x10
31 24 16 8 0
| | | | |
[-------o------------------------]
'-------------------------- [24] (rw) clk_perh0_root_src
Register: clk_perh1_root_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x14
31 24 16 8 0
| | | | |
[-------o------------------------]
'-------------------------- [24] (rw) clk_perh1_root_src
Register: clk_vin_root_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x18
31 24 16 8 0
| | | | |
[------<>------------------------]
'-------------------------- [25:24] (rw) clk_vin_root_src
Register: clk_vout_root_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x1c
31 24 16 8 0
| | | | |
[------<>------------------------]
'-------------------------- [25:24] (rw) clk_vout_root_src
Register: clk_audio_root_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x20
31 24 16 8 0
| | | | |
[o---------------------------<==>]
| '-- [3:0] (rw) clk_audio_root_div
'--------------------------------- [31] (rw) clk_audio_root_en
Register: clk_cdechifi4_root_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x24
31 24 16 8 0
| | | | |
[------<>------------------------]
'-------------------------- [25:24] (rw) clk_cdechifi4_root_src
Register: clk_cdec_root_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x28
31 24 16 8 0
| | | | |
[------<>------------------------]
'-------------------------- [25:24] (rw) clk_cdec_root_src
Register: clk_voutbus_root_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x2c
31 24 16 8 0
| | | | |
[------<>------------------------]
'-------------------------- [25:24] (rw) clk_voutbus_root_src
Register: clk_cpunbus_root_div_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x30
31 24 16 8 0
| | | | |
[------------------------------<>]
'-- [1:0] (rw) clk_cpunbus_root_div_div
Register: clk_dsp_root_div_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x34
31 24 16 8 0
| | | | |
[-----------------------------<=>]
'-- [2:0] (rw) clk_dsp_root_div_div
Register: clk_perh0_src_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x38
31 24 16 8 0
| | | | |
[-----------------------------<=>]
'-- [2:0] (rw) clk_perh0_src_div
Register: clk_perh1_src_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x3c
31 24 16 8 0
| | | | |
[-----------------------------<=>]
'-- [2:0] (rw) clk_perh1_src_div
Register: clk_pll0_testout_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x40
31 24 16 8 0
| | | | |
[o--------------------------<===>]
| '-- [4:0] (rw) clk_pll0_testout_div
'--------------------------------- [31] (rw) clk_pll0_testout_en
Register: clk_pll1_testout_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x44
31 24 16 8 0
| | | | |
[o--------------------------<===>]
| '-- [4:0] (rw) clk_pll1_testout_div
'--------------------------------- [31] (rw) clk_pll1_testout_en
Register: clk_pll2_testout_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x48
31 24 16 8 0
| | | | |
[o--------------------------<===>]
| '-- [4:0] (rw) clk_pll2_testout_div
'--------------------------------- [31] (rw) clk_pll2_testout_en
Register: clk_pll2_refclk_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x4c
31 24 16 8 0
| | | | |
[-------o------------------------]
'-------------------------- [24] (rw) clk_pll2_refclk_src
Register: clk_cpu_core_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x50
31 24 16 8 0
| | | | |
[----------------------------<==>]
'-- [3:0] (rw) clk_cpu_core_div
Register: clk_cpu_axi_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x54
31 24 16 8 0
| | | | |
[----------------------------<==>]
'-- [3:0] (rw) clk_cpu_axi_div
Register: clk_ahb_bus_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x58
31 24 16 8 0
| | | | |
[----------------------------<==>]
'-- [3:0] (rw) clk_ahb_bus_div
Register: clk_apb1_bus_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x5c
31 24 16 8 0
| | | | |
[----------------------------<==>]
'-- [3:0] (rw) clk_apb1_bus_div
Register: clk_apb2_bus_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x60
31 24 16 8 0
| | | | |
[----------------------------<==>]
'-- [3:0] (rw) clk_apb2_bus_div
Register: clk_dom3ahb_bus_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x64
31 24 16 8 0
| | | | |
[o-------------------------------]
'--------------------------------- [31] (rw) clk_dom3ahb_bus_en
Register: clk_dom7ahb_bus_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x68
31 24 16 8 0
| | | | |
[o-------------------------------]
'--------------------------------- [31] (rw) clk_dom7ahb_bus_en
Register: clk_u74_core0_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x6c
31 24 16 8 0
| | | | |
[o-------------------------------]
'--------------------------------- [31] (rw) clk_u74_core0_en
Register: clk_u74_core1_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x70
31 24 16 8 0
| | | | |
[o---------------------------<==>]
| '-- [3:0] (rw) clk_u74_core1_div
'--------------------------------- [31] (rw) clk_u74_core1_en
Register: clk_u74_axi_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x74
31 24 16 8 0
| | | | |
[o-------------------------------]
'--------------------------------- [31] (rw) clk_u74_axi_en
Register: clk_u74rtc_toggle_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x78
31 24 16 8 0
| | | | |
[o-------------------------------]
'--------------------------------- [31] (rw) clk_u74rtc_toggle_en
Register: clk_sgdma2p_axi_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x7c
31 24 16 8 0
| | | | |
[o-------------------------------]
'--------------------------------- [31] (rw) clk_sgdma2p_axi_en
Register: clk_dma2pnoc_axi_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x80
31 24 16 8 0
| | | | |
[o-------------------------------]
'--------------------------------- [31] (rw) clk_dma2pnoc_axi_en
Register: clk_sgdma2p_ahb_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x84
31 24 16 8 0
| | | | |
[o-------------------------------]
'--------------------------------- [31] (rw) clk_sgdma2p_ahb_en
Register: clk_dla_bus_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x88
31 24 16 8 0
| | | | |
[-----------------------------<=>]
'-- [2:0] (rw) clk_dla_bus_div
Register: clk_dla_axi_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x8c
31 24 16 8 0
| | | | |
[o-------------------------------]
'--------------------------------- [31] (rw) clk_dla_axi_en
Register: clk_dlanoc_axi_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x90
31 24 16 8 0
| | | | |
[o-------------------------------]
'--------------------------------- [31] (rw) clk_dlanoc_axi_en
Register: clk_dla_apb_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x94
31 24 16 8 0
| | | | |
[o-------------------------------]
'--------------------------------- [31] (rw) clk_dla_apb_en
Register: clk_vp6_core_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x98
31 24 16 8 0
| | | | |
[o----------------------------<=>]
| '-- [2:0] (rw) clk_vp6_core_div
'--------------------------------- [31] (rw) clk_vp6_core_en
Register: clk_vp6bus_src_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x9c
31 24 16 8 0
| | | | |
[-----------------------------<=>]
'-- [2:0] (rw) clk_vp6bus_src_div
Register: clk_vp6_axi_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0xa0
31 24 16 8 0
| | | | |
[o----------------------------<=>]
| '-- [2:0] (rw) clk_vp6_axi_div
'--------------------------------- [31] (rw) clk_vp6_axi_en
Register: clk_vcdecbus_src_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0xa4
31 24 16 8 0
| | | | |
[-----------------------------<=>]
'-- [2:0] (rw) clk_vcdecbus_src_div
Register: clk_vdec_bus_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0xa8
31 24 16 8 0
| | | | |
[----------------------------<==>]
'-- [3:0] (rw) clk_vdec_bus_div
Register: clk_vdec_axi_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0xac
31 24 16 8 0
| | | | |
[o-------------------------------]
'--------------------------------- [31] (rw) clk_vdec_axi_en
Register: clk_vdecbrg_mainclk_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0xb0
31 24 16 8 0
| | | | |
[o-------------------------------]
'--------------------------------- [31] (rw) clk_vdecbrg_mainclk_en
Register: clk_vdec_bclk_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0xb4
31 24 16 8 0
| | | | |
[o---------------------------<==>]
| '-- [3:0] (rw) clk_vdec_bclk_div
'--------------------------------- [31] (rw) clk_vdec_bclk_en
Register: clk_vdec_cclk_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0xb8
31 24 16 8 0
| | | | |
[o---------------------------<==>]
| '-- [3:0] (rw) clk_vdec_cclk_div
'--------------------------------- [31] (rw) clk_vdec_cclk_en
Register: clk_vdec_apb_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0xbc
31 24 16 8 0
| | | | |
[o-------------------------------]
'--------------------------------- [31] (rw) clk_vdec_apb_en
Register: clk_jpeg_axi_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0xc0
31 24 16 8 0
| | | | |
[o---------------------------<==>]
| '-- [3:0] (rw) clk_jpeg_axi_div
'--------------------------------- [31] (rw) clk_jpeg_axi_en
Register: clk_jpeg_cclk_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0xc4
31 24 16 8 0
| | | | |
[o---------------------------<==>]
| '-- [3:0] (rw) clk_jpeg_cclk_div
'--------------------------------- [31] (rw) clk_jpeg_cclk_en
Register: clk_jpeg_apb_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0xc8
31 24 16 8 0
| | | | |
[o-------------------------------]
'--------------------------------- [31] (rw) clk_jpeg_apb_en
Register: clk_gc300_2x_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0xcc
31 24 16 8 0
| | | | |
[o---------------------------<==>]
| '-- [3:0] (rw) clk_gc300_2x_div
'--------------------------------- [31] (rw) clk_gc300_2x_en
Register: clk_gc300_ahb_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0xd0
31 24 16 8 0
| | | | |
[o-------------------------------]
'--------------------------------- [31] (rw) clk_gc300_ahb_en
Register: clk_jpcgc300_axibus_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0xd4
31 24 16 8 0
| | | | |
[----------------------------<==>]
'-- [3:0] (rw) clk_jpcgc300_axibus_div
Register: clk_gc300_axi_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0xd8
31 24 16 8 0
| | | | |
[o-------------------------------]
'--------------------------------- [31] (rw) clk_gc300_axi_en
Register: clk_jpcgc300_mainclk_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0xdc
31 24 16 8 0
| | | | |
[o-------------------------------]
'--------------------------------- [31] (rw) clk_jpcgc300_mainclk_en
Register: clk_venc_bus_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0xe0
31 24 16 8 0
| | | | |
[----------------------------<==>]
'-- [3:0] (rw) clk_venc_bus_div
Register: clk_venc_axi_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0xe4
31 24 16 8 0
| | | | |
[o-------------------------------]
'--------------------------------- [31] (rw) clk_venc_axi_en
Register: clk_vencbrg_mainclk_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0xe8
31 24 16 8 0
| | | | |
[o-------------------------------]
'--------------------------------- [31] (rw) clk_vencbrg_mainclk_en
Register: clk_venc_bclk_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0xec
31 24 16 8 0
| | | | |
[o---------------------------<==>]
| '-- [3:0] (rw) clk_venc_bclk_div
'--------------------------------- [31] (rw) clk_venc_bclk_en
Register: clk_venc_cclk_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0xf0
31 24 16 8 0
| | | | |
[o---------------------------<==>]
| '-- [3:0] (rw) clk_venc_cclk_div
'--------------------------------- [31] (rw) clk_venc_cclk_en
Register: clk_venc_apb_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0xf4
31 24 16 8 0
| | | | |
[o-------------------------------]
'--------------------------------- [31] (rw) clk_venc_apb_en
Register: clk_ddrpll_div2_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0xf8
31 24 16 8 0
| | | | |
[o-----------------------------<>]
| '-- [1:0] (rw) clk_ddrpll_div2_div
'--------------------------------- [31] (rw) clk_ddrpll_div2_en
Register: clk_ddrpll_div4_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0xfc
31 24 16 8 0
| | | | |
[o-----------------------------<>]
| '-- [1:0] (rw) clk_ddrpll_div4_div
'--------------------------------- [31] (rw) clk_ddrpll_div4_en
Register: clk_ddrpll_div8_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x100
31 24 16 8 0
| | | | |
[o-----------------------------<>]
| '-- [1:0] (rw) clk_ddrpll_div8_div
'--------------------------------- [31] (rw) clk_ddrpll_div8_en
Register: clk_ddrosc_div2_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x104
31 24 16 8 0
| | | | |
[o-----------------------------<>]
| '-- [1:0] (rw) clk_ddrosc_div2_div
'--------------------------------- [31] (rw) clk_ddrosc_div2_en
Register: clk_ddrc0_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x108
31 24 16 8 0
| | | | |
[o-----<>------------------------]
| '-------------------------- [25:24] (rw) clk_ddrc0_src
'--------------------------------- [31] (rw) clk_ddrc0_en
Register: clk_ddrc1_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x10c
31 24 16 8 0
| | | | |
[o-----<>------------------------]
| '-------------------------- [25:24] (rw) clk_ddrc1_src
'--------------------------------- [31] (rw) clk_ddrc1_en
Register: clk_ddrphy_apb_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x110
31 24 16 8 0
| | | | |
[o-------------------------------]
'--------------------------------- [31] (rw) clk_ddrphy_apb_en
Register: clk_noc_rob_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x114
31 24 16 8 0
| | | | |
[----------------------------<==>]
'-- [3:0] (rw) clk_noc_rob_div
Register: clk_noc_cog_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x118
31 24 16 8 0
| | | | |
[----------------------------<==>]
'-- [3:0] (rw) clk_noc_cog_div
Register: clk_nne_ahb_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x11c
31 24 16 8 0
| | | | |
[o-------------------------------]
'--------------------------------- [31] (rw) clk_nne_ahb_en
Register: clk_nnebus_src1_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x120
31 24 16 8 0
| | | | |
[-----------------------------<=>]
'-- [2:0] (rw) clk_nnebus_src1_div
Register: clk_nne_bus_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x124
31 24 16 8 0
| | | | |
[-------o------------------------]
'-------------------------- [24] (rw) clk_nne_bus_src
Register: clk_nne_axi_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x128
31 24 16 8 0
| | | | |
[o-------------------------------]
'--------------------------------- [31] (rw) clk_nne_axi_en
Register: clk_nnenoc_axi_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x12c
31 24 16 8 0
| | | | |
[o-------------------------------]
'--------------------------------- [31] (rw) clk_nnenoc_axi_en
Register: clk_dlaslv_axi_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x130
31 24 16 8 0
| | | | |
[o-------------------------------]
'--------------------------------- [31] (rw) clk_dlaslv_axi_en
Register: clk_dspx2c_axi_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x134
31 24 16 8 0
| | | | |
[o-------------------------------]
'--------------------------------- [31] (rw) clk_dspx2c_axi_en
Register: clk_hifi4_src_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x138
31 24 16 8 0
| | | | |
[-----------------------------<=>]
'-- [2:0] (rw) clk_hifi4_src_div
Register: clk_hifi4_corefree_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x13c
31 24 16 8 0
| | | | |
[----------------------------<==>]
'-- [3:0] (rw) clk_hifi4_corefree_div
Register: clk_hifi4_core_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x140
31 24 16 8 0
| | | | |
[o-------------------------------]
'--------------------------------- [31] (rw) clk_hifi4_core_en
Register: clk_hifi4_bus_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x144
31 24 16 8 0
| | | | |
[----------------------------<==>]
'-- [3:0] (rw) clk_hifi4_bus_div
Register: clk_hifi4_axi_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x148
31 24 16 8 0
| | | | |
[o-------------------------------]
'--------------------------------- [31] (rw) clk_hifi4_axi_en
Register: clk_hifi4noc_axi_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x14c
31 24 16 8 0
| | | | |
[o-------------------------------]
'--------------------------------- [31] (rw) clk_hifi4noc_axi_en
Register: clk_sgdma1p_bus_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x150
31 24 16 8 0
| | | | |
[----------------------------<==>]
'-- [3:0] (rw) clk_sgdma1p_bus_div
Register: clk_sgdma1p_axi_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x154
31 24 16 8 0
| | | | |
[o-------------------------------]
'--------------------------------- [31] (rw) clk_sgdma1p_axi_en
Register: clk_dma1p_axi_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x158
31 24 16 8 0
| | | | |
[o-------------------------------]
'--------------------------------- [31] (rw) clk_dma1p_axi_en
Register: clk_x2c_axi_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x15c
31 24 16 8 0
| | | | |
[o---------------------------<==>]
| '-- [3:0] (rw) clk_x2c_axi_div
'--------------------------------- [31] (rw) clk_x2c_axi_en
Register: clk_usb_bus_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x160
31 24 16 8 0
| | | | |
[----------------------------<==>]
'-- [3:0] (rw) clk_usb_bus_div
Register: clk_usb_axi_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x164
31 24 16 8 0
| | | | |
[o-------------------------------]
'--------------------------------- [31] (rw) clk_usb_axi_en
Register: clk_usbnoc_axi_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x168
31 24 16 8 0
| | | | |
[o-------------------------------]
'--------------------------------- [31] (rw) clk_usbnoc_axi_en
Register: clk_usbphy_rootdiv_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x16c
31 24 16 8 0
| | | | |
[-----------------------------<=>]
'-- [2:0] (rw) clk_usbphy_rootdiv_div
Register: clk_usbphy_125m_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x170
31 24 16 8 0
| | | | |
[o---------------------------<==>]
| '-- [3:0] (rw) clk_usbphy_125m_div
'--------------------------------- [31] (rw) clk_usbphy_125m_en
Register: clk_usbphy_plldiv25m_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x174
31 24 16 8 0
| | | | |
[o-------------------------<====>]
| '-- [5:0] (rw) clk_usbphy_plldiv25m_div
'--------------------------------- [31] (rw) clk_usbphy_plldiv25m_en
Register: clk_usbphy_25m_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x178
31 24 16 8 0
| | | | |
[-------o------------------------]
'-------------------------- [24] (rw) clk_usbphy_25m_src
Register: clk_audio_div_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x17c
31 24 16 8 0
| | | | |
[--------------<================>]
'-- [17:0] (rw) clk_audio_div_div
Register: clk_audio_src_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x180
31 24 16 8 0
| | | | |
[o-------------------------------]
'--------------------------------- [31] (rw) clk_audio_src_en
Register: clk_audio_12288_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x184
31 24 16 8 0
| | | | |
[o-------------------------------]
'--------------------------------- [31] (rw) clk_audio_12288_en
Register: clk_vin_src_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x188
31 24 16 8 0
| | | | |
[o----------------------------<=>]
| '-- [2:0] (rw) clk_vin_src_div
'--------------------------------- [31] (rw) clk_vin_src_en
Register: clk_isp0_bus_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x18c
31 24 16 8 0
| | | | |
[----------------------------<==>]
'-- [3:0] (rw) clk_isp0_bus_div
Register: clk_isp0_axi_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x190
31 24 16 8 0
| | | | |
[o-------------------------------]
'--------------------------------- [31] (rw) clk_isp0_axi_en
Register: clk_isp0noc_axi_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x194
31 24 16 8 0
| | | | |
[o-------------------------------]
'--------------------------------- [31] (rw) clk_isp0noc_axi_en
Register: clk_ispslv_axi_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x198
31 24 16 8 0
| | | | |
[o-------------------------------]
'--------------------------------- [31] (rw) clk_ispslv_axi_en
Register: clk_isp1_bus_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x19c
31 24 16 8 0
| | | | |
[----------------------------<==>]
'-- [3:0] (rw) clk_isp1_bus_div
Register: clk_isp1_axi_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x1a0
31 24 16 8 0
| | | | |
[o-------------------------------]
'--------------------------------- [31] (rw) clk_isp1_axi_en
Register: clk_isp1noc_axi_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x1a4
31 24 16 8 0
| | | | |
[o-------------------------------]
'--------------------------------- [31] (rw) clk_isp1noc_axi_en
Register: clk_vin_bus_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x1a8
31 24 16 8 0
| | | | |
[----------------------------<==>]
'-- [3:0] (rw) clk_vin_bus_div
Register: clk_vin_axi_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x1ac
31 24 16 8 0
| | | | |
[o-------------------------------]
'--------------------------------- [31] (rw) clk_vin_axi_en
Register: clk_vinnoc_axi_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x1b0
31 24 16 8 0
| | | | |
[o-------------------------------]
'--------------------------------- [31] (rw) clk_vinnoc_axi_en
Register: clk_vout_src_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x1b4
31 24 16 8 0
| | | | |
[o----------------------------<=>]
| '-- [2:0] (rw) clk_vout_src_div
'--------------------------------- [31] (rw) clk_vout_src_en
Register: clk_dispbus_src_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x1b8
31 24 16 8 0
| | | | |
[-----------------------------<=>]
'-- [2:0] (rw) clk_dispbus_src_div
Register: clk_disp_bus_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x1bc
31 24 16 8 0
| | | | |
[-----------------------------<=>]
'-- [2:0] (rw) clk_disp_bus_div
Register: clk_disp_axi_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x1c0
31 24 16 8 0
| | | | |
[o-------------------------------]
'--------------------------------- [31] (rw) clk_disp_axi_en
Register: clk_dispnoc_axi_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x1c4
31 24 16 8 0
| | | | |
[o-------------------------------]
'--------------------------------- [31] (rw) clk_dispnoc_axi_en
Register: clk_sdio0_ahb_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x1c8
31 24 16 8 0
| | | | |
[o-------------------------------]
'--------------------------------- [31] (rw) clk_sdio0_ahb_en
Register: clk_sdio0_cclkint_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x1cc
31 24 16 8 0
| | | | |
[o--------------------------<===>]
| '-- [4:0] (rw) clk_sdio0_cclkint_div
'--------------------------------- [31] (rw) clk_sdio0_cclkint_en
Register: clk_sdio0_cclkint_inv_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x1d0
31 24 16 8 0
| | | | |
[-o------------------------------]
'-------------------------------- [30] (rw) clk_sdio0_cclkint_inv_pol
Register: clk_sdio1_ahb_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x1d4
31 24 16 8 0
| | | | |
[o-------------------------------]
'--------------------------------- [31] (rw) clk_sdio1_ahb_en
Register: clk_sdio1_cclkint_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x1d8
31 24 16 8 0
| | | | |
[o--------------------------<===>]
| '-- [4:0] (rw) clk_sdio1_cclkint_div
'--------------------------------- [31] (rw) clk_sdio1_cclkint_en
Register: clk_sdio1_cclkint_inv_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x1dc
31 24 16 8 0
| | | | |
[-o------------------------------]
'-------------------------------- [30] (rw) clk_sdio1_cclkint_inv_pol
Register: clk_gmac_ahb_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x1e0
31 24 16 8 0
| | | | |
[o-------------------------------]
'--------------------------------- [31] (rw) clk_gmac_ahb_en
Register: clk_gmac_root_div_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x1e4
31 24 16 8 0
| | | | |
[----------------------------<==>]
'-- [3:0] (rw) clk_gmac_root_div_div
Register: clk_gmac_ptp_refclk_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x1e8
31 24 16 8 0
| | | | |
[o--------------------------<===>]
| '-- [4:0] (rw) clk_gmac_ptp_refclk_div
'--------------------------------- [31] (rw) clk_gmac_ptp_refclk_en
Register: clk_gmac_gtxclk_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x1ec
31 24 16 8 0
| | | | |
[o-----------------------<======>]
| '-- [7:0] (rw) clk_gmac_gtxclk_div
'--------------------------------- [31] (rw) clk_gmac_gtxclk_en
Register: clk_gmac_rmii_txclk_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x1f0
31 24 16 8 0
| | | | |
[o---------------------------<==>]
| '-- [3:0] (rw) clk_gmac_rmii_txclk_div
'--------------------------------- [31] (rw) clk_gmac_rmii_txclk_en
Register: clk_gmac_rmii_rxclk_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x1f4
31 24 16 8 0
| | | | |
[o---------------------------<==>]
| '-- [3:0] (rw) clk_gmac_rmii_rxclk_div
'--------------------------------- [31] (rw) clk_gmac_rmii_rxclk_en
Register: clk_gmac_tx_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x1f8
31 24 16 8 0
| | | | |
[------<>------------------------]
'-------------------------- [25:24] (rw) clk_gmac_tx_src
Register: clk_gmac_tx_inv_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x1fc
31 24 16 8 0
| | | | |
[-o------------------------------]
'-------------------------------- [30] (rw) clk_gmac_tx_inv_pol
Register: clk_gmac_rx_pre_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x200
31 24 16 8 0
| | | | |
[-------o------------------------]
'-------------------------- [24] (rw) clk_gmac_rx_pre_src
Register: clk_gmac_rx_inv_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x204
31 24 16 8 0
| | | | |
[-o------------------------------]
'-------------------------------- [30] (rw) clk_gmac_rx_inv_pol
Register: clk_gmac_rmii_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x208
31 24 16 8 0
| | | | |
[o-------------------------------]
'--------------------------------- [31] (rw) clk_gmac_rmii_en
Register: clk_gmac_tophyref_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x20c
31 24 16 8 0
| | | | |
[o------------------------<=====>]
| '-- [6:0] (rw) clk_gmac_tophyref_div
'--------------------------------- [31] (rw) clk_gmac_tophyref_en
Register: clk_spi2ahb_ahb_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x210
31 24 16 8 0
| | | | |
[o-------------------------------]
'--------------------------------- [31] (rw) clk_spi2ahb_ahb_en
Register: clk_spi2ahb_core_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x214
31 24 16 8 0
| | | | |
[o--------------------------<===>]
| '-- [4:0] (rw) clk_spi2ahb_core_div
'--------------------------------- [31] (rw) clk_spi2ahb_core_en
Register: clk_ezmaster_ahb_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x218
31 24 16 8 0
| | | | |
[o-------------------------------]
'--------------------------------- [31] (rw) clk_ezmaster_ahb_en
Register: clk_e24_ahb_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x21c
31 24 16 8 0
| | | | |
[o-------------------------------]
'--------------------------------- [31] (rw) clk_e24_ahb_en
Register: clk_e24rtc_toggle_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x220
31 24 16 8 0
| | | | |
[o-------------------------------]
'--------------------------------- [31] (rw) clk_e24rtc_toggle_en
Register: clk_qspi_ahb_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x224
31 24 16 8 0
| | | | |
[o-------------------------------]
'--------------------------------- [31] (rw) clk_qspi_ahb_en
Register: clk_qspi_apb_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x228
31 24 16 8 0
| | | | |
[o-------------------------------]
'--------------------------------- [31] (rw) clk_qspi_apb_en
Register: clk_qspi_refclk_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x22c
31 24 16 8 0
| | | | |
[o--------------------------<===>]
| '-- [4:0] (rw) clk_qspi_refclk_div
'--------------------------------- [31] (rw) clk_qspi_refclk_en
Register: clk_sec_ahb_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x230
31 24 16 8 0
| | | | |
[o-------------------------------]
'--------------------------------- [31] (rw) clk_sec_ahb_en
Register: clk_aes_clk_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x234
31 24 16 8 0
| | | | |
[o-------------------------------]
'--------------------------------- [31] (rw) clk_aes_clk_en
Register: clk_sha_clk_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x238
31 24 16 8 0
| | | | |
[o-------------------------------]
'--------------------------------- [31] (rw) clk_sha_clk_en
Register: clk_pka_clk_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x23c
31 24 16 8 0
| | | | |
[o-------------------------------]
'--------------------------------- [31] (rw) clk_pka_clk_en
Register: clk_trng_apb_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x240
31 24 16 8 0
| | | | |
[o-------------------------------]
'--------------------------------- [31] (rw) clk_trng_apb_en
Register: clk_otp_apb_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x244
31 24 16 8 0
| | | | |
[o-------------------------------]
'--------------------------------- [31] (rw) clk_otp_apb_en
Register: clk_uart0_apb_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x248
31 24 16 8 0
| | | | |
[o-------------------------------]
'--------------------------------- [31] (rw) clk_uart0_apb_en
Register: clk_uart0_core_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x24c
31 24 16 8 0
| | | | |
[o-------------------------<====>]
| '-- [5:0] (rw) clk_uart0_core_div
'--------------------------------- [31] (rw) clk_uart0_core_en
Register: clk_uart1_apb_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x250
31 24 16 8 0
| | | | |
[o-------------------------------]
'--------------------------------- [31] (rw) clk_uart1_apb_en
Register: clk_uart1_core_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x254
31 24 16 8 0
| | | | |
[o-------------------------<====>]
| '-- [5:0] (rw) clk_uart1_core_div
'--------------------------------- [31] (rw) clk_uart1_core_en
Register: clk_spi0_apb_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x258
31 24 16 8 0
| | | | |
[o-------------------------------]
'--------------------------------- [31] (rw) clk_spi0_apb_en
Register: clk_spi0_core_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x25c
31 24 16 8 0
| | | | |
[o-------------------------<====>]
| '-- [5:0] (rw) clk_spi0_core_div
'--------------------------------- [31] (rw) clk_spi0_core_en
Register: clk_spi1_apb_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x260
31 24 16 8 0
| | | | |
[o-------------------------------]
'--------------------------------- [31] (rw) clk_spi1_apb_en
Register: clk_spi1_core_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x264
31 24 16 8 0
| | | | |
[o-------------------------<====>]
| '-- [5:0] (rw) clk_spi1_core_div
'--------------------------------- [31] (rw) clk_spi1_core_en
Register: clk_i2c0_apb_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x268
31 24 16 8 0
| | | | |
[o-------------------------------]
'--------------------------------- [31] (rw) clk_i2c0_apb_en
Register: clk_i2c0_core_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x26c
31 24 16 8 0
| | | | |
[o-------------------------<====>]
| '-- [5:0] (rw) clk_i2c0_core_div
'--------------------------------- [31] (rw) clk_i2c0_core_en
Register: clk_i2c1_apb_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x270
31 24 16 8 0
| | | | |
[o-------------------------------]
'--------------------------------- [31] (rw) clk_i2c1_apb_en
Register: clk_i2c1_core_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x274
31 24 16 8 0
| | | | |
[o-------------------------<====>]
| '-- [5:0] (rw) clk_i2c1_core_div
'--------------------------------- [31] (rw) clk_i2c1_core_en
Register: clk_gpio_apb_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x278
31 24 16 8 0
| | | | |
[o-------------------------------]
'--------------------------------- [31] (rw) clk_gpio_apb_en
Register: clk_uart2_apb_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x27c
31 24 16 8 0
| | | | |
[o-------------------------------]
'--------------------------------- [31] (rw) clk_uart2_apb_en
Register: clk_uart2_core_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x280
31 24 16 8 0
| | | | |
[o-------------------------<====>]
| '-- [5:0] (rw) clk_uart2_core_div
'--------------------------------- [31] (rw) clk_uart2_core_en
Register: clk_uart3_apb_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x284
31 24 16 8 0
| | | | |
[o-------------------------------]
'--------------------------------- [31] (rw) clk_uart3_apb_en
Register: clk_uart3_core_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x288
31 24 16 8 0
| | | | |
[o-------------------------<====>]
| '-- [5:0] (rw) clk_uart3_core_div
'--------------------------------- [31] (rw) clk_uart3_core_en
Register: clk_spi2_apb_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x28c
31 24 16 8 0
| | | | |
[o-------------------------------]
'--------------------------------- [31] (rw) clk_spi2_apb_en
Register: clk_spi2_core_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x290
31 24 16 8 0
| | | | |
[o-------------------------<====>]
| '-- [5:0] (rw) clk_spi2_core_div
'--------------------------------- [31] (rw) clk_spi2_core_en
Register: clk_spi3_apb_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x294
31 24 16 8 0
| | | | |
[o-------------------------------]
'--------------------------------- [31] (rw) clk_spi3_apb_en
Register: clk_spi3_core_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x298
31 24 16 8 0
| | | | |
[o-------------------------<====>]
| '-- [5:0] (rw) clk_spi3_core_div
'--------------------------------- [31] (rw) clk_spi3_core_en
Register: clk_i2c2_apb_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x29c
31 24 16 8 0
| | | | |
[o-------------------------------]
'--------------------------------- [31] (rw) clk_i2c2_apb_en
Register: clk_i2c2_core_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x2a0
31 24 16 8 0
| | | | |
[o-------------------------<====>]
| '-- [5:0] (rw) clk_i2c2_core_div
'--------------------------------- [31] (rw) clk_i2c2_core_en
Register: clk_i2c3_apb_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x2a4
31 24 16 8 0
| | | | |
[o-------------------------------]
'--------------------------------- [31] (rw) clk_i2c3_apb_en
Register: clk_i2c3_core_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x2a8
31 24 16 8 0
| | | | |
[o-------------------------<====>]
| '-- [5:0] (rw) clk_i2c3_core_div
'--------------------------------- [31] (rw) clk_i2c3_core_en
Register: clk_wdtimer_apb_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x2ac
31 24 16 8 0
| | | | |
[o-------------------------------]
'--------------------------------- [31] (rw) clk_wdtimer_apb_en
Register: clk_wdt_coreclk_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x2b0
31 24 16 8 0
| | | | |
[o-------------------------<====>]
| '-- [5:0] (rw) clk_wdt_coreclk_div
'--------------------------------- [31] (rw) clk_wdt_coreclk_en
Register: clk_timer0_coreclk_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x2b4
31 24 16 8 0
| | | | |
[o-------------------------<====>]
| '-- [5:0] (rw) clk_timer0_coreclk_div
'--------------------------------- [31] (rw) clk_timer0_coreclk_en
Register: clk_timer1_coreclk_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x2b8
31 24 16 8 0
| | | | |
[o-------------------------<====>]
| '-- [5:0] (rw) clk_timer1_coreclk_div
'--------------------------------- [31] (rw) clk_timer1_coreclk_en
Register: clk_timer2_coreclk_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x2bc
31 24 16 8 0
| | | | |
[o-------------------------<====>]
| '-- [5:0] (rw) clk_timer2_coreclk_div
'--------------------------------- [31] (rw) clk_timer2_coreclk_en
Register: clk_timer3_coreclk_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x2c0
31 24 16 8 0
| | | | |
[o-------------------------<====>]
| '-- [5:0] (rw) clk_timer3_coreclk_div
'--------------------------------- [31] (rw) clk_timer3_coreclk_en
Register: clk_timer4_coreclk_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x2c4
31 24 16 8 0
| | | | |
[o-------------------------<====>]
| '-- [5:0] (rw) clk_timer4_coreclk_div
'--------------------------------- [31] (rw) clk_timer4_coreclk_en
Register: clk_timer5_coreclk_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x2c8
31 24 16 8 0
| | | | |
[o-------------------------<====>]
| '-- [5:0] (rw) clk_timer5_coreclk_div
'--------------------------------- [31] (rw) clk_timer5_coreclk_en
Register: clk_timer6_coreclk_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x2cc
31 24 16 8 0
| | | | |
[o-------------------------<====>]
| '-- [5:0] (rw) clk_timer6_coreclk_div
'--------------------------------- [31] (rw) clk_timer6_coreclk_en
Register: clk_vp6intc_apb_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x2d0
31 24 16 8 0
| | | | |
[o-------------------------------]
'--------------------------------- [31] (rw) clk_vp6intc_apb_en
Register: clk_pwm_apb_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x2d4
31 24 16 8 0
| | | | |
[o-------------------------------]
'--------------------------------- [31] (rw) clk_pwm_apb_en
Register: clk_msi_apb_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x2d8
31 24 16 8 0
| | | | |
[o-------------------------------]
'--------------------------------- [31] (rw) clk_msi_apb_en
Register: clk_temp_apb_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x2dc
31 24 16 8 0
| | | | |
[o-------------------------------]
'--------------------------------- [31] (rw) clk_temp_apb_en
Register: clk_temp_sense_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x2e0
31 24 16 8 0
| | | | |
[o--------------------------<===>]
| '-- [4:0] (rw) clk_temp_sense_div
'--------------------------------- [31] (rw) clk_temp_sense_en
Register: clk_syserr_apb_ctrl_REG_ADDR
Address: CLKGEN_BASE_ADDR + 0x2e4
31 24 16 8 0
| | | | |
[o-------------------------------]
'--------------------------------- [31] (rw) clk_syserr_apb_en
Raw
iopad.txt
Register: syscon_iopad_ctrl_register103_REG_ADDR
Address: SYSCON_IOPAD_CTRL_BASE_ADDR + 0x19c
31 24 16 8 0
| | | | |
[-------------------------<=====>]
'-- [6:0] (rw) register103_SCFG_qspi_ioctrl
Register: syscon_iopad_ctrl_register104_REG_ADDR
Address: SYSCON_IOPAD_CTRL_BASE_ADDR + 0x1a0
31 24 16 8 0
| | | | |
[-----------------------------<=>]
'-- [2:0] (rw) register104_SCFG_io_padshare_sel
Raw
sysmain.txt
Register: syscon_sysmain_ctrl_SCFG_pll0_REG_ADDR
Address: SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x0
31 24 16 8 0
| | | | |
[----<==>--<====>--<====><==>oooo]
| | | ||||'-- [0] (rw) SCFG_pll0_reset
| | | |||'--- [1] (rw) SCFG_pll0_pwrdn
| | | ||'---- [2] (rw) SCFG_pll0_intfb
| | | |'----- [3] (rw) SCFG_pll0_bypass
| | | '------ [7:4] (rw) SCFG_pll0_clk_refdiv
| | '---------- [13:8] (rw) SCFG_pll0_clk_fbkdiv
| '------------------ [21:16] (rw) SCFG_pll0_bw_adj
'-------------------------- [27:24] (rw) SCFG_pll0_clk_outdiv
Register: syscon_sysmain_ctrl_SCFG_pll1_REG_ADDR
Address: SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x4
31 24 16 8 0
| | | | |
[----<==>--<====>--<====><==>oooo]
| | | ||||'-- [0] (rw) SCFG_pll1_reset
| | | |||'--- [1] (rw) SCFG_pll1_pwrdn
| | | ||'---- [2] (rw) SCFG_pll1_intfb
| | | |'----- [3] (rw) SCFG_pll1_bypass
| | | '------ [7:4] (rw) SCFG_pll1_clk_refdiv
| | '---------- [13:8] (rw) SCFG_pll1_clk_fbkdiv
| '------------------ [21:16] (rw) SCFG_pll1_bw_adj
'-------------------------- [27:24] (rw) SCFG_pll1_clk_outdiv
Register: syscon_sysmain_ctrl_SCFG_pll2_REG_ADDR
Address: SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x8
31 24 16 8 0
| | | | |
[----<==>--<====>--<====><==>oooo]
| | | ||||'-- [0] (rw) SCFG_pll2_reset
| | | |||'--- [1] (rw) SCFG_pll2_pwrdn
| | | ||'---- [2] (rw) SCFG_pll2_intfb
| | | |'----- [3] (rw) SCFG_pll2_bypass
| | | '------ [7:4] (rw) SCFG_pll2_clk_refdiv
| | '---------- [13:8] (rw) SCFG_pll2_clk_fbkdiv
| '------------------ [21:16] (rw) SCFG_pll2_bw_adj
'-------------------------- [27:24] (rw) SCFG_pll2_clk_outdiv
Register: syscon_sysmain_ctrl_SCFG_plls_stat_REG_ADDR
Address: SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0xc
31 24 16 8 0
| | | | |
[-----------------ooo-ooo-ooo-ooo]
||| ||| ||| ||'-- [0] (rw) SCFG_plls_stat_pll0_test
||| ||| ||| |'--- [1] (rw) SCFG_plls_stat_pll1_test
||| ||| ||| '---- [2] (rw) SCFG_plls_stat_pll2_test
||| ||| ||'------ [4] (r-) SCFG_plls_stat_pll0_lock
||| ||| |'------- [5] (r-) SCFG_plls_stat_pll0_ref_slip
||| ||| '-------- [6] (r-) SCFG_plls_stat_pll0_fdbk_slip
||| ||'---------- [8] (r-) SCFG_plls_stat_pll1_lock
||| |'----------- [9] (r-) SCFG_plls_stat_pll1_ref_slip
||| '------------ [10] (r-) SCFG_plls_stat_pll1_fdbk_slip
||'-------------- [12] (r-) SCFG_plls_stat_pll2_lock
|'--------------- [13] (r-) SCFG_plls_stat_pll2_ref_slip
'---------------- [14] (r-) SCFG_plls_stat_pll2_fdbk_slip
Register: syscon_sysmain_ctrl_register4_REG_ADDR
Address: SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x10
31 24 16 8 0
| | | | |
[----------------------------oooo]
|||'-- [0] (r-) register4_SCFG_u74_halt_from_tile0
||'--- [1] (r-) register4_SCFG_u74_halt_from_tile1
|'---- [2] (r-) register4_SCFG_u74_debug_ndreset
'----- [3] (r-) register4_SCFG_u74_debug_dmactive
Register: syscon_sysmain_ctrl_SCFG_u74_boot_vect0_low_REG_ADDR
Address: SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x14
31 24 16 8 0
| | | | |
[<==============================>]
'-- [31:0] (rw) SCFG_u74_boot_vect0_low_b32
Register: syscon_sysmain_ctrl_SCFG_u74_boot_vect0_hi_REG_ADDR
Address: SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x18
31 24 16 8 0
| | | | |
[--------------------------<====>]
'-- [5:0] (rw) SCFG_u74_boot_vect0_hi_b6
Register: syscon_sysmain_ctrl_SCFG_u74_boot_vect1_low_REG_ADDR
Address: SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x1c
31 24 16 8 0
| | | | |
[<==============================>]
'-- [31:0] (rw) SCFG_u74_boot_vect1_low_b32
Register: syscon_sysmain_ctrl_SCFG_u74_boot_vect1_hi_REG_ADDR
Address: SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x20
31 24 16 8 0
| | | | |
[--------------------------<====>]
'-- [5:0] (rw) SCFG_u74_boot_vect1_hi_b6
Register: syscon_sysmain_ctrl_SCFG_u74_REG_ADDR
Address: SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x24
31 24 16 8 0
| | | | |
[---------------------<=========>]
'-- [10:0] (rw) SCFG_u74_PRID
Register: syscon_sysmain_ctrl_register10_REG_ADDR
Address: SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x28
31 24 16 8 0
| | | | |
[-----------------------------ooo]
||'-- [0] (r-) register10_e24_halt
|'--- [1] (r-) register10_e24_dbg_reset
'---- [2] (r-) register10_e24_dbg_active
Register: syscon_sysmain_ctrl_register11_REG_ADDR
Address: SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x2c
31 24 16 8 0
| | | | |
[<==============================>]
'-- [31:0] (rw) register11_SCFG_nbdla_pwrbus_ram_a_pd
Register: syscon_sysmain_ctrl_register12_REG_ADDR
Address: SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x30
31 24 16 8 0
| | | | |
[<==============================>]
'-- [31:0] (rw) register12_SCFG_nbdla_pwrbus_ram_c_pd
Register: syscon_sysmain_ctrl_register13_REG_ADDR
Address: SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x34
31 24 16 8 0
| | | | |
[<==============================>]
'-- [31:0] (rw) register13_SCFG_nbdla_pwrbus_ram_o_pd
Register: syscon_sysmain_ctrl_register14_REG_ADDR
Address: SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x38
31 24 16 8 0
| | | | |
[<==============================>]
'-- [31:0] (rw) register14_SCFG_nbdla_pwrbus_ram_p_pd
Register: syscon_sysmain_ctrl_register15_REG_ADDR
Address: SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x3c
31 24 16 8 0
| | | | |
[<==============================>]
'-- [31:0] (rw) register15_SCFG_nbdla_pwrbus_ram_x_pd
Register: syscon_sysmain_ctrl_register16_REG_ADDR
Address: SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x40
31 24 16 8 0
| | | | |
[----------------------------oooo]
|||'-- [0] (rw) register16_SCFG_nbdla_globclk_ovr_on
||'--- [1] (rw) register16_SCFG_nbdla_disable_clock_gating
|'---- [2] (rw) register16_SCFG_nbdla_direct_reset
'----- [3] (rw) register16_SCFG_nbdla_clkgating_en
Register: syscon_sysmain_ctrl_register17_REG_ADDR
Address: SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x44
31 24 16 8 0
| | | | |
[------------------------------<>]
'-- [1:0] (r-) register17_SCFG_jpegc_cur_inst_a
Register: syscon_sysmain_ctrl_register18_REG_ADDR
Address: SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x48
31 24 16 8 0
| | | | |
[-------------------------------o]
'-- [0] (r-) register18_SCFG_wave511_vpu_idle
Register: syscon_sysmain_ctrl_register19_REG_ADDR
Address: SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x4c
31 24 16 8 0
| | | | |
[-------------------------------o]
'-- [0] (r-) register19_SCFG_wave521_vpu_idle
Register: syscon_sysmain_ctrl_register20_REG_ADDR
Address: SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x50
31 24 16 8 0
| | | | |
[-------------------------------o]
'-- [0] (rw) register20_u0_syscon_162_SCFG_gc300_csys_req
Register: syscon_sysmain_ctrl_register21_REG_ADDR
Address: SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x54
31 24 16 8 0
| | | | |
[------------------------------oo]
|'-- [0] (r-) register21_u0_syscon_162_SCFG_gc300_cactive
'--- [1] (r-) register21_u0_syscon_162_SCFG_gc300_csys_ack
Register: syscon_sysmain_ctrl_register22_REG_ADDR
Address: SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x58
31 24 16 8 0
| | | | |
[------------------------<======>]
'-- [7:0] (r-) register22_u0_syscon_162_SCFG_gc300_debug_out
Register: syscon_sysmain_ctrl_register23_REG_ADDR
Address: SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x5c
31 24 16 8 0
| | | | |
[------------------------------oo]
|'-- [0] (rw) register23_SCFG_cmsensor_rst0
'--- [1] (rw) register23_SCFG_cmsensor_rst1
Register: syscon_sysmain_ctrl_qspi_REG_ADDR
Address: SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x60
31 24 16 8 0
| | | | |
[------------------------<======>]
'-- [7:0] (rw) qspi_SCFG_sram_config
Register: syscon_sysmain_ctrl_intmem_REG_ADDR
Address: SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x64
31 24 16 8 0
| | | | |
[----------------<======><======>]
| '-- [7:0] (rw) intmem_SCFG_sram_config
'---------- [15:8] (rw) intmem_SCFG_sram_config_rom
Register: syscon_sysmain_ctrl_register26_REG_ADDR
Address: SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x68
31 24 16 8 0
| | | | |
[<==============================>]
'-- [31:0] (rw) register26_SCFG_dma1p2p_sel
Register: syscon_sysmain_ctrl_register27_REG_ADDR
Address: SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x6c
31 24 16 8 0
| | | | |
[<==============================>]
'-- [31:0] (rw) register27_SCFG_dmaezMst_sel
Register: syscon_sysmain_ctrl_register28_REG_ADDR
Address: SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x70
31 24 16 8 0
| | | | |
[--------------------<======>-<=>]
| '-- [2:0] (rw) register28_SCFG_gmac_phy_intf_sel
'------ [11:4] (rw) register28_gmac_SCFG_sram_cfg
Register: syscon_sysmain_ctrl_register29_REG_ADDR
Address: SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x74
31 24 16 8 0
| | | | |
[----------------------------oo<>]
|| '-- [1:0] (r-) register29_gmac_speed
|'---- [2] (r-) register29_gmac_ptp_pps
'----- [3] (r-) register29_gmac_tx_ckg_ctrl
Register: syscon_sysmain_ctrl_SCFG_gmac_timestamp0_REG_ADDR
Address: SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x78
31 24 16 8 0
| | | | |
[<==============================>]
'-- [31:0] (r-) SCFG_gmac_timestamp0_ptp
Register: syscon_sysmain_ctrl_SCFG_gmac_timestamp1_REG_ADDR
Address: SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x7c
31 24 16 8 0
| | | | |
[<==============================>]
'-- [31:0] (r-) SCFG_gmac_timestamp1_ptp
Register: syscon_sysmain_ctrl_register32_REG_ADDR
Address: SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x80
31 24 16 8 0
| | | | |
[-------------------------------o]
'-- [0] (rw) register32_SCFG_gmac_phy_rstn
Register: syscon_sysmain_ctrl_register33_REG_ADDR
Address: SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x84
31 24 16 8 0
| | | | |
[----------------------<======>oo]
||'-- [0] (rw) register33_SCFG_sdio0_hbig_endian
|'--- [1] (rw) register33_SCFG_sdio0_m_hbig_endian
'---- [9:2] (rw) register33_sdio0_SCFG_sram_config
Register: syscon_sysmain_ctrl_register34_REG_ADDR
Address: SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x88
31 24 16 8 0
| | | | |
[----------------------<======>oo]
||'-- [0] (rw) register34_SCFG_sdio1_hbig_endian
|'--- [1] (rw) register34_SCFG_sdio1_m_hbig_endian
'---- [9:2] (rw) register34_sdio1_SCFG_sram_config
Register: syscon_sysmain_ctrl_register35_REG_ADDR
Address: SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x8c
31 24 16 8 0
| | | | |
[------------------------------<>]
'-- [1:0] (rw) register35_SCFG_spi2ahb_mode
Register: syscon_sysmain_ctrl_register36_REG_ADDR
Address: SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x90
31 24 16 8 0
| | | | |
[-------------------------------o]
'-- [0] (r-) register36_spi2ahb_sleep
Register: syscon_sysmain_ctrl_register37_REG_ADDR
Address: SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x94
31 24 16 8 0
| | | | |
[------------------------<======>]
'-- [7:0] (rw) register37_ezmst_SCFG_sram_config
Register: syscon_sysmain_ctrl_register38_REG_ADDR
Address: SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x98
31 24 16 8 0
| | | | |
[------------------------<======>]
'-- [7:0] (rw) register38_sec_SCFG_sram_cfg
Register: syscon_sysmain_ctrl_register39_REG_ADDR
Address: SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x9c
31 24 16 8 0
| | | | |
[----------------<======><======>]
| '-- [7:0] (rw) register39_uart0_SCFG_sram_config
'---------- [15:8] (rw) register39_uart1_SCFG_sram_config
Register: syscon_sysmain_ctrl_register40_REG_ADDR
Address: SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0xa0
31 24 16 8 0
| | | | |
[------------------------------oo]
|'-- [0] (r-) register40_trng_secure_mode
'--- [1] (r-) register40_trng_nonce_mode
Register: syscon_sysmain_ctrl_SCFG_intC1_7to0_REG_ADDR
Address: SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0xa4
31 24 16 8 0
| | | | |
[------------------------<======>]
'-- [7:0] (rw) SCFG_intC1_7to0_int_src1
Register: syscon_sysmain_ctrl_SCFG_intC0_src15to8_REG_ADDR
Address: SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0xa8
31 24 16 8 0
| | | | |
[------------------------<======>]
'-- [7:0] (rw) SCFG_intC0_src15to8_int_src1
Register: syscon_sysmain_ctrl_SCFG_intC0_src23to16_REG_ADDR
Address: SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0xac
31 24 16 8 0
| | | | |
[------------------------<======>]
'-- [7:0] (rw) SCFG_intC0_src23to16_int_src1
Register: syscon_sysmain_ctrl_SCFG_intC0_src31to24_REG_ADDR
Address: SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0xb0
31 24 16 8 0
| | | | |
[------------------------<======>]
'-- [7:0] (rw) SCFG_intC0_src31to24_int_src1
Register: syscon_sysmain_ctrl_register47_REG_ADDR
Address: SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0xbc
31 24 16 8 0
| | | | |
[<==============================>]
'-- [31:0] (rw) register47_e24_reset_vector
Register: syscon_sysmain_ctrl_register48_REG_ADDR
Address: SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0xc0
31 24 16 8 0
| | | | |
[<==============================>]
'-- [31:0] (rw) register48_SCFG_qspi_sclk_dlychain_sel
Register: syscon_sysmain_ctrl_register52_REG_ADDR
Address: SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0xc4
31 24 16 8 0
| | | | |
[<==============================>]
'-- [31:0] (rw) register52_SCFG_gmac_rxclk_dlychain_sel
Register: syscon_sysmain_ctrl_register49_REG_ADDR
Address: SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0xc8
31 24 16 8 0
| | | | |
[<==============================>]
'-- [31:0] (rw) register49_SCFG_gmac_gtxclk_dlychain_sel
Register: syscon_sysmain_ctrl_register50_REG_ADDR
Address: SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0xcc
31 24 16 8 0
| | | | |
[<==============================>]
'-- [31:0] (rw) register50_SCFG_sdio0_cclk_dlychain_sel
Register: syscon_sysmain_ctrl_register51_REG_ADDR
Address: SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0xd0
31 24 16 8 0
| | | | |
[<==============================>]
'-- [31:0] (rw) register51_SCFG_sdio1_cclk_dlychain_sel
Register: syscon_sysmain_ctrl_register66_REG_ADDR
Address: SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0xd8
31 24 16 8 0
| | | | |
[----------------<==><==><======>]
| | '-- [7:0] (rw) register66_SCFG_axi_cache_sel
| '---------- [11:8] (rw) register66_SCFG_default_arcache
'-------------- [15:12] (rw) register66_SCFG_default_awcache
Register: syscon_sysmain_ctrl_register53_REG_ADDR
Address: SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0xdc
31 24 16 8 0
| | | | |
[----------------<==><==><======>]
| | '-- [7:0] (rw) register53_SCFG_axi_cache_sel
| '---------- [11:8] (rw) register53_SCFG_default_arcache
'-------------- [15:12] (rw) register53_SCFG_default_awcache
Register: syscon_sysmain_ctrl_register54_REG_ADDR
Address: SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0xe0
31 24 16 8 0
| | | | |
[----------------<==><==><======>]
| | '-- [7:0] (rw) register54_SCFG_axi_cache_sel
| '---------- [11:8] (rw) register54_SCFG_default_arcache
'-------------- [15:12] (rw) register54_SCFG_default_awcache
Register: syscon_sysmain_ctrl_register55_REG_ADDR
Address: SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0xe4
31 24 16 8 0
| | | | |
[----------------<==><==><======>]
| | '-- [7:0] (rw) register55_SCFG_axi_cache_sel
| '---------- [11:8] (rw) register55_SCFG_default_arcache
'-------------- [15:12] (rw) register55_SCFG_default_awcache
Register: syscon_sysmain_ctrl_register56_REG_ADDR
Address: SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0xe8
31 24 16 8 0
| | | | |
[----------------<==><==><======>]
| | '-- [7:0] (rw) register56_SCFG_axi_cache_sel
| '---------- [11:8] (rw) register56_SCFG_default_arcache
'-------------- [15:12] (rw) register56_SCFG_default_awcache
Register: syscon_sysmain_ctrl_register57_REG_ADDR
Address: SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0xec
31 24 16 8 0
| | | | |
[----------------<==><==><======>]
| | '-- [7:0] (rw) register57_SCFG_axi_cache_sel
| '---------- [11:8] (rw) register57_SCFG_default_arcache
'-------------- [15:12] (rw) register57_SCFG_default_awcache
Register: syscon_sysmain_ctrl_register58_REG_ADDR
Address: SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0xf0
31 24 16 8 0
| | | | |
[----------------<==><==><======>]
| | '-- [7:0] (rw) register58_SCFG_axi_cache_sel
| '---------- [11:8] (rw) register58_SCFG_default_arcache
'-------------- [15:12] (rw) register58_SCFG_default_awcache
Register: syscon_sysmain_ctrl_register59_REG_ADDR
Address: SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0xf4
31 24 16 8 0
| | | | |
[----------------<==><==><======>]
| | '-- [7:0] (rw) register59_SCFG_axi_cache_sel
| '---------- [11:8] (rw) register59_SCFG_default_arcache
'-------------- [15:12] (rw) register59_SCFG_default_awcache
Register: syscon_sysmain_ctrl_register60_REG_ADDR
Address: SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0xf8
31 24 16 8 0
| | | | |
[----------------<==><==><======>]
| | '-- [7:0] (rw) register60_SCFG_axi_cache_sel
| '---------- [11:8] (rw) register60_SCFG_default_arcache
'-------------- [15:12] (rw) register60_SCFG_default_awcache
Register: syscon_sysmain_ctrl_register61_REG_ADDR
Address: SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0xfc
31 24 16 8 0
| | | | |
[----------------<==><==><======>]
| | '-- [7:0] (rw) register61_SCFG_axi_cache_sel
| '---------- [11:8] (rw) register61_SCFG_default_arcache
'-------------- [15:12] (rw) register61_SCFG_default_awcache
Register: syscon_sysmain_ctrl_register62_REG_ADDR
Address: SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x100
31 24 16 8 0
| | | | |
[----------------<==><==><======>]
| | '-- [7:0] (rw) register62_SCFG_axi_cache_sel
| '---------- [11:8] (rw) register62_SCFG_default_arcache
'-------------- [15:12] (rw) register62_SCFG_default_awcache
Register: syscon_sysmain_ctrl_register63_REG_ADDR
Address: SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x104
31 24 16 8 0
| | | | |
[----------------<==><==><======>]
| | '-- [7:0] (rw) register63_SCFG_axi_cache_sel
| '---------- [11:8] (rw) register63_SCFG_default_arcache
'-------------- [15:12] (rw) register63_SCFG_default_awcache
Register: syscon_sysmain_ctrl_register64_REG_ADDR
Address: SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x108
31 24 16 8 0
| | | | |
[----------------<==><==><======>]
| | '-- [7:0] (rw) register64_SCFG_axi_cache_sel
| '---------- [11:8] (rw) register64_SCFG_default_arcache
'-------------- [15:12] (rw) register64_SCFG_default_awcache
Register: syscon_sysmain_ctrl_register65_REG_ADDR
Address: SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x10c
31 24 16 8 0
| | | | |
[----------------<==><==><======>]
| | '-- [7:0] (rw) register65_SCFG_axi_cache_sel
| '---------- [11:8] (rw) register65_SCFG_default_arcache
'-------------- [15:12] (rw) register65_SCFG_default_awcache
Register: syscon_sysmain_ctrl_register68_REG_ADDR
Address: SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x110
31 24 16 8 0
| | | | |
[-------------------------------o]
'-- [0] (rw) register68_SCFG_disable_u74_memaxi_remap
Register: syscon_sysmain_ctrl_register67_REG_ADDR
Address: SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x114
31 24 16 8 0
| | | | |
[----------------<==><==><======>]
| | '-- [7:0] (rw) register67_SCFG_axi_cache_sel
| '---------- [11:8] (rw) register67_SCFG_default_arcache
'-------------- [15:12] (rw) register67_SCFG_default_awcache
Register: syscon_sysmain_ctrl_register69_REG_ADDR
Address: SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x118
31 24 16 8 0
| | | | |
[-------------------------------o]
'-- [0] (rw) register69_core1_en
Register: syscon_sysmain_ctrl_register70_REG_ADDR
Address: SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x11c
31 24 16 8 0
| | | | |
[------------------------------oo]
|'-- [0] (rw) register70_SCFG_boot_mode
'--- [1] (r-) register70_SCFG_u74_IOPAD_bootmode
Register: syscon_sysmain_ctrl_register71_REG_ADDR
Address: SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x120
31 24 16 8 0
| | | | |
[<==============================>]
'-- [31:0] (rw) register71_SCFG_u74_reset_vector
Register: syscon_sysmain_ctrl_register72_REG_ADDR
Address: SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x124
31 24 16 8 0
| | | | |
[-----------------------------<=>]
'-- [2:0] (r-) register72_u74_boot_device_sel
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