qemu-aia.dts

// QEMU emulator version 7.2.0
// qemu-system-riscv64 -M virt,aia=aplic-imsic,aia-guests=2,aclint=true,dumpdtb=dtb.dtb -smp 2

#include <dt-bindings/interrupt-controller/irq.h>

/dts-v1/;

/ {
	compatible = "riscv-virtio";
	model = "riscv-virtio,qemu";

	#address-cells = <2>;
	#size-cells = <2>;

	chosen {
		// rng-seed is likely to be different, of course
		rng-seed = <0x52cfbb98 0xa3e4d9bc 0x23396eb0 0xae0fb378 0xc982844c 0xba361a25 0xbc83ab1b 0x1bfa9e53>;
		stdout-path = &serial0;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		timebase-frequency = <10000000>;

		cpu0: cpu@0 {
			phandle = <3>;
			compatible = "riscv";
			device_type = "cpu";
			reg = <0>;
			riscv,isa = "rv64imafdch_zicsr_zifencei_zihintpause_zba_zbb_zbc_zbs_smaia_ssaia_sstc";
			mmu-type = "riscv,sv48";
			status = "okay";

			cpu0_intc: interrupt-controller {
				phandle = <4>;
				compatible = "riscv,cpu-intc";
				interrupt-controller;
				#interrupt-cells = <1>;
			};
		};

		cpu1: cpu@1 {
			phandle = <1>;
			compatible = "riscv";
			device_type = "cpu";
			reg = <1>;
			riscv,isa = "rv64imafdch_zicsr_zifencei_zihintpause_zba_zbb_zbc_zbs_smaia_ssaia_sstc";
			mmu-type = "riscv,sv48";
			status = "okay";

			cpu1_intc: interrupt-controller {
				phandle = <2>;
				compatible = "riscv,cpu-intc";
				interrupt-controller;
				#interrupt-cells = <1>;
			};
		};

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&cpu0>;
				};

				core1 {
					cpu = <&cpu1>;
				};
			};
		};
	};

	flash@20000000 {
		compatible = "cfi-flash";
		reg =
			<0x0 0x20000000 0x0 0x02000000>,
			<0x0 0x22000000 0x0 0x02000000>;
		bank-width = <4>;
	};

	fw-cfg@10100000 {
		compatible = "qemu,fw-cfg-mmio";
		reg = <0x0 0x10100000 0x0 0x18>;
		dma-coherent;
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0x0 0x80000000 0x0 0x08000000>;
	};

	platform-bus@4000000 {
		compatible = "qemu,platform", "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		interrupt-parent = <&aplic_s>;
		ranges = <0x00000000 0x0 0x04000000 0x02000000>;
	};

	poweroff {
		compatible = "syscon-poweroff";
		regmap = <&test>;
		offset = <0x0>;
		value = <0x5555>;
	};

	reboot {
		compatible = "syscon-reboot";
		regmap = <&test>;
		offset = <0x0>;
		value = <0x7777>;
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		pmu {
			compatible = "riscv,pmu";
			riscv,event-to-mhpmcounters =
				<0x00001 0x00001 0x7fff9>,
				<0x00002 0x00002 0x7fffc>,
				<0x10019 0x10019 0x7fff8>,
				<0x1001b 0x1001b 0x7fff8>,
				<0x10021 0x10021 0x7fff8>,
				<0x00000 0x00000 0x0>,
				<0x0 0x0>; // ???
		};

		mtimer@2000000 {
			compatible = "riscv,aclint-mtimer";
			interrupts-extended = <&cpu0_intc 7>, <&cpu1_intc 7>;
			reg = <0x0 0x02007ff8 0x0 0x8>, <0x0 0x02000000 0x0 0x7ff8>;
		};

		rtc@101000 {
			compatible = "google,goldfish-rtc";
			reg = <0x0 0x00101000 0x0 0x1000>;
			interrupt-parent = <&aplic_s>;
			interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
		};

		serial0: serial@10000000 {
			compatible = "ns16550a";
			reg = <0x0 0x10000000 0x0 0x100>;
			interrupt-parent = <&aplic_s>;
			interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
			clock-frequency = <3686400>;
		};

		test: test@100000 {
			phandle = <9>;
			compatible = "sifive,test1", "sifive,test0", "syscon";
			reg = <0x0 0x00100000 0x0 0x1000>;
		};

		aplic@c000000 {
			phandle = <7>;
			compatible = "riscv,aplic";
			reg = <0x0 0x0c000000 0x0 0x8000>;

			interrupt-controller;
			#interrupt-cells = <2>;

			msi-parent = <&imsics_m>;

			riscv,children = <&aplic_s>;
			riscv,delegate = <&aplic_s 1 96>;
			riscv,num-sources = <96>;
		};

		aplic_s: aplic@d000000 {
			phandle = <8>;
			compatible = "riscv,aplic";
			reg = <0x0 0x0d000000 0x0 0x8000>;

			interrupt-controller;
			#interrupt-cells = <2>;

			msi-parent = <&imsics_s>;

			riscv,num-sources = <96>;
		};

		imsics_m: imsics@24000000 {
			phandle = <5>;
			compatible = "riscv,imsics";
			reg = <0x00 0x24000000 0x00 0x2000>;

			interrupt-controller;
			#interrupt-cells = <0>;

			interrupts-extended = <&cpu0_intc 11>, <&cpu1_intc 11>;

			msi-controller;

			riscv,ipi-id = <1>;
			riscv,num-ids = <255>;
		};

		imsics_s: imsics@28000000 {
			phandle = <6>;
			compatible = "riscv,imsics";
			reg = <0x0 0x28000000 0x0 0x8000>;

			interrupt-controller;
			#interrupt-cells = <0>;

			interrupts-extended = <&cpu0_intc 9>, <&cpu1_intc 9>;

			msi-controller;

			riscv,guest-index-bits = <2>;
			riscv,ipi-id = <1>;
			riscv,num-ids = <255>;
		};

		pci@30000000 {
			device_type = "pci";
			compatible = "pci-host-ecam-generic";
			reg = <0x0 0x30000000 0x0 0x10000000>;
			#address-cells = <3>;
			#size-cells = <2>;
			#interrupt-cells = <1>;

			bus-range = <0x0 0xff>;
			linux,pci-domain = <0>;
			dma-coherent;

			msi-parent = <&imsics_s>;

			ranges =
				<0x01000000 0x0 0x00000000  0x0 0x03000000  0x0 0x00010000>,
				<0x02000000 0x0 0x40000000  0x0 0x40000000  0x0 0x40000000>,
				<0x03000000 0x4 0x00000000  0x4 0x00000000  0x4 0x00000000>;

			interrupt-map =
				<0x0000 0x0 0x0  0x1  &aplic_s 32 IRQ_TYPE_LEVEL_HIGH>,
				<0x0000 0x0 0x0  0x2  &aplic_s 33 IRQ_TYPE_LEVEL_HIGH>,
				<0x0000 0x0 0x0  0x3  &aplic_s 34 IRQ_TYPE_LEVEL_HIGH>,
				<0x0000 0x0 0x0  0x4  &aplic_s 35 IRQ_TYPE_LEVEL_HIGH>,
				<0x0800 0x0 0x0  0x1  &aplic_s 33 IRQ_TYPE_LEVEL_HIGH>,
				<0x0800 0x0 0x0  0x2  &aplic_s 34 IRQ_TYPE_LEVEL_HIGH>,
				<0x0800 0x0 0x0  0x3  &aplic_s 35 IRQ_TYPE_LEVEL_HIGH>,
				<0x0800 0x0 0x0  0x4  &aplic_s 32 IRQ_TYPE_LEVEL_HIGH>,
				<0x1000 0x0 0x0  0x1  &aplic_s 34 IRQ_TYPE_LEVEL_HIGH>,
				<0x1000 0x0 0x0  0x2  &aplic_s 35 IRQ_TYPE_LEVEL_HIGH>,
				<0x1000 0x0 0x0  0x3  &aplic_s 32 IRQ_TYPE_LEVEL_HIGH>,
				<0x1000 0x0 0x0  0x4  &aplic_s 33 IRQ_TYPE_LEVEL_HIGH>,
				<0x1800 0x0 0x0  0x1  &aplic_s 35 IRQ_TYPE_LEVEL_HIGH>,
				<0x1800 0x0 0x0  0x2  &aplic_s 32 IRQ_TYPE_LEVEL_HIGH>,
				<0x1800 0x0 0x0  0x3  &aplic_s 33 IRQ_TYPE_LEVEL_HIGH>,
				<0x1800 0x0 0x0  0x4  &aplic_s 34 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-map-mask =
				<0x1800 0x0 0x0  0x7>;
		};

		virtio_mmio@10001000 {
			compatible = "virtio,mmio";
			reg = <0x0 0x10001000 0x0 0x1000>;
			interrupt-parent = <&aplic_s>;
			interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
		};

		virtio_mmio@10002000 {
			compatible = "virtio,mmio";
			reg = <0x0 0x10002000 0x0 0x1000>;
			interrupt-parent = <&aplic_s>;
			interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
		};

		virtio_mmio@10003000 {
			compatible = "virtio,mmio";
			reg = <0x0 0x10003000 0x0 0x1000>;
			interrupt-parent = <&aplic_s>;
			interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
		};

		virtio_mmio@10004000 {
			compatible = "virtio,mmio";
			reg = <0x0 0x10004000 0x0 0x1000>;
			interrupt-parent = <&aplic_s>;
			interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
		};

		virtio_mmio@10005000 {
			compatible = "virtio,mmio";
			reg = <0x0 0x10005000 0x0 0x1000>;
			interrupt-parent = <&aplic_s>;
			interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
		};

		virtio_mmio@10006000 {
			compatible = "virtio,mmio";
			reg = <0x0 0x10006000 0x0 0x1000>;
			interrupt-parent = <&aplic_s>;
			interrupts = <6 IRQ_TYPE_LEVEL_HIGH>;
		};

		virtio_mmio@10007000 {
			compatible = "virtio,mmio";
			reg = <0x0 0x10007000 0x0 0x1000>;
			interrupt-parent = <&aplic_s>;
			interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
		};

		virtio_mmio@10008000 {
			compatible = "virtio,mmio";
			reg = <0x0 0x10008000 0x0 0x1000>;
			interrupt-parent = <&aplic_s>;
			interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
		};
	};
};