gcd.test

.power Vdd=1
.thresholds Vol=0 Vil=0.1 Vih=0.9 Voh=1

.group inputs RESET START A[31:0] B[31:0]
.group outputs S[31:0] 


.mode gate
.cycle CLK=1 tran 5n assert inputs tran 45n CLK=0 tran 49n sample outputs tran 1n

1 1 00000000000000000000000000001100 00000000000000000000000000001000 -------------------------------- 
1 1 00000000000000000000000000001100 00000000000000000000000000001000 --------------------------------
0 1 00000000000000000000000000001100 00000000000000000000000000001000 -------------------------------- 
0 1 00000000000000000000000000001100 00000000000000000000000000001000 -------------------------------- 
0 0 00000000000000000000000000001100 00000000000000000000000000001000 -------------------------------- 
0 0 00000000000000000000000000001100 00000000000000000000000000001000 -------------------------------- 
0 0 00000000000000000000000000001100 00000000000000000000000000001000 -------------------------------- 
0 0 00000000000000000000000000001100 00000000000000000000000000001000 -------------------------------- 
0 0 00000000000000000000000000001100 00000000000000000000000000001000 -------------------------------- 
0 0 00000000000000000000000000001100 00000000000000000000000000001000 -------------------------------- 
0 0 00000000000000000000000000001100 00000000000000000000000000001000 -------------------------------- 
0 0 00000000000000000000000000001100 00000000000000000000000000001000 -------------------------------- 
0 0 00000000000000000000000000001100 00000000000000000000000000001000 -------------------------------- 
0 0 00000000000000000000000000001100 00000000000000000000000000001000 -------------------------------- 
0 0 00000000000000000000000000001100 00000000000000000000000000001000 -------------------------------- 
0 0 00000000000000000000000000001100 00000000000000000000000000001000 -------------------------------- 
0 0 00000000000000000000000000001100 00000000000000000000000000001000 -------------------------------- 
0 0 00000000000000000000000000001100 00000000000000000000000000001000 -------------------------------- 
0 0 00000000000000000000000000001100 00000000000000000000000000001000 -------------------------------- 



.plot CLK
.plot RESET
.plot START
.plot FN
.plot Z
.plot N
.plot ASEL
.plot ALE
.plot BSEL
.plot BLE
.plot BUSY
.plot B(STATE[2:0])
.plot B(NEXT_STATE[2:0])
.plot B(ROM_IN[5:0])
.plot D(A[31:0])    // D is for Decimal
.plot D(B[31:0])
.plot X(REGA[31:0])
.plot X(REGB[31:0])
.plot X(S[31:0])

updates test to hold START=1 for another cycle

"START to 1 until the BUSY output becomes 1"