drom

TOP
core_clk
tb_top
ifu_axi_arvalid
ifu_axi_arready
ifu_axi_araddr
ifu_axi_arlen
ifu_axi_arsize
ifu_axi_arburst
ifu_axi_arid

drom

$date
	Thu Jul 22 22:29:56 2021
$end
$version
	Icarus Verilog
$end
$timescale
	1ps
$end
$scope module friscv_rv32i_testbench $end

drom

; seed: 528570
circuit top_mod :
  module mod_0 :
    input clock: Clock
    input reset: UInt<1>
    input arst: AsyncReset
    input inp_a: {inp_b: {inp_c: {inp_j: SInt<117>, inp_k: {inp_ek: UInt<88>}, inp_fd: SInt<88>, inp_de: UInt<123>}, inp_f: {inp_cc: UInt<119>, inp_ce: UInt<43>}[4][1][3], inp_l: {inp_eb: {inp_fb: {inp_hd: {inp_md: {inp_ol: SInt<190>[3][4][5]}, inp_ge: {inp_bf: UInt<82>, inp_mh: {inp_ji: {inp_dj: UInt<117>}}, inp_hl: SInt<33>}[5][2], inp_mi: UInt<188>}, inp_gf: {inp_hh: UInt<16>}}, inp_lc: {inp_if: {inp_hg: {inp_og: {inp_lh: {inp_dk: UInt<127>[5][3][3]}}}}}, inp_bd: {inp_pf: {inp_hi: {inp_fl: UInt<70>}}}, inp_ei: UInt<136>}, inp_dd: SInt<196>, inp_am: {inp_cm: UInt<105>}}, inp_gb: {inp_hb: {inp_jb: {inp_ke: {inp_jg: UInt<214>}}, inp_mc: {inp_he: {inp_bg: {inp_ij: SInt<243>[2][1]}}, inp_jh: {inp_nj: UInt<211>[5], inp_em: UInt<148>[1][2][4]}[2], inp_pi: UInt<155>[3]}, inp_jd: {inp_gk: {inp_hk: UInt<88>}, inp_el: SInt<73>}, inp_nd: {inp_pe: {inp_ih: UInt<23>, inp_ph: {inp_gl: SInt<86>, inp

drom

#!/usr/bin/env node
'use strict';

const fs = require('fs');
const glob = require('glob');

const tag = {
  key: '\u001b[36m',
  boolean: '\u001b[33m',
  number: '\u001b[35m',

drom

drom

• https://wiki.analog.com/resources/tools-software/linux-software/libiio/iio_info
• https://wiki.analog.com/resources/tools-software/linux-software/libiio/iio_attr
• https://wiki.analog.com/university/tools/pluto/users/customizing

drom

Tests

Timing Diagram

{ signal: [
  { name: "clk",         wave: "p.....|..." },
  { name: "Data",        wave: "x.345x|=.x", data: ["head", "body", "tail", "data"] },
  { name: "Request",     wave: "0.1..0|1.0" },
 {},

drom

drom

drom