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September 7, 2017 21:54
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<?xml version="1.0" encoding="utf-8"?> | |
<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd" > | |
<vendor>SiFive</vendor> | |
<name>FE310</name> | |
<addressUnitBits>8</addressUnitBits> | |
<width>32</width> | |
<size>32</size> | |
<access>read-write</access> | |
<resetValue>0x00000000</resetValue> | |
<resetMask>0xFFFFFFFF</resetMask> | |
<peripherals> | |
<!-- CLINT --> | |
<peripheral> | |
<name>CLINT</name> | |
<baseAddress>0x02000000</baseAddress> | |
<groupName>CLINT</groupName> | |
<description>Coreplex Local Interrupts</description> | |
<registers> | |
<register> | |
<name>msip</name> | |
<description>Hart 0 software interrupt register</description> | |
<addressOffset>0x0000</addressOffset> | |
<fields> | |
<field><name>value</name><msb>0</msb><lsb>0</lsb></field> | |
</fields> | |
</register> | |
<register> | |
<name>mtimecmplo</name> | |
<description>Hart 0 time comparator register</description> | |
<addressOffset>0x4000</addressOffset> | |
</register> | |
<register> | |
<name>mtimecmphi</name> | |
<description>Hart 0 time comparator register</description> | |
<addressOffset>0x4004</addressOffset> | |
</register> | |
<register> | |
<name>mtimelo</name> | |
<description>Timer register</description> | |
<addressOffset>0xBFF8</addressOffset> | |
</register> | |
<register> | |
<name>mtimehi</name> | |
<description>Timer register</description> | |
<addressOffset>0xBFFC</addressOffset> | |
</register> | |
</registers> | |
</peripheral> | |
<!-- CLINT --> | |
<!-- PLIC --> | |
<peripheral> | |
<name>PLIC</name> | |
<baseAddress>0x0C000000</baseAddress> | |
<groupName>PLIC</groupName> | |
<description>Platform Level Interrupt Control</description> | |
<registers> | |
<!-- TODO: source priority 2-255 --> | |
<register> | |
<name>priority1</name> | |
<description>Interrupt Priority Register</description> | |
<addressOffset>0x000004</addressOffset> | |
<enumeratedValues> | |
<name>InterruptPriority</name> | |
<enumerateValue> | |
<name>Never</name><value>0</value> | |
</enumerateValue> | |
<enumerateValue> | |
<name>P1</name><value>1</value> | |
</enumerateValue> | |
<enumerateValue> | |
<name>P2</name><value>2</value> | |
</enumerateValue> | |
<enumerateValue> | |
<name>P3</name><value>3</value> | |
</enumerateValue> | |
<enumerateValue> | |
<name>P4</name><value>4</value> | |
</enumerateValue> | |
<enumerateValue> | |
<name>P5</name><value>5</value> | |
</enumerateValue> | |
<enumerateValue> | |
<name>P6</name><value>6</value> | |
</enumerateValue> | |
<enumerateValue> | |
<name>P7</name><value>7</value> | |
</enumerateValue> | |
</enumeratedValues> | |
</register> | |
<!-- TODO --> | |
<register> | |
<name>pending0to31</name> | |
<description>Interrupt Pending Register</description> | |
<addressOffset>0x001000</addressOffset> | |
</register> | |
<!-- TODO --> | |
<register> | |
<name>enable0to31</name> | |
<description>Interrupt Enable Register</description> | |
<addressOffset>0x002000</addressOffset> | |
</register> | |
<register> | |
<name>threshold</name> | |
<description>Priority Threshold Register</description> | |
<addressOffset>0x200000</addressOffset> | |
<enumeratedValues> | |
<name>InterruptPriority</name> | |
<enumerateValue> | |
<name>Never</name><value>0</value> | |
</enumerateValue> | |
<enumerateValue> | |
<name>P1</name><value>1</value> | |
</enumerateValue> | |
<enumerateValue> | |
<name>P2</name><value>2</value> | |
</enumerateValue> | |
<enumerateValue> | |
<name>P3</name><value>3</value> | |
</enumerateValue> | |
<enumerateValue> | |
<name>P4</name><value>4</value> | |
</enumerateValue> | |
<enumerateValue> | |
<name>P5</name><value>5</value> | |
</enumerateValue> | |
<enumerateValue> | |
<name>P6</name><value>6</value> | |
</enumerateValue> | |
<enumerateValue> | |
<name>P7</name><value>7</value> | |
</enumerateValue> | |
</enumeratedValues> | |
</register> | |
<register> | |
<name>claim</name> | |
<description>Claim/Complete Register</description> | |
<addressOffset>0x200004</addressOffset> | |
</register> | |
</registers> | |
</peripheral> | |
<!-- PLIC --> | |
<!-- AON --> | |
<peripheral> | |
<name>AON</name> | |
<baseAddress>0x10000000</baseAddress> | |
<groupName>AON</groupName> | |
<description>Always On</description> | |
<registers> | |
<!-- Watchdog Registers --> | |
<register> | |
<name>wdogcfg</name> | |
<description>Watchdog Configuration Register</description> | |
<addressOffset>0x000</addressOffset> | |
<fields> | |
<field><name>cmpip</name><msb>28</msb><lsb>28</lsb></field> | |
<field><name>encoreawake</name><msb>13</msb><lsb>13</lsb></field> | |
<field><name>enalways</name><msb>12</msb><lsb>12</lsb></field> | |
<field><name>zerocmp</name><msb>9</msb><lsb>9</lsb></field> | |
<field><name>rsten</name><msb>8</msb><lsb>8</lsb></field> | |
<field><name>scale</name><msb>3</msb><lsb>0</lsb></field> | |
</fields> | |
</register> | |
<register> | |
<name>wdogcount</name> | |
<description>Watchdog Counter Register</description> | |
<addressOffset>0x008</addressOffset> | |
</register> | |
<register> | |
<name>wdogs</name> | |
<description>Watchdog Scaled Counter Register</description> | |
<addressOffset>0x010</addressOffset> | |
</register> | |
<register> | |
<name>wdogfeed</name> | |
<description>Watchdog Feed Register</description> | |
<addressOffset>0x018</addressOffset> | |
</register> | |
<register> | |
<name>wdogkey</name> | |
<description>Watchdog Key Register</description> | |
<addressOffset>0x01C</addressOffset> | |
<access>write-only</access> | |
<resetValue>0x51F15E</resetValue> | |
</register> | |
<register> | |
<name>wdogcmp</name> | |
<description>Watchdog Compare Register</description> | |
<addressOffset>0x020</addressOffset> | |
<fields> | |
<field><name>value</name><msb>15</msb><lsb>0</lsb></field> | |
</fields> | |
</register> | |
<!-- Watchdog Registers --> | |
<!-- Real Time Clock Registers --> | |
<register> | |
<name>rtccfg</name> | |
<description>RTC Configuration Register</description> | |
<addressOffset>0x040</addressOffset> | |
<fields> | |
<field><name>cmpip</name><msb>28</msb><lsb>28</lsb></field> | |
<field><name>enalways</name><msb>12</msb><lsb>12</lsb></field> | |
<field><name>scale</name><msb>3</msb><lsb>0</lsb></field> | |
</fields> | |
</register> | |
<register> | |
<name>rtclo</name> | |
<description>RTC Counter Low Register</description> | |
<addressOffset>0x048</addressOffset> | |
</register> | |
<register> | |
<name>rtchi</name> | |
<description>RTC Counter High Register</description> | |
<addressOffset>0x04C</addressOffset> | |
<fields> | |
<field><name>value</name><msb>15</msb><lsb>0</lsb></field> | |
</fields> | |
</register> | |
<register> | |
<name>rtcs</name> | |
<description>RTC Scaled Counter Register</description> | |
<addressOffset>0x050</addressOffset> | |
</register> | |
<register> | |
<name>rtccmp</name> | |
<description>RTC Compare Register</description> | |
<addressOffset>0x060</addressOffset> | |
</register> | |
<!-- Real Time Clock Registers --> | |
<!-- Always On Clock Configuration Registers --> | |
<register> | |
<name>lfrosccfg</name> | |
<description>AON Clock Configuration Register</description> | |
<addressOffset>0x070</addressOffset> | |
<fields> | |
<field><name>ready</name><msb>31</msb><lsb>31</lsb></field> | |
<field><name>enable</name><msb>30</msb><lsb>30</lsb></field> | |
<field><name>div</name><msb>5</msb><lsb>0</lsb></field> | |
</fields> | |
</register> | |
<register> | |
<name>lfxosccfg</name> | |
<description>AON Clock Configuration Register</description> | |
<addressOffset>0x074</addressOffset> | |
<fields> | |
<field><name>ready</name><msb>31</msb><lsb>31</lsb></field> | |
<field><name>enable</name><msb>30</msb><lsb>30</lsb></field> | |
</fields> | |
</register> | |
<!-- Always On Clock Configuration Registers --> | |
<!-- Backup Registers --> | |
<register> | |
<name>backup0</name> | |
<description>Backup Register</description> | |
<addressOffset>0x080</addressOffset> | |
</register> | |
<register> | |
<name>backup1</name> | |
<description>Backup Register</description> | |
<addressOffset>0x084</addressOffset> | |
</register> | |
<register> | |
<name>backup2</name> | |
<description>Backup Register</description> | |
<addressOffset>0x088</addressOffset> | |
</register> | |
<register> | |
<name>backup3</name> | |
<description>Backup Register</description> | |
<addressOffset>0x08C</addressOffset> | |
</register> | |
<register> | |
<name>backup4</name> | |
<description>Backup Register</description> | |
<addressOffset>0x090</addressOffset> | |
</register> | |
<register> | |
<name>backup5</name> | |
<description>Backup Register</description> | |
<addressOffset>0x094</addressOffset> | |
</register> | |
<register> | |
<name>backup6</name> | |
<description>Backup Register</description> | |
<addressOffset>0x098</addressOffset> | |
</register> | |
<register> | |
<name>backup7</name> | |
<description>Backup Register</description> | |
<addressOffset>0x09C</addressOffset> | |
</register> | |
<register> | |
<name>backup8</name> | |
<description>Backup Register</description> | |
<addressOffset>0x0A0</addressOffset> | |
</register> | |
<register> | |
<name>backup9</name> | |
<description>Backup Register</description> | |
<addressOffset>0x0A4</addressOffset> | |
</register> | |
<register> | |
<name>backup10</name> | |
<description>Backup Register</description> | |
<addressOffset>0x0A8</addressOffset> | |
</register> | |
<register> | |
<name>backup11</name> | |
<description>Backup Register</description> | |
<addressOffset>0x0AC</addressOffset> | |
</register> | |
<register> | |
<name>backup12</name> | |
<description>Backup Register</description> | |
<addressOffset>0x0B0</addressOffset> | |
</register> | |
<register> | |
<name>backup13</name> | |
<description>Backup Register</description> | |
<addressOffset>0x0B4</addressOffset> | |
</register> | |
<register> | |
<name>backup14</name> | |
<description>Backup Register</description> | |
<addressOffset>0x0B8</addressOffset> | |
</register> | |
<register> | |
<name>backup15</name> | |
<description>Backup Register</description> | |
<addressOffset>0x0BC</addressOffset> | |
</register> | |
<register> | |
<name>backup16</name> | |
<description>Backup Register</description> | |
<addressOffset>0x0C0</addressOffset> | |
</register> | |
<register> | |
<name>backup17</name> | |
<description>Backup Register</description> | |
<addressOffset>0x0C4</addressOffset> | |
</register> | |
<register> | |
<name>backup18</name> | |
<description>Backup Register</description> | |
<addressOffset>0x0C8</addressOffset> | |
</register> | |
<register> | |
<name>backup19</name> | |
<description>Backup Register</description> | |
<addressOffset>0x0CC</addressOffset> | |
</register> | |
<register> | |
<name>backup20</name> | |
<description>Backup Register</description> | |
<addressOffset>0x0D0</addressOffset> | |
</register> | |
<register> | |
<name>backup21</name> | |
<description>Backup Register</description> | |
<addressOffset>0x0D4</addressOffset> | |
</register> | |
<register> | |
<name>backup22</name> | |
<description>Backup Register</description> | |
<addressOffset>0x0D8</addressOffset> | |
</register> | |
<register> | |
<name>backup23</name> | |
<description>Backup Register</description> | |
<addressOffset>0x0DC</addressOffset> | |
</register> | |
<register> | |
<name>backup24</name> | |
<description>Backup Register</description> | |
<addressOffset>0x0E0</addressOffset> | |
</register> | |
<register> | |
<name>backup25</name> | |
<description>Backup Register</description> | |
<addressOffset>0x0E4</addressOffset> | |
</register> | |
<register> | |
<name>backup26</name> | |
<description>Backup Register</description> | |
<addressOffset>0x0E8</addressOffset> | |
</register> | |
<register> | |
<name>backup27</name> | |
<description>Backup Register</description> | |
<addressOffset>0x0EC</addressOffset> | |
</register> | |
<register> | |
<name>backup28</name> | |
<description>Backup Register</description> | |
<addressOffset>0x0F0</addressOffset> | |
</register> | |
<register> | |
<name>backup29</name> | |
<description>Backup Register</description> | |
<addressOffset>0x0F4</addressOffset> | |
</register> | |
<register> | |
<name>backup30</name> | |
<description>Backup Register</description> | |
<addressOffset>0x0F8</addressOffset> | |
</register> | |
<register> | |
<name>backup31</name> | |
<description>Backup Register</description> | |
<addressOffset>0x0FC</addressOffset> | |
</register> | |
<!-- Backup Registers --> | |
<!-- Power Management Unit Registers --> | |
<register> | |
<name>pmuwakepm0</name> | |
<description>PMU Wake Program Memory</description> | |
<addressOffset>0x100</addressOffset> | |
<fields> | |
<field><name>hfclkrst</name><msb>8</msb><lsb>8</lsb></field> | |
<field><name>corerst</name><msb>7</msb><lsb>7</lsb></field> | |
<field><name>vddpaden</name><msb>5</msb><lsb>5</lsb></field> | |
<field><name>delay</name><msb>3</msb><lsb>0</lsb></field> | |
</fields> | |
</register> | |
<register> | |
<name>pmuwakepm1</name> | |
<description>PMU Wake Program Memory</description> | |
<addressOffset>0x104</addressOffset> | |
<fields> | |
<field><name>hfclkrst</name><msb>8</msb><lsb>8</lsb></field> | |
<field><name>corerst</name><msb>7</msb><lsb>7</lsb></field> | |
<field><name>vddpaden</name><msb>5</msb><lsb>5</lsb></field> | |
<field><name>delay</name><msb>3</msb><lsb>0</lsb></field> | |
</fields> | |
</register> | |
<register> | |
<name>pmuwakepm2</name> | |
<description>PMU Wake Program Memory</description> | |
<addressOffset>0x108</addressOffset> | |
<fields> | |
<field><name>hfclkrst</name><msb>8</msb><lsb>8</lsb></field> | |
<field><name>corerst</name><msb>7</msb><lsb>7</lsb></field> | |
<field><name>vddpaden</name><msb>5</msb><lsb>5</lsb></field> | |
<field><name>delay</name><msb>3</msb><lsb>0</lsb></field> | |
</fields> | |
</register> | |
<register> | |
<name>pmuwakepm3</name> | |
<description>PMU Wake Program Memory</description> | |
<addressOffset>0x10C</addressOffset> | |
<fields> | |
<field><name>hfclkrst</name><msb>8</msb><lsb>8</lsb></field> | |
<field><name>corerst</name><msb>7</msb><lsb>7</lsb></field> | |
<field><name>vddpaden</name><msb>5</msb><lsb>5</lsb></field> | |
<field><name>delay</name><msb>3</msb><lsb>0</lsb></field> | |
</fields> | |
</register> | |
<register> | |
<name>pmuwakepm4</name> | |
<description>PMU Wake Program Memory</description> | |
<addressOffset>0x110</addressOffset> | |
<fields> | |
<field><name>hfclkrst</name><msb>8</msb><lsb>8</lsb></field> | |
<field><name>corerst</name><msb>7</msb><lsb>7</lsb></field> | |
<field><name>vddpaden</name><msb>5</msb><lsb>5</lsb></field> | |
<field><name>delay</name><msb>3</msb><lsb>0</lsb></field> | |
</fields> | |
</register> | |
<register> | |
<name>pmuwakepm5</name> | |
<description>PMU Wake Program Memory</description> | |
<addressOffset>0x114</addressOffset> | |
<fields> | |
<field><name>hfclkrst</name><msb>8</msb><lsb>8</lsb></field> | |
<field><name>corerst</name><msb>7</msb><lsb>7</lsb></field> | |
<field><name>vddpaden</name><msb>5</msb><lsb>5</lsb></field> | |
<field><name>delay</name><msb>3</msb><lsb>0</lsb></field> | |
</fields> | |
</register> | |
<register> | |
<name>pmuwakepm6</name> | |
<description>PMU Wake Program Memory</description> | |
<addressOffset>0x118</addressOffset> | |
<fields> | |
<field><name>hfclkrst</name><msb>8</msb><lsb>8</lsb></field> | |
<field><name>corerst</name><msb>7</msb><lsb>7</lsb></field> | |
<field><name>vddpaden</name><msb>5</msb><lsb>5</lsb></field> | |
<field><name>delay</name><msb>3</msb><lsb>0</lsb></field> | |
</fields> | |
</register> | |
<register> | |
<name>pmuwakepm7</name> | |
<description>PMU Wake Program Memory</description> | |
<addressOffset>0x11C</addressOffset> | |
<fields> | |
<field><name>hfclkrst</name><msb>8</msb><lsb>8</lsb></field> | |
<field><name>corerst</name><msb>7</msb><lsb>7</lsb></field> | |
<field><name>vddpaden</name><msb>5</msb><lsb>5</lsb></field> | |
<field><name>delay</name><msb>3</msb><lsb>0</lsb></field> | |
</fields> | |
</register> | |
<register> | |
<name>pmusleeppm0</name> | |
<description>PMU Sleep Program Memory</description> | |
<addressOffset>0x120</addressOffset> | |
<fields> | |
<field><name>hfclkrst</name><msb>8</msb><lsb>8</lsb></field> | |
<field><name>corerst</name><msb>7</msb><lsb>7</lsb></field> | |
<field><name>vddpaden</name><msb>5</msb><lsb>5</lsb></field> | |
<field><name>delay</name><msb>3</msb><lsb>0</lsb></field> | |
</fields> | |
</register> | |
<register> | |
<name>pmusleeppm1</name> | |
<description>PMU Sleep Program Memory</description> | |
<addressOffset>0x124</addressOffset> | |
<fields> | |
<field><name>hfclkrst</name><msb>8</msb><lsb>8</lsb></field> | |
<field><name>corerst</name><msb>7</msb><lsb>7</lsb></field> | |
<field><name>vddpaden</name><msb>5</msb><lsb>5</lsb></field> | |
<field><name>delay</name><msb>3</msb><lsb>0</lsb></field> | |
</fields> | |
</register> | |
<register> | |
<name>pmusleeppm2</name> | |
<description>PMU Sleep Program Memory</description> | |
<addressOffset>0x128</addressOffset> | |
<fields> | |
<field><name>hfclkrst</name><msb>8</msb><lsb>8</lsb></field> | |
<field><name>corerst</name><msb>7</msb><lsb>7</lsb></field> | |
<field><name>vddpaden</name><msb>5</msb><lsb>5</lsb></field> | |
<field><name>delay</name><msb>3</msb><lsb>0</lsb></field> | |
</fields> | |
</register> | |
<register> | |
<name>pmusleeppm3</name> | |
<description>PMU Sleep Program Memory</description> | |
<addressOffset>0x12C</addressOffset> | |
<fields> | |
<field><name>hfclkrst</name><msb>8</msb><lsb>8</lsb></field> | |
<field><name>corerst</name><msb>7</msb><lsb>7</lsb></field> | |
<field><name>vddpaden</name><msb>5</msb><lsb>5</lsb></field> | |
<field><name>delay</name><msb>3</msb><lsb>0</lsb></field> | |
</fields> | |
</register> | |
<register> | |
<name>pmusleeppm4</name> | |
<description>PMU Sleep Program Memory</description> | |
<addressOffset>0x130</addressOffset> | |
<fields> | |
<field><name>hfclkrst</name><msb>8</msb><lsb>8</lsb></field> | |
<field><name>corerst</name><msb>7</msb><lsb>7</lsb></field> | |
<field><name>vddpaden</name><msb>5</msb><lsb>5</lsb></field> | |
<field><name>delay</name><msb>3</msb><lsb>0</lsb></field> | |
</fields> | |
</register> | |
<register> | |
<name>pmusleeppm5</name> | |
<description>PMU Sleep Program Memory</description> | |
<addressOffset>0x134</addressOffset> | |
<fields> | |
<field><name>hfclkrst</name><msb>8</msb><lsb>8</lsb></field> | |
<field><name>corerst</name><msb>7</msb><lsb>7</lsb></field> | |
<field><name>vddpaden</name><msb>5</msb><lsb>5</lsb></field> | |
<field><name>delay</name><msb>3</msb><lsb>0</lsb></field> | |
</fields> | |
</register> | |
<register> | |
<name>pmusleeppm6</name> | |
<description>PMU Sleep Program Memory</description> | |
<addressOffset>0x138</addressOffset> | |
<fields> | |
<field><name>hfclkrst</name><msb>8</msb><lsb>8</lsb></field> | |
<field><name>corerst</name><msb>7</msb><lsb>7</lsb></field> | |
<field><name>vddpaden</name><msb>5</msb><lsb>5</lsb></field> | |
<field><name>delay</name><msb>3</msb><lsb>0</lsb></field> | |
</fields> | |
</register> | |
<register> | |
<name>pmusleeppm7</name> | |
<description>PMU Sleep Program Memory</description> | |
<addressOffset>0x13C</addressOffset> | |
<fields> | |
<field><name>hfclkrst</name><msb>8</msb><lsb>8</lsb></field> | |
<field><name>corerst</name><msb>7</msb><lsb>7</lsb></field> | |
<field><name>vddpaden</name><msb>5</msb><lsb>5</lsb></field> | |
<field><name>delay</name><msb>3</msb><lsb>0</lsb></field> | |
</fields> | |
</register> | |
<register> | |
<name>pmuie</name> | |
<description>PMU Interrupt Enable Register</description> | |
<addressOffset>0x140</addressOffset> | |
<fields> | |
<field><name>awakeup</name><msb>3</msb><lsb>3</lsb></field> | |
<field><name>dwakeup</name><msb>2</msb><lsb>2</lsb></field> | |
<field><name>rtc</name><msb>1</msb><lsb>1</lsb></field> | |
</fields> | |
</register> | |
<register> | |
<name>pmucause</name> | |
<description>PMU Cause Register</description> | |
<addressOffset>0x144</addressOffset> | |
<fields> | |
<field> | |
<name>resetcause</name> | |
<msb>9</msb><lsb>8</lsb> | |
<enumeratedValues> | |
<name>PMUResetCause</name> | |
<enumeratedValue> | |
<name>PowerOn</name> | |
<description>Power-on reset</description> | |
<value>0</value> | |
</enumeratedValue> | |
<enumeratedValue> | |
<name>External</name> | |
<description>External reset</description> | |
<value>1</value> | |
</enumeratedValue> | |
<enumeratedValue> | |
<name>Watchdog</name> | |
<description>Watchdog reset</description> | |
<value>2</value> | |
</enumeratedValue> | |
</enumeratedValues> | |
</field> | |
<field> | |
<name>wakeupcause</name> | |
<msb>1</msb><lsb>0</lsb> | |
<!-- NOTE: Missing documentation, assuming enumeration is the same | |
as the reset cause. --> | |
<enumeratedValues> | |
<name>PMUWakeupCause</name> | |
<enumeratedValue> | |
<name>PowerOn</name> | |
<description>Power-on wakeup</description> | |
<value>0</value> | |
</enumeratedValue> | |
<enumeratedValue> | |
<name>External</name> | |
<description>External wakeup</description> | |
<value>1</value> | |
</enumeratedValue> | |
<enumeratedValue> | |
<name>Watchdog</name> | |
<description>Watchdog wakeup</description> | |
<value>2</value> | |
</enumeratedValue> | |
</enumeratedValues> | |
</field> | |
</fields> | |
</register> | |
<register> | |
<name>pmusleep</name> | |
<description>PMU Sleep Register</description> | |
<addressOffset>0x148</addressOffset> | |
<access>write-only</access> | |
<fields> | |
<!-- Writing any value to pmusleep will start the sleep sequence --> | |
<field><name>sleep</name><msb>0</msb><lsb>0</lsb></field> | |
</fields> | |
</register> | |
<register> | |
<name>pmukey</name> | |
<description>PMU Key Register</description> | |
<addressOffset>0x14C</addressOffset> | |
<access>write-only</access> | |
<resetValue>0x51F15E</resetValue> | |
</register> | |
<!-- Power Management Unit Registers --> | |
</registers> | |
<interrupt> | |
<name>WATCHDOG</name> | |
<value>1</value> | |
</interrupt> | |
<interrupt> | |
<name>RTC</name> | |
<value>2</value> | |
</interrupt> | |
</peripheral> | |
<!-- AON --> | |
<!-- PRCI --> | |
<peripheral> | |
<name>PRCI</name> | |
<baseAddress>0x10008000</baseAddress> | |
<groupName>PRCI</groupName> | |
<description>Power Reset Clock Interrupts</description> | |
<registers> | |
<register> | |
<name>hfrosccfg</name> | |
<description>Clock Configuration Register</description> | |
<addressOffset>0x000</addressOffset> | |
<fields> | |
<field><name>ready</name><msb>31</msb><lsb>31</lsb></field> | |
<field><name>enable</name><msb>30</msb><lsb>30</lsb></field> | |
<field><name>trim</name><msb>20</msb><lsb>16</lsb></field> | |
<field><name>div</name><msb>5</msb><lsb>0</lsb></field> | |
</fields> | |
</register> | |
<register> | |
<name>hfxosccfg</name> | |
<description>Clock Configuration Register</description> | |
<addressOffset>0x004</addressOffset> | |
<fields> | |
<field><name>ready</name><msb>31</msb><lsb>31</lsb></field> | |
<field><name>enable</name><msb>30</msb><lsb>30</lsb></field> | |
</fields> | |
</register> | |
<register> | |
<name>pllcfg</name> | |
<description>PLL Configuration Register</description> | |
<addressOffset>0x008</addressOffset> | |
<fields> | |
<!-- TODO: Enumerate valid values --> | |
<field><name>lock</name><msb>31</msb><lsb>31</lsb></field> | |
<field><name>bypass</name><msb>18</msb><lsb>18</lsb></field> | |
<field><name>refsel</name><msb>17</msb><lsb>17</lsb></field> | |
<field><name>sel</name><msb>16</msb><lsb>16</lsb></field> | |
<field><name>q</name><msb>11</msb><lsb>10</lsb></field> | |
<field><name>f</name><msb>9</msb><lsb>4</lsb></field> | |
<field><name>r</name><msb>2</msb><lsb>0</lsb></field> | |
</fields> | |
</register> | |
<register> | |
<name>plloutdiv</name> | |
<description>PLL Divider Register</description> | |
<addressOffset>0x00C</addressOffset> | |
<!-- divby1 is enabled after reset --> | |
<resetValue>0x100</resetValue> | |
<fields> | |
<field><name>divby1</name><msb>8</msb><lsb>8</lsb></field> | |
<field><name>div</name><msb>5</msb><lsb>0</lsb></field> | |
</fields> | |
</register> | |
<register> | |
<name>coreclkcfg</name> | |
<description>Clock Configuration Register</description> | |
<addressOffset>0x010</addressOffset> | |
</register> | |
</registers> | |
</peripheral> | |
<!-- PRCI --> | |
<!-- OTP --> | |
<peripheral> | |
<name>OTP</name> | |
<baseAddress>0x10010000</baseAddress> | |
<groupName>OTP</groupName> | |
<description>One Time Programmable Memory</description> | |
<registers> | |
<!-- TODO --> | |
</registers> | |
</peripheral> | |
<!-- OTP --> | |
<!-- GPIO0 --> | |
<peripheral> | |
<name>GPIO0</name> | |
<baseAddress>0x10012000</baseAddress> | |
<groupName>GPIO</groupName> | |
<description>General Purpose Input Output</description> | |
<registers> | |
<register> | |
<name>value</name> | |
<description>Pin value.</description> | |
<addressOffset>0x000</addressOffset> | |
<fields> | |
<field><name>pin0</name><lsb>0</lsb><msb>0</msb></field> | |
<field><name>pin1</name><lsb>1</lsb><msb>1</msb></field> | |
<field><name>pin2</name><lsb>2</lsb><msb>2</msb></field> | |
<field><name>pin3</name><lsb>3</lsb><msb>3</msb></field> | |
<field><name>pin4</name><lsb>4</lsb><msb>4</msb></field> | |
<field><name>pin5</name><lsb>5</lsb><msb>5</msb></field> | |
<field><name>pin6</name><lsb>6</lsb><msb>6</msb></field> | |
<field><name>pin7</name><lsb>7</lsb><msb>7</msb></field> | |
<field><name>pin8</name><lsb>8</lsb><msb>8</msb></field> | |
<field><name>pin9</name><lsb>9</lsb><msb>9</msb></field> | |
<field><name>pin10</name><lsb>10</lsb><msb>10</msb></field> | |
<field><name>pin11</name><lsb>11</lsb><msb>11</msb></field> | |
<field><name>pin12</name><lsb>12</lsb><msb>12</msb></field> | |
<field><name>pin13</name><lsb>13</lsb><msb>13</msb></field> | |
<field><name>pin14</name><lsb>14</lsb><msb>14</msb></field> | |
<field><name>pin15</name><lsb>15</lsb><msb>15</msb></field> | |
<field><name>pin16</name><lsb>16</lsb><msb>16</msb></field> | |
<field><name>pin17</name><lsb>17</lsb><msb>17</msb></field> | |
<field><name>pin18</name><lsb>18</lsb><msb>18</msb></field> | |
<field><name>pin19</name><lsb>19</lsb><msb>19</msb></field> | |
<field><name>pin20</name><lsb>20</lsb><msb>20</msb></field> | |
<field><name>pin21</name><lsb>21</lsb><msb>21</msb></field> | |
<field><name>pin22</name><lsb>22</lsb><msb>22</msb></field> | |
<field><name>pin23</name><lsb>23</lsb><msb>23</msb></field> | |
<field><name>pin24</name><lsb>24</lsb><msb>24</msb></field> | |
<field><name>pin25</name><lsb>25</lsb><msb>25</msb></field> | |
<field><name>pin26</name><lsb>26</lsb><msb>26</msb></field> | |
<field><name>pin27</name><lsb>27</lsb><msb>27</msb></field> | |
<field><name>pin28</name><lsb>28</lsb><msb>28</msb></field> | |
<field><name>pin29</name><lsb>29</lsb><msb>29</msb></field> | |
<field><name>pin30</name><lsb>30</lsb><msb>30</msb></field> | |
<field><name>pin31</name><lsb>31</lsb><msb>31</msb></field> | |
</fields> | |
</register> | |
<register> | |
<name>input_en</name> | |
<description>Pin Input Enable Register</description> | |
<addressOffset>0x004</addressOffset> | |
<fields> | |
<field><name>pin0</name><lsb>0</lsb><msb>0</msb></field> | |
<field><name>pin1</name><lsb>1</lsb><msb>1</msb></field> | |
<field><name>pin2</name><lsb>2</lsb><msb>2</msb></field> | |
<field><name>pin3</name><lsb>3</lsb><msb>3</msb></field> | |
<field><name>pin4</name><lsb>4</lsb><msb>4</msb></field> | |
<field><name>pin5</name><lsb>5</lsb><msb>5</msb></field> | |
<field><name>pin6</name><lsb>6</lsb><msb>6</msb></field> | |
<field><name>pin7</name><lsb>7</lsb><msb>7</msb></field> | |
<field><name>pin8</name><lsb>8</lsb><msb>8</msb></field> | |
<field><name>pin9</name><lsb>9</lsb><msb>9</msb></field> | |
<field><name>pin10</name><lsb>10</lsb><msb>10</msb></field> | |
<field><name>pin11</name><lsb>11</lsb><msb>11</msb></field> | |
<field><name>pin12</name><lsb>12</lsb><msb>12</msb></field> | |
<field><name>pin13</name><lsb>13</lsb><msb>13</msb></field> | |
<field><name>pin14</name><lsb>14</lsb><msb>14</msb></field> | |
<field><name>pin15</name><lsb>15</lsb><msb>15</msb></field> | |
<field><name>pin16</name><lsb>16</lsb><msb>16</msb></field> | |
<field><name>pin17</name><lsb>17</lsb><msb>17</msb></field> | |
<field><name>pin18</name><lsb>18</lsb><msb>18</msb></field> | |
<field><name>pin19</name><lsb>19</lsb><msb>19</msb></field> | |
<field><name>pin20</name><lsb>20</lsb><msb>20</msb></field> | |
<field><name>pin21</name><lsb>21</lsb><msb>21</msb></field> | |
<field><name>pin22</name><lsb>22</lsb><msb>22</msb></field> | |
<field><name>pin23</name><lsb>23</lsb><msb>23</msb></field> | |
<field><name>pin24</name><lsb>24</lsb><msb>24</msb></field> | |
<field><name>pin25</name><lsb>25</lsb><msb>25</msb></field> | |
<field><name>pin26</name><lsb>26</lsb><msb>26</msb></field> | |
<field><name>pin27</name><lsb>27</lsb><msb>27</msb></field> | |
<field><name>pin28</name><lsb>28</lsb><msb>28</msb></field> | |
<field><name>pin29</name><lsb>29</lsb><msb>29</msb></field> | |
<field><name>pin30</name><lsb>30</lsb><msb>30</msb></field> | |
<field><name>pin31</name><lsb>31</lsb><msb>31</msb></field> | |
</fields> | |
</register> | |
<register> | |
<name>output_en</name> | |
<description>Pin Output Enable Register</description> | |
<addressOffset>0x008</addressOffset> | |
<fields> | |
<field><name>pin0</name><lsb>0</lsb><msb>0</msb></field> | |
<field><name>pin1</name><lsb>1</lsb><msb>1</msb></field> | |
<field><name>pin2</name><lsb>2</lsb><msb>2</msb></field> | |
<field><name>pin3</name><lsb>3</lsb><msb>3</msb></field> | |
<field><name>pin4</name><lsb>4</lsb><msb>4</msb></field> | |
<field><name>pin5</name><lsb>5</lsb><msb>5</msb></field> | |
<field><name>pin6</name><lsb>6</lsb><msb>6</msb></field> | |
<field><name>pin7</name><lsb>7</lsb><msb>7</msb></field> | |
<field><name>pin8</name><lsb>8</lsb><msb>8</msb></field> | |
<field><name>pin9</name><lsb>9</lsb><msb>9</msb></field> | |
<field><name>pin10</name><lsb>10</lsb><msb>10</msb></field> | |
<field><name>pin11</name><lsb>11</lsb><msb>11</msb></field> | |
<field><name>pin12</name><lsb>12</lsb><msb>12</msb></field> | |
<field><name>pin13</name><lsb>13</lsb><msb>13</msb></field> | |
<field><name>pin14</name><lsb>14</lsb><msb>14</msb></field> | |
<field><name>pin15</name><lsb>15</lsb><msb>15</msb></field> | |
<field><name>pin16</name><lsb>16</lsb><msb>16</msb></field> | |
<field><name>pin17</name><lsb>17</lsb><msb>17</msb></field> | |
<field><name>pin18</name><lsb>18</lsb><msb>18</msb></field> | |
<field><name>pin19</name><lsb>19</lsb><msb>19</msb></field> | |
<field><name>pin20</name><lsb>20</lsb><msb>20</msb></field> | |
<field><name>pin21</name><lsb>21</lsb><msb>21</msb></field> | |
<field><name>pin22</name><lsb>22</lsb><msb>22</msb></field> | |
<field><name>pin23</name><lsb>23</lsb><msb>23</msb></field> | |
<field><name>pin24</name><lsb>24</lsb><msb>24</msb></field> | |
<field><name>pin25</name><lsb>25</lsb><msb>25</msb></field> | |
<field><name>pin26</name><lsb>26</lsb><msb>26</msb></field> | |
<field><name>pin27</name><lsb>27</lsb><msb>27</msb></field> | |
<field><name>pin28</name><lsb>28</lsb><msb>28</msb></field> | |
<field><name>pin29</name><lsb>29</lsb><msb>29</msb></field> | |
<field><name>pin30</name><lsb>30</lsb><msb>30</msb></field> | |
<field><name>pin31</name><lsb>31</lsb><msb>31</msb></field> | |
</fields> | |
</register> | |
<register> | |
<name>port</name> | |
<description>Output Port Value Register</description> | |
<addressOffset>0x00C</addressOffset> | |
<fields> | |
<field><name>pin0</name><lsb>0</lsb><msb>0</msb></field> | |
<field><name>pin1</name><lsb>1</lsb><msb>1</msb></field> | |
<field><name>pin2</name><lsb>2</lsb><msb>2</msb></field> | |
<field><name>pin3</name><lsb>3</lsb><msb>3</msb></field> | |
<field><name>pin4</name><lsb>4</lsb><msb>4</msb></field> | |
<field><name>pin5</name><lsb>5</lsb><msb>5</msb></field> | |
<field><name>pin6</name><lsb>6</lsb><msb>6</msb></field> | |
<field><name>pin7</name><lsb>7</lsb><msb>7</msb></field> | |
<field><name>pin8</name><lsb>8</lsb><msb>8</msb></field> | |
<field><name>pin9</name><lsb>9</lsb><msb>9</msb></field> | |
<field><name>pin10</name><lsb>10</lsb><msb>10</msb></field> | |
<field><name>pin11</name><lsb>11</lsb><msb>11</msb></field> | |
<field><name>pin12</name><lsb>12</lsb><msb>12</msb></field> | |
<field><name>pin13</name><lsb>13</lsb><msb>13</msb></field> | |
<field><name>pin14</name><lsb>14</lsb><msb>14</msb></field> | |
<field><name>pin15</name><lsb>15</lsb><msb>15</msb></field> | |
<field><name>pin16</name><lsb>16</lsb><msb>16</msb></field> | |
<field><name>pin17</name><lsb>17</lsb><msb>17</msb></field> | |
<field><name>pin18</name><lsb>18</lsb><msb>18</msb></field> | |
<field><name>pin19</name><lsb>19</lsb><msb>19</msb></field> | |
<field><name>pin20</name><lsb>20</lsb><msb>20</msb></field> | |
<field><name>pin21</name><lsb>21</lsb><msb>21</msb></field> | |
<field><name>pin22</name><lsb>22</lsb><msb>22</msb></field> | |
<field><name>pin23</name><lsb>23</lsb><msb>23</msb></field> | |
<field><name>pin24</name><lsb>24</lsb><msb>24</msb></field> | |
<field><name>pin25</name><lsb>25</lsb><msb>25</msb></field> | |
<field><name>pin26</name><lsb>26</lsb><msb>26</msb></field> | |
<field><name>pin27</name><lsb>27</lsb><msb>27</msb></field> | |
<field><name>pin28</name><lsb>28</lsb><msb>28</msb></field> | |
<field><name>pin29</name><lsb>29</lsb><msb>29</msb></field> | |
<field><name>pin30</name><lsb>30</lsb><msb>30</msb></field> | |
<field><name>pin31</name><lsb>31</lsb><msb>31</msb></field> | |
</fields> | |
</register> | |
<register> | |
<name>pullup</name> | |
<description>Internal Pull-Up Enable Register</description> | |
<addressOffset>0x010</addressOffset> | |
<fields> | |
<field><name>pin0</name><lsb>0</lsb><msb>0</msb></field> | |
<field><name>pin1</name><lsb>1</lsb><msb>1</msb></field> | |
<field><name>pin2</name><lsb>2</lsb><msb>2</msb></field> | |
<field><name>pin3</name><lsb>3</lsb><msb>3</msb></field> | |
<field><name>pin4</name><lsb>4</lsb><msb>4</msb></field> | |
<field><name>pin5</name><lsb>5</lsb><msb>5</msb></field> | |
<field><name>pin6</name><lsb>6</lsb><msb>6</msb></field> | |
<field><name>pin7</name><lsb>7</lsb><msb>7</msb></field> | |
<field><name>pin8</name><lsb>8</lsb><msb>8</msb></field> | |
<field><name>pin9</name><lsb>9</lsb><msb>9</msb></field> | |
<field><name>pin10</name><lsb>10</lsb><msb>10</msb></field> | |
<field><name>pin11</name><lsb>11</lsb><msb>11</msb></field> | |
<field><name>pin12</name><lsb>12</lsb><msb>12</msb></field> | |
<field><name>pin13</name><lsb>13</lsb><msb>13</msb></field> | |
<field><name>pin14</name><lsb>14</lsb><msb>14</msb></field> | |
<field><name>pin15</name><lsb>15</lsb><msb>15</msb></field> | |
<field><name>pin16</name><lsb>16</lsb><msb>16</msb></field> | |
<field><name>pin17</name><lsb>17</lsb><msb>17</msb></field> | |
<field><name>pin18</name><lsb>18</lsb><msb>18</msb></field> | |
<field><name>pin19</name><lsb>19</lsb><msb>19</msb></field> | |
<field><name>pin20</name><lsb>20</lsb><msb>20</msb></field> | |
<field><name>pin21</name><lsb>21</lsb><msb>21</msb></field> | |
<field><name>pin22</name><lsb>22</lsb><msb>22</msb></field> | |
<field><name>pin23</name><lsb>23</lsb><msb>23</msb></field> | |
<field><name>pin24</name><lsb>24</lsb><msb>24</msb></field> | |
<field><name>pin25</name><lsb>25</lsb><msb>25</msb></field> | |
<field><name>pin26</name><lsb>26</lsb><msb>26</msb></field> | |
<field><name>pin27</name><lsb>27</lsb><msb>27</msb></field> | |
<field><name>pin28</name><lsb>28</lsb><msb>28</msb></field> | |
<field><name>pin29</name><lsb>29</lsb><msb>29</msb></field> | |
<field><name>pin30</name><lsb>30</lsb><msb>30</msb></field> | |
<field><name>pin31</name><lsb>31</lsb><msb>31</msb></field> | |
</fields> | |
</register> | |
<register> | |
<name>drive</name> | |
<description>Drive Strength Register</description> | |
<addressOffset>0x014</addressOffset> | |
<fields> | |
<field><name>pin0</name><lsb>0</lsb><msb>0</msb></field> | |
<field><name>pin1</name><lsb>1</lsb><msb>1</msb></field> | |
<field><name>pin2</name><lsb>2</lsb><msb>2</msb></field> | |
<field><name>pin3</name><lsb>3</lsb><msb>3</msb></field> | |
<field><name>pin4</name><lsb>4</lsb><msb>4</msb></field> | |
<field><name>pin5</name><lsb>5</lsb><msb>5</msb></field> | |
<field><name>pin6</name><lsb>6</lsb><msb>6</msb></field> | |
<field><name>pin7</name><lsb>7</lsb><msb>7</msb></field> | |
<field><name>pin8</name><lsb>8</lsb><msb>8</msb></field> | |
<field><name>pin9</name><lsb>9</lsb><msb>9</msb></field> | |
<field><name>pin10</name><lsb>10</lsb><msb>10</msb></field> | |
<field><name>pin11</name><lsb>11</lsb><msb>11</msb></field> | |
<field><name>pin12</name><lsb>12</lsb><msb>12</msb></field> | |
<field><name>pin13</name><lsb>13</lsb><msb>13</msb></field> | |
<field><name>pin14</name><lsb>14</lsb><msb>14</msb></field> | |
<field><name>pin15</name><lsb>15</lsb><msb>15</msb></field> | |
<field><name>pin16</name><lsb>16</lsb><msb>16</msb></field> | |
<field><name>pin17</name><lsb>17</lsb><msb>17</msb></field> | |
<field><name>pin18</name><lsb>18</lsb><msb>18</msb></field> | |
<field><name>pin19</name><lsb>19</lsb><msb>19</msb></field> | |
<field><name>pin20</name><lsb>20</lsb><msb>20</msb></field> | |
<field><name>pin21</name><lsb>21</lsb><msb>21</msb></field> | |
<field><name>pin22</name><lsb>22</lsb><msb>22</msb></field> | |
<field><name>pin23</name><lsb>23</lsb><msb>23</msb></field> | |
<field><name>pin24</name><lsb>24</lsb><msb>24</msb></field> | |
<field><name>pin25</name><lsb>25</lsb><msb>25</msb></field> | |
<field><name>pin26</name><lsb>26</lsb><msb>26</msb></field> | |
<field><name>pin27</name><lsb>27</lsb><msb>27</msb></field> | |
<field><name>pin28</name><lsb>28</lsb><msb>28</msb></field> | |
<field><name>pin29</name><lsb>29</lsb><msb>29</msb></field> | |
<field><name>pin30</name><lsb>30</lsb><msb>30</msb></field> | |
<field><name>pin31</name><lsb>31</lsb><msb>31</msb></field> | |
</fields> | |
</register> | |
<register> | |
<name>rise_ie</name> | |
<description>Rise Interrupt Enable Register</description> | |
<addressOffset>0x018</addressOffset> | |
<fields> | |
<field><name>pin0</name><lsb>0</lsb><msb>0</msb></field> | |
<field><name>pin1</name><lsb>1</lsb><msb>1</msb></field> | |
<field><name>pin2</name><lsb>2</lsb><msb>2</msb></field> | |
<field><name>pin3</name><lsb>3</lsb><msb>3</msb></field> | |
<field><name>pin4</name><lsb>4</lsb><msb>4</msb></field> | |
<field><name>pin5</name><lsb>5</lsb><msb>5</msb></field> | |
<field><name>pin6</name><lsb>6</lsb><msb>6</msb></field> | |
<field><name>pin7</name><lsb>7</lsb><msb>7</msb></field> | |
<field><name>pin8</name><lsb>8</lsb><msb>8</msb></field> | |
<field><name>pin9</name><lsb>9</lsb><msb>9</msb></field> | |
<field><name>pin10</name><lsb>10</lsb><msb>10</msb></field> | |
<field><name>pin11</name><lsb>11</lsb><msb>11</msb></field> | |
<field><name>pin12</name><lsb>12</lsb><msb>12</msb></field> | |
<field><name>pin13</name><lsb>13</lsb><msb>13</msb></field> | |
<field><name>pin14</name><lsb>14</lsb><msb>14</msb></field> | |
<field><name>pin15</name><lsb>15</lsb><msb>15</msb></field> | |
<field><name>pin16</name><lsb>16</lsb><msb>16</msb></field> | |
<field><name>pin17</name><lsb>17</lsb><msb>17</msb></field> | |
<field><name>pin18</name><lsb>18</lsb><msb>18</msb></field> | |
<field><name>pin19</name><lsb>19</lsb><msb>19</msb></field> | |
<field><name>pin20</name><lsb>20</lsb><msb>20</msb></field> | |
<field><name>pin21</name><lsb>21</lsb><msb>21</msb></field> | |
<field><name>pin22</name><lsb>22</lsb><msb>22</msb></field> | |
<field><name>pin23</name><lsb>23</lsb><msb>23</msb></field> | |
<field><name>pin24</name><lsb>24</lsb><msb>24</msb></field> | |
<field><name>pin25</name><lsb>25</lsb><msb>25</msb></field> | |
<field><name>pin26</name><lsb>26</lsb><msb>26</msb></field> | |
<field><name>pin27</name><lsb>27</lsb><msb>27</msb></field> | |
<field><name>pin28</name><lsb>28</lsb><msb>28</msb></field> | |
<field><name>pin29</name><lsb>29</lsb><msb>29</msb></field> | |
<field><name>pin30</name><lsb>30</lsb><msb>30</msb></field> | |
<field><name>pin31</name><lsb>31</lsb><msb>31</msb></field> | |
</fields> | |
</register> | |
<register> | |
<name>rise_ip</name> | |
<description>Rise Interrupt Pending Register</description> | |
<addressOffset>0x01C</addressOffset> | |
<fields> | |
<field><name>pin0</name><lsb>0</lsb><msb>0</msb></field> | |
<field><name>pin1</name><lsb>1</lsb><msb>1</msb></field> | |
<field><name>pin2</name><lsb>2</lsb><msb>2</msb></field> | |
<field><name>pin3</name><lsb>3</lsb><msb>3</msb></field> | |
<field><name>pin4</name><lsb>4</lsb><msb>4</msb></field> | |
<field><name>pin5</name><lsb>5</lsb><msb>5</msb></field> | |
<field><name>pin6</name><lsb>6</lsb><msb>6</msb></field> | |
<field><name>pin7</name><lsb>7</lsb><msb>7</msb></field> | |
<field><name>pin8</name><lsb>8</lsb><msb>8</msb></field> | |
<field><name>pin9</name><lsb>9</lsb><msb>9</msb></field> | |
<field><name>pin10</name><lsb>10</lsb><msb>10</msb></field> | |
<field><name>pin11</name><lsb>11</lsb><msb>11</msb></field> | |
<field><name>pin12</name><lsb>12</lsb><msb>12</msb></field> | |
<field><name>pin13</name><lsb>13</lsb><msb>13</msb></field> | |
<field><name>pin14</name><lsb>14</lsb><msb>14</msb></field> | |
<field><name>pin15</name><lsb>15</lsb><msb>15</msb></field> | |
<field><name>pin16</name><lsb>16</lsb><msb>16</msb></field> | |
<field><name>pin17</name><lsb>17</lsb><msb>17</msb></field> | |
<field><name>pin18</name><lsb>18</lsb><msb>18</msb></field> | |
<field><name>pin19</name><lsb>19</lsb><msb>19</msb></field> | |
<field><name>pin20</name><lsb>20</lsb><msb>20</msb></field> | |
<field><name>pin21</name><lsb>21</lsb><msb>21</msb></field> | |
<field><name>pin22</name><lsb>22</lsb><msb>22</msb></field> | |
<field><name>pin23</name><lsb>23</lsb><msb>23</msb></field> | |
<field><name>pin24</name><lsb>24</lsb><msb>24</msb></field> | |
<field><name>pin25</name><lsb>25</lsb><msb>25</msb></field> | |
<field><name>pin26</name><lsb>26</lsb><msb>26</msb></field> | |
<field><name>pin27</name><lsb>27</lsb><msb>27</msb></field> | |
<field><name>pin28</name><lsb>28</lsb><msb>28</msb></field> | |
<field><name>pin29</name><lsb>29</lsb><msb>29</msb></field> | |
<field><name>pin30</name><lsb>30</lsb><msb>30</msb></field> | |
<field><name>pin31</name><lsb>31</lsb><msb>31</msb></field> | |
</fields> | |
</register> | |
<register> | |
<name>fall_ie</name> | |
<description>Fall Interrupt Enable Register</description> | |
<addressOffset>0x020</addressOffset> | |
<fields> | |
<field><name>pin0</name><lsb>0</lsb><msb>0</msb></field> | |
<field><name>pin1</name><lsb>1</lsb><msb>1</msb></field> | |
<field><name>pin2</name><lsb>2</lsb><msb>2</msb></field> | |
<field><name>pin3</name><lsb>3</lsb><msb>3</msb></field> | |
<field><name>pin4</name><lsb>4</lsb><msb>4</msb></field> | |
<field><name>pin5</name><lsb>5</lsb><msb>5</msb></field> | |
<field><name>pin6</name><lsb>6</lsb><msb>6</msb></field> | |
<field><name>pin7</name><lsb>7</lsb><msb>7</msb></field> | |
<field><name>pin8</name><lsb>8</lsb><msb>8</msb></field> | |
<field><name>pin9</name><lsb>9</lsb><msb>9</msb></field> | |
<field><name>pin10</name><lsb>10</lsb><msb>10</msb></field> | |
<field><name>pin11</name><lsb>11</lsb><msb>11</msb></field> | |
<field><name>pin12</name><lsb>12</lsb><msb>12</msb></field> | |
<field><name>pin13</name><lsb>13</lsb><msb>13</msb></field> | |
<field><name>pin14</name><lsb>14</lsb><msb>14</msb></field> | |
<field><name>pin15</name><lsb>15</lsb><msb>15</msb></field> | |
<field><name>pin16</name><lsb>16</lsb><msb>16</msb></field> | |
<field><name>pin17</name><lsb>17</lsb><msb>17</msb></field> | |
<field><name>pin18</name><lsb>18</lsb><msb>18</msb></field> | |
<field><name>pin19</name><lsb>19</lsb><msb>19</msb></field> | |
<field><name>pin20</name><lsb>20</lsb><msb>20</msb></field> | |
<field><name>pin21</name><lsb>21</lsb><msb>21</msb></field> | |
<field><name>pin22</name><lsb>22</lsb><msb>22</msb></field> | |
<field><name>pin23</name><lsb>23</lsb><msb>23</msb></field> | |
<field><name>pin24</name><lsb>24</lsb><msb>24</msb></field> | |
<field><name>pin25</name><lsb>25</lsb><msb>25</msb></field> | |
<field><name>pin26</name><lsb>26</lsb><msb>26</msb></field> | |
<field><name>pin27</name><lsb>27</lsb><msb>27</msb></field> | |
<field><name>pin28</name><lsb>28</lsb><msb>28</msb></field> | |
<field><name>pin29</name><lsb>29</lsb><msb>29</msb></field> | |
<field><name>pin30</name><lsb>30</lsb><msb>30</msb></field> | |
<field><name>pin31</name><lsb>31</lsb><msb>31</msb></field> | |
</fields> | |
</register> | |
<register> | |
<name>fall_ip</name> | |
<description>Fall Interrupt Pending Register</description> | |
<addressOffset>0x024</addressOffset> | |
<fields> | |
<field><name>pin0</name><lsb>0</lsb><msb>0</msb></field> | |
<field><name>pin1</name><lsb>1</lsb><msb>1</msb></field> | |
<field><name>pin2</name><lsb>2</lsb><msb>2</msb></field> | |
<field><name>pin3</name><lsb>3</lsb><msb>3</msb></field> | |
<field><name>pin4</name><lsb>4</lsb><msb>4</msb></field> | |
<field><name>pin5</name><lsb>5</lsb><msb>5</msb></field> | |
<field><name>pin6</name><lsb>6</lsb><msb>6</msb></field> | |
<field><name>pin7</name><lsb>7</lsb><msb>7</msb></field> | |
<field><name>pin8</name><lsb>8</lsb><msb>8</msb></field> | |
<field><name>pin9</name><lsb>9</lsb><msb>9</msb></field> | |
<field><name>pin10</name><lsb>10</lsb><msb>10</msb></field> | |
<field><name>pin11</name><lsb>11</lsb><msb>11</msb></field> | |
<field><name>pin12</name><lsb>12</lsb><msb>12</msb></field> | |
<field><name>pin13</name><lsb>13</lsb><msb>13</msb></field> | |
<field><name>pin14</name><lsb>14</lsb><msb>14</msb></field> | |
<field><name>pin15</name><lsb>15</lsb><msb>15</msb></field> | |
<field><name>pin16</name><lsb>16</lsb><msb>16</msb></field> | |
<field><name>pin17</name><lsb>17</lsb><msb>17</msb></field> | |
<field><name>pin18</name><lsb>18</lsb><msb>18</msb></field> | |
<field><name>pin19</name><lsb>19</lsb><msb>19</msb></field> | |
<field><name>pin20</name><lsb>20</lsb><msb>20</msb></field> | |
<field><name>pin21</name><lsb>21</lsb><msb>21</msb></field> | |
<field><name>pin22</name><lsb>22</lsb><msb>22</msb></field> | |
<field><name>pin23</name><lsb>23</lsb><msb>23</msb></field> | |
<field><name>pin24</name><lsb>24</lsb><msb>24</msb></field> | |
<field><name>pin25</name><lsb>25</lsb><msb>25</msb></field> | |
<field><name>pin26</name><lsb>26</lsb><msb>26</msb></field> | |
<field><name>pin27</name><lsb>27</lsb><msb>27</msb></field> | |
<field><name>pin28</name><lsb>28</lsb><msb>28</msb></field> | |
<field><name>pin29</name><lsb>29</lsb><msb>29</msb></field> | |
<field><name>pin30</name><lsb>30</lsb><msb>30</msb></field> | |
<field><name>pin31</name><lsb>31</lsb><msb>31</msb></field> | |
</fields> | |
</register> | |
<register> | |
<name>high_ie</name> | |
<description>High Interrupt Enable Register</description> | |
<addressOffset>0x028</addressOffset> | |
<fields> | |
<field><name>pin0</name><lsb>0</lsb><msb>0</msb></field> | |
<field><name>pin1</name><lsb>1</lsb><msb>1</msb></field> | |
<field><name>pin2</name><lsb>2</lsb><msb>2</msb></field> | |
<field><name>pin3</name><lsb>3</lsb><msb>3</msb></field> | |
<field><name>pin4</name><lsb>4</lsb><msb>4</msb></field> | |
<field><name>pin5</name><lsb>5</lsb><msb>5</msb></field> | |
<field><name>pin6</name><lsb>6</lsb><msb>6</msb></field> | |
<field><name>pin7</name><lsb>7</lsb><msb>7</msb></field> | |
<field><name>pin8</name><lsb>8</lsb><msb>8</msb></field> | |
<field><name>pin9</name><lsb>9</lsb><msb>9</msb></field> | |
<field><name>pin10</name><lsb>10</lsb><msb>10</msb></field> | |
<field><name>pin11</name><lsb>11</lsb><msb>11</msb></field> | |
<field><name>pin12</name><lsb>12</lsb><msb>12</msb></field> | |
<field><name>pin13</name><lsb>13</lsb><msb>13</msb></field> | |
<field><name>pin14</name><lsb>14</lsb><msb>14</msb></field> | |
<field><name>pin15</name><lsb>15</lsb><msb>15</msb></field> | |
<field><name>pin16</name><lsb>16</lsb><msb>16</msb></field> | |
<field><name>pin17</name><lsb>17</lsb><msb>17</msb></field> | |
<field><name>pin18</name><lsb>18</lsb><msb>18</msb></field> | |
<field><name>pin19</name><lsb>19</lsb><msb>19</msb></field> | |
<field><name>pin20</name><lsb>20</lsb><msb>20</msb></field> | |
<field><name>pin21</name><lsb>21</lsb><msb>21</msb></field> | |
<field><name>pin22</name><lsb>22</lsb><msb>22</msb></field> | |
<field><name>pin23</name><lsb>23</lsb><msb>23</msb></field> | |
<field><name>pin24</name><lsb>24</lsb><msb>24</msb></field> | |
<field><name>pin25</name><lsb>25</lsb><msb>25</msb></field> | |
<field><name>pin26</name><lsb>26</lsb><msb>26</msb></field> | |
<field><name>pin27</name><lsb>27</lsb><msb>27</msb></field> | |
<field><name>pin28</name><lsb>28</lsb><msb>28</msb></field> | |
<field><name>pin29</name><lsb>29</lsb><msb>29</msb></field> | |
<field><name>pin30</name><lsb>30</lsb><msb>30</msb></field> | |
<field><name>pin31</name><lsb>31</lsb><msb>31</msb></field> | |
</fields> | |
</register> | |
<register> | |
<name>high_ip</name> | |
<description>High Interrupt Pending Register</description> | |
<addressOffset>0x02C</addressOffset> | |
<fields> | |
<field><name>pin0</name><lsb>0</lsb><msb>0</msb></field> | |
<field><name>pin1</name><lsb>1</lsb><msb>1</msb></field> | |
<field><name>pin2</name><lsb>2</lsb><msb>2</msb></field> | |
<field><name>pin3</name><lsb>3</lsb><msb>3</msb></field> | |
<field><name>pin4</name><lsb>4</lsb><msb>4</msb></field> | |
<field><name>pin5</name><lsb>5</lsb><msb>5</msb></field> | |
<field><name>pin6</name><lsb>6</lsb><msb>6</msb></field> | |
<field><name>pin7</name><lsb>7</lsb><msb>7</msb></field> | |
<field><name>pin8</name><lsb>8</lsb><msb>8</msb></field> | |
<field><name>pin9</name><lsb>9</lsb><msb>9</msb></field> | |
<field><name>pin10</name><lsb>10</lsb><msb>10</msb></field> | |
<field><name>pin11</name><lsb>11</lsb><msb>11</msb></field> | |
<field><name>pin12</name><lsb>12</lsb><msb>12</msb></field> | |
<field><name>pin13</name><lsb>13</lsb><msb>13</msb></field> | |
<field><name>pin14</name><lsb>14</lsb><msb>14</msb></field> | |
<field><name>pin15</name><lsb>15</lsb><msb>15</msb></field> | |
<field><name>pin16</name><lsb>16</lsb><msb>16</msb></field> | |
<field><name>pin17</name><lsb>17</lsb><msb>17</msb></field> | |
<field><name>pin18</name><lsb>18</lsb><msb>18</msb></field> | |
<field><name>pin19</name><lsb>19</lsb><msb>19</msb></field> | |
<field><name>pin20</name><lsb>20</lsb><msb>20</msb></field> | |
<field><name>pin21</name><lsb>21</lsb><msb>21</msb></field> | |
<field><name>pin22</name><lsb>22</lsb><msb>22</msb></field> | |
<field><name>pin23</name><lsb>23</lsb><msb>23</msb></field> | |
<field><name>pin24</name><lsb>24</lsb><msb>24</msb></field> | |
<field><name>pin25</name><lsb>25</lsb><msb>25</msb></field> | |
<field><name>pin26</name><lsb>26</lsb><msb>26</msb></field> | |
<field><name>pin27</name><lsb>27</lsb><msb>27</msb></field> | |
<field><name>pin28</name><lsb>28</lsb><msb>28</msb></field> | |
<field><name>pin29</name><lsb>29</lsb><msb>29</msb></field> | |
<field><name>pin30</name><lsb>30</lsb><msb>30</msb></field> | |
<field><name>pin31</name><lsb>31</lsb><msb>31</msb></field> | |
</fields> | |
</register> | |
<register> | |
<name>low_ie</name> | |
<description>Low Interrupt Enable Register</description> | |
<addressOffset>0x030</addressOffset> | |
<fields> | |
<field><name>pin0</name><lsb>0</lsb><msb>0</msb></field> | |
<field><name>pin1</name><lsb>1</lsb><msb>1</msb></field> | |
<field><name>pin2</name><lsb>2</lsb><msb>2</msb></field> | |
<field><name>pin3</name><lsb>3</lsb><msb>3</msb></field> | |
<field><name>pin4</name><lsb>4</lsb><msb>4</msb></field> | |
<field><name>pin5</name><lsb>5</lsb><msb>5</msb></field> | |
<field><name>pin6</name><lsb>6</lsb><msb>6</msb></field> | |
<field><name>pin7</name><lsb>7</lsb><msb>7</msb></field> | |
<field><name>pin8</name><lsb>8</lsb><msb>8</msb></field> | |
<field><name>pin9</name><lsb>9</lsb><msb>9</msb></field> | |
<field><name>pin10</name><lsb>10</lsb><msb>10</msb></field> | |
<field><name>pin11</name><lsb>11</lsb><msb>11</msb></field> | |
<field><name>pin12</name><lsb>12</lsb><msb>12</msb></field> | |
<field><name>pin13</name><lsb>13</lsb><msb>13</msb></field> | |
<field><name>pin14</name><lsb>14</lsb><msb>14</msb></field> | |
<field><name>pin15</name><lsb>15</lsb><msb>15</msb></field> | |
<field><name>pin16</name><lsb>16</lsb><msb>16</msb></field> | |
<field><name>pin17</name><lsb>17</lsb><msb>17</msb></field> | |
<field><name>pin18</name><lsb>18</lsb><msb>18</msb></field> | |
<field><name>pin19</name><lsb>19</lsb><msb>19</msb></field> | |
<field><name>pin20</name><lsb>20</lsb><msb>20</msb></field> | |
<field><name>pin21</name><lsb>21</lsb><msb>21</msb></field> | |
<field><name>pin22</name><lsb>22</lsb><msb>22</msb></field> | |
<field><name>pin23</name><lsb>23</lsb><msb>23</msb></field> | |
<field><name>pin24</name><lsb>24</lsb><msb>24</msb></field> | |
<field><name>pin25</name><lsb>25</lsb><msb>25</msb></field> | |
<field><name>pin26</name><lsb>26</lsb><msb>26</msb></field> | |
<field><name>pin27</name><lsb>27</lsb><msb>27</msb></field> | |
<field><name>pin28</name><lsb>28</lsb><msb>28</msb></field> | |
<field><name>pin29</name><lsb>29</lsb><msb>29</msb></field> | |
<field><name>pin30</name><lsb>30</lsb><msb>30</msb></field> | |
<field><name>pin31</name><lsb>31</lsb><msb>31</msb></field> | |
</fields> | |
</register> | |
<register> | |
<name>low_ip</name> | |
<description>Low Interrupt Pending Register</description> | |
<addressOffset>0x034</addressOffset> | |
<fields> | |
<field><name>pin0</name><lsb>0</lsb><msb>0</msb></field> | |
<field><name>pin1</name><lsb>1</lsb><msb>1</msb></field> | |
<field><name>pin2</name><lsb>2</lsb><msb>2</msb></field> | |
<field><name>pin3</name><lsb>3</lsb><msb>3</msb></field> | |
<field><name>pin4</name><lsb>4</lsb><msb>4</msb></field> | |
<field><name>pin5</name><lsb>5</lsb><msb>5</msb></field> | |
<field><name>pin6</name><lsb>6</lsb><msb>6</msb></field> | |
<field><name>pin7</name><lsb>7</lsb><msb>7</msb></field> | |
<field><name>pin8</name><lsb>8</lsb><msb>8</msb></field> | |
<field><name>pin9</name><lsb>9</lsb><msb>9</msb></field> | |
<field><name>pin10</name><lsb>10</lsb><msb>10</msb></field> | |
<field><name>pin11</name><lsb>11</lsb><msb>11</msb></field> | |
<field><name>pin12</name><lsb>12</lsb><msb>12</msb></field> | |
<field><name>pin13</name><lsb>13</lsb><msb>13</msb></field> | |
<field><name>pin14</name><lsb>14</lsb><msb>14</msb></field> | |
<field><name>pin15</name><lsb>15</lsb><msb>15</msb></field> | |
<field><name>pin16</name><lsb>16</lsb><msb>16</msb></field> | |
<field><name>pin17</name><lsb>17</lsb><msb>17</msb></field> | |
<field><name>pin18</name><lsb>18</lsb><msb>18</msb></field> | |
<field><name>pin19</name><lsb>19</lsb><msb>19</msb></field> | |
<field><name>pin20</name><lsb>20</lsb><msb>20</msb></field> | |
<field><name>pin21</name><lsb>21</lsb><msb>21</msb></field> | |
<field><name>pin22</name><lsb>22</lsb><msb>22</msb></field> | |
<field><name>pin23</name><lsb>23</lsb><msb>23</msb></field> | |
<field><name>pin24</name><lsb>24</lsb><msb>24</msb></field> | |
<field><name>pin25</name><lsb>25</lsb><msb>25</msb></field> | |
<field><name>pin26</name><lsb>26</lsb><msb>26</msb></field> | |
<field><name>pin27</name><lsb>27</lsb><msb>27</msb></field> | |
<field><name>pin28</name><lsb>28</lsb><msb>28</msb></field> | |
<field><name>pin29</name><lsb>29</lsb><msb>29</msb></field> | |
<field><name>pin30</name><lsb>30</lsb><msb>30</msb></field> | |
<field><name>pin31</name><lsb>31</lsb><msb>31</msb></field> | |
</fields> | |
</register> | |
<register> | |
<name>iof_en</name> | |
<description>HW I/O Function Enable Register</description> | |
<addressOffset>0x038</addressOffset> | |
<fields> | |
<field><name>pin0</name><lsb>0</lsb><msb>0</msb></field> | |
<field><name>pin1</name><lsb>1</lsb><msb>1</msb></field> | |
<field><name>pin2</name><lsb>2</lsb><msb>2</msb></field> | |
<field><name>pin3</name><lsb>3</lsb><msb>3</msb></field> | |
<field><name>pin4</name><lsb>4</lsb><msb>4</msb></field> | |
<field><name>pin5</name><lsb>5</lsb><msb>5</msb></field> | |
<field><name>pin6</name><lsb>6</lsb><msb>6</msb></field> | |
<field><name>pin7</name><lsb>7</lsb><msb>7</msb></field> | |
<field><name>pin8</name><lsb>8</lsb><msb>8</msb></field> | |
<field><name>pin9</name><lsb>9</lsb><msb>9</msb></field> | |
<field><name>pin10</name><lsb>10</lsb><msb>10</msb></field> | |
<field><name>pin11</name><lsb>11</lsb><msb>11</msb></field> | |
<field><name>pin12</name><lsb>12</lsb><msb>12</msb></field> | |
<field><name>pin13</name><lsb>13</lsb><msb>13</msb></field> | |
<field><name>pin14</name><lsb>14</lsb><msb>14</msb></field> | |
<field><name>pin15</name><lsb>15</lsb><msb>15</msb></field> | |
<field><name>pin16</name><lsb>16</lsb><msb>16</msb></field> | |
<field><name>pin17</name><lsb>17</lsb><msb>17</msb></field> | |
<field><name>pin18</name><lsb>18</lsb><msb>18</msb></field> | |
<field><name>pin19</name><lsb>19</lsb><msb>19</msb></field> | |
<field><name>pin20</name><lsb>20</lsb><msb>20</msb></field> | |
<field><name>pin21</name><lsb>21</lsb><msb>21</msb></field> | |
<field><name>pin22</name><lsb>22</lsb><msb>22</msb></field> | |
<field><name>pin23</name><lsb>23</lsb><msb>23</msb></field> | |
<field><name>pin24</name><lsb>24</lsb><msb>24</msb></field> | |
<field><name>pin25</name><lsb>25</lsb><msb>25</msb></field> | |
<field><name>pin26</name><lsb>26</lsb><msb>26</msb></field> | |
<field><name>pin27</name><lsb>27</lsb><msb>27</msb></field> | |
<field><name>pin28</name><lsb>28</lsb><msb>28</msb></field> | |
<field><name>pin29</name><lsb>29</lsb><msb>29</msb></field> | |
<field><name>pin30</name><lsb>30</lsb><msb>30</msb></field> | |
<field><name>pin31</name><lsb>31</lsb><msb>31</msb></field> | |
</fields> | |
</register> | |
<register> | |
<name>iof_sel</name> | |
<description>HW I/O Function Select Register</description> | |
<addressOffset>0x03C</addressOffset> | |
<fields> | |
<field> | |
<name>pin0</name><msb>0</msb><lsb>0</lsb> | |
<enumeratedValues> | |
<enumerateValue><name>IOF0</name><value>0</value></enumerateValue> | |
<enumerateValue><name>PWM0_0</name><value>1</value></enumerateValue> | |
</enumeratedValues> | |
</field> | |
<field> | |
<name>pin1</name><msb>1</msb><lsb>1</lsb> | |
<enumeratedValues> | |
<enumerateValue><name>IOF0</name><value>0</value></enumerateValue> | |
<enumerateValue><name>PWM0_1</name><value>1</value></enumerateValue> | |
</enumeratedValues> | |
</field> | |
<field> | |
<name>pin2</name><msb>2</msb><lsb>2</lsb> | |
<enumeratedValues> | |
<enumerateValue><name>QSPI1_SS0</name><value>0</value></enumerateValue> | |
<enumerateValue><name>PWM0_2</name><value>1</value></enumerateValue> | |
</enumeratedValues> | |
</field> | |
<field> | |
<name>pin3</name><msb>3</msb><lsb>3</lsb> | |
<enumeratedValues> | |
<enumerateValue><name>QSPI1_SD0</name><value>0</value></enumerateValue> | |
<enumerateValue><name>PWM0_3</name><value>1</value></enumerateValue> | |
</enumeratedValues> | |
</field> | |
<field> | |
<name>pin4</name><msb>4</msb><lsb>4</lsb> | |
<enumeratedValues> | |
<enumerateValue><name>QSPI1_SD1</name><value>0</value></enumerateValue> | |
<enumerateValue><name>IOF1</name><value>1</value></enumerateValue> | |
</enumeratedValues> | |
</field> | |
<field> | |
<name>pin5</name><msb>5</msb><lsb>5</lsb> | |
<enumeratedValues> | |
<enumerateValue><name>QSPI1_SCK</name><value>0</value></enumerateValue> | |
<enumerateValue><name>IOF1</name><value>1</value></enumerateValue> | |
</enumeratedValues> | |
</field> | |
<field> | |
<name>pin6</name><msb>6</msb><lsb>6</lsb> | |
<enumeratedValues> | |
<enumerateValue><name>QSPI1_SD2</name><value>0</value></enumerateValue> | |
<enumerateValue><name>IOF1</name><value>1</value></enumerateValue> | |
</enumeratedValues> | |
</field> | |
<field> | |
<name>pin7</name><msb>7</msb><lsb>7</lsb> | |
<enumeratedValues> | |
<enumerateValue><name>QSPI1_SD3</name><value>0</value></enumerateValue> | |
<enumerateValue><name>IOF1</name><value>1</value></enumerateValue> | |
</enumeratedValues> | |
</field> | |
<field> | |
<name>pin8</name><msb>8</msb><lsb>8</lsb> | |
<enumeratedValues> | |
<enumerateValue><name>QSPI1_SS1</name><value>0</value></enumerateValue> | |
<enumerateValue><name>IOF1</name><value>1</value></enumerateValue> | |
</enumeratedValues> | |
</field> | |
<field> | |
<name>pin9</name><msb>9</msb><lsb>9</lsb> | |
<enumeratedValues> | |
<enumerateValue><name>QSPI1_SS2</name><value>0</value></enumerateValue> | |
<enumerateValue><name>IOF1</name><value>1</value></enumerateValue> | |
</enumeratedValues> | |
</field> | |
<field> | |
<name>pin10</name><msb>10</msb><lsb>10</lsb> | |
<enumeratedValues> | |
<enumerateValue><name>QSPI1_SS3</name><value>0</value></enumerateValue> | |
<enumerateValue><name>PWM2_0</name><value>1</value></enumerateValue> | |
</enumeratedValues> | |
</field> | |
<field> | |
<name>pin11</name><msb>11</msb><lsb>11</lsb> | |
<enumeratedValues> | |
<enumerateValue><name>IOF0</name><value>0</value></enumerateValue> | |
<enumerateValue><name>PWM2_1</name><value>1</value></enumerateValue> | |
</enumeratedValues> | |
</field> | |
<field> | |
<name>pin12</name><msb>12</msb><lsb>12</lsb> | |
<enumeratedValues> | |
<enumerateValue><name>IOF0</name><value>0</value></enumerateValue> | |
<enumerateValue><name>PWM2_2</name><value>1</value></enumerateValue> | |
</enumeratedValues> | |
</field> | |
<field> | |
<name>pin13</name><msb>13</msb><lsb>13</lsb> | |
<enumeratedValues> | |
<enumerateValue><name>IOF0</name><value>0</value></enumerateValue> | |
<enumerateValue><name>PWM2_3</name><value>1</value></enumerateValue> | |
</enumeratedValues> | |
</field> | |
<field> | |
<name>pin14</name><msb>14</msb><lsb>14</lsb> | |
<enumeratedValues> | |
<enumerateValue><name>IOF0</name><value>0</value></enumerateValue> | |
<enumerateValue><name>IOF1</name><value>1</value></enumerateValue> | |
</enumeratedValues> | |
</field> | |
<field> | |
<name>pin15</name><msb>15</msb><lsb>15</lsb> | |
<enumeratedValues> | |
<enumerateValue><name>IOF0</name><value>0</value></enumerateValue> | |
<enumerateValue><name>IOF1</name><value>1</value></enumerateValue> | |
</enumeratedValues> | |
</field> | |
<field> | |
<name>pin16</name><msb>16</msb><lsb>16</lsb> | |
<enumeratedValues> | |
<enumerateValue><name>UART0_RX</name><value>0</value></enumerateValue> | |
<enumerateValue><name>IOF1</name><value>1</value></enumerateValue> | |
</enumeratedValues> | |
</field> | |
<field> | |
<name>pin17</name><msb>17</msb><lsb>17</lsb> | |
<enumeratedValues> | |
<enumerateValue><name>UART0_TX</name><value>0</value></enumerateValue> | |
<enumerateValue><name>IOF1</name><value>1</value></enumerateValue> | |
</enumeratedValues> | |
</field> | |
<field> | |
<name>pin18</name><msb>18</msb><lsb>18</lsb> | |
<enumeratedValues> | |
<enumerateValue><name>IOF0</name><value>0</value></enumerateValue> | |
<enumerateValue><name>IOF1</name><value>1</value></enumerateValue> | |
</enumeratedValues> | |
</field> | |
<field> | |
<name>pin19</name><msb>19</msb><lsb>19</lsb> | |
<enumeratedValues> | |
<enumerateValue><name>IOF0</name><value>0</value></enumerateValue> | |
<enumerateValue><name>PWM1_1</name><value>1</value></enumerateValue> | |
</enumeratedValues> | |
</field> | |
<field> | |
<name>pin20</name><msb>20</msb><lsb>20</lsb> | |
<enumeratedValues> | |
<enumerateValue><name>IOF0</name><value>0</value></enumerateValue> | |
<enumerateValue><name>PWM1_0</name><value>1</value></enumerateValue> | |
</enumeratedValues> | |
</field> | |
<field> | |
<name>pin21</name><msb>21</msb><lsb>21</lsb> | |
<enumeratedValues> | |
<enumerateValue><name>IOF0</name><value>0</value></enumerateValue> | |
<enumerateValue><name>PWM1_2</name><value>1</value></enumerateValue> | |
</enumeratedValues> | |
</field> | |
<field> | |
<name>pin22</name><msb>22</msb><lsb>22</lsb> | |
<enumeratedValues> | |
<enumerateValue><name>IOF0</name><value>0</value></enumerateValue> | |
<enumerateValue><name>PWM1_3</name><value>1</value></enumerateValue> | |
</enumeratedValues> | |
</field> | |
<field> | |
<name>pin23</name><msb>23</msb><lsb>23</lsb> | |
<enumeratedValues> | |
<enumerateValue><name>IOF0</name><value>0</value></enumerateValue> | |
<enumerateValue><name>IOF1</name><value>1</value></enumerateValue> | |
</enumeratedValues> | |
</field> | |
<field> | |
<name>pin24</name><msb>24</msb><lsb>24</lsb> | |
<enumeratedValues> | |
<enumerateValue><name>UART1_RX</name><value>0</value></enumerateValue> | |
<enumerateValue><name>IOF1</name><value>1</value></enumerateValue> | |
</enumeratedValues> | |
</field> | |
<field> | |
<name>pin25</name><msb>25</msb><lsb>25</lsb> | |
<enumeratedValues> | |
<enumerateValue><name>UART1_TX</name><value>0</value></enumerateValue> | |
<enumerateValue><name>IOF1</name><value>1</value></enumerateValue> | |
</enumeratedValues> | |
</field> | |
<field> | |
<name>pin26</name><msb>26</msb><lsb>26</lsb> | |
<enumeratedValues> | |
<enumerateValue><name>QSPI2_SS</name><value>0</value></enumerateValue> | |
<enumerateValue><name>IOF1</name><value>1</value></enumerateValue> | |
</enumeratedValues> | |
</field> | |
<field> | |
<name>pin27</name><msb>27</msb><lsb>27</lsb> | |
<enumeratedValues> | |
<enumerateValue><name>QSPI2_SD0</name><value>0</value></enumerateValue> | |
<enumerateValue><name>IOF1</name><value>1</value></enumerateValue> | |
</enumeratedValues> | |
</field> | |
<field> | |
<name>pin28</name><msb>28</msb><lsb>28</lsb> | |
<enumeratedValues> | |
<enumerateValue><name>QSPI2_SD1</name><value>0</value></enumerateValue> | |
<enumerateValue><name>IOF1</name><value>1</value></enumerateValue> | |
</enumeratedValues> | |
</field> | |
<field> | |
<name>pin29</name><msb>29</msb><lsb>29</lsb> | |
<enumeratedValues> | |
<enumerateValue><name>QSPI2_SCK</name><value>0</value></enumerateValue> | |
<enumerateValue><name>IOF1</name><value>1</value></enumerateValue> | |
</enumeratedValues> | |
</field> | |
<field> | |
<name>pin30</name><msb>30</msb><lsb>30</lsb> | |
<enumeratedValues> | |
<enumerateValue><name>QSPI2_SD2</name><value>0</value></enumerateValue> | |
<enumerateValue><name>IOF1</name><value>1</value></enumerateValue> | |
</enumeratedValues> | |
</field> | |
<field> | |
<name>pin31</name><msb>31</msb><lsb>31</lsb> | |
<enumeratedValues> | |
<enumerateValue><name>QSPI2_SD3</name><value>0</value></enumerateValue> | |
<enumerateValue><name>IOF1</name><value>1</value></enumerateValue> | |
</enumeratedValues> | |
</field> | |
</fields> | |
</register> | |
<register> | |
<name>out_xor</name> | |
<description>Output XOR (invert) Register</description> | |
<addressOffset>0x040</addressOffset> | |
<fields> | |
<field><name>pin0</name><lsb>0</lsb><msb>0</msb></field> | |
<field><name>pin1</name><lsb>1</lsb><msb>1</msb></field> | |
<field><name>pin2</name><lsb>2</lsb><msb>2</msb></field> | |
<field><name>pin3</name><lsb>3</lsb><msb>3</msb></field> | |
<field><name>pin4</name><lsb>4</lsb><msb>4</msb></field> | |
<field><name>pin5</name><lsb>5</lsb><msb>5</msb></field> | |
<field><name>pin6</name><lsb>6</lsb><msb>6</msb></field> | |
<field><name>pin7</name><lsb>7</lsb><msb>7</msb></field> | |
<field><name>pin8</name><lsb>8</lsb><msb>8</msb></field> | |
<field><name>pin9</name><lsb>9</lsb><msb>9</msb></field> | |
<field><name>pin10</name><lsb>10</lsb><msb>10</msb></field> | |
<field><name>pin11</name><lsb>11</lsb><msb>11</msb></field> | |
<field><name>pin12</name><lsb>12</lsb><msb>12</msb></field> | |
<field><name>pin13</name><lsb>13</lsb><msb>13</msb></field> | |
<field><name>pin14</name><lsb>14</lsb><msb>14</msb></field> | |
<field><name>pin15</name><lsb>15</lsb><msb>15</msb></field> | |
<field><name>pin16</name><lsb>16</lsb><msb>16</msb></field> | |
<field><name>pin17</name><lsb>17</lsb><msb>17</msb></field> | |
<field><name>pin18</name><lsb>18</lsb><msb>18</msb></field> | |
<field><name>pin19</name><lsb>19</lsb><msb>19</msb></field> | |
<field><name>pin20</name><lsb>20</lsb><msb>20</msb></field> | |
<field><name>pin21</name><lsb>21</lsb><msb>21</msb></field> | |
<field><name>pin22</name><lsb>22</lsb><msb>22</msb></field> | |
<field><name>pin23</name><lsb>23</lsb><msb>23</msb></field> | |
<field><name>pin24</name><lsb>24</lsb><msb>24</msb></field> | |
<field><name>pin25</name><lsb>25</lsb><msb>25</msb></field> | |
<field><name>pin26</name><lsb>26</lsb><msb>26</msb></field> | |
<field><name>pin27</name><lsb>27</lsb><msb>27</msb></field> | |
<field><name>pin28</name><lsb>28</lsb><msb>28</msb></field> | |
<field><name>pin29</name><lsb>29</lsb><msb>29</msb></field> | |
<field><name>pin30</name><lsb>30</lsb><msb>30</msb></field> | |
<field><name>pin31</name><lsb>31</lsb><msb>31</msb></field> | |
</fields> | |
</register> | |
</registers> | |
<interrupt> | |
<name>GPIO0</name> | |
<value>8</value> | |
</interrupt> | |
<interrupt> | |
<name>GPIO1</name> | |
<value>9</value> | |
</interrupt> | |
<interrupt> | |
<name>GPIO2</name> | |
<value>10</value> | |
</interrupt> | |
<interrupt> | |
<name>GPIO3</name> | |
<value>11</value> | |
</interrupt> | |
<interrupt> | |
<name>GPIO4</name> | |
<value>12</value> | |
</interrupt> | |
<interrupt> | |
<name>GPIO5</name> | |
<value>13</value> | |
</interrupt> | |
<interrupt> | |
<name>GPIO6</name> | |
<value>14</value> | |
</interrupt> | |
<interrupt> | |
<name>GPIO7</name> | |
<value>15</value> | |
</interrupt> | |
<interrupt> | |
<name>GPIO8</name> | |
<value>16</value> | |
</interrupt> | |
<interrupt> | |
<name>GPIO9</name> | |
<value>17</value> | |
</interrupt> | |
<interrupt> | |
<name>GPIO10</name> | |
<value>18</value> | |
</interrupt> | |
<interrupt> | |
<name>GPIO11</name> | |
<value>19</value> | |
</interrupt> | |
<interrupt> | |
<name>GPIO12</name> | |
<value>20</value> | |
</interrupt> | |
<interrupt> | |
<name>GPIO13</name> | |
<value>21</value> | |
</interrupt> | |
<interrupt> | |
<name>GPIO14</name> | |
<value>22</value> | |
</interrupt> | |
<interrupt> | |
<name>GPIO15</name> | |
<value>23</value> | |
</interrupt> | |
<interrupt> | |
<name>GPIO16</name> | |
<value>24</value> | |
</interrupt> | |
<interrupt> | |
<name>GPIO17</name> | |
<value>25</value> | |
</interrupt> | |
<interrupt> | |
<name>GPIO18</name> | |
<value>26</value> | |
</interrupt> | |
<interrupt> | |
<name>GPIO19</name> | |
<value>27</value> | |
</interrupt> | |
<interrupt> | |
<name>GPIO20</name> | |
<value>28</value> | |
</interrupt> | |
<interrupt> | |
<name>GPIO21</name> | |
<value>29</value> | |
</interrupt> | |
<interrupt> | |
<name>GPIO22</name> | |
<value>30</value> | |
</interrupt> | |
<interrupt> | |
<name>GPIO23</name> | |
<value>31</value> | |
</interrupt> | |
<interrupt> | |
<name>GPIO24</name> | |
<value>32</value> | |
</interrupt> | |
<interrupt> | |
<name>GPIO25</name> | |
<value>33</value> | |
</interrupt> | |
<interrupt> | |
<name>GPIO26</name> | |
<value>34</value> | |
</interrupt> | |
<interrupt> | |
<name>GPIO27</name> | |
<value>35</value> | |
</interrupt> | |
<interrupt> | |
<name>GPIO28</name> | |
<value>36</value> | |
</interrupt> | |
<interrupt> | |
<name>GPIO29</name> | |
<value>37</value> | |
</interrupt> | |
<interrupt> | |
<name>GPIO30</name> | |
<value>38</value> | |
</interrupt> | |
<interrupt> | |
<name>GPIO31</name> | |
<value>39</value> | |
</interrupt> | |
</peripheral> | |
<!-- GPIO0 --> | |
<!-- UART0 --> | |
<peripheral> | |
<name>UART0</name> | |
<baseAddress>0x10013000</baseAddress> | |
<groupName>UART</groupName> | |
<description>Universal Asynchronous Receiver Transmitter</description> | |
<registers> | |
<!-- Data Registers --> | |
<register> | |
<name>txdata</name> | |
<description>Transmit Data Register</description> | |
<addressOffset>0x00</addressOffset> | |
<fields> | |
<field><name>full</name><msb>31</msb><lsb>31</lsb></field> | |
<field><name>data</name><msb>7</msb><lsb>0</lsb></field> | |
</fields> | |
</register> | |
<register> | |
<name>rxdata</name> | |
<description>Receive Data Register</description> | |
<addressOffset>0x04</addressOffset> | |
<fields> | |
<field><name>empty</name><msb>31</msb><lsb>31</lsb></field> | |
<field><name>data</name><msb>7</msb><lsb>0</lsb></field> | |
</fields> | |
</register> | |
<!-- Data Registers --> | |
<!-- Control Registers --> | |
<register> | |
<name>txctrl</name> | |
<description>Transmit Control Register</description> | |
<addressOffset>0x08</addressOffset> | |
<fields> | |
<field><name>counter</name><msb>18</msb><lsb>16</lsb></field> | |
<field><name>nstop</name><msb>1</msb><lsb>1</lsb></field> | |
<field><name>enable</name><msb>0</msb><lsb>0</lsb></field> | |
</fields> | |
</register> | |
<register> | |
<name>rxctrl</name> | |
<description>Receive Control Register</description> | |
<addressOffset>0x0C</addressOffset> | |
<fields> | |
<field><name>counter</name><msb>18</msb><lsb>16</lsb></field> | |
<field><name>enable</name><msb>0</msb><lsb>0</lsb></field> | |
</fields> | |
</register> | |
<!-- Control Registers --> | |
<!-- Interrupt Registers --> | |
<register> | |
<name>ie</name> | |
<description>Interrupt Enable Register</description> | |
<addressOffset>0x10</addressOffset> | |
<fields> | |
<field><name>rxwm</name><msb>1</msb><lsb>1</lsb></field> | |
<field><name>txwm</name><msb>0</msb><lsb>0</lsb></field> | |
</fields> | |
</register> | |
<register> | |
<name>ip</name> | |
<description>Interrupt Pending Register</description> | |
<addressOffset>0x14</addressOffset> | |
<fields> | |
<field><name>rxwm</name><msb>1</msb><lsb>1</lsb></field> | |
<field><name>txwm</name><msb>0</msb><lsb>0</lsb></field> | |
</fields> | |
</register> | |
<!-- Interrupt Registers --> | |
<!-- Configuration Registers --> | |
<register> | |
<name>div</name> | |
<description>Baud Rate Divisor Register</description> | |
<addressOffset>0x18</addressOffset> | |
<fields> | |
<field><name>value</name><msb>15</msb><lsb>0</lsb></field> | |
</fields> | |
</register> | |
<!-- Configuration Registers --> | |
</registers> | |
<interrupt> | |
<name>UART0</name> | |
<value>3</value> | |
</interrupt> | |
</peripheral> | |
<!-- UART0 --> | |
<!-- QSPI0 --> | |
<peripheral> | |
<name>QSPI0</name> | |
<baseAddress>0x10014000</baseAddress> | |
<groupName>QSPI</groupName> | |
<description>Quad Serial Peripheral Interface</description> | |
<registers> | |
<register> | |
<name>div</name> | |
<description>Serial Clock Divisor Register</description> | |
<addressOffset>0x00</addressOffset> | |
<fields> | |
<field><name>value</name><msb>11</msb><lsb>0</lsb></field> | |
</fields> | |
</register> | |
<register> | |
<name>mode</name> | |
<description>Serial Clock Mode Register</description> | |
<addressOffset>0x04</addressOffset> | |
<fields> | |
<field><name>polarity</name><msb>1</msb><lsb>1</lsb></field> | |
<field><name>phase</name><msb>0</msb><lsb>0</lsb></field> | |
</fields> | |
</register> | |
<register> | |
<name>csid</name> | |
<description>Chip Select ID Register</description> | |
<addressOffset>0x10</addressOffset> | |
</register> | |
<register> | |
<name>csdef</name> | |
<description>Chip Select Default Register</description> | |
<addressOffset>0x14</addressOffset> | |
<resetValue>0xFFFF</resetValue> | |
</register> | |
<register> | |
<name>csmode</name> | |
<description>Chip Select Mode Register</description> | |
<addressOffset>0x18</addressOffset> | |
<enumeratedValues> | |
<enumeratedValue> | |
<name>Auto</name> | |
<description> | |
Assert/de-assert CS at the beginning/end of each frame. | |
</description> | |
<value>0</value> | |
</enumeratedValue> | |
<enumeratedValue> | |
<name>Hold</name> | |
<description> | |
Keep CS continuously asserted after the initial frame. | |
</description> | |
<value>2</value> | |
</enumeratedValue> | |
<enumeratedValue> | |
<name>Off</name> | |
<description>Disable hardware control of the CS pin.</description> | |
<value>3</value> | |
</enumeratedValue> | |
</enumeratedValues> | |
</register> | |
<register> | |
<name>delay0</name> | |
<description>Delay Control 0 Register</description> | |
<addressOffset>0x28</addressOffset> | |
<fields> | |
<field><name>sckcs</name><msb>23</msb><lsb>16</lsb></field> | |
<field><name>cssck</name><msb>7</msb><lsb>0</lsb></field> | |
</fields> | |
</register> | |
<register> | |
<name>delay1</name> | |
<description>Delay Control 1 Register</description> | |
<addressOffset>0x2C</addressOffset> | |
<fields> | |
<field><name>interxfr</name><msb>23</msb><lsb>16</lsb></field> | |
<field><name>intercs</name><msb>7</msb><lsb>0</lsb></field> | |
</fields> | |
</register> | |
<register> | |
<name>fmt</name> | |
<description>Frame Format Register</description> | |
<addressOffset>0x40</addressOffset> | |
<fields> | |
<field><name>length</name><msb>19</msb><lsb>16</lsb></field> | |
<field> | |
<name>direction</name> | |
<msb>3</msb><lsb>3</lsb> | |
<enumeratedValues> | |
<enumeratedValue> | |
<name>Rx</name> | |
<description> | |
For dual and quad protocols, the DQ pins are tri-stated. For | |
the single protocol, the DQ0 pin is driven with the transmit | |
data as normal. | |
</description> | |
<value>0</value> | |
</enumeratedValue> | |
<enumeratedValue> | |
<name>Tx</name> | |
<description>The receive FIFO is not populated.</description> | |
<value>1</value> | |
</enumeratedValue> | |
</enumeratedValues> | |
</field> | |
<field> | |
<name>endian</name> | |
<msb>2</msb><lsb>2</lsb> | |
<enumeratedValues> | |
<enumerateValue> | |
<name>Big</name> | |
<description>Transmit MSB first.</description> | |
<value>0</value> | |
</enumerateValue> | |
<enumerateValue> | |
<name>Little</name> | |
<description>Transmit LSB first.</description> | |
<value>1</value> | |
</enumerateValue> | |
</enumeratedValues> | |
</field> | |
<field> | |
<name>protocol</name> | |
<msb>1</msb><lsb>0</lsb> | |
<enumeratedValues> | |
<enumerateValue> | |
<name>Single</name> | |
<description>DQ0 (MOSI), DQ1 (MISO)</description> | |
<value>0</value> | |
</enumerateValue> | |
<enumerateValue> | |
<name>Dual</name> | |
<description>DQ0, DQ1</description> | |
<value>1</value> | |
</enumerateValue> | |
<enumerateValue> | |
<name>Quad</name> | |
<description>DQ0, DQ1, DQ2, DQ3</description> | |
<value>2</value> | |
</enumerateValue> | |
</enumeratedValues> | |
</field> | |
</fields> | |
</register> | |
<register> | |
<name>txdata</name> | |
<description>Transmit Data Register</description> | |
<addressOffset>0x48</addressOffset> | |
<fields> | |
<field><name>full</name><msb>31</msb><lsb>31</lsb></field> | |
<field><name>data</name><msb>7</msb><lsb>0</lsb></field> | |
</fields> | |
</register> | |
<register> | |
<name>rxdata</name> | |
<description>Receive Data Register</description> | |
<addressOffset>0x4C</addressOffset> | |
<fields> | |
<field><name>empty</name><msb>31</msb><lsb>31</lsb></field> | |
<field><name>data</name><msb>7</msb><lsb>0</lsb></field> | |
</fields> | |
</register> | |
<register> | |
<name>txmark</name> | |
<description>Transmit Watermark Register</description> | |
<addressOffset>0x50</addressOffset> | |
<fields> | |
<field><name>value</name><msb>2</msb><lsb>0</lsb></field> | |
</fields> | |
</register> | |
<register> | |
<name>rxmark</name> | |
<description>Receive Watermark Register</description> | |
<addressOffset>0x54</addressOffset> | |
<fields> | |
<field><name>value</name><msb>2</msb><lsb>0</lsb></field> | |
</fields> | |
</register> | |
<register> | |
<name>fctrl</name> | |
<description>SPI Flash Interface Control Register</description> | |
<addressOffset>0x60</addressOffset> | |
<fields> | |
<field><name>enable</name><msb>0</msb><lsb>0</lsb></field> | |
</fields> | |
</register> | |
<register> | |
<name>ffmt</name> | |
<description>SPI Flash Instruction Format Register</description> | |
<addressOffset>0x64</addressOffset> | |
<fields> | |
<field> | |
<name>pad_code</name> | |
<msb>31</msb><lsb>24</lsb> | |
<description>First 8 bits to transmit during dummy cycles</description> | |
<resetValue>0x00</resetValue> | |
</field> | |
<field> | |
<name>cmd_code</name> | |
<msb>23</msb><lsb>16</lsb> | |
<description>Value of command byte</description> | |
<resetValue>0x03</resetValue> | |
</field> | |
<field> | |
<name>data_proto</name> | |
<msb>13</msb><lsb>12</lsb> | |
<description>Protocol for receiving data bytes</description> | |
<resetValue>0x0</resetValue> | |
<enumeratedValues> | |
<enumerateValue> | |
<name>Single</name> | |
<description>DQ0 (MOSI), DQ1 (MISO)</description> | |
<value>0</value> | |
</enumerateValue> | |
<enumerateValue> | |
<name>Dual</name> | |
<description>DQ0, DQ1</description> | |
<value>1</value> | |
</enumerateValue> | |
<enumerateValue> | |
<name>Quad</name> | |
<description>DQ0, DQ1, DQ2, DQ3</description> | |
<value>2</value> | |
</enumerateValue> | |
</enumeratedValues> | |
</field> | |
<field> | |
<name>addr_proto</name> | |
<msb>11</msb><lsb>10</lsb> | |
<description>Protocol for transmitting address and padding</description> | |
<resetValue>0x0</resetValue> | |
<enumeratedValues> | |
<enumerateValue> | |
<name>Single</name> | |
<description>DQ0 (MOSI), DQ1 (MISO)</description> | |
<value>0</value> | |
</enumerateValue> | |
<enumerateValue> | |
<name>Dual</name> | |
<description>DQ0, DQ1</description> | |
<value>1</value> | |
</enumerateValue> | |
<enumerateValue> | |
<name>Quad</name> | |
<description>DQ0, DQ1, DQ2, DQ3</description> | |
<value>2</value> | |
</enumerateValue> | |
</enumeratedValues> | |
</field> | |
<field> | |
<name>cmd_proto</name> | |
<msb>9</msb><lsb>8</lsb> | |
<description>Protocol for transmitting command</description> | |
<resetValue>0x0</resetValue> | |
<enumeratedValues> | |
<enumerateValue> | |
<name>Single</name> | |
<description>DQ0 (MOSI), DQ1 (MISO)</description> | |
<value>0</value> | |
</enumerateValue> | |
<enumerateValue> | |
<name>Dual</name> | |
<description>DQ0, DQ1</description> | |
<value>1</value> | |
</enumerateValue> | |
<enumerateValue> | |
<name>Quad</name> | |
<description>DQ0, DQ1, DQ2, DQ3</description> | |
<value>2</value> | |
</enumerateValue> | |
</enumeratedValues> | |
</field> | |
<field> | |
<name>pad_cnt</name> | |
<msb>0</msb><lsb>0</lsb> | |
<description>Number of dummy cycles</description> | |
<resetValue>0x0</resetValue> | |
</field> | |
<field> | |
<name>addr_len</name> | |
<msb>3</msb><lsb>1</lsb> | |
<description>Number of address bytes (0 to 4)</description> | |
<resetValue>0x3</resetValue> | |
</field> | |
<field> | |
<name>cmd_en</name> | |
<msb>0</msb><lsb>0</lsb> | |
<description>Enable sending of command</description> | |
<resetValue>0x1</resetValue> | |
</field> | |
</fields> | |
</register> | |
<register> | |
<name>ie</name> | |
<description>SPI Interrupt Enable Register</description> | |
<addressOffset>0x70</addressOffset> | |
<fields> | |
<field><name>rxwm</name><msb>1</msb><lsb>1</lsb></field> | |
<field><name>txwm</name><msb>0</msb><lsb>0</lsb></field> | |
</fields> | |
</register> | |
<register> | |
<name>ip</name> | |
<description>SPI Interrupt Pending Register</description> | |
<addressOffset>0x74</addressOffset> | |
<fields> | |
<field><name>rxwm</name><msb>1</msb><lsb>1</lsb></field> | |
<field><name>txwm</name><msb>0</msb><lsb>0</lsb></field> | |
</fields> | |
</register> | |
</registers> | |
<interrupt> | |
<name>QSPI0</name> | |
<value>5</value> | |
</interrupt> | |
</peripheral> | |
<!-- QSPI0 --> | |
<!-- PWM0 --> | |
<peripheral> | |
<name>PWM0</name> | |
<baseAddress>0x10015000</baseAddress> | |
<groupName>PWM</groupName> | |
<description>8-bit timer with 4 cmp</description> | |
<registers> | |
<register> | |
<name>cfg</name> | |
<description>PWM Configuration Register</description> | |
<addressOffset>0x00</addressOffset> | |
<fields> | |
<field><name>cmp3ip</name><msb>31</msb><lsb>31</lsb></field> | |
<field><name>cmp2ip</name><msb>30</msb><lsb>30</lsb></field> | |
<field><name>cmp1ip</name><msb>29</msb><lsb>29</lsb></field> | |
<field><name>cmp0ip</name><msb>28</msb><lsb>28</lsb></field> | |
<field><name>cmp3gang</name><msb>27</msb><lsb>27</lsb></field> | |
<field><name>cmp2gang</name><msb>36</msb><lsb>26</lsb></field> | |
<field><name>cmp1gang</name><msb>25</msb><lsb>25</lsb></field> | |
<field><name>cmp0gang</name><msb>24</msb><lsb>24</lsb></field> | |
<field><name>cmp3center</name><msb>19</msb><lsb>19</lsb></field> | |
<field><name>cmp2center</name><msb>18</msb><lsb>18</lsb></field> | |
<field><name>cmp1center</name><msb>17</msb><lsb>17</lsb></field> | |
<field><name>cmp0center</name><msb>16</msb><lsb>16</lsb></field> | |
<field> | |
<name>enable</name> | |
<msb>13</msb><lsb>12</lsb> | |
<enumeratedValues> | |
<enumeratedValue> | |
<name>OneShot</name> | |
<description>Increments counter until overflow.</description> | |
<value>2</value> | |
</enumeratedValue> | |
<enumeratedValue> | |
<name>Always</name> | |
<description>Increments counter.</description> | |
<value>1</value> | |
</enumeratedValue> | |
<enumeratedValue> | |
<name>Off</name> | |
<description>Doesn't increment counter.</description> | |
<value>0</value> | |
</enumeratedValue> | |
</enumeratedValues> | |
</field> | |
<field><name>deglitch</name><msb>10</msb><lsb>10</lsb></field> | |
<field><name>zerocmp</name><msb>9</msb><lsb>9</lsb></field> | |
<field><name>sticky</name><msb>8</msb><lsb>8</lsb></field> | |
<field><name>scale</name><msb>3</msb><lsb>0</lsb></field> | |
</fields> | |
</register> | |
<register> | |
<name>count</name> | |
<description>Counter Register</description> | |
<addressOffset>0x04</addressOffset> | |
</register> | |
<register> | |
<name>pwms</name> | |
<description>Scaled Halfword Counter Register</description> | |
<addressOffset>0x10</addressOffset> | |
</register> | |
<register> | |
<name>cmp0</name> | |
<description>Compare Register</description> | |
<addressOffset>0x20</addressOffset> | |
<fields> | |
<field><name>value</name><msb>15</msb><lsb>0</lsb></field> | |
</fields> | |
</register> | |
<register> | |
<name>cmp1</name> | |
<description>Compare Register</description> | |
<addressOffset>0x24</addressOffset> | |
<fields> | |
<field><name>value</name><msb>15</msb><lsb>0</lsb></field> | |
</fields> | |
</register> | |
<register> | |
<name>cmp2</name> | |
<description>Compare Register</description> | |
<addressOffset>0x28</addressOffset> | |
<fields> | |
<field><name>value</name><msb>15</msb><lsb>0</lsb></field> | |
</fields> | |
</register> | |
<register> | |
<name>cmp3</name> | |
<description>Compare Register</description> | |
<addressOffset>0x2C</addressOffset> | |
<fields> | |
<field><name>value</name><msb>15</msb><lsb>0</lsb></field> | |
</fields> | |
</register> | |
</registers> | |
<interrupt> | |
<name>PWM0CMP0</name> | |
<value>40</value> | |
</interrupt> | |
<interrupt> | |
<name>PWM0CMP1</name> | |
<value>41</value> | |
</interrupt> | |
<interrupt> | |
<name>PWM0CMP2</name> | |
<value>42</value> | |
</interrupt> | |
<interrupt> | |
<name>PWM0CMP3</name> | |
<value>43</value> | |
</interrupt> | |
</peripheral> | |
<!-- PWM0 --> | |
<!-- UART1 --> | |
<peripheral derivedFrom="UART0"> | |
<name>UART1</name> | |
<baseAddress>0x10023000</baseAddress> | |
<interrupt> | |
<name>UART1</name> | |
<value>4</value> | |
</interrupt> | |
</peripheral> | |
<!-- UART1 --> | |
<!-- QSPI1 --> | |
<peripheral derivedFrom="QSPI0"> | |
<name>QSPI1</name> | |
<baseAddress>0x10024000</baseAddress> | |
<interrupt> | |
<name>QSPI1</name> | |
<value>6</value> | |
</interrupt> | |
</peripheral> | |
<!-- QSPI1 --> | |
<!-- PWM1 --> | |
<peripheral derivedFrom="PWM0"> | |
<name>PWM1</name> | |
<baseAddress>0x10025000</baseAddress> | |
<interrupt> | |
<name>PWM1Cmp0</name> | |
<value>44</value> | |
</interrupt> | |
<interrupt> | |
<name>PWM1CMP1</name> | |
<value>45</value> | |
</interrupt> | |
<interrupt> | |
<name>PWM1CMP2</name> | |
<value>46</value> | |
</interrupt> | |
<interrupt> | |
<name>PWM1CMP3</name> | |
<value>47</value> | |
</interrupt> | |
</peripheral> | |
<!-- PWM1 --> | |
<!-- QSPI2 --> | |
<peripheral derivedFrom="QSPI0"> | |
<name>QSPI2</name> | |
<baseAddress>0x10034000</baseAddress> | |
<interrupt> | |
<name>QSPI2</name> | |
<value>7</value> | |
</interrupt> | |
</peripheral> | |
<!-- QSPI2 --> | |
<!-- PWM2 --> | |
<peripheral derivedFrom="PWM0"> | |
<name>PWM2</name> | |
<baseAddress>0x10035000</baseAddress> | |
<interrupt> | |
<name>PWM2CMP0</name> | |
<value>48</value> | |
</interrupt> | |
<interrupt> | |
<name>PWM2CMP1</name> | |
<value>49</value> | |
</interrupt> | |
<interrupt> | |
<name>PWM2CMP2</name> | |
<value>50</value> | |
</interrupt> | |
<interrupt> | |
<name>PWM2CMP3</name> | |
<value>51</value> | |
</interrupt> | |
</peripheral> | |
<!-- PWM2 --> | |
</peripherals> | |
</device> |
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