Created
November 14, 2018 09:16
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Sample Blink Test for e-Gizmo FPGA
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library IEEE; | |
use IEEE.STD_LOGIC_1164.ALL; | |
--use IEEE.STD_LOGIC_ARITH.ALL; | |
--use IEEE.STD_LOGIC_UNSIGNED.ALL; | |
library machxo2; | |
use machxo2.all; | |
entity blinky is | |
Port ( led_out : out std_logic); | |
end blinky; | |
architecture behavioral of blinky is | |
component OSCH | |
-- synthesis translate_off | |
generic (NOM_FREQ: string := "2.08"); | |
-- synthesis translate_on | |
port ( STDBY : in std_logic; | |
OSC : out std_logic; | |
SEDSTDBY :out std_logic); | |
end component; | |
attribute NOM_FREQ : string; | |
attribute NOM_FREQ of OSCinst0 : label is "2.08"; | |
signal osc_int : std_logic; | |
signal stdby_sed : std_logic; | |
component CLKDIVC | |
generic ( DIV : string; | |
GSR : string); | |
port ( RST: in std_logic; | |
CLKI: in std_logic; | |
ALIGNWD: in std_logic; | |
CDIV1: out std_logic; | |
CDIVX : out std_logic); | |
end component; | |
signal clock_div1 : std_logic; | |
signal clock_divx : std_logic; | |
begin | |
OSCInst0: OSCH | |
-- synthesis translate_off | |
generic map( NOM_FREQ => "2.08" ) | |
-- synthesis translate_on | |
port map ( STDBY => '0', | |
OSC => osc_int, | |
SEDSTDBY => stdby_sed); | |
clock_div: CLKDIVC | |
generic map ( DIV => "4.0", | |
GSR => "DISABLED") | |
port map ( RST => '0', | |
CLKI => osc_int, | |
ALIGNWD => '0', | |
CDIV1 => clock_div1, | |
CDIVX => clock_divx); -- outputs 0.520000 MHz | |
process (clock_divx) | |
variable clockDelay : integer range 0 to 520000 := 0; | |
begin | |
if clock_divx'event and clock_divx = '1' then | |
clockDelay := clockDelay + 1; | |
if clockDelay = 0 then | |
led_out <= '1'; | |
elsif clockDelay = 260000 then | |
led_out <= '0'; | |
end if; | |
end if; | |
end process; | |
end behavioral; |
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