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@ebal5
Last active January 28, 2016 15:53
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作ったはいいけど思った通りの動作をしてくれない子。馬鹿な子ほど可愛いというけれども……
// module stack
// it is submodule of pc
module stack(clk, en, pu_po, qi, qo);
parameter WIDTH = 9;
input clk, en, pu_po;
input [WIDTH-1:0] qi;
output [WIDTH-1:0] qo;
reg [WIDTH-1:0] qo;
reg [WIDTH-1:0] s1,s2;
always @(posedge clk)
begin
if(en == 1)
begin
// if(pu_po == 1)
// begin
// s2 <= s1;
// s1 <= qi;
// end
// else if(pu_po == 0)
// begin
// $display("test2");
// qo <= s1;
// s1 <= s2;
// end
case (pu_po)
1:
begin
$display("test1");
s2 <= s1;
s1 <= qi;
end
0:
begin
$display("test2");
qo <= s1;
s1 <= s2;
end
endcase
end
end // always @ (posedge clk)
initial qo <= 0;
endmodule // stack
// module stack_tp
// test bench for stack module.
`timescale 1ms/1ms
module stack_tp;
parameter WIDTH = 9;
parameter STEP = 10;
wire [WIDTH-1:0] qo;
reg [WIDTH-1:0] qi;
reg en,pu_po;
reg clk;
stack stack0(clk, en, pu_po, qi, qo);
always begin
#(STEP/2) clk = 1;
#(STEP/2) clk = 0;
end
initial begin
$dumpfile("stack.vcd");
$dumpvars(0, stack0);
$monitor("en: %b, pu_po: %b, qi: %h, qo: %h",en, pu_po, qi, qo);
end
initial begin
en <= 1;
pu_po <= 1;
qi <= 9'h13f;
repeat (1) @(posedge clk);
en <= 1;
qi <= 9'h03d;
repeat (1) @(posedge clk);
pu_po <= 0;
en <= 1;
repeat (2) @(posedge clk);
en <= 1;
pu_po <= 1;
qi <= 9'h099;
repeat (1) @(posedge clk);
en <= 1;
pu_po <= 0;
repeat (1) @(posedge clk);
en <= 1;
pu_po <= 1;
qi <= 9'h077;
repeat (1) @(posedge clk);
$finish;
end // initial begin
endmodule // stack_tp
@ebal5
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ebal5 commented Jan 28, 2016

if文は私にとって裏切りの言葉だったらしいな。case でまともに書いたら動作した。どういうことなの???

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