rr.diff

diff --git a/src/PerfCounters.cc b/src/PerfCounters.cc
index e3b7010..0681714 100644
--- a/src/PerfCounters.cc
+++ b/src/PerfCounters.cc
@@ -43,7 +43,9 @@ enum CpuMicroarch {
   IntelSandyBridge,
   IntelIvyBridge,
   IntelHaswell,
-  IntelBroadwell
+  IntelBroadwell,
+
+  AMDPiledriver
 };
 
 struct PmuConfig {
@@ -66,6 +68,8 @@ static const PmuConfig pmu_configs[] = {
   { IntelWestmere, "Intel Westmere", 0x5101c4, 0x5100c0, 0x50011d, true },
   { IntelPenryn, "Intel Penryn", 0, 0, 0, false },
   { IntelMerom, "Intel Merom", 0, 0, 0, false },
+
+  { AMDPiledriver, "AMD Piledriver", 0x5100c4, 0x5100c0, 0x5300cf, true }
 };
 
 static string lowercase(const string& s) {
@@ -93,6 +97,19 @@ static CpuMicroarch get_cpu_microarch() {
   }
 
   unsigned int cpu_type, eax, ecx, edx;
+  cpuid(CPUID_GETVENDORSTRING, 0, &eax, &ecx, &edx);
+  if (edx == 0x69746e65 && ecx == 0x444d4163) {
+      cpuid(CPUID_GETFEATURES, 0, &eax, &ecx, &edx);
+      cpu_type = (eax & 0xFF0FF0);
+      switch (cpu_type) {
+          case 0x600f20:
+              return AMDPiledriver;
+        default:
+          FATAL() << "CPU " << HEX(cpu_type) << " unknown AMD.";
+          return UnknownCpu; // not reached
+      }
+  }
+
   cpuid(CPUID_GETFEATURES, 0, &eax, &ecx, &edx);
   cpu_type = (eax & 0xF0FF0);
   switch (cpu_type) {
diff --git a/src/task.cc b/src/task.cc
index b0e5dd7..bf65be5 100644
--- a/src/task.cc
+++ b/src/task.cc
@@ -1311,9 +1311,10 @@ const ExtraRegisters& Task::extra_regs() {
       struct iovec vec = { extra_registers.data.data(),
                            extra_registers.data.size() };
       xptrace(PTRACE_GETREGSET, NT_X86_XSTATE, &vec);
-      ASSERT(this, vec.iov_len == xsave_area_size)
+      ASSERT(this, vec.iov_len <= xsave_area_size)
           << "Didn't get enough register data; expected " << xsave_area_size
           << " but got " << vec.iov_len;
+      extra_registers.data.resize(vec.iov_len);
     } else {
 #if defined(__i386__)
       LOG(debug) << "  (refreshing extra-register cache using FPXREGS)";