Created
November 26, 2015 22:31
-
-
Save edwintorok/48b767542b50cdbb3b34 to your computer and use it in GitHub Desktop.
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Generating results for AMD Fam15h machine #3 | |
Hostname: debian | |
Kernel: Linux 4.2.0-0.bpo.1-amd64 | |
Interface: perf_event | |
CPU: 21/2/0 | |
CPU type: fam15h | |
CPU name: AMD FX(tm)-8350 Eight-Core Processor | |
data gathered with tool version: 0.23 | |
data analyzed with tool version: 0.23 | |
############################################# | |
# Retired Instructions | |
############################################# | |
Retired Instructions | |
Expected value: 226990030 | |
Raw Average: 227701300 +/- 72 | |
All Values: 227701296, 227701263, 227701349, 227701372, 227701257, 227701252, 227701282, 227701293, 227701288, 227701349, ) | |
Raw diff: 711270 +/- 72 | |
Attempting to adjust for overcount | |
Adjusting 629 for hwints | |
Adjusting 1 for first-time FPU use | |
Affected by FP Exceptions | |
Adjusting 10,008 for first-time memory accesses | |
Adjusting 100,000 for fclex with PE set | |
Adjusting 100,000 for finit with PE set | |
Adjusting 100,000 for fnsave with PE set | |
Adjusting 400,000 for fldcw to change rounding mode | |
Adjusted Average: 226990662 +/- 39 | |
============================== | |
Adjusted diff: 632 +/- 39 | |
Issues adjusted for: | |
h: hardware interrupts also increment event count | |
p: page faults also incremement event count | |
E: x87 exceptions increment event count | |
D: Some instructions are counted multiple times | |
F: Lazy-FPU handling causes an extra count | |
############################################# | |
# Retired Branches | |
############################################# | |
Retired Branches | |
Expected value: 9240001 | |
Raw Average: 9251305 +/- 282 | |
All Values: 9251219, 9251285, 9251260, 9251243, 9251353, 9251587, 9251301, 9251334, 9251250, 9251226, ) | |
Raw diff: 11304 +/- 282 | |
Attempting to adjust for overcount | |
Adjusting 644 for hwints | |
Adjusting 10,008 for first-time memory accesses | |
Adjusted Average: 9240653 +/- 141 | |
============================== | |
Adjusted diff: 652 +/- 141 | |
Issues adjusted for: | |
h: hardware interrupts also increment event count | |
p: page faults also incremement event count | |
############################################# | |
# Conditional Branches | |
############################################# | |
Conditional Branches | |
Expected value: 8220000 | |
Raw Average: 6851225 +/- 23 | |
All Values: 6851233, 6851236, 6851240, 6851219, 6851227, 6851206, 6851213, 6851217, 6851215, 6851248, ) | |
Raw diff: -1368775 +/- 23 | |
Attempting to adjust for overcount | |
Adjusting 612 for hwints | |
Adjusting 1,370,000 as we measure only taken branches | |
Adjusted Average: 8220613 +/- 12 | |
============================== | |
Adjusted diff: 613 +/- 12 | |
Issues adjusted for: | |
h: hardware interrupts also increment event count | |
D: Some instructions are counted multiple times | |
############################################# | |
# Retired Uops | |
############################################# | |
Retired Uops | |
Expected value: 0 | |
Raw Average: 14076139149 +/- 4508 | |
All Values: 14076135987, 14076138522, 14076137983, 14076143657, 14076141122, 14076141382, 14076136543, 14076137226, 14076140162, 14076138913, ) | |
Raw diff: 14076139149 +/- 4508 | |
Attempting to adjust for overcount | |
Adjusting 596 for hwints | |
Adjusted Average: 14076138553 +/- 4493 | |
============================== | |
Adjusted diff: 14076138553 +/- 4493 | |
This is a machine-specific event without a "known" correct result. | |
############################################# | |
# Retired Loads | |
############################################# | |
Retired Loads | |
Expected value: 79590000 | |
Raw Average: 2585679370 +/- 15805 | |
All Values: 2585675165, 2585687020, 2585665944, 2585683486, 2585673601, 2585678467, 2585676324, 2585679816, 2585695175, 2585678707, ) | |
Raw diff: 2506089370 +/- 15805 | |
Attempting to adjust for overcount | |
Adjusting 599 for hwints | |
Adjusted Average: 2585678771 +/- 15757 | |
============================== | |
Adjusted diff: 2506088771 +/- 15757 | |
Issues adjusted for: | |
h: hardware interrupts also increment event count | |
############################################# | |
# Retired Stores | |
############################################# | |
Retired Stores | |
Expected value: 24060000 | |
Raw Average: 228643885 +/- 7142 | |
All Values: 228636786, 228645395, 228642710, 228643945, 228640217, 228651027, 228640050, 228650082, 228642229, 228646412, ) | |
Raw diff: 204583885 +/- 7142 | |
Attempting to adjust for overcount | |
Adjusting 594 for hwints | |
Adjusted Average: 228643291 +/- 7142 | |
============================== | |
Adjusted diff: 204583291 +/- 7142 | |
Issues adjusted for: | |
h: hardware interrupts also increment event count | |
############################################# | |
# Multiplies | |
############################################# | |
Multiplies | |
Expected value: 0 | |
Raw Average: 2400475 +/- 2042 | |
All Values: 2400118, 2400002, 2400118, 2400105, 2400118, 2401401, 2400372, 2402517, 2400000, 2400000, ) | |
Raw diff: 2400475 +/- 2042 | |
Attempting to adjust for overcount | |
Adjusted Average: 2400475 +/- 2042 | |
============================== | |
Adjusted diff: 2400475 +/- 2042 | |
This is a machine-specific event without a "known" correct result. | |
############################################# | |
# Divides | |
############################################# | |
Divides | |
Expected value: 0 | |
Raw Average: 3200151 +/- 1145 | |
All Values: 3200000, 3200000, 3200000, 3200000, 3200000, 3200117, 3200000, 3201296, 3200100, 3200000, ) | |
Raw diff: 3200151 +/- 1145 | |
Attempting to adjust for overcount | |
Adjusted Average: 3200151 +/- 1145 | |
============================== | |
Adjusted diff: 3200151 +/- 1145 | |
This is a machine-specific event without a "known" correct result. | |
############################################# | |
# FP1 | |
############################################# | |
FP | |
Expected value: 0 | |
Raw Average: 691952444 +/- -278318 | |
All Values: 691674126, 692073317, 692067992, 691678586, 691806347, 692076217, 692072000, 692076290, 691968816, 692030751, ) | |
Raw diff: 691952444 +/- -278318 | |
Attempting to adjust for overcount | |
Adjusted Average: 691952444 +/- -278318 | |
============================== | |
Adjusted diff: 691952444 +/- -278318 | |
This is a machine-specific event without a "known" correct result. | |
############################################# | |
# FP2 | |
############################################# | |
FP | |
Expected value: 0 | |
Raw Average: 113810000 +/- 1 | |
All Values: 113810000, 113810000, 113810001, 113810001, 113810001, 113810000, 113810001, 113810001, 113810001, 113810001, ) | |
Raw diff: 113810000 +/- 1 | |
Attempting to adjust for overcount | |
Adjusted Average: 113810000 +/- 1 | |
============================== | |
Adjusted diff: 113810000 +/- 1 | |
This is a machine-specific event without a "known" correct result. | |
############################################# | |
# SSE | |
############################################# | |
SSE | |
Expected value: 0 | |
Raw Average: 15800687 +/- 2898 | |
All Values: 15803585, 15800562, 15800095, 15800118, 15801772, 15800003, 15800000, 15800000, 15800496, 15800239, ) | |
Raw diff: 15800687 +/- 2898 | |
Attempting to adjust for overcount | |
Adjusted Average: 15800687 +/- 2898 | |
============================== | |
Adjusted diff: 15800687 +/- 2898 | |
This is a machine-specific event without a "known" correct result. | |
############################################# | |
# SW Prefetch NTA | |
############################################# | |
No data found for this event | |
############################################# | |
# SW Prefetch L1 | |
############################################# | |
No data found for this event | |
############################################# | |
# SW Prefetch L2 | |
############################################# | |
No data found for this event |
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment