Compare FIFO interfaces.

FIFO_simple_interface.md

FIFO interface

valid-ready

from https://github.com/EECS150/fpga_project_skeleton_fa22/blob/master/hardware/src/io_circuits/fifo.v

module fifo #(
  parameter WIDTH    = 32, // data width is 32-bit
  parameter LOGDEPTH = 3   // 2^3 = 8 entries
) (
  input clk,
  input rst,

  // Write interface (enqueue)
  input  enq_valid,
  input  [WIDTH-1:0] enq_data,
  output enq_ready,

  // Read interface (dequeue)
  output deq_valid,
  output [WIDTH-1:0] deq_data,
  input deq_ready
);
endmodule

In valid-ready interface, we cannot tell which side is providing status, and which side is querying status and push/pull data using event.

status-event

from from https://github.com/EECS-151/fpga_projects_fa23/blob/main/hardware/src/io_circuits/fifo.v

module fifo #(
    parameter WIDTH = 8,
    parameter DEPTH = 32,
    parameter POINTER_WIDTH = $clog2(DEPTH)
) (
    input clk, rst,

    // Write side
    input wr_en,
    input [WIDTH-1:0] din,
    output full,

    // Read side
    input rd_en,
    output [WIDTH-1:0] dout,
    output empty
);
endmodule

Slightly change/rename the input/output, it is easy to tell that FIFO is providing service with status, user/client will check the status and provide events to drive the data push/pull.