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tempate of verilog test
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// 设定单位时间和解析精度 | |
`timescale 1ns/1ns | |
// 后续的#1表明经过1个时间单位 | |
// iverilog -g2012 -o demo.vvp demo.v | |
// vvp demo.vvp -fst | |
// gtkwave demo.fst | |
module test (); | |
// 执行由initial块开始 | |
initial begin | |
$dumpfile("demo.fst"); // 指定波形文件名,后缀fst并不是必须的,格式由vvp决定 | |
$dumpvars(0, test); | |
// 普通的输出 | |
$display("display message"); | |
// 带有时间戳的输出 | |
$display("%t display message", $time); | |
// 带有时间戳的输出,但是不换行 | |
$write("%t write message", $time); | |
$display(); // 输出空行 | |
// 错误输出 | |
$error("This is an error message"); | |
// 警告输出 | |
$warning("This is a warning message"); | |
// assertion | |
assert(0) else $error("assertion failure"); // 需要 -g2012 来激活assert功能 | |
// 结束仿真 | |
$finish; | |
end | |
endmodule |
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