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gistfile1.txt
Searching 6027 files for "^( +)[^ \n][^\n][^\n][^\n][^\n][^\n][^\n][^(\n][^(\n][^(\n][^\n]*= *\n\1 [^ ]" (regex)
qemu/block.c:
3762 static void bdrv_aio_cancel_em(BlockDriverAIOCB *blockacb)
3763 {
3764: BlockDriverAIOCBSync *acb =
3765: container_of(blockacb, BlockDriverAIOCBSync, common);
3766 qemu_bh_delete(acb->bh);
3767 acb->bh = NULL;
....
3841 static void bdrv_aio_co_cancel_em(BlockDriverAIOCB *blockacb)
3842 {
3843: BlockDriverAIOCBCoroutine *acb =
3844: container_of(blockacb, BlockDriverAIOCBCoroutine, common);
3845 bool done = false;
3846
....
4571
4572 /* backing files always opened read-only */
4573: back_flags =
4574: flags & ~(BDRV_O_RDWR | BDRV_O_SNAPSHOT | BDRV_O_NO_BACKING);
4575
4576 bs = bdrv_new("");
qemu/coroutine-ucontext.c:
170
171 #ifdef CONFIG_VALGRIND_H
172: co->valgrind_stack_id =
173: VALGRIND_STACK_REGISTER(co->stack, co->stack + stack_size);
174 #endif
175
qemu/exec.c:
1255 return xen_map_cache(addr, 0, 0);
1256 } else if (block->host == NULL) {
1257: block->host =
1258: xen_map_cache(block->offset, block->length, 1);
1259 }
1260 }
....
1282 return xen_map_cache(addr, 0, 0);
1283 } else if (block->host == NULL) {
1284: block->host =
1285: xen_map_cache(block->offset, block->length, 1);
1286 }
1287 }
qemu/kvm-all.c:
250
251 if (s->coalesced_mmio && !s->coalesced_mmio_ring) {
252: s->coalesced_mmio_ring =
253: (void *)cpu->kvm_run + s->coalesced_mmio * PAGE_SIZE;
254 }
255
...
1246 int kvm_init(void)
1247 {
1248: static const char upgrade_note[] =
1249: "Please upgrade to at least kernel 2.6.29 or recent kvm-kmod\n"
1250 "(see http://sourceforge.net/projects/kvm).\n";
1251 KVMState *s;
....
1314 missing_cap = kvm_check_extension_list(s, kvm_required_capabilites);
1315 if (!missing_cap) {
1316: missing_cap =
1317: kvm_check_extension_list(s, kvm_arch_required_capabilities);
1318 }
1319 if (missing_cap) {
....
1336 #endif
1337
1338: s->robust_singlestep =
1339: kvm_check_extension(s, KVM_CAP_X86_ROBUST_SINGLESTEP);
1340
1341 #ifdef KVM_CAP_DEBUGREGS
qemu/migration.c:
159 caps = caps->next;
160 }
161: caps->value =
162: g_malloc(sizeof(*caps->value));
163 caps->value->capability = i;
164 caps->value->state = s->enabled_capabilities[i];
qemu/nbd.c:
503 *flags = be16_to_cpu(tmp) << 16;
504 /* reserved for future use */
505: if (write_sync(csock, &reserved, sizeof(reserved)) !=
506: sizeof(reserved)) {
507 LOG("write failed (reserved)");
508 goto fail;
...
520 }
521 namesize = cpu_to_be32(strlen(name));
522: if (write_sync(csock, &namesize, sizeof(namesize)) !=
523: sizeof(namesize)) {
524 LOG("write failed (namesize)");
525 goto fail;
qemu/qemu-img.c:
838 /* Check if compression is supported */
839 if (compress) {
840: QEMUOptionParameter *encryption =
841: get_option_parameter(param, BLOCK_OPT_ENCRYPT);
842: QEMUOptionParameter *preallocation =
843: get_option_parameter(param, BLOCK_OPT_PREALLOC);
844
845 if (!drv->bdrv_write_compressed) {
qemu/savevm.c:
1958 int qemu_loadvm_state(QEMUFile *f)
1959 {
1960: QLIST_HEAD(, LoadStateEntry) loadvm_handlers =
1961: QLIST_HEAD_INITIALIZER(loadvm_handlers);
1962 LoadStateEntry *le, *new_le;
1963 uint8_t section_type;
qemu/vl.c:
3340 opts = qemu_opts_parse(qemu_find_opts("option-rom"), optarg, 1);
3341 option_rom[nb_option_roms].name = qemu_opt_get(opts, "romfile");
3342: option_rom[nb_option_roms].bootindex =
3343: qemu_opt_get_number(opts, "bootindex", -1);
3344 if (!option_rom[nb_option_roms].name) {
3345 fprintf(stderr, "Option ROM file is not specified\n");
qemu/xen-mapcache.c:
130 setrlimit(RLIMIT_AS, &rlimit_as);
131
132: mapcache->nr_buckets =
133: (((mapcache->max_mcache_size >> XC_PAGE_SHIFT) +
134 (1UL << (MCACHE_BUCKET_SHIFT - XC_PAGE_SHIFT)) - 1) >>
135 (MCACHE_BUCKET_SHIFT - XC_PAGE_SHIFT));
qemu/audio/alsaaudio.c:
836 req.buffer_size = conf.buffer_size_out;
837 req.size_in_usec = conf.size_in_usec_out;
838: req.override_mask =
839: (conf.period_size_out_overridden ? 1 : 0) |
840 (conf.buffer_size_out_overridden ? 2 : 0);
841
...
945 req.buffer_size = conf.buffer_size_in;
946 req.size_in_usec = conf.size_in_usec_in;
947: req.override_mask =
948: (conf.period_size_in_overridden ? 1 : 0) |
949 (conf.buffer_size_in_overridden ? 2 : 0);
950
qemu/audio/audio.c:
1904 conf.period.ticks = 1;
1905 } else {
1906: conf.period.ticks =
1907: muldiv64 (1, get_ticks_per_sec (), conf.period.hertz);
1908 }
1909
qemu/audio/audio_template.h:
491 #ifdef DAC
492 if (live) {
493: int mixed =
494: (live << old_sw->info.shift)
495 * old_sw->info.bytes_per_second
496 / sw->info.bytes_per_second;
qemu/audio/noaudio.c:
105 int64_t now = qemu_get_clock_ns (vm_clock);
106 int64_t ticks = now - no->old_ticks;
107: int64_t bytes =
108: muldiv64 (ticks, hw->info.bytes_per_second, get_ticks_per_sec ());
109
110 no->old_ticks = now;
qemu/audio/wavaudio.c:
55 int64_t now = qemu_get_clock_ns (vm_clock);
56 int64_t ticks = now - wav->old_ticks;
57: int64_t bytes =
58: muldiv64 (ticks, hw->info.bytes_per_second, get_ticks_per_sec ());
59
60 if (bytes > INT_MAX) {
qemu/block/blkdebug.c:
231 rule->options.inject.error = qemu_opt_get_number(opts, "errno", EIO);
232 rule->options.inject.once = qemu_opt_get_bool(opts, "once", 0);
233: rule->options.inject.immediately =
234: qemu_opt_get_bool(opts, "immediately", 0);
235 rule->options.inject.sector = qemu_opt_get_number(opts, "sector", -1);
236 break;
237
238 case ACTION_SET_STATE:
239: rule->options.set_state.new_state =
240: qemu_opt_get_number(opts, "new_state", 0);
241 break;
242
243 case ACTION_SUSPEND:
244: rule->options.suspend.tag =
245: g_strdup(qemu_opt_get(opts, "tag"));
246 break;
247 };
qemu/block/cloop.c:
145
146 for (i = 0; i < nb_sectors; i++) {
147: uint32_t sector_offset_in_block =
148: ((sector_num + i) % s->sectors_per_block),
149 block_num = (sector_num + i) / s->sectors_per_block;
150 if (cloop_read_block(bs, block_num) != 0) {
qemu/block/qcow.c:
327 return 0;
328 } else {
329: if (bdrv_pread(bs->file, l2_offset, l2_table, s->l2_size * sizeof(uint64_t)) !=
330: s->l2_size * sizeof(uint64_t))
331 return 0;
332 }
...
352 ~(s->cluster_size - 1);
353 /* write the cluster content */
354: if (bdrv_pwrite(bs->file, cluster_offset, s->cluster_cache, s->cluster_size) !=
355: s->cluster_size)
356 return -1;
357 } else {
qemu/block/qcow2-cluster.c:
835 trace_qcow2_cluster_alloc_phys(qemu_coroutine_self());
836 if (*host_offset == 0) {
837: int64_t cluster_offset =
838: qcow2_alloc_clusters(bs, *nb_clusters * s->cluster_size);
839 if (cluster_offset < 0) {
840 return cluster_offset;
...
907 {
908 /* We keep all QCOW_OFLAG_COPIED clusters */
909: keep_clusters =
910: count_contiguous_clusters(nb_clusters, s->cluster_size,
911 &l2_table[l2_index], 0,
912 QCOW_OFLAG_COPIED | QCOW_OFLAG_ZERO);
qemu/block/qcow2-refcount.c:
126 {
127 unsigned int min_clusters = (min_size >> (s->cluster_bits - 3)) + 1;
128: unsigned int refcount_table_clusters =
129: MAX(1, s->refcount_table_size >> (s->cluster_bits - 3));
130
131 while (min_clusters > refcount_table_clusters) {
...
167 if (refcount_table_index < s->refcount_table_size) {
168
169: uint64_t refcount_block_offset =
170: s->refcount_table[refcount_table_index] & REFT_OFFSET_MASK;
171
172 /* If it's already there, we're done */
...
302 uint64_t blocks_clusters;
303 do {
304: uint64_t table_clusters =
305: size_to_clusters(s, table_size * sizeof(uint64_t));
306 blocks_clusters = 1 +
307 ((table_clusters + refcount_block_clusters - 1)
...
445 int block_index, refcount;
446 int64_t cluster_index = cluster_offset >> s->cluster_bits;
447: int64_t table_index =
448: cluster_index >> (s->cluster_bits - REFCOUNT_SHIFT);
449
450 /* Load the refcount block and allocate it if needed */
qemu/block/qcow2-snapshot.c:
247 }
248
249: QEMU_BUILD_BUG_ON(offsetof(QCowHeader, snapshots_offset) !=
250: offsetof(QCowHeader, nb_snapshots) + sizeof(header_data.nb_snapshots));
251
252 header_data.nb_snapshots = cpu_to_be32(s->nb_snapshots);
qemu/block/qcow2.c:
401 s->cluster_offset_mask = (1LL << s->csize_shift) - 1;
402 s->refcount_table_offset = header.refcount_table_offset;
403: s->refcount_table_size =
404: header.refcount_table_clusters << (s->cluster_bits - 3);
405
406 s->snapshots_offset = header.snapshots_offset;
...
697 */
698 if (!cluster_data) {
699: cluster_data =
700: qemu_blockalign(bs, QCOW_MAX_CRYPT_CLUSTERS * s->cluster_size);
701 }
702
703: assert(cur_nr_sectors <=
704: QCOW_MAX_CRYPT_CLUSTERS * s->cluster_sectors);
705 qemu_iovec_reset(&hd_qiov);
706 qemu_iovec_add(&hd_qiov, cluster_data,
...
1239
1240 if (flags & BLOCK_FLAG_LAZY_REFCOUNTS) {
1241: header.compatible_features |=
1242: cpu_to_be64(QCOW2_COMPAT_LAZY_REFCOUNTS);
1243 }
1244
qemu/block/qed-check.c:
231 sizeof(check.used_clusters[0]));
232
233: check.result->bfi.total_clusters =
234: (s->header.image_size + s->header.cluster_size - 1) /
235 s->header.cluster_size;
236 ret = qed_check_l1_table(&check, s->l1_table);
qemu/block/qed.c:
1048 BDRVQEDState *s = acb_to_s(acb);
1049 uint64_t start = acb->cur_pos + acb->cur_qiov.size;
1050: uint64_t len =
1051: qed_start_of_cluster(s, start + s->header.cluster_size - 1) - start;
1052 uint64_t offset = acb->cur_cluster +
1053 qed_offset_into_cluster(s, acb->cur_pos) +
qemu/block/raw-win32.c:
366 const char *filename = bs->filename;
367 /* WinNT support GetCompressedFileSize to determine allocate size */
368: get_compressed =
369: (get_compressed_t) GetProcAddress(GetModuleHandle("kernel32"),
370 "GetCompressedFileSizeA");
371 if (get_compressed) {
qemu/block/stream.c:
145 }
146 if (ret < 0) {
147: BlockErrorAction action =
148: block_job_error_action(&s->common, s->common.bs, s->on_error,
149 true, -ret);
150 if (action == BDRV_ACTION_STOP) {
qemu/block/vmdk.c:
436 }
437
438: extent->l2_cache =
439: g_malloc(extent->l2_size * L2_CACHE_SIZE * sizeof(uint32_t));
440 return 0;
441 fail_l1b:
...
559 le32_to_cpu(header.num_gtes_per_gte),
560 le64_to_cpu(header.granularity));
561: extent->compressed =
562: le16_to_cpu(header.compressAlgorithm) == VMDK4_COMPRESSION_DEFLATE;
563 extent->has_marker = le32_to_cpu(header.flags) & VMDK4_FLAG_MARKER;
564 ret = vmdk_init_tables(bs, extent);
...
1274 memset(&header, 0, sizeof(header));
1275 header.version = 1;
1276: header.flags =
1277: 3 | (compress ? VMDK4_FLAG_COMPRESS | VMDK4_FLAG_MARKER : 0);
1278 header.compressAlgorithm = compress ? VMDK4_COMPRESSION_DEFLATE : 0;
1279 header.capacity = filesize / 512;
....
1454 char parent_desc_line[BUF_SIZE] = "";
1455 uint32_t parent_cid = 0xffffffff;
1456: const char desc_template[] =
1457: "# Disk DescriptorFile\n"
1458 "version=1\n"
1459 "CID=%x\n"
qemu/block/vpc.c:
232 }
233
234: s->free_data_block_offset =
235: (s->bat_offset + (s->max_table_entries * 4) + 511) & ~511;
236
237 for (i = 0; i < s->max_table_entries; i++) {
...
579 static int create_dynamic_disk(int fd, uint8_t *buf, int64_t total_sectors)
580 {
581: struct vhd_dyndisk_header* dyndisk_header =
582: (struct vhd_dyndisk_header*) buf;
583 size_t block_size, num_bat_entries;
584 int i;
qemu/hw/acpi.c:
229
230 if (changed || !has_header || 1) {
231: ((struct acpi_table_header *)f)->checksum =
232: acpi_checksum((uint8_t *)f + ACPI_TABLE_PFX_SIZE, len);
233 }
234
235 /* increase number of tables */
236: (*(uint16_t *)acpi_tables) =
237: cpu_to_le32(le32_to_cpu(*(uint16_t *)acpi_tables) + 1);
238
239 acpi_tables_len = allen;
...
249 switch (*reason) {
250 case QEMU_WAKEUP_REASON_RTC:
251: ar->pm1.evt.sts |=
252: (ACPI_BITMASK_WAKE_STATUS | ACPI_BITMASK_RT_CLOCK_STATUS);
253 break;
254 case QEMU_WAKEUP_REASON_PMTIMER:
255: ar->pm1.evt.sts |=
256: (ACPI_BITMASK_WAKE_STATUS | ACPI_BITMASK_TIMER_STATUS);
257 break;
258 case QEMU_WAKEUP_REASON_OTHER:
...
260 /* ACPI_BITMASK_WAKE_STATUS should be set on resume.
261 Pretend that resume was caused by power button */
262: ar->pm1.evt.sts |=
263: (ACPI_BITMASK_WAKE_STATUS | ACPI_BITMASK_POWER_BUTTON_STATUS);
264 break;
265 }
qemu/hw/arm_mptimer.c:
236 static void arm_mptimer_reset(DeviceState *dev)
237 {
238: arm_mptimer_state *s =
239: FROM_SYSBUS(arm_mptimer_state, sysbus_from_qdev(dev));
240 int i;
241 /* We reset every timer in the array, not just the ones we're using,
qemu/hw/armv7m_nvic.c:
415 case 0xd18 ... 0xd23: /* System Handler Priority. */
416 for (i = 0; i < size; i++) {
417: s->gic.priority1[(offset - 0xd14) + i][0] =
418: (value >> (i * 8)) & 0xff;
419 }
420 gic_update(&s->gic);
qemu/hw/bt-hid.c:
371 static void bt_hid_datain(HIDState *hs)
372 {
373: struct bt_hid_device_s *hid =
374: container_of(hs, struct bt_hid_device_s, hid);
375
376 /* If suspended, wake-up and send a wake-up event first. We might
qemu/hw/ccid-card-passthru.c:
121
122 capabilities = init->capabilities;
123: num_capabilities =
124: 1 + ((hdr->length - sizeof(VSCMsgInit)) / sizeof(uint32_t));
125 init->version = ntohl(init->version);
126 for (i = 0 ; i < num_capabilities; ++i) {
qemu/hw/cirrus_vga.c:
2879 memory_region_set_flush_coalesced(&s->cirrus_mmio_io);
2880
2881: s->real_vram_size =
2882: (s->device_id == CIRRUS_ID_CLGD5446) ? 4096 * 1024 : 2048 * 1024;
2883
2884 /* XXX: s->vga.vram_size must be a power of two */
qemu/hw/e1000.c:
385 if (++s->eecd_state.bitnum_in == 9 && !s->eecd_state.reading) {
386 s->eecd_state.bitnum_out = ((s->eecd_state.val_in & 0x3f)<<4)-1;
387: s->eecd_state.reading = (((s->eecd_state.val_in >> 6) & 7) ==
388: EEPROM_READ_OPCODE_MICROWIRE);
389 }
390 DBGOUT(EEPROM, "eeprom bitnum in %d out %d, reading %d\n",
qemu/hw/eepro100.c:
1639 uint8_t min_buf[60];
1640 #endif
1641: static const uint8_t broadcast_macaddr[6] =
1642: { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
1643
1644 #if defined(CONFIG_PAD_RECEIVED_FRAMES)
qemu/hw/es1370.c:
426
427 if (i == ADC_CHANNEL) {
428: s->adc_voice =
429: AUD_open_in (
430 &s->card,
431 s->adc_voice,
...
437 }
438 else {
439: s->dac_voice[i] =
440: AUD_open_out (
441 &s->card,
442 s->dac_voice[i],
qemu/hw/exynos4210_fimd.c:
1459 s->window[w].osdsize = val;
1460 } else {
1461: s->window[w].alpha_val[0] =
1462: unpack_upper_4((val & FIMD_VIDOSD_ALPHA_AEN0) >>
1463 FIMD_VIDOSD_AEN0_SHIFT) |
1464 (s->window[w].alpha_val[0] & FIMD_VIDALPHA_ALPHA_LOWER);
1465: s->window[w].alpha_val[1] =
1466: unpack_upper_4(val & FIMD_VIDOSD_ALPHA_AEN1) |
1467 (s->window[w].alpha_val[1] & FIMD_VIDALPHA_ALPHA_LOWER);
1468 }
....
1499 s->window[w].virtpage_offsize)) {
1500 s->window[w].virtpage_width = val & FIMD_VIDWADD2_PAGEWIDTH;
1501: s->window[w].virtpage_offsize =
1502: (val >> FIMD_VIDWADD2_OFFSIZE_SHIFT) & FIMD_VIDWADD2_OFFSIZE;
1503 fimd_update_memory_section(s, w);
1504 }
qemu/hw/fdc.c:
1655 else
1656 fdctrl->data_state &= ~FD_STATE_MULTI;
1657: cur_drv->bps =
1658: fdctrl->fifo[2] > 7 ? 16384 : 128 << fdctrl->fifo[2];
1659 #if 0
1660: cur_drv->last_sect =
1661: cur_drv->flags & FDISK_DBL_SIDES ? fdctrl->fifo[3] :
1662 fdctrl->fifo[3] / 2;
1663 #else
....
1718
1719 if (fdctrl->reset_sensei > 0) {
1720: fdctrl->fifo[0] =
1721: FD_SR0_RDYCHG + FD_RESET_SENSEI_COUNT - fdctrl->reset_sensei;
1722 fdctrl->reset_sensei--;
1723 } else if (!(fdctrl->sra & FD_SRA_INTPEND)) {
qemu/hw/hpet.c:
514 */
515 new_val &= (timer->config & HPET_TN_32BIT ? ~0u : ~0ull) >> 1;
516: timer->period =
517: (timer->period & 0xffffffff00000000ULL) | new_val;
518 }
519 timer->config &= ~HPET_TN_SETVAL;
...
533 */
534 new_val &= (timer->config & HPET_TN_32BIT ? ~0u : ~0ull) >> 1;
535: timer->period =
536: (timer->period & 0xffffffffULL) | new_val << 32;
537 }
538 timer->config &= ~HPET_TN_SETVAL;
...
561 if (activating_bit(old_val, new_val, HPET_CFG_ENABLE)) {
562 /* Enable main counter and interrupt generation. */
563: s->hpet_offset =
564: ticks_to_ns(s->hpet_counter) - qemu_get_clock_ns(vm_clock);
565 for (i = 0; i < s->num_timers; i++) {
566 if ((&s->timer[i])->cmp != ~0ULL) {
...
602 DPRINTF("qemu: Writing counter while HPET enabled!\n");
603 }
604: s->hpet_counter =
605: (s->hpet_counter & 0xffffffff00000000ULL) | value;
606 DPRINTF("qemu: HPET counter written. ctr = %#x -> %" PRIx64 "\n",
607 value, s->hpet_counter);
...
611 DPRINTF("qemu: Writing counter while HPET enabled!\n");
612 }
613: s->hpet_counter =
614: (s->hpet_counter & 0xffffffffULL) | (((uint64_t)value) << 32);
615 DPRINTF("qemu: HPET counter + 4 written. ctr = %#x -> %" PRIx64 "\n",
616 value, s->hpet_counter);
qemu/hw/i8254.c:
133 /* status latch */
134 /* XXX: add BCD and null count */
135: s->status =
136: (pit_get_out(s,
137 qemu_get_clock_ns(vm_clock)) << 7) |
138 (s->rw_mode << 4) |
qemu/hw/i8254_common.c:
161 s->count = 0x10000;
162 if (i == 0 && !s->irq_disabled) {
163: s->next_transition_time =
164: pit_get_next_transition_time(s, s->count_load_time);
165 }
166 }
qemu/hw/ioapic.c:
57 dest = entry >> IOAPIC_LVT_DEST_SHIFT;
58 dest_mode = (entry >> IOAPIC_LVT_DEST_MODE_SHIFT) & 1;
59: delivery_mode =
60: (entry >> IOAPIC_LVT_DELIV_MODE_SHIFT) & IOAPIC_DM_MASK;
61 if (trig_mode == IOAPIC_TRIGGER_EDGE) {
62 s->irr &= ~mask;
..
95 level = !level;
96 }
97: if (((entry >> IOAPIC_LVT_TRIGGER_MODE_SHIFT) & 1) ==
98: IOAPIC_TRIGGER_LEVEL) {
99 /* level triggered */
100 if (level) {
qemu/hw/ioh3420.c:
68 uint32_t address, uint32_t val, int len)
69 {
70: uint32_t root_cmd =
71: pci_get_long(d->config + d->exp.aer_cap + PCI_ERR_ROOT_COMMAND);
72
73 pci_bridge_write_config(d, address, val, len);
qemu/hw/lsi53c895a.c:
1252 int operator;
1253 #ifdef DEBUG_LSI
1254: static const char *opcode_names[3] =
1255: {"Write", "Read", "Read-Modify-Write"};
1256: static const char *operator_names[8] =
1257: {"MOV", "SHL", "OR", "XOR", "AND", "SHR", "ADD", "ADC"};
1258 #endif
1259
qemu/hw/mc146818rtc.c:
165 cur_clock = muldiv64(current_time, RTC_CLOCK_RATE, get_ticks_per_sec());
166 next_irq_clock = (cur_clock & ~(period - 1)) + period;
167: s->next_periodic_time =
168: muldiv64(next_irq_clock, get_ticks_per_sec(), RTC_CLOCK_RATE) + 1;
169 qemu_mod_timer(s->periodic_timer, s->next_periodic_time);
170 } else {
...
522 tm->tm_mday = rtc_from_bcd(s, s->cmos_data[RTC_DAY_OF_MONTH]);
523 tm->tm_mon = rtc_from_bcd(s, s->cmos_data[RTC_MONTH]) - 1;
524: tm->tm_year =
525: rtc_from_bcd(s, s->cmos_data[RTC_YEAR]) + s->base_year +
526 rtc_from_bcd(s, s->cmos_data[RTC_CENTURY]) * 100 - 1900;
527 }
...
833 switch (s->lost_tick_policy) {
834 case LOST_TICK_SLEW:
835: s->coalesced_timer =
836: qemu_new_timer_ns(rtc_clock, rtc_coalesced_timer, s);
837 break;
838 case LOST_TICK_DISCARD:
qemu/hw/megasas.c:
113 static bool megasas_intr_enabled(MegasasState *s)
114 {
115: if ((s->intr_mask & MEGASAS_INTR_DISABLED_MASK) !=
116: MEGASAS_INTR_DISABLED_MASK) {
117 return true;
118 }
...
692 if (num_ld_disks < 8) {
693 sdev_id = ((sdev->id & 0xFF) >> 8) | (sdev->lun & 0xFF);
694: info.device.port_addr[num_ld_disks] =
695: cpu_to_le64(megasas_get_sata_addr(sdev_id));
696 }
697 num_ld_disks++;
...
913 info.addr[num_pd_disks].scsi_dev_type = sdev->type;
914 info.addr[num_pd_disks].connect_port_bitmap = 0x1;
915: info.addr[num_pd_disks].sas_addr[0] =
916: cpu_to_le64(megasas_get_sata_addr(sdev_id));
917 num_pd_disks++;
918 offset += sizeof(struct mfi_pd_address);
...
1016 info->slot_number = (sdev->id & 0xFF);
1017 info->path_info.count = 1;
1018: info->path_info.sas_addr[0] =
1019: cpu_to_le64(megasas_get_sata_addr(sdev_id));
1020 info->connected_port_bitmap = 0x1;
1021 info->device_speed = 1;
qemu/hw/milkymist-pfpu.c:
226 uint32_t a = cpu_to_be32(s->gp_regs[reg_a]);
227 uint32_t b = cpu_to_be32(s->gp_regs[reg_b]);
228: hwaddr dma_ptr =
229: get_dma_address(s->regs[R_MESHBASE],
230 s->gp_regs[GPR_X], s->gp_regs[GPR_Y]);
231 cpu_physical_memory_write(dma_ptr, (uint8_t *)&a, 4);
qemu/hw/mips_timer.c:
90 else {
91 /* Store new count register */
92: env->CP0_Count =
93: count - (uint32_t)muldiv64(qemu_get_clock_ns(vm_clock),
94 TIMER_FREQ, get_ticks_per_sec());
95 /* Update timer timer */
qemu/hw/musicpal.c:
352
353 case MP_ETH_CRDP0 ... MP_ETH_CRDP3:
354: s->rx_queue[(offset - MP_ETH_CRDP0)/4] =
355: s->cur_rx[(offset - MP_ETH_CRDP0)/4] = value;
356 break;
357
qemu/hw/nand.c:
570 (1 << s->page_shift) + (1 << s->oob_shift)) {
571 for (i = s->buswidth; i--; s->addr++, value >>= 8) {
572: s->io[s->iolen + (s->addr & ((1 << s->addr_shift) - 1))] =
573: (uint8_t) (value & 0xff);
574 }
575 }
qemu/hw/ne2000.c:
184 unsigned int total_len, next, avail, len, index, mcast_idx;
185 uint8_t buf1[60];
186: static const uint8_t broadcast_macaddr[6] =
187: { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
188
189 #if defined(DEBUG_NE2000)
qemu/hw/omap_gpmc.c:
299 }
300 data = s->prefetch.fifo[63 - s->prefetch.fifopointer];
301: if (s->prefetch.fifopointer ==
302: (64 - prefetch_threshold(s->prefetch.config1))) {
303 /* We've drained THRESHOLD bytes now. So deassert the
304 * DMA request, then refill the FIFO (which will probably
qemu/hw/piix_pci.c:
458
459 for (i = 0; i < ARRAY_SIZE(piix3->pci_irq_levels_vmstate); i++) {
460: piix3->pci_irq_levels_vmstate[i] =
461: pci_bus_get_irq_level(piix3->dev.bus, i);
462 }
463 }
qemu/hw/ppc.c:
1053 /* We use decr timer for PIT */
1054 tb_env->decr_timer = qemu_new_timer_ns(vm_clock, &cpu_4xx_pit_cb, env);
1055: ppc40x_timer->fit_timer =
1056: qemu_new_timer_ns(vm_clock, &cpu_4xx_fit_cb, env);
1057: ppc40x_timer->wdt_timer =
1058: qemu_new_timer_ns(vm_clock, &cpu_4xx_wdt_cb, env);
1059 ppc40x_timer->decr_excp = decr_excp;
1060 }
qemu/hw/ppc405_uc.c:
2129 /* Universal interrupt controller */
2130 irqs = g_malloc0(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB);
2131: irqs[PPCUIC_OUTPUT_INT] =
2132: ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT];
2133: irqs[PPCUIC_OUTPUT_CINT] =
2134: ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT];
2135 pic = ppcuic_init(env, irqs, 0x0C0, 0, 1);
2136 *picp = pic;
....
2486 /* Universal interrupt controller */
2487 irqs = g_malloc0(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB);
2488: irqs[PPCUIC_OUTPUT_INT] =
2489: ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT];
2490: irqs[PPCUIC_OUTPUT_CINT] =
2491: ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT];
2492 pic = ppcuic_init(env, irqs, 0x0C0, 0, 1);
2493 *picp = pic;
qemu/hw/ppc_booke.c:
254 tb_env->decr_timer = qemu_new_timer_ns(vm_clock, &booke_decr_cb, cpu);
255
256: booke_timer->fit_timer =
257: qemu_new_timer_ns(vm_clock, &booke_fit_cb, cpu);
258: booke_timer->wdt_timer =
259: qemu_new_timer_ns(vm_clock, &booke_wdt_cb, cpu);
260 }
261
qemu/hw/ppc_newworld.c:
282
283 openpic_irqs = g_malloc0(smp_cpus * sizeof(qemu_irq *));
284: openpic_irqs[0] =
285: g_malloc0(smp_cpus * sizeof(qemu_irq) * OPENPIC_OUTPUT_NB);
286 for (i = 0; i < smp_cpus; i++) {
287 /* Mac99 IRQ connection between OpenPIC outputs pins
...
291 case PPC_FLAGS_INPUT_6xx:
292 openpic_irqs[i] = openpic_irqs[0] + (i * OPENPIC_OUTPUT_NB);
293: openpic_irqs[i][OPENPIC_OUTPUT_INT] =
294: ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];
295: openpic_irqs[i][OPENPIC_OUTPUT_CINT] =
296: ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];
297: openpic_irqs[i][OPENPIC_OUTPUT_MCK] =
298: ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_MCP];
299 /* Not connected ? */
300 openpic_irqs[i][OPENPIC_OUTPUT_DEBUG] = NULL;
301 /* Check this */
302: openpic_irqs[i][OPENPIC_OUTPUT_RESET] =
303: ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_HRESET];
304 break;
305 #if defined(TARGET_PPC64)
306 case PPC_FLAGS_INPUT_970:
307 openpic_irqs[i] = openpic_irqs[0] + (i * OPENPIC_OUTPUT_NB);
308: openpic_irqs[i][OPENPIC_OUTPUT_INT] =
309: ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT];
310: openpic_irqs[i][OPENPIC_OUTPUT_CINT] =
311: ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT];
312: openpic_irqs[i][OPENPIC_OUTPUT_MCK] =
313: ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_MCP];
314 /* Not connected ? */
315 openpic_irqs[i][OPENPIC_OUTPUT_DEBUG] = NULL;
316 /* Check this */
317: openpic_irqs[i][OPENPIC_OUTPUT_RESET] =
318: ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_HRESET];
319 break;
320 #endif /* defined(TARGET_PPC64) */
qemu/hw/ppc_oldworld.c:
228 /* XXX: we register only 1 output pin for heathrow PIC */
229 heathrow_irqs = g_malloc0(smp_cpus * sizeof(qemu_irq *));
230: heathrow_irqs[0] =
231: g_malloc0(smp_cpus * sizeof(qemu_irq) * 1);
232 /* Connect the heathrow PIC outputs to the 6xx bus */
233 for (i = 0; i < smp_cpus; i++) {
...
235 case PPC_FLAGS_INPUT_6xx:
236 heathrow_irqs[i] = heathrow_irqs[0] + (i * 1);
237: heathrow_irqs[i][0] =
238: ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];
239 break;
240 default:
qemu/hw/ppce500_pci.c:
327
328 pci_config_set_class(d->config, PCI_CLASS_BRIDGE_PCI);
329: d->config[PCI_HEADER_TYPE] =
330: (d->config[PCI_HEADER_TYPE] & PCI_HEADER_TYPE_MULTI_FUNCTION) |
331 PCI_HEADER_TYPE_BRIDGE;
332
qemu/hw/pxa2xx.c:
276
277 case 3:
278: s->cpu->env.uncached_cpsr =
279: ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I;
280 s->cpu->env.cp15.c1_sys = 0;
281 s->cpu->env.cp15.c1_coproc = 0;
qemu/hw/pxa2xx_mmci.c:
132 } else
133 while (s->bytesleft && s->rx_len < 32) {
134: s->rx_fifo[(s->rx_start + (s->rx_len ++)) & 0x1f] =
135: sd_read_data(s->card);
136 s->bytesleft --;
137 s->intreq |= INT_RXFIFO_REQ;
qemu/hw/qxl.c:
1011 monitors_config->num_of_monitors,
1012 ARRAY_SIZE(rom->client_monitors_config.heads));
1013: rom->client_monitors_config.count =
1014: ARRAY_SIZE(rom->client_monitors_config.heads);
1015 }
1016 for (i = 0 ; i < rom->client_monitors_config.count ; ++i) {
qemu/hw/rtl8139.c:
817
818 uint8_t buf1[MIN_BUF_SIZE + VLAN_HLEN];
819: static const uint8_t broadcast_macaddr[6] =
820: { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
821
822 DPRINTF(">>> received len=%d\n", size);
qemu/hw/sd.c:
1592 sd->state = sd_programming_state;
1593 for (i = 0; i < sizeof(sd->csd); i ++)
1594: if ((sd->csd[i] | sd_csd_rw_mask[i]) !=
1595: (sd->data[i] | sd_csd_rw_mask[i]))
1596 sd->card_status |= CID_CSD_OVERWRITE;
1597
qemu/hw/smbus_ich9.c:
107 i2c_bus *ich9_smb_init(PCIBus *bus, int devfn, uint32_t smb_io_base)
108 {
109: PCIDevice *d =
110: pci_create_simple_multifunction(bus, devfn, true, TYPE_ICH9_SMB_DEVICE);
111 ICH9SMBState *s = ICH9_SMB_DEVICE(d);
112 return s->smb.smbus;
qemu/hw/vga.c:
177 s->chain4_alias = NULL;
178
179: if ((s->sr[VGA_SEQ_PLANE_WRITE] & VGA_SR02_ALL_PLANES) ==
180: VGA_SR02_ALL_PLANES && s->sr[VGA_SEQ_MEMORY_MODE] & VGA_SR04_CHN_4M) {
181 offset = 0;
182 switch ((s->gr[VGA_GFX_MISC] >> 2) & 3) {
...
684 int h, shift_control;
685
686: s->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH] =
687: s->vbe_regs[VBE_DISPI_INDEX_XRES];
688: s->vbe_regs[VBE_DISPI_INDEX_VIRT_HEIGHT] =
689: s->vbe_regs[VBE_DISPI_INDEX_YRES];
690 s->vbe_regs[VBE_DISPI_INDEX_X_OFFSET] = 0;
691 s->vbe_regs[VBE_DISPI_INDEX_Y_OFFSET] = 0;
...
712 s->cr[VGA_CRTC_OFFSET] = s->vbe_line_offset >> 3;
713 /* width */
714: s->cr[VGA_CRTC_H_DISP] =
715: (s->vbe_regs[VBE_DISPI_INDEX_XRES] >> 3) - 1;
716 /* height (only meaningful if < 1024) */
717 h = s->vbe_regs[VBE_DISPI_INDEX_YRES] - 1;
...
966 s->plane_updated |= mask; /* only used to detect font change */
967 write_mask = mask16[mask];
968: ((uint32_t *)s->vram_ptr)[addr] =
969: (((uint32_t *)s->vram_ptr)[addr] & ~write_mask) |
970 (val & write_mask);
971 #ifdef DEBUG_VGA_MEM
...
1355 full_update = 1;
1356 }
1357: s->rgb_to_pixel =
1358: rgb_to_pixel_dup_table[get_depth_index(s->ds)];
1359 full_update |= update_palette16(s);
1360 palette = s->last_palette;
....
1720 }
1721
1722: s->rgb_to_pixel =
1723: rgb_to_pixel_dup_table[get_depth_index(s->ds)];
1724
1725 if (shift_control == 0) {
....
1866 return;
1867
1868: s->rgb_to_pixel =
1869: rgb_to_pixel_dup_table[get_depth_index(s->ds)];
1870 if (ds_get_bits_per_pixel(s->ds) == 8)
1871 val = s->rgb_to_pixel(0, 0, 0);
qemu/hw/virtio-pci.c:
620 /* Must set vector notifier after guest notifier has been assigned */
621 if (kvm_msi_via_irqfd_enabled() && assign) {
622: proxy->vector_irqfd =
623: g_malloc0(sizeof(*proxy->vector_irqfd) *
624 msix_nr_vectors_allocated(&proxy->pci_dev));
625 r = msix_set_vector_notifiers(&proxy->pci_dev,
qemu/hw/virtio-scsi.c:
273 req->sreq = sreq;
274 if (req->sreq->cmd.mode != SCSI_XFER_NONE) {
275: int req_mode =
276: (req->elem.in_num > 1 ? SCSI_XFER_FROM_DEV : SCSI_XFER_TO_DEV);
277
278 assert(req->sreq->cmd.mode == req_mode);
...
504
505 if (req->sreq->cmd.mode != SCSI_XFER_NONE) {
506: int req_mode =
507: (req->elem.in_num > 1 ? SCSI_XFER_FROM_DEV : SCSI_XFER_TO_DEV);
508
509 if (req->sreq->cmd.mode != req_mode ||
qemu/hw/virtio-serial-bus.c:
672 s->post_load = g_malloc0(sizeof(*s->post_load));
673 s->post_load->nr_active_ports = nr_active_ports;
674: s->post_load->connected =
675: g_malloc0(sizeof(*s->post_load->connected) * nr_active_ports);
676
677 s->post_load->timer = qemu_new_timer_ns(vm_clock,
qemu/hw/virtio.c:
799 int virtio_set_features(VirtIODevice *vdev, uint32_t val)
800 {
801: uint32_t supported_features =
802: vdev->binding->get_features(vdev->binding_opaque);
803 bool bad = (val & ~supported_features) != 0;
804
qemu/hw/vmware_vga.c:
1013 static void vmsvga_reset(DeviceState *dev)
1014 {
1015: struct pci_vmsvga_state_s *pci =
1016: DO_UPCAST(struct pci_vmsvga_state_s, card.qdev, dev);
1017 struct vmsvga_state_s *s = &pci->chip;
1018
....
1194 static int pci_vmsvga_initfn(PCIDevice *dev)
1195 {
1196: struct pci_vmsvga_state_s *s =
1197: DO_UPCAST(struct pci_vmsvga_state_s, card, dev);
1198
1199 s->card.config[PCI_CACHE_LINE_SIZE] = 0x08; /* Cache line size */
qemu/hw/wdt_i6300esb.c:
215 if (addr == ESB_CONFIG_REG && len == 2) {
216 d->reboot_enabled = (data & ESB_WDT_REBOOT) == 0;
217: d->clock_scale =
218: (data & ESB_WDT_FREQ) != 0 ? CLOCK_SCALE_1MHZ : CLOCK_SCALE_1KHZ;
219 d->int_type = (data & ESB_WDT_INTTYPE);
220 } else if (addr == ESB_LOCK_REG && len == 1) {
qemu/hw/xen_pt_msi.c:
565 table_off, total_entries);
566 msix->table_offset_adjust = table_off & 0x0fff;
567: msix->phys_iomem_base =
568: mmap(NULL,
569 total_entries * PCI_MSIX_ENTRY_SIZE + msix->table_offset_adjust,
570 PROT_READ,
qemu/hw/xilinx_spips.c:
182 IXR_TX_FIFO_MODE_FAIL);
183 /* these are pure functions of fifo state, set them here */
184: s->regs[R_INTR_STATUS] |=
185: (fifo8_is_full(&s->rx_fifo) ? IXR_RX_FIFO_FULL : 0) |
186 (s->rx_fifo.num >= s->regs[R_RX_THRES] ? IXR_RX_FIFO_NOT_EMPTY : 0) |
187 (fifo8_is_full(&s->tx_fifo) ? IXR_TX_FIFO_FULL : 0) |
qemu/hw/xtensa_pic.c:
147 if (xtensa_option_enabled(env->config, XTENSA_OPTION_TIMER_INTERRUPT) &&
148 env->config->nccompare > 0) {
149: env->ccompare_timer =
150: qemu_new_timer_ns(vm_clock, &xtensa_ccompare_cb, cpu);
151 }
152 }
qemu/hw/9pfs/virtio-9p.c:
2625 }
2626 v9_mode = stat_to_v9mode(&stbuf);
2627: if ((v9stat.mode & P9_STAT_MODE_TYPE_BITS) !=
2628: (v9_mode & P9_STAT_MODE_TYPE_BITS)) {
2629 /* Attempting to change the type */
2630 err = -EIO;
qemu/hw/ide/cmd646.c:
178 break;
179 case 1:
180: pci_dev->dev.config[MRDMODE] =
181: (pci_dev->dev.config[MRDMODE] & ~0x30) | (val & 0x30);
182 cmd646_update_irq(pci_dev);
183 break;
qemu/hw/ide/pci.c:
386 uint8_t abused_bits = BM_MIGRATION_COMPAT_STATUS_BITS;
387
388: bm->migration_compat_status =
389: (bm->status & ~abused_bits) | (bm->bus->error_status & abused_bits);
390 }
391
qemu/hw/kvm/i8254.c:
119
120 sc = &pit->channels[0];
121: sc->next_transition_time =
122: pit_get_next_transition_time(sc, sc->count_load_time);
123 }
124
qemu/hw/kvm/pci-assign.c:
465
466 /* add offset */
467: pci_dev->v_addrs[i].u.r_virtbase +=
468: (cur_region->base_addr & 0xFFF);
469
470 if (cur_region->size & 0xFFF) {
...
1486 /* If real and virtual capability list status bits differ, virtualize the
1487 * access. */
1488: if ((pci_get_word(pci_dev->config + PCI_STATUS) & PCI_STATUS_CAP_LIST) !=
1489: (assigned_dev_pci_read_byte(pci_dev, PCI_STATUS) &
1490 PCI_STATUS_CAP_LIST)) {
1491 dev->emulate_config_read[PCI_STATUS] |= PCI_STATUS_CAP_LIST;
qemu/hw/pci/msi.c:
354 * just don't crash the host
355 */
356: log_num_vecs =
357: (flags & PCI_MSI_FLAGS_QSIZE) >> (ffs(PCI_MSI_FLAGS_QSIZE) - 1);
358: log_max_vecs =
359: (flags & PCI_MSI_FLAGS_QMASK) >> (ffs(PCI_MSI_FLAGS_QMASK) - 1);
360 if (log_num_vecs > log_max_vecs) {
361 flags &= ~PCI_MSI_FLAGS_QSIZE;
qemu/hw/pci/msix.c:
210
211 for (vector = 0; vector < nentries; ++vector) {
212: unsigned offset =
213: vector * PCI_MSIX_ENTRY_SIZE + PCI_MSIX_ENTRY_VECTOR_CTRL;
214 bool was_masked = msix_is_masked(dev, vector);
215
qemu/hw/pci/pci_bridge.c:
308 PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK);
309 pci_config_set_class(dev->config, PCI_CLASS_BRIDGE_PCI);
310: dev->config[PCI_HEADER_TYPE] =
311: (dev->config[PCI_HEADER_TYPE] & PCI_HEADER_TYPE_MULTI_FUNCTION) |
312 PCI_HEADER_TYPE_BRIDGE;
313 pci_set_word(dev->config + PCI_SEC_STATUS,
qemu/hw/pci/pcie_aer.c:
424 for (i = 0; i < ARRAY_SIZE(err->header); ++i) {
425 /* 7.10.8 Header Log Register */
426: uint8_t *header_log =
427: aer_cap + PCI_ERR_HEADER_LOG + i * sizeof err->header[0];
428 cpu_to_be32wu((uint32_t*)header_log, err->header[i]);
429 }
...
438 for (i = 0; i < ARRAY_SIZE(err->prefix); ++i) {
439 /* 7.10.12 tlp prefix log register */
440: uint8_t *prefix_log =
441: aer_cap + PCI_ERR_TLP_PREFIX_LOG + i * sizeof err->prefix[0];
442 cpu_to_be32wu((uint32_t*)prefix_log, err->prefix[i]);
443 }
...
545 }
546 if (is_advisory_nonfatal) {
547: uint32_t uncor_mask =
548: pci_get_long(inj->aer_cap + PCI_ERR_UNCOR_MASK);
549 if (!(uncor_mask & uncor_status)) {
550 inj->log_overflow = !!pcie_aer_record_error(dev, inj->err);
...
671 }
672 } else {
673: bool is_fatal =
674: pcie_aer_uncor_default_severity(error_status) ==
675 PCI_ERR_ROOT_CMD_FATAL_EN;
676 if (aer_cap) {
qemu/hw/pci/shpc.c:
304 shpc_set_status(shpc, slot, SHPC_SLOT_STATUS_PRSNT_EMPTY,
305 SHPC_SLOT_STATUS_PRSNT_MASK);
306: shpc->config[SHPC_SLOT_EVENT_LATCH(slot)] |=
307: SHPC_SLOT_EVENT_BUTTON |
308 SHPC_SLOT_EVENT_MRL |
309 SHPC_SLOT_EVENT_PRESENCE;
...
525 shpc_set_status(shpc, slot, SHPC_SLOT_STATUS_PRSNT_EMPTY,
526 SHPC_SLOT_STATUS_PRSNT_MASK);
527: shpc->config[SHPC_SLOT_EVENT_LATCH(slot)] |=
528: SHPC_SLOT_EVENT_MRL |
529 SHPC_SLOT_EVENT_PRESENCE;
530 }
...
536 shpc_set_status(shpc, slot, SHPC_SLOT_STATUS_PRSNT_7_5W,
537 SHPC_SLOT_STATUS_PRSNT_MASK);
538: shpc->config[SHPC_SLOT_EVENT_LATCH(slot)] |=
539: SHPC_SLOT_EVENT_BUTTON |
540 SHPC_SLOT_EVENT_MRL |
541 SHPC_SLOT_EVENT_PRESENCE;
542 } else {
543 /* Press attention button to cancel removal */
544: shpc->config[SHPC_SLOT_EVENT_LATCH(slot)] |=
545: SHPC_SLOT_EVENT_BUTTON;
546 }
547 }
qemu/hw/ppc/e500.c:
147 uint32_t *pci_map = NULL;
148 int len;
149: uint32_t pci_ranges[14] =
150: {
151 0x2000000, 0x0, 0xc0000000,
152 0x0, 0xc0000000,
qemu/hw/usb/desc.c:
238 d->u.super_endpoint.bMaxBurst = ep->bMaxBurst;
239 d->u.super_endpoint.bmAttributes = ep->bmAttributes_super;
240: d->u.super_endpoint.wBytesPerInterval_lo =
241: usb_lo(ep->wBytesPerInterval);
242: d->u.super_endpoint.wBytesPerInterval_hi =
243: usb_hi(ep->wBytesPerInterval);
244 }
245
qemu/hw/usb/dev-smartcard-reader.c:
587 assert(s->bulk_in_pending_num > 0);
588 s->bulk_in_pending_num--;
589: s->current_bulk_in =
590: &s->bulk_in_pending[(s->bulk_in_pending_start++) % BULK_IN_PENDING_NUM];
591 }
592
...
1078 void ccid_card_card_removed(CCIDCardState *card)
1079 {
1080: USBCCIDState *s =
1081: DO_UPCAST(USBCCIDState, dev.qdev, card->qdev.parent_bus->parent);
1082
1083 ccid_on_slot_change(s, false);
....
1088 int ccid_card_ccid_attach(CCIDCardState *card)
1089 {
1090: USBCCIDState *s =
1091: DO_UPCAST(USBCCIDState, dev.qdev, card->qdev.parent_bus->parent);
1092
1093 DPRINTF(s, 1, "CCID Attach\n");
....
1100 void ccid_card_ccid_detach(CCIDCardState *card)
1101 {
1102: USBCCIDState *s =
1103: DO_UPCAST(USBCCIDState, dev.qdev, card->qdev.parent_bus->parent);
1104
1105 DPRINTF(s, 1, "CCID Detach\n");
....
1112 void ccid_card_card_error(CCIDCardState *card, uint64_t error)
1113 {
1114: USBCCIDState *s =
1115: DO_UPCAST(USBCCIDState, dev.qdev, card->qdev.parent_bus->parent);
1116
1117 s->bmCommandStatus = COMMAND_STATUS_FAILED;
....
1130 void ccid_card_card_inserted(CCIDCardState *card)
1131 {
1132: USBCCIDState *s =
1133: DO_UPCAST(USBCCIDState, dev.qdev, card->qdev.parent_bus->parent);
1134
1135 s->bmCommandStatus = COMMAND_STATUS_NO_ERROR;
....
1142 int ret = 0;
1143 CCIDCardState *card = CCID_CARD(qdev);
1144: USBCCIDState *s =
1145: DO_UPCAST(USBCCIDState, dev.qdev, card->qdev.parent_bus->parent);
1146
1147 if (ccid_card_inserted(s)) {
....
1156 {
1157 CCIDCardState *card = CCID_CARD(qdev);
1158: USBCCIDState *s =
1159: DO_UPCAST(USBCCIDState, dev.qdev, card->qdev.parent_bus->parent);
1160 int ret = 0;
1161
qemu/hw/usb/hcd-ehci.c:
728 for (i = 0; i < portcount; i++) {
729 s->companion_ports[firstport + i] = ports[i];
730: s->ports[firstport + i].speedmask |=
731: USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL;
732 /* Ensure devs attached before the initial reset go to the companion */
733 s->portsc[firstport + i] = PORTSC_POWNER;
...
958 }
959
960: if (((USBCMD_RUNSTOP | USBCMD_PSE | USBCMD_ASE) & val) !=
961: ((USBCMD_RUNSTOP | USBCMD_PSE | USBCMD_ASE) & s->usbcmd)) {
962 if (s->pstate == EST_INACTIVE) {
963 SET_LAST_RUN_CLOCK(s);
qemu/hw/usb/hcd-xhci.c:
3045 port->portnr = i + 1;
3046 port->uport = &xhci->uports[i];
3047: port->speedmask =
3048: USB_SPEED_MASK_LOW |
3049 USB_SPEED_MASK_FULL |
3050 USB_SPEED_MASK_HIGH;
qemu/hw/usb/redirect.c:
929 dev->parser->alt_setting_status_func = usbredir_alt_setting_status;
930 dev->parser->iso_stream_status_func = usbredir_iso_stream_status;
931: dev->parser->interrupt_receiving_status_func =
932: usbredir_interrupt_receiving_status;
933 dev->parser->bulk_streams_status_func = usbredir_bulk_streams_status;
934 dev->parser->control_packet_func = usbredir_control_packet;
...
1502 }
1503
1504: dev->endpoint[EP2I(ep)].interrupt_error =
1505: interrupt_receiving_status->status;
1506 if (interrupt_receiving_status->status == usb_redir_stall) {
1507 DPRINTF("interrupt receiving stopped by peer ep %02X\n", ep);
qemu/include/exec/exec-all.h:
224
225 /* we could use a ldr pc, [pc, #-4] kind of branch and avoid the flush */
226: *(uint32_t *)jmp_addr =
227: (*(uint32_t *)jmp_addr & ~0xffffff)
228 | (((addr - (jmp_addr + 8)) >> 2) & 0xffffff);
229
qemu/libcacard/card_7816.c:
232 case 0xf0:
233 default:
234: apdu->a_gen_type =
235: (apdu->a_cla == 0xff) ? VCARD_7816_PTS : VCARD_7816_PROPIETARY;
236 break;
237 }
...
695 }
696 if (*response == NULL) {
697: *response =
698: vcard_make_response(VCARD7816_STATUS_EXC_ERROR_MEMORY_FAILURE);
699 }
700 break;
701
702 case VCARD7816_INS_GET_DATA:
703: *response =
704: vcard_make_response(VCARD7816_STATUS_ERROR_COMMAND_NOT_SUPPORTED);
705 break;
706
707 default:
708: *response =
709: vcard_make_response(VCARD7816_STATUS_ERROR_COMMAND_NOT_SUPPORTED);
710 break;
711 }
...
758 break;
759 }
760: *response =
761: vcard_make_response(VCARD7816_STATUS_ERROR_COMMAND_NOT_SUPPORTED);
762 return VCARD_DONE;
763 }
qemu/libcacard/vcard_emul_nss.c:
1189 vreaderOpt->vname = g_strndup(vname, vname_length);
1190 vreaderOpt->card_type = type;
1191: vreaderOpt->type_params =
1192: g_strndup(type_params, type_params_length);
1193 count = count_tokens(args, ',', ')') + 1;
1194 vreaderOpt->cert_count = count;
qemu/libcacard/vscclient.c:
389 {
390 uint32_t *capabilities = (incoming->capabilities);
391: int num_capabilities =
392: 1 + ((mhHeader->length - sizeof(VSCMsgInit)) / sizeof(uint32_t));
393 int i;
394 int rv;
qemu/libdis/Makefile
qemu/libdis-user/Makefile
qemu/libuser/Makefile
qemu/linux-user/elfload.c:
1676 #ifdef CONFIG_USE_FDPIC
1677 {
1678: struct elf32_fdpic_loadseg *loadsegs = info->loadsegs =
1679: g_malloc(sizeof(*loadsegs) * info->nsegs);
1680
1681 for (i = 0; i < ehdr->e_phnum; ++i) {
qemu/linux-user/signal.c:
398 if (core_dump_signal(target_sig) && (ts->bprm->core_dump != NULL)) {
399 stop_all_tasks();
400: core_dumped =
401: ((*ts->bprm->core_dump)(target_sig, thread_env) == 0);
402 }
403 if (core_dumped) {
qemu/linux-user/syscall.c:
3885 const struct target_termios *target = src;
3886
3887: host->c_iflag =
3888: target_to_host_bitmask(tswap32(target->c_iflag), iflag_tbl);
3889: host->c_oflag =
3890: target_to_host_bitmask(tswap32(target->c_oflag), oflag_tbl);
3891: host->c_cflag =
3892: target_to_host_bitmask(tswap32(target->c_cflag), cflag_tbl);
3893: host->c_lflag =
3894: target_to_host_bitmask(tswap32(target->c_lflag), lflag_tbl);
3895 host->c_line = target->c_line;
3896
....
3920 const struct host_termios *host = src;
3921
3922: target->c_iflag =
3923: tswap32(host_to_target_bitmask(host->c_iflag, iflag_tbl));
3924: target->c_oflag =
3925: tswap32(host_to_target_bitmask(host->c_oflag, oflag_tbl));
3926: target->c_cflag =
3927: tswap32(host_to_target_bitmask(host->c_cflag, cflag_tbl));
3928: target->c_lflag =
3929: tswap32(host_to_target_bitmask(host->c_lflag, lflag_tbl));
3930 target->c_line = host->c_line;
3931
....
4707 ie = ioctl_entries;
4708 while (ie->target_cmd != 0) {
4709: if (((ie->target_cmd >> TARGET_IOC_SIZESHIFT) & TARGET_IOC_SIZEMASK) ==
4710: TARGET_IOC_SIZEMASK) {
4711 arg_type = ie->arg_type;
4712 if (arg_type[0] != TYPE_PTR) {
qemu/linux-user/arm/nwfpe/fpa11_cprt.c:
89 {
90 fpa11->fType[getFn(opcode)] = typeDouble;
91: fpa11->fpreg[getFn(opcode)].fDouble =
92: int32_to_float64(readRegister(getRd(opcode)), &fpa11->fp_status);
93 }
94 break;
qemu/net/socket.c:
725
726 if (sock->has_connect) {
727: if (net_socket_connect_init(peer, "socket", name, sock->connect) ==
728: -1) {
729 return -1;
730 }
...
747 return -1;
748 }
749: if (net_socket_udp_init(peer, "socket", name, sock->udp, sock->localaddr) ==
750: -1) {
751 return -1;
752 }
qemu/qga/commands-posix.c:
898 * This is safe as '1' and '0' cannot be shuffled in netmask. */
899 p = &((struct sockaddr_in6 *)ifa->ifa_netmask)->sin6_addr;
900: address_item->value->prefix =
901: ctpop32(((uint32_t *) p)[0]) +
902 ctpop32(((uint32_t *) p)[1]) +
903 ctpop32(((uint32_t *) p)[2]) +
qemu/roms/seabios/Makefile
qemu/roms/vgabios/Makefile
qemu/slirp/arp_table.c:
27 void arp_table_add(Slirp *slirp, uint32_t ip_addr, uint8_t ethaddr[ETH_ALEN])
28 {
29: const uint32_t broadcast_addr =
30: ~slirp->vnetwork_mask.s_addr | slirp->vnetwork_addr.s_addr;
31 ArpTable *arptbl = &slirp->arp_table;
32 int i;
..
66 uint8_t out_ethaddr[ETH_ALEN])
67 {
68: const uint32_t broadcast_addr =
69: ~slirp->vnetwork_mask.s_addr | slirp->vnetwork_addr.s_addr;
70 ArpTable *arptbl = &slirp->arp_table;
71 int i;
qemu/slirp/ip_icmp.c:
181 /* Send the packet */
182 addr.sin_family = AF_INET;
183: if ((so->so_faddr.s_addr & slirp->vnetwork_mask.s_addr) ==
184: slirp->vnetwork_addr.s_addr) {
185 /* It's an alias */
186 if (so->so_faddr.s_addr == slirp->vnameserver_addr.s_addr) {
qemu/slirp/slirp.c:
632 }
633
634: if ((ah->ar_tip & slirp->vnetwork_mask.s_addr) ==
635: slirp->vnetwork_addr.s_addr) {
636 if (ah->ar_tip == slirp->vnameserver_addr.s_addr ||
637 ah->ar_tip == slirp->vhost_addr.s_addr)
...
820 (htonl(0x0204) & ~slirp->vnetwork_mask.s_addr);
821 }
822: if ((guest_addr->s_addr & slirp->vnetwork_mask.s_addr) !=
823: slirp->vnetwork_addr.s_addr ||
824 guest_addr->s_addr == slirp->vhost_addr.s_addr ||
825 guest_addr->s_addr == slirp->vnameserver_addr.s_addr) {
...
1116 return ret;
1117
1118: if ((so->so_faddr.s_addr & slirp->vnetwork_mask.s_addr) !=
1119: slirp->vnetwork_addr.s_addr) {
1120 return -EINVAL;
1121 }
qemu/slirp/tcp_subr.c:
344
345 addr.sin_family = AF_INET;
346: if ((so->so_faddr.s_addr & slirp->vnetwork_mask.s_addr) ==
347: slirp->vnetwork_addr.s_addr) {
348 /* It's an alias */
349 if (so->so_faddr.s_addr == slirp->vnameserver_addr.s_addr) {
...
918 }
919 }
920: sb->sb_cc =
921: snprintf(sb->sb_wptr, sb->sb_datalen - (sb->sb_wptr - sb->sb_data),
922 "Error: No application configured.\r\n");
923 sb->sb_wptr += sb->sb_cc;
qemu/slirp/udp.c:
293
294 saddr = *addr;
295: if ((so->so_faddr.s_addr & slirp->vnetwork_mask.s_addr) ==
296: slirp->vnetwork_addr.s_addr) {
297 uint32_t inv_mask = ~slirp->vnetwork_mask.s_addr;
298
qemu/target-arm/iwmmxt_helper.c:
471 (((x & (0xffffll << 32)) >> n) & (0xffffll << 32)) |
472 (((x & (0xffffll << 48)) >> n) & (0xffffll << 48));
473: env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =
474: NZBIT16(x >> 0, 0) | NZBIT16(x >> 16, 1) |
475 NZBIT16(x >> 32, 2) | NZBIT16(x >> 48, 3);
476 return x;
...
481 x = ((x & (0xffffffffll << 0)) >> n) |
482 ((x >> n) & (0xffffffffll << 32));
483: env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =
484: NZBIT32(x >> 0, 0) | NZBIT32(x >> 32, 1);
485 return x;
486 }
...
499 (((x & (0xffffll << 32)) << n) & (0xffffll << 32)) |
500 (((x & (0xffffll << 48)) << n) & (0xffffll << 48));
501: env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =
502: NZBIT16(x >> 0, 0) | NZBIT16(x >> 16, 1) |
503 NZBIT16(x >> 32, 2) | NZBIT16(x >> 48, 3);
504 return x;
...
509 x = ((x << n) & (0xffffffffll << 0)) |
510 ((x & (0xffffffffll << 32)) << n);
511: env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =
512: NZBIT32(x >> 0, 0) | NZBIT32(x >> 32, 1);
513 return x;
514 }
...
527 ((uint64_t) ((EXTEND16(x >> 32) >> n) & 0xffff) << 32) |
528 ((uint64_t) ((EXTEND16(x >> 48) >> n) & 0xffff) << 48);
529: env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =
530: NZBIT16(x >> 0, 0) | NZBIT16(x >> 16, 1) |
531 NZBIT16(x >> 32, 2) | NZBIT16(x >> 48, 3);
532 return x;
...
537 x = (((EXTEND32(x >> 0) >> n) & 0xffffffff) << 0) |
538 (((EXTEND32(x >> 32) >> n) & 0xffffffff) << 32);
539: env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =
540: NZBIT32(x >> 0, 0) | NZBIT32(x >> 32, 1);
541 return x;
542 }
...
559 ((((x & (0xffffll << 48)) >> n) |
560 ((x & (0xffffll << 48)) << (16 - n))) & (0xffffll << 48));
561: env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =
562: NZBIT16(x >> 0, 0) | NZBIT16(x >> 16, 1) |
563 NZBIT16(x >> 32, 2) | NZBIT16(x >> 48, 3);
564 return x;
...
571 ((x << (32 - n)) & (0xffffffffll << 0)) |
572 ((x & (0xffffffffll << 32)) << (32 - n));
573: env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =
574: NZBIT32(x >> 0, 0) | NZBIT32(x >> 32, 1);
575 return x;
576 }
...
589 (((x >> ((n << 0) & 0x30)) & 0xffff) << 32) |
590 (((x >> ((n >> 2) & 0x30)) & 0xffff) << 48);
591: env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =
592: NZBIT16(x >> 0, 0) | NZBIT16(x >> 16, 1) |
593 NZBIT16(x >> 32, 2) | NZBIT16(x >> 48, 3);
594 return x;
...
602 (((b >> 0) & 0xff) << 32) | (((b >> 16) & 0xff) << 40) |
603 (((b >> 32) & 0xff) << 48) | (((b >> 48) & 0xff) << 56);
604: env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =
605: NZBIT8(a >> 0, 0) | NZBIT8(a >> 8, 1) |
606 NZBIT8(a >> 16, 2) | NZBIT8(a >> 24, 3) |
607 NZBIT8(a >> 32, 4) | NZBIT8(a >> 40, 5) |
...
614 a = (((a >> 0) & 0xffff) << 0) | (((a >> 32) & 0xffff) << 16) |
615 (((b >> 0) & 0xffff) << 32) | (((b >> 32) & 0xffff) << 48);
616: env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =
617: NZBIT16(a >> 0, 0) | NZBIT16(a >> 16, 1) |
618 NZBIT16(a >> 32, 2) | NZBIT16(a >> 48, 3);
619 return a;
...
623 {
624 a = (a & 0xffffffff) | ((b & 0xffffffff) << 32);
625: env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =
626: NZBIT32(a >> 0, 0) | NZBIT32(a >> 32, 1);
627 return a;
628 }
...
635 (((b >> 0) & 0xff) << 32) | (((b >> 16) & 0xff) << 40) |
636 (((b >> 32) & 0xff) << 48) | (((b >> 48) & 0xff) << 56);
637: env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =
638: NZBIT8(a >> 0, 0) | NZBIT8(a >> 8, 1) |
639 NZBIT8(a >> 16, 2) | NZBIT8(a >> 24, 3) |
640 NZBIT8(a >> 32, 4) | NZBIT8(a >> 40, 5) |
...
647 a = (((a >> 0) & 0xffff) << 0) | (((a >> 32) & 0xffff) << 16) |
648 (((b >> 0) & 0xffff) << 32) | (((b >> 32) & 0xffff) << 48);
649: env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =
650: NZBIT16(a >> 0, 0) | NZBIT16(a >> 16, 1) |
651 NZBIT16(a >> 32, 2) | NZBIT16(a >> 48, 3);
652 return a;
...
656 {
657 a = (a & 0xffffffff) | ((b & 0xffffffff) << 32);
658: env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =
659: NZBIT32(a >> 0, 0) | NZBIT32(a >> 32, 1);
660 return a;
661 }
qemu/target-i386/cpu.c:
1470 KVMState *s = kvm_state;
1471
1472: env->cpuid_features &=
1473: kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
1474: env->cpuid_ext_features &=
1475: kvm_arch_get_supported_cpuid(s, 1, 0, R_ECX);
1476: env->cpuid_ext2_features &=
1477: kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX);
1478: env->cpuid_ext3_features &=
1479: kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_ECX);
1480: env->cpuid_svm_features &=
1481: kvm_arch_get_supported_cpuid(s, 0x8000000A, 0, R_EDX);
1482: env->cpuid_7_0_ebx_features &=
1483: kvm_arch_get_supported_cpuid(s, 7, 0, R_EBX);
1484: env->cpuid_kvm_features &=
1485: kvm_arch_get_supported_cpuid(s, KVM_CPUID_FEATURES, 0, R_EAX);
1486: env->cpuid_ext4_features &=
1487: kvm_arch_get_supported_cpuid(s, 0xC0000001, 0, R_EDX);
1488
1489 }
....
2021
2022 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
2023: && (cenv->cpuid_features & (CPUID_MCE | CPUID_MCA)) ==
2024: (CPUID_MCE | CPUID_MCA)) {
2025 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF;
2026 cenv->mcg_ctl = ~(uint64_t)0;
qemu/target-i386/helper.c:
392 printf("CR0 update: CR0=0x%08x\n", new_cr0);
393 #endif
394: if ((new_cr0 & (CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK)) !=
395: (env->cr[0] & (CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK))) {
396 tlb_flush(env, 1);
397 }
qemu/target-i386/kvm.c:
1492 events.flags = 0;
1493 if (level >= KVM_PUT_RESET_STATE) {
1494: events.flags |=
1495: KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR;
1496 }
1497
....
1518 env->error_code = events.exception.error_code;
1519
1520: env->interrupt_injected =
1521: events.interrupt.injected ? events.interrupt.nr : -1;
1522 env->soft_interrupt = events.interrupt.soft;
1523
....
2160 int ret;
2161
2162: dev_data.assigned_dev_id =
2163: (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn;
2164
2165 ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data);
qemu/target-i386/translate.c:
3704 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op2_offset);
3705 if (ot == OT_LONG) {
3706: SSEFunc_i_ep sse_fn_i_ep =
3707: sse_op_table3bi[((b >> 7) & 2) | (b & 1)];
3708 sse_fn_i_ep(cpu_tmp2_i32, cpu_env, cpu_ptr0);
3709 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
3710 } else {
3711 #ifdef TARGET_X86_64
3712: SSEFunc_l_ep sse_fn_l_ep =
3713: sse_op_table3bq[((b >> 7) & 2) | (b & 1)];
3714 sse_fn_l_ep(cpu_T[0], cpu_env, cpu_ptr0);
3715 #else
....
6818 break;
6819 case 0x9b: /* fwait */
6820: if ((s->flags & (HF_MP_MASK | HF_TS_MASK)) ==
6821: (HF_MP_MASK | HF_TS_MASK)) {
6822 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
6823 } else {
qemu/target-mips/helper.c:
242 env->CP0_Context = (env->CP0_Context & ~0x007fffff) |
243 ((address >> 9) & 0x007ffff0);
244: env->CP0_EntryHi =
245: (env->CP0_EntryHi & 0xFF) | (address & (TARGET_PAGE_MASK << 1));
246 #if defined(TARGET_MIPS64)
247 env->CP0_EntryHi &= env->SEGMask;
qemu/target-mips/op_helper.c:
451
452 for (i = 0; i < base_reglist; i++) {
453: env->active_tc.gpr[multiple_regs[i]] =
454: (target_long)do_lw(env, addr, mem_idx);
455 addr += 4;
456 }
qemu/target-openrisc/interrupt_helper.c:
35 #ifndef CONFIG_USER_ONLY
36 if (cpu->env.sr & SR_DME) {
37: cpu->env.tlb->cpu_openrisc_map_address_data =
38: &cpu_openrisc_get_phys_data;
39 } else {
40: cpu->env.tlb->cpu_openrisc_map_address_data =
41: &cpu_openrisc_get_phys_nommu;
42 }
43
44 if (cpu->env.sr & SR_IME) {
45: cpu->env.tlb->cpu_openrisc_map_address_code =
46: &cpu_openrisc_get_phys_code;
47 } else {
48: cpu->env.tlb->cpu_openrisc_map_address_code =
49: &cpu_openrisc_get_phys_nommu;
50 }
51
qemu/target-openrisc/sys_helper.c:
50 env->sr |= SR_FO; /* FO is const equal to 1 */
51 if (env->sr & SR_DME) {
52: env->tlb->cpu_openrisc_map_address_data =
53: &cpu_openrisc_get_phys_data;
54 } else {
55: env->tlb->cpu_openrisc_map_address_data =
56: &cpu_openrisc_get_phys_nommu;
57 }
58
59 if (env->sr & SR_IME) {
60: env->tlb->cpu_openrisc_map_address_code =
61: &cpu_openrisc_get_phys_code;
62 } else {
63: env->tlb->cpu_openrisc_map_address_code =
64: &cpu_openrisc_get_phys_nommu;
65 }
66 break;
qemu/target-ppc/mmu_helper.c:
2089 printf("DSI: invalid exception (%d)\n", ret);
2090 env->exception_index = POWERPC_EXCP_PROGRAM;
2091: env->error_code =
2092: POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL;
2093 env->spr[SPR_DAR] = address;
2094 break;
qemu/target-sparc/ldst_helper.c:
880 /* Mappings generated during no-fault mode or MMU
881 disabled mode are invalid in normal mode */
882: if ((oldreg & (MMU_E | MMU_NF | env->def->mmu_bm)) !=
883: (env->mmuregs[reg] & (MMU_E | MMU_NF | env->def->mmu_bm))) {
884 tlb_flush(env, 1);
885 }
qemu/target-xtensa/helper.c:
164 env->sregs[EPC1 + level - 1] = env->pc;
165 env->sregs[EPS2 + level - 2] = env->sregs[PS];
166: env->sregs[PS] =
167: (env->sregs[PS] & ~PS_INTLEVEL) | level | PS_EXCM;
168 env->pc = relocated_vector(env,
169 env->config->interrupt_vector[level]);
...
180 } else {
181 env->sregs[EPC1] = env->pc;
182: env->exception_index =
183: (env->sregs[PS] & PS_UM) ? EXC_USER : EXC_KERNEL;
184 }
185 env->sregs[PS] |= PS_EXCM;
...
544 uint32_t page_size;
545 unsigned access;
546: uint32_t pt_vaddr =
547: (env->sregs[PTEVADDR] | (vaddr >> 10)) & 0xfffffffc;
548 int ret = get_physical_addr_mmu(env, false, pt_vaddr, 0, 0,
549 &paddr, &page_size, &access, false);
...
565 uint32_t wi = 0;
566 uint32_t ei = (vaddr >> 29) & 0x7;
567: const xtensa_tlb_entry *entry =
568: xtensa_tlb_get_entry(env, dtlb, wi, ei);
569
570 *access = region_attr_to_access(entry->attr);
...
614 {
615 unsigned wi, ei;
616: const xtensa_tlb *conf =
617: dtlb ? &env->config->dtlb : &env->config->itlb;
618 unsigned (*attr_to_access)(uint32_t) =
619 xtensa_option_enabled(env->config, XTENSA_OPTION_MMU) ?
...
634
635 for (ei = 0; ei < conf->way_size[wi]; ++ei) {
636: const xtensa_tlb_entry *entry =
637: xtensa_tlb_get_entry(env, dtlb, wi, ei);
638
639 if (entry->asid) {
qemu/target-xtensa/op_helper.c:
243 env->regs[(callinc << 2) | (s & 3)] = env->regs[s] - (imm << 3);
244 rotate_window(env, callinc);
245: env->sregs[WINDOW_START] |=
246: windowstart_bit(env->sregs[WINDOW_BASE], env);
247 }
248 }
qemu/target-xtensa/translate.c:
2896 int max_insns = tb->cflags & CF_COUNT_MASK;
2897 uint32_t pc_start = tb->pc;
2898: uint32_t next_page_start =
2899: (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
2900
2901 if (max_insns == 0) {
qemu/target-xtensa/xtensa-semi.c:
170
171 while (len > 0) {
172: hwaddr paddr =
173: cpu_get_phys_page_debug(env, vaddr);
174: uint32_t page_left =
175: TARGET_PAGE_SIZE - (vaddr & (TARGET_PAGE_SIZE - 1));
176 uint32_t io_sz = page_left < len ? page_left : len;
177 hwaddr sz = io_sz;
qemu/tcg/tcg.c:
2219
2220 #ifdef USE_TCG_OPTIMIZATIONS
2221: s->gen_opparam_ptr =
2222: tcg_optimize(s, s->gen_opc_ptr, s->gen_opparam_buf, tcg_op_defs);
2223 #endif
2224
qemu/ui/console.c:
1499 }
1500
1501: s->cursor_timer =
1502: qemu_new_timer_ms(rt_clock, text_console_update_cursor, s);
1503
1504 s->hw_invalidate = text_console_invalidate;
qemu/ui/vnc-auth-sasl.c:
575 secprops.maxbufsize = 8192;
576 /* Forbid any anonymous or trivially crackable auth */
577: secprops.security_flags =
578: SASL_SEC_NOANONYMOUS | SASL_SEC_NOPLAINTEXT;
579 }
580
qemu/ui/vnc-enc-zrle.c:
304 bool fits_in_ms3bytes;
305
306: fits_in_ls3bytes =
307: ((vs->client_pf.rmax << vs->client_pf.rshift) < (1 << 24) &&
308 (vs->client_pf.gmax << vs->client_pf.gshift) < (1 << 24) &&
309 (vs->client_pf.bmax << vs->client_pf.bshift) < (1 << 24));
265 matches across 126 files
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