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#!/usr/bin/env python | |
from amaranth import * | |
from amaranth.lib.wiring import * | |
from amaranth.back import verilog | |
class RequestConsumer(Signature): | |
def __init__(self): | |
super().__init__({ | |
"data": In(32), | |
"valid": In(1), | |
"ready": Out(1), | |
}) | |
class ResponseProducer(Signature): | |
def __init__(self): | |
super().__init__({ | |
"data": Out(32), | |
"valid": Out(1), | |
}) | |
class MyModule(Component): | |
def __init__(self): | |
signature = Signature({ | |
"req": In(RequestConsumer()), | |
"resp": Out(ResponseProducer()), | |
}) | |
super().__init__(signature) | |
def elaborate(self, platform): | |
m = Module() | |
m.d.comb += [ | |
self.req.ready.eq(1), | |
self.resp.data.eq(self.req.data + 1), | |
self.req.valid.eq(1), | |
] | |
return m | |
m = MyModule() | |
v = verilog.convert(m) |
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