ekiwi

cd gtkwave-gtk3
./configure --disable-dependency-tracking --disable-mime-update --enable-gtk3 --enable-judy --with-gsettings --with-tirpc

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/* verilator lint_off UNOPTFLAT */
// behavioral clock gate
module ClockBufferBB(input I, input CE, output O);
  reg en_latched /*verilator clock_enable*/;
  always_latch @(*) if (!I) en_latched = CE;
  assign O = en_latched & I;
endmodule

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// Copyright 2020 The Regents of the University of California
// released under BSD 3-Clause License
// author: Kevin Laeufer <laeufer@cs.berkeley.edu>

// Chisel implementations of various multiported FPGA memories
// as described by Charles Eric LaForest, University of Toronto.
// see: http://fpgacpu.ca/multiport/ and http://fpgacpu.ca/multiport/Multiported-Memory-Example-Code/

package impl
import chisel3._

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module mem(
    input  wire clock,
    input  wire [7:0]  write_addr,
    input  wire [31:0] write_data,
    input  wire [7:0]  read_addr,
    output wire [31:0] read_data
);

reg [31:0] m [255:0];
reg [31:0] r;

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// See LICENSE for license details.

package firrtl.formal

import uclid.smt
import uclid.smt.SolverResult

trait CallCount {
  def callCount: Int
}

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#!/usr/bin/env python3
# -*- coding: utf-8 -*-
#
# Copyright (c) 2015 Kevin Laeufer <kevin.laeufer@rwth-aachen.de>

# bite_time.py

class UserSettings(object):
	def __init__(self, clk, bitrate, sampling_point, max_tolerance=0.02):
		self.clk = clk

ekiwi

use std::mem;

#[repr(u8)]
#[derive(PartialEq, Debug)]
enum Field {
	Invalid = 0x00,	// FIXME: this is ugly
	A = 0x01,
	B = 0x02,
	C = 0x03
}

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#
# Freescale Kinetis K20 devices
#
# This microcontroller is used on the mchck board.
#
# This file is based on k40.cfg and stm32_stlink.cfg from
# openocd git repository.
# This has only been tested with an stlink-v2
# and a MK20DX128VLF5.
# The default WORKAREASIZE is probably too small.