Skip to content

Instantly share code, notes, and snippets.

Rigol LA schematics from this thread: https://www.eevblog.com/forum/testgear/rpl1116-active-logic-probe-pod-for-1000z-series-teardown/msg2086255/#msg2086255
@electroniceel
electroniceel / gist:478a0b3c7ae572e01482f9caee491f63
Created February 2, 2020 13:22
sipgate pjsip_wizard config
[sipgate-template](!)
type = wizard
sends_auth = yes
sends_registrations = yes
accepts_registrations = no
transport = transport-udp
; no tcp or tls support
remote_hosts = sipgate.de:5060
endpoint/allow = !all,g722,alaw
endpoint/context = from-sipgate
CPLD output enable
@electroniceel
electroniceel / _init_.py
Last active January 7, 2020 18:41
asterisk cti dial with callfiles
from flask import *
import re
import json
import os
import tempfile
import shutil
import stat
script_dir = os.path.dirname(os.path.realpath(__file__))
[gerd@rdx software]$ ~/.local/bin/glasgow run selftest pins-ext
Traceback (most recent call last):
File "/home/gerd/.local/bin/glasgow", line 11, in <module>
load_entry_point('glasgow', 'console_scripts', 'glasgow')()
File "/home/gerd/opensource/Glasgow/software/glasgow/cli.py", line 787, in main
exit(loop.run_until_complete(_main()))
File "/usr/lib64/python3.7/asyncio/base_events.py", line 579, in run_until_complete
return future.result()
File "/home/gerd/opensource/Glasgow/software/glasgow/cli.py", line 477, in _main
plan = target.build_plan()