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@elimelec elimelec/cactigen
Created May 7, 2017

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new string[]{
@"# Cache size",
@"-size (bytes) 134217728",
@"",
@"# Line size",
@"-block size (bytes) 64",
@"",
@"# To model Fully Associative cache, set associativity to zero",
@"-associativity 1",
@"",
@"-read-write port 1",
@"-exclusive read port 0",
@"-exclusive write port 0",
@"-single ended read ports 0",
@"",
@"# Multiple banks connected using a bus",
@"-UCA bank count 1",
@"-technology (u) 0.090",
@"",
@"# following three parameters are meaningful only for main memories",
@"",
@"-page size (bits) 8192 ",
@"-burst length 8",
@"-internal prefetch width 8",
@"",
@"# following parameter can have one of five values -- (itrs-hp, itrs-lstp, itrs-lop, lp-dram, comm-dram)",
@"-Data array cell type - ""comm-dram""",
@"",
@"# following parameter can have one of three values -- (itrs-hp, itrs-lstp, itrs-lop)",
@"-Data array peripheral type - ""itrs-hp""",
@"",
@"# following parameter can have one of five values -- (itrs-hp, itrs-lstp, itrs-lop, lp-dram, comm-dram)",
@"-Tag array cell type - ""itrs-hp""",
@"",
@"# following parameter can have one of three values -- (itrs-hp, itrs-lstp, itrs-lop)",
@"-Tag array peripheral type - ""itrs-hp""",
@"",
@"# Bus width include data bits and address bits required by the decoder",
@"-output/input bus width 256",
@"",
@"// 300-400 in steps of 10",
@"-operating temperature (K) 350",
@"",
@"# Type of memory - cache (with a tag array) or ram (scratch ram similar to a register file) ",
@"# or main memory (no tag array and every access will happen at a page granularity Ref: CACTI 5.3 report)",
@"-cache type ""main memory""",
@"",
@"# to model special structure like branch target buffers, directory, etc. ",
@"# change the tag size parameter",
@"# if you want cacti to calculate the tagbits, set the tag size to ""default""",
@"-tag size (b) ""default""",
@"",
@"# fast - data and tag access happen in parallel",
@"# sequential - data array is accessed after accessing the tag array",
@"# normal - data array lookup and tag access happen in parallel",
@"# final data block is broadcasted in data array h-tree ",
@"# after getting the signal from the tag array",
@"-access mode (normal, sequential, fast) - ""normal""",
@"",
@"",
@"# DESIGN OBJECTIVE for UCA (or banks in NUCA)",
@"-design objective (weight delay, dynamic power, leakage power, cycle time, area) 0:0:0:0:100",
@"",
@"# Percentage deviation from the minimum value ",
@"# Ex: A deviation value of 10:1000:1000:1000:1000 will try to find an organization",
@"# that compromises at most 10% delay. ",
@"# NOTE: Try reasonable values for % deviation. Inconsistent deviation",
@"# percentage values will not produce any valid organizations. For example,",
@"# 0:0:100:100:100 will try to identify an organization that has both",
@"# least delay and dynamic power. Since such an organization is not possible, CACTI will",
@"# throw an error. Refer CACTI-6 Technical report for more details",
@"-deviate (delay, dynamic power, leakage power, cycle time, area) 60:100000:100000:100000:1000000",
@"",
@"# Objective for NUCA",
@"-NUCAdesign objective (weight delay, dynamic power, leakage power, cycle time, area) 100:100:0:0:100",
@"-NUCAdeviate (delay, dynamic power, leakage power, cycle time, area) 10:10000:10000:10000:10000",
@"",
@"# Set optimize tag to ED or ED^2 to obtain a cache configuration optimized for",
@"# energy-delay or energy-delay sq. product",
@"# Note: Optimize tag will disable weight or deviate values mentioned above",
@"# Set it to NONE to let weight and deviate values determine the ",
@"# appropriate cache configuration",
@"-Optimize ED or ED^2 (ED, ED^2, NONE): ""NONE""",
@"",
@"-Cache model (NUCA, UCA) - ""UCA""",
@"",
@"# In order for CACTI to find the optimal NUCA bank value the following",
@"# variable should be assigned 0.",
@"-NUCA bank count 0",
@"",
@"# NOTE: for nuca network frequency is set to a default value of ",
@"# 5GHz in time.c. CACTI automatically",
@"# calculates the maximum possible frequency and downgrades this value if necessary",
@"",
@"# By default CACTI considers both full-swing and low-swing ",
@"# wires to find an optimal configuration. However, it is possible to ",
@"# restrict the search space by changing the signalling from ""default"" to ",
@"# ""fullswing"" or ""lowswing"" type.",
@"-Wire signalling (fullswing, lowswing, default) - ""Global_10""",
@"",
@"-Wire inside mat - ""global""",
@"-Wire outside mat - ""global""",
@"",
@"-Interconnect projection - ""conservative""",
@"",
@"# Contention in network (which is a function of core count and cache level) is one of",
@"# the critical factor used for deciding the optimal bank count value",
@"# core count can be 4, 8, or 16",
@"-Core count 8",
@"-Cache level (L2/L3) - ""L3""",
@"",
@"-Add ECC - ""true""",
@"",
@"-Print level (DETAILED, CONCISE) - ""DETAILED""",
@"",
@"# for debugging",
@"-Print input parameters - ""true""",
@"# force CACTI to model the cache with the ",
@"# following Ndbl, Ndwl, Nspd, Ndsam,",
@"# and Ndcm values",
@"-Force cache config - ""false""",
@"-Ndwl 64",
@"-Ndbl 64",
@"-Nspd 64",
@"-Ndcm 1",
@"-Ndsam1 4",
@"-Ndsam2 1",
@""
}
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