emoon/68k_timing.md Secret

## 68k_timing.md

      
    Raw
  

              68k_timing.md
            
          
    | #xxx     | 12 | *  |  *   |   *   |   *   |   *   |    *     |   *   |   *   |
BTST

Operation:      TEST ( < bit number > of Destination) → Z
Assembler: btest dn, < ea >        btest # < data > , < ea >        
Attributes: Size = (Byte, Long)
Description: Tests a bit in the destination operand and sets the Z condition code appropriately. When a data register is the destination, any of the 32 bits can be specified by a modulo 32- bit number. When a memory location is the destination, the operation is a byte operation, and the bit number is modulo 8. In all cases, bit zero refers to the least significant bit. The bit number for this operation can be specified in either of two ways:
1. Immediate—The bit number is specified in a second word of the instruction.
2. Register—The specified data register contains the bit number.


btst
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


Dn
6
*
8
8
10
12
14
12
16


#xxx
10
*
12
12
14
16
18
16
20


btst.l
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


Dn
6
*
*
*
*
*
*
*
*


#xxx
10
*
*
*
*
*
*
*
*


CMP

Operation:      Destination – Source → cc
Assembler: cmp < ea > , Dn        
Attributes: Size = (Byte, Word, Long)
Description: Subtracts the source operand from the destination data register and sets the condition codes according to the result; the data register is not changed. The size of the operation can be byte, word, or long.


cmp
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


Dn
4
6
*
*
*
*
*
*
*


An
4
6
*
*
*
*
*
*
*


(An)
8
10
*
*
*
*
*
*
*


(An)+
8
10
*
12
*
*
*
*
*


-(An)
10
12
*
*
*
*
*
*
*


d(An)
12
14
*
*
*
*
*
*
*


d(An,Dn)
14
16
*
*
*
*
*
*
*


xxx.W
12
14
*
*
*
*
*
*
*


xxx.L
16
18
*
*
*
*
*
*
*


d(PC)
12
14
*
*
*
*
*
*
*


d(PC,Dn)
14
16
*
*
*
*
*
*
*


#xxx
8
10
12
12
14
16
18
16
20


cmp.l
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


Dn
6
6
*
*
*
*
*
*
*


An
6
6
*
*
*
*
*
*
*


(An)
14
14
*
*
*
*
*
*
*


(An)+
14
14
*
20
*
*
*
*
*


-(An)
16
16
*
*
*
*
*
*
*


d(An)
18
18
*
*
*
*
*
*
*


d(An,Dn)
20
20
*
*
*
*
*
*
*


xxx.W
18
18
*
*
*
*
*
*
*


xxx.L
22
22
*
*
*
*
*
*
*


d(PC)
18
18
*
*
*
*
*
*
*


d(PC,Dn)
20
20
*
*
*
*
*
*
*


#xxx
14
10
20
20
22
24
26
24
28


DIVU

Operation:      Destination / Source → Destination
Assembler: DIVS.W < ea > ,Dn32/16 → 16r – 16q        
Attributes: Size = (Word)
Description: Divides the signed destination operand by the signed source operand and stores the signed result in the destination. The result is a quotient in the lower word (least significant 16 bits) and a remainder in the upper word (most significant 16 bits). The sign of the remainder is the same as the sign of the dividend.
Two special conditions may arise during the operation:
1. Division by zero causes a trap.
2. Overflow may be detected and set before the instruction completes. If the instruction detects an overflow, it sets the overflow condition code, and the operands are unaffected.


divu
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


Dn
140
*
*
*
*
*
*
*
*


(An)
144
*
*
*
*
*
*
*
*


(An)+
144
*
*
*
*
*
*
*
*


-(An)
146
*
*
*
*
*
*
*
*


d(An)
148
*
*
*
*
*
*
*
*


d(An,Dn)
150
*
*
*
*
*
*
*
*


xxx.W
148
*
*
*
*
*
*
*
*


xxx.L
152
*
*
*
*
*
*
*
*


d(PC)
148
*
*
*
*
*
*
*
*


d(PC,Dn)
150
*
*
*
*
*
*
*
*


#xxx
144
*
*
*
*
*
*
*
*


divu.l
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


DIVS

Operation:      Destination / Source → Destination
Assembler: DIVS.W < ea > ,Dn32/16 → 16r – 16q        
Attributes: Size = (Word)
Description: Divides the signed destination operand by the signed source operand and stores the signed result in the destination. The result is a quotient in the lower word (least significant 16 bits) and a remainder in the upper word (most significant 16 bits). The sign of the remainder is the same as the sign of the dividend.
Two special conditions may arise during the operation:
1. Division by zero causes a trap.
2. Overflow may be detected and set before the instruction completes. If the instruction detects an overflow, it sets the overflow condition code, and the operands are unaffected.


divs
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


Dn
158
*
*
*
*
*
*
*
*


(An)
162
*
*
*
*
*
*
*
*


(An)+
162
*
*
*
*
*
*
*
*


-(An)
164
*
*
*
*
*
*
*
*


d(An)
166
*
*
*
*
*
*
*
*


d(An,Dn)
168
*
*
*
*
*
*
*
*


xxx.W
166
*
*
*
*
*
*
*
*


xxx.L
170
*
*
*
*
*
*
*
*


d(PC)
166
*
*
*
*
*
*
*
*


d(PC,Dn)
168
*
*
*
*
*
*
*
*


#xxx
162
*
*
*
*
*
*
*
*


divs.l
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


EOR

Operation:      Destination EOR Source → Destination
Assembler: eor Dn, < ea >        
Attributes: Size = (Byte, Word, Long)
Description: Performs an exclusive-OR operation on the destination operand using the source operand and stores the result in the destination location. The size of the operation may be specified to be byte, word, or long. The source operand must be a data register. The destination operand is specified in the effective address field.


eor
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


Dn
4
*
12
12
14
16
18
16
20


#xxx
8
*
16
16
18
20
22
20
24


eor.l
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


Dn
8
*
20
20
22
24
26
24
28


#xxx
16
*
28
28
30
32
34
32
36


EXG

Operation:      Rx ←→ Ry
Assembler: exg Dx,Dy        exg Ax,Ay        exg Dx,Ay        
Attributes: Size = (Long)
Description: Exchanges the contents of two 32-bit registers. The instruction performs three types of exchanges.
1. Exchange data registers.
2. Exchange address registers.
3. Exchange a data register and an address register.


exg
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


Dn
6
6
*
*
*
*
*
*
*


An
6
6
*
*
*
*
*
*
*


exg.l
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


Dn
6
6
*
*
*
*
*
*
*


An
6
6
*
*
*
*
*
*
*


LEA

Operation:      < ea > → An
Assembler: lea < ea >, An         
Attributes: Size = (Long)
Description: Loads the effective address into the specified address register. All 32 bits of the address register are affected by this instruction.


lea
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


(An)
*
8
*
*
*
*
*
*
*


d(An)
*
12
*
*
*
*
*
*
*


d(An,Dn)
*
8
*
*
*
*
*
*
*


xxx.W
*
12
*
*
*
*
*
*
*


xxx.L
*
8
*
*
*
*
*
*
*


d(PC)
*
12
*
*
*
*
*
*
*


d(PC,Dn)
*
8
*
*
*
*
*
*
*


lea.l
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


(An)
*
8
*
*
*
*
*
*
*


d(An)
*
12
*
*
*
*
*
*
*


d(An,Dn)
*
8
*
*
*
*
*
*
*


xxx.W
*
12
*
*
*
*
*
*
*


xxx.L
*
8
*
*
*
*
*
*
*


d(PC)
*
12
*
*
*
*
*
*
*


d(PC,Dn)
*
8
*
*
*
*
*
*
*


MOVE

Operation:      Source → Destination
Assembler: move < ea >, < ea >        
Attributes: Size = (Byte, Word, Long)
Description: Moves the data at the source to the destination location and sets the condition codes according to the data. The size of the operation may be specified as byte, word, or long.


move
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


Dn
4
4
8
8
8
12
14
12
16


An
4
4
8
8
8
12
14
12
16


(An)
8
8
12
12
12
16
18
16
20


(An)+
8
8
12
12
12
16
18
16
20


-(An)
10
10
14
14
14
18
20
18
22


d(An)
12
12
16
16
16
20
22
20
24


d(An,Dn)
14
14
18
18
18
22
24
22
26


xxx.W
12
12
16
16
16
20
22
20
24


xxx.L
16
16
20
20
20
24
26
24
28


d(PC)
12
12
16
16
16
20
22
20
24


d(PC,Dn)
14
14
18
18
18
22
24
22
26


#xxx
8
8
12
12
12
16
18
16
20


move.l
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


Dn
4
4
12
12
12
16
18
16
20


An
4
4
12
12
12
16
18
16
20


(An)
12
12
20
20
20
24
26
24
28


(An)+
12
12
20
20
20
24
26
24
28


-(An)
14
14
22
22
22
26
28
26
30


d(An)
16
16
24
24
24
28
30
28
32


d(An,Dn)
18
18
26
26
26
30
32
30
34


xxx.W
16
16
24
24
24
28
30
28
32


xxx.L
20
20
28
28
28
32
34
32
36


d(PC)
16
16
24
24
24
28
30
28
32


d(PC,Dn)
18
18
26
26
26
30
32
30
34


#xxx
4
8
20
20
20
24
26
24
28


MULS

Operation:      Source * Destination → Destination
Assembler: muls.w < ea > ,Dn - 16 x 16 → 32        
Attributes: Size = (Long)
Description: Multiplies two signed operands yielding a signed result. The multiplier and multiplicand are both word operands, and the result is a long-word operand. A register operand is the low-order word; the upper word of the register is ignored. All 32 bits of the product are saved in the destination data register.


muls
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


Dn
54
*
*
*
*
*
*
*
*


(An)
58
*
*
*
*
*
*
*
*


(An)+
58
*
*
*
*
*
*
*
*


-(An)
60
*
*
*
*
*
*
*
*


d(An)
62
*
*
*
*
*
*
*
*


d(An,Dn)
64
*
*
*
*
*
*
*
*


xxx.W
62
*
*
*
*
*
*
*
*


xxx.L
66
*
*
*
*
*
*
*
*


d(PC)
62
*
*
*
*
*
*
*
*


d(PC,Dn)
64
*
*
*
*
*
*
*
*


#xxx
58
*
*
*
*
*
*
*
*


muls.l
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


MULU

Operation:      Source * Destination → Destination
Assembler: muls.w < ea > ,Dn - 16 x 16 → 32        
Attributes: Size = (Long)
Description: Multiplies two signed operands yielding a unsigned result. The multiplier and multiplicand are both word operands, and the result is a long-word operand. A register operand is the low-order word; the upper word of the register is ignored. All 32 bits of the product are saved in the destination data register.


mulu
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


Dn
54
*
*
*
*
*
*
*
*


(An)
58
*
*
*
*
*
*
*
*


(An)+
58
*
*
*
*
*
*
*
*


-(An)
60
*
*
*
*
*
*
*
*


d(An)
62
*
*
*
*
*
*
*
*


d(An,Dn)
64
*
*
*
*
*
*
*
*


xxx.W
62
*
*
*
*
*
*
*
*


xxx.L
66
*
*
*
*
*
*
*
*


d(PC)
62
*
*
*
*
*
*
*
*


d(PC,Dn)
64
*
*
*
*
*
*
*
*


#xxx
58
*
*
*
*
*
*
*
*


mulu.l
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


OR

Operation:      Source | Destination → Destination
Assembler: or < ea > ,Dn        or Dn, < ea >        
Attributes: Size = (Byte, Word, Long)
Description: Performs an inclusive-OR operation of the source operand with the destination operand and stores the result in the destination location. The size of the operation can be specified as byte, word, or long. The contents of an address register may not be used as an operand.


or
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


Dn
4
*
12
12
14
16
18
16
20


(An)
8
*
*
*
*
*
*
*
*


(An)+
8
*
*
*
*
*
*
*
*


-(An)
10
*
*
*
*
*
*
*
*


d(An)
12
*
*
*
*
*
*
*
*


d(An,Dn)
14
*
*
*
*
*
*
*
*


xxx.W
12
*
*
*
*
*
*
*
*


xxx.L
16
*
*
*
*
*
*
*
*


d(PC)
12
*
*
*
*
*
*
*
*


d(PC,Dn)
14
*
*
*
*
*
*
*
*


#xxx
10
*
16
16
18
20
22
20
24


or.l
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


Dn
6
*
20
20
22
24
26
24
28


(An)
14
*
*
*
*
*
*
*
*


(An)+
14
*
*
*
*
*
*
*
*


-(An)
16
*
*
*
*
*
*
*
*


d(An)
18
*
*
*
*
*
*
*
*


d(An,Dn)
20
*
*
*
*
*
*
*
*


xxx.W
18
*
*
*
*
*
*
*
*


xxx.L
22
*
*
*
*
*
*
*
*


d(PC)
18
*
*
*
*
*
*
*
*


d(PC,Dn)
20
*
*
*
*
*
*
*
*


#xxx
16
*
28
28
30
32
34
32
36


SUB

Operation:      Source - Destination → Destination
Assembler: sub < ea > ,Dn        sub Dn, < ea >        
Attributes: Size = (Byte, Word, Long)
Description: Subtracts the source operand from the destination operand and stores the result in the destination. The size of the operation is specified as byte, word, or long. The mode of the instruction indicates which operand is the source, which is the destination, and which is the operand size.


sub
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


Dn
4
8
12
12
14
16
18
16
20


An
4
8
*
*
*
*
*
*
*


(An)
8
12
*
*
*
*
*
*
*


(An)+
8
12
*
*
*
*
*
*
*


-(An)
10
14
*
*
*
*
*
*
*


d(An)
12
16
*
*
*
*
*
*
*


d(An,Dn)
14
18
*
*
*
*
*
*
*


xxx.W
12
16
*
*
*
*
*
*
*


xxx.L
16
20
*
*
*
*
*
*
*


d(PC)
12
16
*
*
*
*
*
*
*


d(PC,Dn)
14
18
*
*
*
*
*
*
*


#xxx
4
8
12
12
14
16
18
16
20


sub.l
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


Dn
6
6
20
20
22
24
26
24
28


An
6
6
*
*
*
*
*
*
*


(An)
14
14
*
*
*
*
*
*
*


(An)+
14
14
*
*
*
*
*
*
*


-(An)
16
16
*
*
*
*
*
*
*


d(An)
18
18
*
*
*
*
*
*
*


d(An,Dn)
20
20
*
*
*
*
*
*
*


xxx.W
18
18
*
*
*
*
*
*
*


xxx.L
22
22
*
*
*
*
*
*
*


d(PC)
18
18
*
*
*
*
*
*
*


d(PC,Dn)
20
20
*
*
*
*
*
*
*


#xxx
8
8
20
20
22
24
26
24
28


SUBQ

Operation:      Immidate - Destination → Destination
Assembler: subq # < data > , < ea >        
Attributes: Size = (Byte, Word, Long)
Description: Subtracts the immediate data (1 – 8) from the destination operand. The size of the operation is specified as byte, word, or long. Only word and long operations can be used with address registers, and the condition codes are not affected. When subtracting from address registers, the entire destination address register is used, despite the operation size.


subq
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


#xxx
4
8
12
12
14
16
18
16
20


subq.l
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


#xxx
8
8
20
20
22
24
26
24
28


SUBX

Operation:      Source - Destination + X → Destination
Assembler: subx Dy,Dx        subx -(Ay),-(Ax)        
Attributes: Size = (Byte, Word, Long)
Description: Subtracts the source operand and the extend bit from the destination operand and stores the result in the destination location.
The instruction has two modes:
1. Data register to data register—the data registers specified in the instruction con- tain the operands.
2. Memory to memory—the address registers specified in the instruction access the operands from memory using the predecrement addressing mode.


subx
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


Dn
4
*
*
*
*
*
*
*
*


-(An)
*
*
*
*
18
*
*
*
*


subx.l
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


Dn
8
*
*
*
*
*
*
*
*


-(An)
*
*
*
*
30
*
*
*
*


CLR

Operation:       0 → Destination
Assembler: clr < ea >        
Attributes: Size = (Byte, Word, Long)
Description: Clears the destination operand to zero. The size of the operation may be specified as byte, word, or long.


clr
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


4
*
12
12
14
16
18
16
20


clr.l
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


4
*
20
20
22
24
26
24
28


EXT

Operation:      Destination Sign-Extended → Destination
Assembler: ext.w Dn - extend byte to word        ext.l Dn - extend word to long        
Attributes: Size = (Word, Long)
Description:  Extends a byte in a data register to a word or a long word, or a word in a data register to a long word, by replicating the sign bit to the left. If the operation extends a byte to a word, bit 7 of the designated data register is copied to bits 15 – 8 of that data register. If the operation extends a word to a long word, bit 15 of the designated data register is copied to bits 31 – 16 of the data register.


ext
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


4
*
*
*
*
*
*
*
*


ext.l
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


4
*
*
*
*
*
*
*
*


BSR

Operation:      SP – 4 → SP; PC → (SP); PC + dn → PC
Assembler: bsr < label >        
Attributes: Size = (Byte, Word)
Description: Pushes the long-word address of the instruction immediately following the BSR instruction onto the system stack. The program counter contains the address of the instruction word plus two. Program execution then continues at location (PC) + displacement. The displacement is a twos complement integer that represents the relative distance in bytes from the current program counter to the destination program counter. If the 8-bit displacement field in the instruction word is zero, a 16-bit displacement (the word immediately following the instruction) is used. If the 8-bit displacement field in the instruction word is all ones ($FF), the 32-bit displacement (long word immediately following the instruction) is used.


bsr
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


*
*
*
*
*
*
*
*
*


bsr.l
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


*
*
*
*
*
*
*
*
*


JSR

Operation:      SP – 4 → Sp; PC → (SP); Destination Address → PC
Assembler: jsr < ea >         
Attributes: Size = (Unsized)
Description: Pushes the long-word address of the instruction immediately following the JSR instruction onto the system stack. Program execution then continues at the address specified in the instruction.


jsr
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


*
*
16
*
*
8
8
8
4


jsr.l
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


*
*
16
*
*
8
8
8
4


JMP

Operation:      Destination Address → PC
Assembler: jmp < ea >         
Attributes: Size = (Unsized)
Description: Program execution continues at the effective address specified by the instruction. The addressing mode for the effective address must be a control addressing mode.


jmp
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


*
*
8
*
*
8
8
8
4


jmp.l
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


*
*
8
*
*
8
8
8
4


NEG

Operation:      0 – Destination → Destination
Assembler: neg < ea >        
Attributes: Size = (Byte, Word, Long)
Description: Subtracts the destination operand from zero and stores the result in the destination location. The size of the operation is specified as byte, word, or long.


neg
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


4
*
12
12
14
16
18
16
20


neg.l
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


6
*
20
20
22
24
26
24
28


NOT

Operation:      ~ Destination → Destination
Assembler: not < ea >        
Attributes: Size = (Byte, Word, Long)
Description: Calculates the ones complement of the destination operand and stores the result in the destination location. The size of the operation is specified as byte, word, or long.


not
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


4
*
12
12
14
16
18
16
20


not.l
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


6
*
20
20
22
24
26
24
28


SWAP

Operation:      Register 31 – 16 ←→ Register 15 – 0
Assembler: swap dn        
Attributes: Size = (Word)
Description: Exchange the 16-bit words (halves) of a data register.


swap
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


4
*
*
*
*
*
*
*
*


swap.l
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


*
*
*
*
*
*
*
*
*


NOP

Operation:      None
Assembler: nop        
Attributes: Size = (Undefined)
Description: Performs no operation. The processor state, other than the program counter, is unaffected. Execution continues with the instruction following the NOP instruction. The NOP instruction does not begin execution until all pending bus cycles have completed. This synchronizes the pipeline and prevents instruction overlap.
| nop      |  |
|----------|----|----|------|-------|-------|-------|----------|-------|-------|
|          |4 |
| nop.l    |  |
|----------|----|----|------|-------|-------|-------|----------|-------|-------|
|          |4 |
ILLEGAL

No Description
| illegal  |  |
|----------|----|----|------|-------|-------|-------|----------|-------|-------|
|          |34|
| illegal.l|  |
|----------|----|----|------|-------|-------|-------|----------|-------|-------|
|          |34|
RTE

Operation:      (SP) → PC; SP + 4 → SP
Assembler: rts        
Attributes: Size = (Unsized)
Description: Pulls the program counter value from the stack. The previous program counter value is lost.
| rte      |  |
|----------|----|----|------|-------|-------|-------|----------|-------|-------|
|          |20|
| rte.l    |  |
|----------|----|----|------|-------|-------|-------|----------|-------|-------|
|          |20|
RTS

Operation:      (SP) → PC; SP + 4 → SP
Assembler: rts        
Attributes: Size = (Unsized)
Description: Pulls the program counter value from the stack. The previous program counter value is lost.
| rts      |  |
|----------|----|----|------|-------|-------|-------|----------|-------|-------|
|          |16|
| rts.l    |  |
|----------|----|----|------|-------|-------|-------|----------|-------|-------|
|          |16|
cmp	Dn	An	(An)	(An)+	-(An)	d(An)	d(An,Dn)	xxx.W	xxx.L
Dn	4	6	*	*	*	*	*	*	*
An	4	6	*	*	*	*	*	*	*
(An)	8	10	*	*	*	*	*	*	*
(An)+	8	10	*	12	*	*	*	*	*
-(An)	10	12	*	*	*	*	*	*	*
d(An)	12	14	*	*	*	*	*	*	*
d(An,Dn)	14	16	*	*	*	*	*	*	*
xxx.W	12	14	*	*	*	*	*	*	*
xxx.L	16	18	*	*	*	*	*	*	*
d(PC)	12	14	*	*	*	*	*	*	*
d(PC,Dn)	14	16	*	*	*	*	*	*	*
#xxx	8	10	12	12	14	16	18	16	20