emoon/68000_instruction_timings.md

## 68000_instruction_timings.md

      
    Raw
  

              68000_instruction_timings.md
            
          
    68000 instructions timings

When I started to write some pure 68000 I didn't find a nice doc that would cover all the op codes I used which a nice diagram for the cycle counts so I made one.
This info has been assembled / hacked up using this tool https://github.com/emoon/68k_documentation_gen with a bunch of manual work and some automation for generating the cycle tables.
If you find any errors in this (I'm sure there are plenty but it has been useful for me) please contact me or even better do a PR :)
ABCD

Operation:      Source10 + Destination10 + X → Destination


Assembler Syntax
abcd < ea > ,Dn
Add Dn, < ea >


Attributes: Size = (Byte, Word, Long)
Description: Adds the source operand to the destination operand along with the extend bit, and stores the result in the destination location. The addition is performed using binary- coded decimal arithmetic. The operands, which are packed binary-coded decimal numbers, can be addressed in two different ways

Data Register to Data Register: The operands are contained in the data registers specified in the instruction.
Memory to Memory: The operands are addressed with the predecrement addressing mode using the address registers specified in the instruction.

This operation is a byte operation only.
Condition Codes:


X
N
Z
V
C


*
U
0
U
*


X — Set the same as carry


N — Undefined


Z — Cleared if the result is nonzero; unchanged otherwise


V — Undefined


C — Set if a decimal carry was generated; cleared otherwise.


Instruction Execution Times:


abcd
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


Dn
6
*
*
*
*
*
*
*
*


-(An)
*
*
*
*
18
*
*
*
*


ADD

Operation:      Source + Destination → Destination


Assembler Syntax
Add < ea > ,Dn
Add Dn, < ea >


Attributes: Size = (Byte, Word, Long)
Description: Adds the source operand to the destination operand using binary addition and stores the result in the destination location. The size of the operation may be specified as byte, word, or long. The mode of the instruction indicates which operand is the source and which is the destination, as well as the operand size. Notice that conditon flags are not affected when target is An
Condition Codes:


X
N
Z
V
C


*
*
*
*
*


X — Set the same as carry


N — Set if the result is negative; cleared otherwise.


Z — Set if the result is zero; cleared otherwise.


V — Set if an overflow is generated; cleared otherwise.


C — Set if a carry is generated; cleared otherwise.


Instruction Execution Times:


add
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


Dn
4
8
12
12
14
16
18
16
20


An
4
8
*
*
*
*
*
*
*


(An)
8
12
*
*
*
*
*
*
*


(An)+
8
12
*
*
*
*
*
*
*


-(An)
10
14
*
*
*
*
*
*
*


d(An)
12
16
*
*
*
*
*
*
*


d(An,Dn)
14
18
*
*
*
*
*
*
*


xxx.W
12
16
*
*
*
*
*
*
*


xxx.L
16
20
*
*
*
*
*
*
*


d(PC)
12
16
*
*
*
*
*
*
*


d(PC,Dn)
14
18
*
*
*
*
*
*
*


#xxx
10
14
16
16
18
20
22
20
24


add.l
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


Dn
6
6
20
20
22
24
26
24
28


An
6
6
*
*
*
*
*
*
*


(An)
14
14
*
*
*
*
*
*
*


(An)+
14
14
*
*
*
*
*
*
*


-(An)
16
16
*
*
*
*
*
*
*


d(An)
18
18
*
*
*
*
*
*
*


d(An,Dn)
20
20
*
*
*
*
*
*
*


xxx.W
18
18
*
*
*
*
*
*
*


xxx.L
22
22
*
*
*
*
*
*
*


d(PC)
18
18
*
*
*
*
*
*
*


d(PC,Dn)
20
20
*
*
*
*
*
*
*


#xxx
16
16
28
28
30
32
34
32
36


ADDQ

Operation:      Immidate + Destination → Destination


Assembler Syntax
addq # < data > , < ea >


Attributes: Size = (Byte, Word, Long)
Description: Adds an immediate value of one to eight to the operand at the destination location. The size of the operation may be specified as byte, word, or long. Word and long operations are also allowed on the address registers. When adding to address registers, the condition codes are not altered, and the entire destination address register is used regardless of the operation size.
Condition Codes:


X
N
Z
V
C


*
*
*
*
*


X — Set the same as carry


N — Set if the result is negative; cleared otherwise.


Z — Set if the result is zero; cleared otherwise.


V — Set if an overflow is generated; cleared otherwise.


C — Set if a carry is generated; cleared otherwise.


Instruction Execution Times:


addq
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


#xxx
4
4
12
12
14
16
18
16
20


addq.l
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


#xxx
8
8
20
20
22
24
26
24
28


ADDX

Operation:      Source + Destination + X → Destination


Assembler Syntax
addx Dy,Dx
addx -(Ay),-(Ax)


Attributes: Size = (Byte, Word, Long)
Description: Adds the source operand and the extend bit to the destination operand and stores the result in the destination location. The operands can be addressed in two different ways:

Data register to data register—The data registers specified in the instruction contain the operands.
Memory to memory—The address registers specified in the instruction address the operands using the predecrement addressing mode.

The size of the operation can be specified as byte, word, or long.
Condition Codes:


X
N
Z
V
C


*
*
*
*
*


X — Set the same as carry


N — Set if the result is negative; cleared otherwise.


Z — Cleared if the result is non-zero; unchanged otherwise.


V — Set if an overflow is generated; cleared otherwise.


C — Set if a carry is generated; cleared otherwise.


Instruction Execution Times:


addx
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


Dn
4
*
*
*
*
*
*
*
*


-(An)
*
*
*
*
18
*
*
*
*


addx.l
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


Dn
8
*
*
*
*
*
*
*
*


-(An)
*
*
*
*
30
*
*
*
*


AND

Operation:      Source & Destination → Destination


Assembler Syntax
and < ea > ,Dn
Add Dn, < ea >


Attributes: Size = (Byte, Word, Long)
Description: Performs an AND operation of the source operand with the destination operand and stores the result in the destination location. The size of the operation can be specified as byte, word, or long. The contents of an address register may not be used as an operand.
Condition Codes:


X
N
Z
V
C


-
*
*
0
0


X - Not Affected


N — Set if the most significant bit of the result is set; cleared otherwise.


Z — Set if the result is zero; cleared otherwise.


V — Always cleared.


C — Always cleared.


Instruction Execution Times:


and
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


Dn
4
*
12
12
14
16
18
16
20


(An)
8
*
*
*
*
*
*
*
*


(An)+
8
*
*
*
*
*
*
*
*


-(An)
10
*
*
*
*
*
*
*
*


d(An)
12
*
*
*
*
*
*
*
*


d(An,Dn)
14
*
*
*
*
*
*
*
*


xxx.W
12
*
*
*
*
*
*
*
*


xxx.L
16
*
*
*
*
*
*
*
*


d(PC)
12
*
*
*
*
*
*
*
*


d(PC,Dn)
14
*
*
*
*
*
*
*
*


#xxx
10
*
16
16
18
20
22
20
24


and.l
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


Dn
6
*
20
20
22
24
26
24
28


(An)
14
*
*
*
*
*
*
*
*


(An)+
14
*
*
*
*
*
*
*
*


-(An)
16
*
*
*
*
*
*
*
*


d(An)
18
*
*
*
*
*
*
*
*


d(An,Dn)
20
*
*
*
*
*
*
*
*


xxx.W
18
*
*
*
*
*
*
*
*


xxx.L
22
*
*
*
*
*
*
*
*


d(PC)
18
*
*
*
*
*
*
*
*


d(PC,Dn)
20
*
*
*
*
*
*
*
*


#xxx
16
*
28
28
30
32
34
32
36


ASL

Operation:      Destination Shifted By Count → Destination


Assembler Syntax
ASd Dx,Dy
ASd # < data > ,Dy
ASd < ea >
where d is direction, L or R


Attributes: Size = (Byte, Word, Long)
Description: Arithmetically shifts the bits of the operand in the direction (L or R) specified. The carry bit receives the last bit shifted out of the operand. The shift count for the shifting of a register may be specified in two different ways:

Immediate—The shift count is specified in the instruction (shift range, 1 – 8).
Register—The shift count is the value in the data register specified in instruction modulo 64.

The size of the operation can be specified as byte, word, or long. An operand in mem- ory can be shifted one bit only, and the operand size is restricted to a word. For ASL, the operand is shifted left; the number of positions shifted is the shift count. Bits shifted out of the high-order bit go to both the carry and the extend bits; zeros are shifted into the low-order bit. The overflow bit indicates if any sign changes occur dur- ing the shift.
Condition Codes:


X
N
Z
V
C


*
*
*
*
*


X — Set according to the last bit shifted out of the operand; unaffected for a shift count of zero.


N — Set if the most significant bit of the result is set; cleared otherwise.


Z — Set if the result is zero; cleared otherwise.


V — Set if the most significant bit is changed at any time during the shift operation; cleared otherwise.


C — Set according to the last bit shifted out of the operand; cleared for a shift count of zero.


Instruction Execution Times:


asl
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


#1
8
*
12
12
14
16
18
16
20


#1-8
6+2n
*
*
*
*
*
*
*
*


Dn
6+2n
*
*
*
*
*
*
*
*


asl.l
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


#1-8
8+2n
*
*
*
*
*
*
*
*


Dn
8+2n
*
*
*
*
*
*
*
*


Bcc

Operation:      If Condition True Then PC + dn → PC


Assembler Syntax
bcc < label >


Attributes: Size = (Byte, Word)
Description: If the specified condition is true, program execution continues at location (PC) + displacement.
The program counter contains the address of the instruction word for the Bcc instruction plus two.
The displacement is a twos-complement integer that represents the relative distance in bytes from the current program counter to the destination program counter.
If the 8-bit displacement field in the instruction word is zero, a 16-bit displacement (the word immediately following the instruction) is used.
If the 8-bit displacement field in the instruction word is all ones ($FF), the 32-bit displacement (long word immediately following the instruction) is used.
Condition code cc specifies one of the following conditional tests.


Mnemonic
Condition
Mnemonic
Condition


CC (HI)
Carry Clear
LS
Low or Same


CS (LO)
Carry Set
LT
Less Than


EQ
Equal
MI
Minus


F
False
NE
Not Equal


GE
Greater or Equal
PL
PLus


GT
Greather Than
T
True


HI
High
VC
Overflow Clear


LE
Less or Equal
VS
Overflow Set


Condition Codes:

Not affected.
Instruction Execution Times:


bcc
Displacement
Branch Taken
Branch Not Taken


Byte
10
8


Word
10
12


BCHG

Operation:      TEST ( < number > of Destination) → Z;
TEST ( < number > of Destination) → < bit number > of Destination


Assembler Syntax
bchg dn, < ea >
bchg # < data > , < ea >


Attributes: Size = (Byte, Long)
Description: Tests a bit in the destination operand and sets the Z condition code appropriately, then inverts the specified bit in the destination. When the destination is a data register, any of the 32 bits can be specified by the modulo 32-bit number. When the destination is a memory location, the operation is a byte operation, and the bit number is modulo 8. In all cases, bit zero refers to the least significant bit. The bit number for this operation may be specified in either of two ways:

Immediate—The bit number is specified in a second word of the instruction.
Register—The specified data register contains the bit number.

Condition Codes:


X
N
Z
V
C


-
-
*
-
-


X — Not Affected.


N — Not Affected.


Z — Set if the bit tested is zero; cleared otherwise.


V — Not Affected.


C — Not Affected.


Instruction Execution Times:


bchg
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


Dn
8
*
12
12
14
16
18
16
20


#xxx
12
*
16
16
18
20
22
20
24


bchg.l
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


Dn
8
*
*
*
*
*
*
*
*


#xxx
12
*
*
*
*
*
*
*
*


BCLR

Operation:      TEST ( < bit number > of Destination) → Z; 0 → < bit number > of Destination


Assembler Syntax
bclr dn, < ea >
bclr # < data > , < ea >


Attributes: Size = (Byte, Long)
Description: Tests a bit in the destination operand and sets the Z condition code appropriately, then clears the specified bit in the destination. When a data register is the destination, any of the 32 bits can be specified by a modulo 32-bit number. When a memory location is the destination, the operation is a byte operation, and the bit number is modulo 8. In all cases, bit zero refers to the least significant bit. The bit number for this operation can be specified in either of two ways:

Immediate—The bit number is specified in a second word of the instruction.
Register—The specified data register contains the bit number.

Condition Codes:


X
N
Z
V
C


-
-
*
-
-


X — Not Affected.


N — Not Affected.


Z — Set if the bit tested is zero; cleared otherwise.


V — Not Affected.


C — Not Affected.


Instruction Execution Times:


bclr
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


Dn
10
*
12
12
14
16
18
16
20


#xxx
14
*
16
16
18
20
22
20
24


bclr.l
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


Dn
10
*
*
*
*
*
*
*
*


#xxx
14
*
*
*
*
*
*
*
*


BSET

Operation:      TEST ( < bit number > of Destination) → Z; 1 → < bit number > of Destination


Assembler Syntax
btest dn, < ea >
btest # < data > , < ea >


Attributes: Size = (Byte, Long)
Description: Description: Tests a bit in the destination operand and sets the Z condition code appropriately, then sets the specified bit in the destination operand. When a data register is the destination, any of the 32 bits can be specified by a modulo 32-bit number. When a memory location is the destination, the operation is a byte operation, and the bit number is modulo 8. In all cases, bit zero refers to the least significant bit. The bit number for this operation can be specified in either of two ways:

Immediate—The bit number is specified in the second word of the instruction.
Register—The specified data register contains the bit number.

Condition Codes:


X
N
Z
V
C


-
-
*
-
-


X — Not Affected.


N — Not Affected.


Z — Set if the bit tested is zero; cleared otherwise.


V — Not Affected.


C — Not Affected.


Instruction Execution Times:


bset
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


Dn
8
*
12
12
14
16
18
16
20


#xxx
12
*
16
16
18
20
22
20
24


bset.l
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


Dn
8
*
*
*
*
*
*
*
*


#xxx
12
*
*
*
*
*
*
*
*


BSR

Operation:      SP – 4 → SP; PC → (SP); PC + dn → PC


Assembler Syntax
bsr < label >


Attributes: Size = (Byte, Word)
Description: Pushes the long-word address of the instruction immediately following the BSR instruction onto the system stack. The program counter contains the address of the instruction word plus two. Program execution then continues at location (PC) + displacement. The displacement is a twos complement integer that represents the relative distance in bytes from the current program counter to the destination program counter. If the 8-bit displacement field in the instruction word is zero, a 16-bit displacement (the word immediately following the instruction) is used. If the 8-bit displacement field in the instruction word is all ones ($FF), the 32-bit displacement (long word immediately following the instruction) is used.
Condition Codes:

Not affected.
Instruction Execution Times:


bsr
Displacement
Branch Taken
Branch Not Taken


Byte
18
-


Word
18
-


BTST

Operation:      TEST ( < bit number > of Destination) → Z


Assembler Syntax
btest dn, < ea >
btest # < data > , < ea >


Attributes: Size = (Byte, Long)
Description: Tests a bit in the destination operand and sets the Z condition code appropriately. When a data register is the destination, any of the 32 bits can be specified by a modulo 32- bit number. When a memory location is the destination, the operation is a byte operation, and the bit number is modulo 8. In all cases, bit zero refers to the least significant bit. The bit number for this operation can be specified in either of two ways:

Immediate—The bit number is specified in a second word of the instruction.
Register—The specified data register contains the bit number.

Condition Codes:


X
N
Z
V
C


-
-
*
-
-


X — Not Affected.


N — Not Affected.


Z — Set if the bit tested is zero; cleared otherwise.


V — Not Affected.


C — Not Affected.


Instruction Execution Times:


btst
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


Dn
6
*
8
8
10
12
14
12
16


#xxx
10
*
12
12
14
16
18
16
20


btst.l
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


Dn
6
*
*
*
*
*
*
*
*


#xxx
10
*
*
*
*
*
*
*
*


CLR

Operation:       0 → Destination


Assembler Syntax
clr < ea >


Attributes: Size = (Byte, Word, Long)
Description: Clears the destination operand to zero. The size of the operation may be specified as byte, word, or long.
Condition Codes:


X
N
Z
V
C


-
0
*
0
0


X — Not Affected.


N — Always cleared.


Z — Always set.


V — Always cleared.


C — Always cleared.


Instruction Execution Times:


clr
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


4
*
12
12
14
16
18
16
20


clr.l
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


6
*
20
20
22
24
26
24
28


CMP

Operation:      Destination – Source → cc


Assembler Syntax
cmp < ea > , Dn


Attributes: Size = (Byte, Word, Long)
Description: Subtracts the source operand from the destination data register and sets the condition codes according to the result; the data register is not changed. The size of the operation can be byte, word, or long.
Condition Codes:


X
N
Z
V
C


-
*
*
*
*


X — Not Affected.


N — Set if the result is negative; cleared otherwise.


Z — Set if the result is zero; cleared otherwise.


V — Set if an overflow occurs; cleared otherwise.


C — Set if a borrow occurs; cleared otherwise.


Instruction Execution Times:


cmp
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


Dn
4
6
*
*
*
*
*
*
*


An
4
6
*
*
*
*
*
*
*


(An)
8
10
*
*
*
*
*
*
*


(An)+
8
10
*
12
*
*
*
*
*


-(An)
10
12
*
*
*
*
*
*
*


d(An)
12
14
*
*
*
*
*
*
*


d(An,Dn)
14
16
*
*
*
*
*
*
*


xxx.W
12
14
*
*
*
*
*
*
*


xxx.L
16
18
*
*
*
*
*
*
*


d(PC)
12
14
*
*
*
*
*
*
*


d(PC,Dn)
14
16
*
*
*
*
*
*
*


#xxx
8
10
12
12
14
16
18
16
20


cmp.l
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


Dn
6
6
*
*
*
*
*
*
*


An
6
6
*
*
*
*
*
*
*


(An)
14
14
*
*
*
*
*
*
*


(An)+
14
14
*
20
*
*
*
*
*


-(An)
16
16
*
*
*
*
*
*
*


d(An)
18
18
*
*
*
*
*
*
*


d(An,Dn)
20
20
*
*
*
*
*
*
*


xxx.W
18
18
*
*
*
*
*
*
*


xxx.L
22
22
*
*
*
*
*
*
*


d(PC)
18
18
*
*
*
*
*
*
*


d(PC,Dn)
20
20
*
*
*
*
*
*
*


#xxx
14
14
20
20
22
24
26
24
28


DBcc

Operation:       If Condition False
Then (Dn – 1 → Dn; If Dn not equal – 1 Then PC + dn → PC)


Assembler Syntax
dbcc dn, < label >


Attributes: Size = (Word)
Description: Description: Controls a loop of instructions. The parameters are a condition code, a data register (counter), and a displacement value. The instruction first tests the condition for termination; if it is true, no operation is performed. If the termination condition is not true, the low-order 16 bits of the counter data register decrement by one. If the result is – 1, execution continues with the next instruction. If the result is not equal to – 1, execution continues at the location indicated by the current value of the program counter plus the sign-extended 16-bit displacement. The value in the program counter is the address of the instruction word of the DBcc instruction plus two. The displacement is a twos complement integer that represents the relative distance in bytes from the current program counter to the destination program counter. Most assemblers accept DBRA for DBF for use when only a count terminates the loop (no condition is tested).  Condition code cc specifies one of the following conditional tests:


Mnemonic
Condition
Mnemonic
Condition


CC (HI)
Carry Clear
LS
Low or Same


CS (LO)
Carry Set
LT
Less Than


EQ
Equal
MI
Minus


F
False
NE
Not Equal


GE
Greater or Equal
PL
PLus


GT
Greather Than
T
True


HI
High
VC
Overflow Clear


LE
Less or Equal
VS
Overflow Set


Condition Codes:

Not affected.
Instruction Execution Times:


dbcc
Displacement
Branch Taken
Branch Not Taken


cc true
-
12


cc false, Count not Expired
10
-


cc false, Counter Expired
-
14


DIVU

Operation:      Destination / Source → Destination


Assembler Syntax
DIVS.W < ea > ,Dn32/16 → 16r – 16q


Attributes: Size = (Word)
Description: Divides the signed destination operand by the signed source operand and stores the signed result in the destination. The result is a quotient in the lower word (least significant 16 bits) and a remainder in the upper word (most significant 16 bits). The sign of the remainder is the same as the sign of the dividend. Two special conditions may arise during the operation:

Division by zero causes a trap.
Overflow may be detected and set before the instruction completes. If the instruction detects an overflow, it sets the overflow condition code, and the operands are unaffected.

Condition Codes:


X
N
Z
V
C


-
*
*
*
*


X — Not Affected.


N — Set if the quotient is negative; cleared otherwise; undefined if overflow or divide by zero occurs.


Z — Set if the quotient is zero; cleared otherwise; undefined if overflow or divide by zero occurs.


V — Set if division overflow occurs; undefined if divide by zero occurs; cleared otherwise.


C — Always cleared.


Instruction Execution Times:


divu
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


Dn
140
*
*
*
*
*
*
*
*


(An)
144
*
*
*
*
*
*
*
*


(An)+
144
*
*
*
*
*
*
*
*


-(An)
146
*
*
*
*
*
*
*
*


d(An)
148
*
*
*
*
*
*
*
*


d(An,Dn)
150
*
*
*
*
*
*
*
*


xxx.W
148
*
*
*
*
*
*
*
*


xxx.L
152
*
*
*
*
*
*
*
*


d(PC)
148
*
*
*
*
*
*
*
*


d(PC,Dn)
150
*
*
*
*
*
*
*
*


#xxx
144
*
*
*
*
*
*
*
*


DIVS

Operation:      Destination / Source → Destination


Assembler Syntax
DIVS.W < ea > ,Dn32/16 → 16r – 16q


Attributes: Size = (Word)
Description: Divides the signed destination operand by the signed source operand and stores the signed result in the destination. The result is a quotient in the lower word (least significant 16 bits) and a remainder in the upper word (most significant 16 bits). The sign of the remainder is the same as the sign of the dividend. Two special conditions may arise during the operation:

Division by zero causes a trap.
Overflow may be detected and set before the instruction completes. If the instruction detects an overflow, it sets the overflow condition code, and the operands are unaffected.

Condition Codes:


X
N
Z
V
C


-
*
*
*
*


X — Not Affected.


N — Set if the quotient is negative; cleared otherwise; undefined if overflow or divide by zero occurs.


Z — Set if the quotient is zero; cleared otherwise; undefined if overflow or divide by zero occurs.


V — Set if division overflow occurs; undefined if divide by zero occurs; cleared otherwise.


C — Always cleared.


Instruction Execution Times:


divs
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


Dn
158
*
*
*
*
*
*
*
*


(An)
162
*
*
*
*
*
*
*
*


(An)+
162
*
*
*
*
*
*
*
*


-(An)
164
*
*
*
*
*
*
*
*


d(An)
166
*
*
*
*
*
*
*
*


d(An,Dn)
168
*
*
*
*
*
*
*
*


xxx.W
166
*
*
*
*
*
*
*
*


xxx.L
170
*
*
*
*
*
*
*
*


d(PC)
166
*
*
*
*
*
*
*
*


d(PC,Dn)
168
*
*
*
*
*
*
*
*


#xxx
162
*
*
*
*
*
*
*
*


EOR

Operation:      Destination EOR Source → Destination


Assembler Syntax
eor Dn, < ea >


Attributes: Size = (Byte, Word, Long)
Description: Performs an exclusive-OR operation on the destination operand using the source operand and stores the result in the destination location. The size of the operation may be specified to be byte, word, or long. The source operand must be a data register. The destination operand is specified in the effective address field.
Condition Codes:


X
N
Z
V
C


-
*
*
0
0


X - Not Affected


N — Set if the most significant bit of the result is set; cleared otherwise.


Z — Set if the result is zero; cleared otherwise.


V — Always cleared.


C — Always cleared.


Instruction Execution Times:


eor
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


Dn
4
*
12
12
14
16
18
16
20


#xxx
8
*
16
16
18
20
22
20
24


eor.l
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


Dn
8
*
20
20
22
24
26
24
28


#xxx
16
*
28
28
30
32
34
32
36


EXG

Operation:      Rx ←→ Ry


Assembler Syntax
exg Dx,Dy
exg Ax,Ay
exg Dx,Ay


Attributes: Size = (Long)
Description: Exchanges the contents of two 32-bit registers. The instruction performs three types of exchanges.

Exchange data registers.
Exchange address registers.
Exchange a data register and an address register.

Condition Codes:

Not affected.
Instruction Execution Times:


exg
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


Dn
6
6
*
*
*
*
*
*
*


An
6
6
*
*
*
*
*
*
*


exg.l
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


Dn
6
6
*
*
*
*
*
*
*


An
6
6
*
*
*
*
*
*
*


EXT

Operation:      Destination Sign-Extended → Destination


Assembler Syntax
ext.w Dn - extend byte to word
ext.l Dn - extend word to long


Attributes: Size = (Word, Long)
Description:  Extends a byte in a data register to a word or a long word, or a word in a data register to a long word, by replicating the sign bit to the left. If the operation extends a byte to a word, bit 7 of the designated data register is copied to bits 15 – 8 of that data register. If the operation extends a word to a long word, bit 15 of the designated data register is copied to bits 31 – 16 of the data register.
Condition Codes:


X
N
Z
V
C


-
*
*
0
0


X - Not Affected


N — Set if the result is negative; cleared otherwise.


Z — Set if the result is zero; cleared otherwise.


V — Always cleared.


C — Always cleared.


Instruction Execution Times:


ext
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


4
*
*
*
*
*
*
*
*


ext.l
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


4
*
*
*
*
*
*
*
*


ILLEGAL

Operation:      SSP – 4 → SSP; PC → (SSP);  SSP – 2 → SSP; SR → (SSP);


Assembler Syntax
illegal


Attributes: Size = (Unsized)
Description: Forces an illegal instruction exception, vector number 4. All other illegal instruction bit patterns are reserved for future extension of the instruction set and should not be used to force an exception.
Condition Codes:

Not affected.
Instruction Execution Times:


illegal
34


illegal.l
34


JMP

Operation:      Destination Address → PC


Assembler Syntax
jmp < ea >


Attributes: Size = (Unsized)
Description: Program execution continues at the effective address specified by the instruction. The addressing mode for the effective address must be a control addressing mode.
Condition Codes:

Not affected.
Instruction Execution Times:


jmp
(An)
(d16,An)
(d8,An,Xn)
(xxx).W
(xxx).L
(d16,PC)
(d8,PC,Xn)


8
10
14
10
12
10
14


JSR

Operation:      SP – 4 → Sp; PC → (SP); Destination Address → PC


Assembler Syntax
jsr < ea >


Attributes: Size = (Unsized)
Description: Pushes the long-word address of the instruction immediately following the JSR instruction onto the system stack. Program execution then continues at the address specified in the instruction.
Condition Codes:

Not affected.
Instruction Execution Times:


jsr
(An)
(d16,An)
(d8,An,Xn)
(xxx).W
(xxx).L
(d16,PC)
(d8,PC,Xn)


16
18
22
18
20
18
22


LEA

Operation:      < ea > → An


Assembler Syntax
lea < ea >, An


Attributes: Size = (Long)
Description: Loads the effective address into the specified address register. All 32 bits of the address register are affected by this instruction.
Condition Codes:

Not affected.
Instruction Execution Times:


lea
(An)
(d16,An)
(d8,An,Xn)
(xxx).W
(xxx).L
(d16,PC)
(d8,PC,Xn)


4
8
12
8
12
8
12


LSL

Operation:      Destination Shifted By Count → Destination


Assembler Syntax
LSd Dx,Dy
LSd # < data > ,Dy
LSd < ea >
where d is direction, L or R


Attributes: Size = (Byte, Word, Long)
Description: Shifts the bits of the operand in the direction specified (L or R). The carry bit receives the last bit shifted out of the operand. The shift count for the shifting of a register is specified in two different ways:

Immediate—The shift count (1 – 8) is specified in the instruction.
Register—The shift count is the value in the data register specified in the in- struction modulo 64.
The size of the operation for register destinations may be specified as byte, word, or long. The contents of memory, < ea > , can be shifted one bit only, and the operand size is restricted to a word.
The LSL instruction shifts the operand to the left the number of positions specified as the shift count. Bits shifted out of the high-order bit go to both the carry and the extend bits; zeros are shifted into the low-order bit.

Condition Codes:


X
N
Z
V
C


*
*
*
*
*


X — Set according to the last bit shifted out of the operand; unaffected for a shift count of zero.


N — Set if the most significant bit of the result is set; cleared otherwise.


Z — Set if the result is zero; cleared otherwise.


V — Set if the most significant bit is changed at any time during the shift operation; cleared otherwise.


C — Set according to the last bit shifted out of the operand; cleared for a shift count of zero.


Instruction Execution Times:


lsl
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


#1
8
*
12
12
14
16
18
16
20


#1-8
6+2n
*
*
*
*
*
*
*
*


Dn
6+2n
*
*
*
*
*
*
*
*


lsl.l
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


#1-8
8+2n
*
*
*
*
*
*
*
*


Dn
8+2n
*
*
*
*
*
*
*
*


LSR

Operation:      Destination Shifted By Count → Destination


Assembler Syntax
LSd Dx,Dy
LSd # < data > ,Dy
LSd < ea >
where d is direction, L or R


Attributes: Size = (Byte, Word, Long)
Description: Shifts the bits of the operand in the direction specified (L or R). The carry bit receives the last bit shifted out of the operand. The shift count for the shifting of a register is specified in two different ways:

Immediate—The shift count (1 – 8) is specified in the instruction.
Register—The shift count is the value in the data register specified in the in- struction modulo 64.
The size of the operation for register destinations may be specified as byte, word, or long. The contents of memory, < ea > , can be shifted one bit only, and the operand size is restricted to a word.
The LSL instruction shifts the operand to the left the number of positions specified as the shift count. Bits shifted out of the high-order bit go to both the carry and the extend bits; zeros are shifted into the low-order bit.

Condition Codes:


X
N
Z
V
C


*
*
*
*
*


X — Set according to the last bit shifted out of the operand; unaffected for a shift count of zero.


N — Set if the most significant bit of the result is set; cleared otherwise.


Z — Set if the result is zero; cleared otherwise.


V — Set if the most significant bit is changed at any time during the shift operation; cleared otherwise.


C — Set according to the last bit shifted out of the operand; cleared for a shift count of zero.


Instruction Execution Times:


lsr
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


#1
8
*
12
12
14
16
18
16
20


#1-8
6+2n
*
*
*
*
*
*
*
*


Dn
6+2n
*
*
*
*
*
*
*
*


lsr.l
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


#1-8
8+2n
*
*
*
*
*
*
*
*


Dn
8+2n
*
*
*
*
*
*
*
*


MOVE

Operation:      Source → Destination


Assembler Syntax
move < ea >, < ea >


Attributes: Size = (Byte, Word, Long)
Description: Moves the data at the source to the destination location and sets the condition codes according to the data. The size of the operation may be specified as byte, word, or long.
Condition Codes:


X
N
Z
V
C


-
*
*
0
0


X - Not Affected


N — Set if the result is negative; cleared otherwise.


Z — Set if the result is zero; cleared otherwise.


V — Always cleared.


C — Always cleared.


Instruction Execution Times:


move
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


Dn
4
4
8
8
8
12
14
12
16


An
4
4
8
8
8
12
14
12
16


(An)
8
8
12
12
12
16
18
16
20


(An)+
8
8
12
12
12
16
18
16
20


-(An)
10
10
14
14
14
18
20
18
22


d(An)
12
12
16
16
16
20
22
20
24


d(An,Dn)
14
14
18
18
18
22
24
22
26


xxx.W
12
12
16
16
16
20
22
20
24


xxx.L
16
16
20
20
20
24
26
24
28


d(PC)
12
12
16
16
16
20
22
20
24


d(PC,Dn)
14
14
18
18
18
22
24
22
26


#xxx
8
8
12
12
12
16
18
16
20


move.l
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


Dn
4
4
12
12
12
16
18
16
20


An
4
4
12
12
12
16
18
16
20


(An)
12
12
20
20
20
24
26
24
28


(An)+
12
12
20
20
20
24
26
24
28


-(An)
14
14
22
22
22
26
28
26
30


d(An)
16
16
24
24
24
28
30
28
32


d(An,Dn)
18
18
26
26
26
30
32
30
34


xxx.W
16
16
24
24
24
28
30
28
32


xxx.L
20
20
28
28
28
32
34
32
36


d(PC)
16
16
24
24
24
28
30
28
32


d(PC,Dn)
18
18
26
26
26
30
32
30
34


#xxx
12
12
20
20
20
24
26
24
28


MOVEM

Operation:      Registers → Destination; Source → Registers


Assembler Syntax
movem < list >, < ea >
movem < list >, < ea >


Attributes: Size = (Byte, Word, Long)
Description: Moves the contents of selected registers to or from consecutive memory locations starting at the location specified by the effective address. A register is selected if the bit in the mask field corresponding to that register is set. The instruction size determines whether 16 or 32 bits of each register are transferred. In the case of a word transfer to either address or data registers, each word is sign-extended to 32 bits, and the resulting long word is loaded into the associated register.
Selecting the addressing mode also selects the mode of operation of the MOVEM instruction, and only the control modes, the predecrement mode, and the postincre- ment mode are valid. If the effective address is specified by one of the control modes, the registers are transferred starting at the specified address, and the address is incre- mented by the operand length (2 or 4) following each transfer. The order of the regis- ters is from D0 to D7, then from A0 to A7.
If the effective address is specified by the predecrement mode, only a register-to-mem- ory operation is allowed. The registers are stored starting at the specified address minus the operand length (2 or 4), and the address is decremented by the operand length following each transfer. The order of storing is from A7 to A0, then from D7 to D0. When the instruction has completed, the decremented address register contains the address of the last operand stored. For the MC68020, MC68030, MC68040, and CPU32, if the addressing register is also moved to memory, the value written is the ini- tial register value decremented by the size of the operation. The MC68000 and MC68010 write the initial register value (not decremented).
If the effective address is specified by the postincrement mode, only a memory-to-reg- ister operation is allowed. The registers are loaded starting at the specified address; the address is incremented by the operand length (2 or 4) following each transfer. The order of loading is the same as that of control mode addressing. When the instruction has completed, the incremented address register contains the address of the last oper- and loaded plus the operand length. If the addressing register is also loaded from memory, the memory value is ignored and the register is written with the postincre- mented effective address.
Condition Codes:

Not affected.
Instruction Execution Times:


movem
Size
(An)
(An)+
-(An)
(d16,An)
(d8,An,Xn)
(xxx).W
(xxx).L
(d16,PC)
(d8,PC,Xn)


M -> R
Word
12+4n
12+4n
-
16+4n
18+4n
16+4n
20+4n
16+4n
18+4n


M -> R
Long
12+8n
12+8n
-
16+8n
18+8n
16+8n
20+8n
16+8n
18+8n


R -> M
Word
8+4n
-
8+4n
12+4n
14+4n
12+4n
16+4n
-
-


R -> M
Long
8+8n
-
8+8n
12+8n
14+8n
12+8n
16+8n
-
-


MOVEP

Operation:      Source → Destination


Assembler Syntax
movep Dx,(d16,Ay)
movep (d16,Ay),Dx


Attributes: Size = (Word, Long)
Description: Moves data between a data register and alternate bytes within the address space starting at the location specified and incrementing by two. The high-order byte of the data register is transferred first, and the low-order byte is transferred last. The memory address is specified in the address register indirect plus 16-bit displacement addressing mode.
Condition Codes:

Not affected.
Instruction Execution Times:


movep
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


Dn
*
*
16
*
*
16
*
*
*


(An)
16
*
*
*
*
*
*
*
*


d(An)
16
*
*
*
*
*
*
*
*


movep.l
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


Dn
*
*
24
*
*
24
*
*
*


(An)
24
*
*
*
*
*
*
*
*


d(An)
24
*
*
*
*
*
*
*
*


MOVEQ

Operation:      Immediate Data → Destination


Assembler Syntax
moveq # < data >, Dn


Attributes: Size = (Long)
Description: Moves a byte of immediate data to a 32-bit data register. The data in an 8-bit field within the operation word is sign- extended to a long operand in the data register as it is transferred.
Condition Codes:


X
N
Z
V
C


-
*
*
0
0


X - Not Affected


N — Set if the result is negative; cleared otherwise.


Z — Set if the result is zero; cleared otherwise.


V — Always cleared.


C — Always cleared.


Instruction Execution Times:


moveq
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


#xxx
4
*
*
*
*
*
*
*
*


moveq.l
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


#xxx
4
*
*
*
*
*
*
*
*


MULS

Operation:      Source * Destination → Destination


Assembler Syntax
muls.w < ea > ,Dn - 16 x 16 → 32


Attributes: Size = (Long)
Description: Multiplies two signed operands yielding a signed result. The multiplier and multiplicand are both word operands, and the result is a long-word operand. A register operand is the low-order word; the upper word of the register is ignored. All 32 bits of the product are saved in the destination data register.
Condition Codes:


X
N
Z
V
C


-
*
*
*
0


X - Not Affected


N — Set if the result is negative; cleared otherwise.


Z — Set if the result is zero; cleared otherwise.


V — Set if overflow; cleared otherwise.


C — Always cleared.


Instruction Execution Times:


muls
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


Dn
54
*
*
*
*
*
*
*
*


(An)
58
*
*
*
*
*
*
*
*


(An)+
58
*
*
*
*
*
*
*
*


-(An)
60
*
*
*
*
*
*
*
*


d(An)
62
*
*
*
*
*
*
*
*


d(An,Dn)
64
*
*
*
*
*
*
*
*


xxx.W
62
*
*
*
*
*
*
*
*


xxx.L
66
*
*
*
*
*
*
*
*


d(PC)
62
*
*
*
*
*
*
*
*


d(PC,Dn)
64
*
*
*
*
*
*
*
*


#xxx
58
*
*
*
*
*
*
*
*


MULU

Operation:      Source * Destination → Destination


Assembler Syntax
muls.w < ea > ,Dn - 16 x 16 → 32


Attributes: Size = (Long)
Description: Multiplies two signed operands yielding a unsigned result. The multiplier and multiplicand are both word operands, and the result is a long-word operand. A register operand is the low-order word; the upper word of the register is ignored. All 32 bits of the product are saved in the destination data register.
Condition Codes:


X
N
Z
V
C


-
*
*
*
0


X - Not Affected


N — Set if the result is negative; cleared otherwise.


Z — Set if the result is zero; cleared otherwise.


V — Set if overflow; cleared otherwise.


C — Always cleared.


Instruction Execution Times:


mulu
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


Dn
54
*
*
*
*
*
*
*
*


(An)
58
*
*
*
*
*
*
*
*


(An)+
58
*
*
*
*
*
*
*
*


-(An)
60
*
*
*
*
*
*
*
*


d(An)
62
*
*
*
*
*
*
*
*


d(An,Dn)
64
*
*
*
*
*
*
*
*


xxx.W
62
*
*
*
*
*
*
*
*


xxx.L
66
*
*
*
*
*
*
*
*


d(PC)
62
*
*
*
*
*
*
*
*


d(PC,Dn)
64
*
*
*
*
*
*
*
*


#xxx
58
*
*
*
*
*
*
*
*


NEG

Operation:      0 – Destination → Destination


Assembler Syntax
neg < ea >


Attributes: Size = (Byte, Word, Long)
Description: Subtracts the destination operand from zero and stores the result in the destination location. The size of the operation is specified as byte, word, or long.
Condition Codes:


X
N
Z
V
C


*
*
*
*
*


X — Set the same as the carry bit.


N — Set if the result is negative; cleared otherwise.


Z — Set if the result is zero; cleared otherwise.


V — Set if an overflow occurs; cleared otherwise.


C — Cleared if the result is zero; set otherwise.


Instruction Execution Times:


neg
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


4
*
12
12
14
16
18
16
20


neg.l
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


6
*
20
20
22
24
26
24
28


NEGX

Operation:      0 – Destination – X → Destination


Assembler Syntax
negx < ea >


Attributes: Size = (Byte, Word, Long)
Description: Subtracts the destination operand and the extend bit from zero. Stores the result in the destination location. The size of the operation is specified as byte, word, or long.
Condition Codes:


X
N
Z
V
C


*
*
0
*
*


X — Set the same as the carry bit.


N — Set if the result is negative; cleared otherwise.


Z — Cleared if the result is nonzero; unchanged otherwise.


V — Set if an overflow occurs; cleared otherwise.


C — Set if a borrow occurs; cleared otherwise.


Instruction Execution Times:


negx
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


4
*
12
12
14
16
18
16
20


negx.l
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


6
*
20
20
22
24
26
24
28


NOP

Operation:      None


Assembler Syntax
nop


Attributes: Size = (Undefined)
Description: Performs no operation. The processor state, other than the program counter, is unaffected. Execution continues with the instruction following the NOP instruction. The NOP instruction does not begin execution until all pending bus cycles have completed. This synchronizes the pipeline and prevents instruction overlap.
Condition Codes:

Not affected.
Instruction Execution Times:


nop
4


nop.l
4


NOT

Operation:      ~ Destination → Destination


Assembler Syntax
not < ea >


Attributes: Size = (Byte, Word, Long)
Description: Calculates the ones complement of the destination operand and stores the result in the destination location. The size of the operation is specified as byte, word, or long.
Condition Codes:


X
N
Z
V
C


-
*
*
0
0


X - Not Affected


N — Set if the result is negative; cleared otherwise.


Z — Set if the result is zero; cleared otherwise.


V — Always cleared.


C — Always cleared.


Instruction Execution Times:


not
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


4
*
12
12
14
16
18
16
20


not.l
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


6
*
20
20
22
24
26
24
28


OR

Operation:      Source | Destination → Destination


Assembler Syntax
or < ea > ,Dn
or Dn, < ea >


Attributes: Size = (Byte, Word, Long)
Description: Performs an inclusive-OR operation of the source operand with the destination operand and stores the result in the destination location. The size of the operation can be specified as byte, word, or long. The contents of an address register may not be used as an operand.
Condition Codes:


X
N
Z
V
C


-
*
*
0
0


X - Not Affected


N — Set if the most significant bit of the result is set; cleared otherwise.


Z — Set if the result is zero; cleared otherwise.


V — Always cleared.


C — Always cleared.


Instruction Execution Times:


or
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


Dn
4
*
12
12
14
16
18
16
20


(An)
8
*
*
*
*
*
*
*
*


(An)+
8
*
*
*
*
*
*
*
*


-(An)
10
*
*
*
*
*
*
*
*


d(An)
12
*
*
*
*
*
*
*
*


d(An,Dn)
14
*
*
*
*
*
*
*
*


xxx.W
12
*
*
*
*
*
*
*
*


xxx.L
16
*
*
*
*
*
*
*
*


d(PC)
12
*
*
*
*
*
*
*
*


d(PC,Dn)
14
*
*
*
*
*
*
*
*


#xxx
10
*
16
16
18
20
22
20
24


or.l
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


Dn
6
*
20
20
22
24
26
24
28


(An)
14
*
*
*
*
*
*
*
*


(An)+
14
*
*
*
*
*
*
*
*


-(An)
16
*
*
*
*
*
*
*
*


d(An)
18
*
*
*
*
*
*
*
*


d(An,Dn)
20
*
*
*
*
*
*
*
*


xxx.W
18
*
*
*
*
*
*
*
*


xxx.L
22
*
*
*
*
*
*
*
*


d(PC)
18
*
*
*
*
*
*
*
*


d(PC,Dn)
20
*
*
*
*
*
*
*
*


#xxx
16
*
28
28
30
32
34
32
36


ROL

Operation:      Destination Rotated By Count → Destination


Assembler Syntax
ROd Dx,Dy
ROd # < data > ,Dy
ROd < ea >
where d is direction, L or R


Attributes: Size = (Byte, Word, Long)
Description: Rotates the bits of the operand in the direction specified (L or R). The extend bit is not included in the rotation. The rotate count for the rotation of a register is specified in either of two ways:

Immediate—The rotate count (1 – 8) is specified in the instruction.
Register—The rotate count is the value in the data register specified in the in- struction, modulo 64.

The size of the operation for register destinations is specified as byte, word, or long. The contents of memory, (ROd < ea > ), can be rotated one bit only, and operand size is restricted to a word.
The ROL instruction rotates the bits of the operand to the left; the rotate count deter- mines the number of bit positions rotated. Bits rotated out of the high-order bit go to the carry bit and also back into the low-order bit.
Condition Codes:


X
N
Z
V
C


*
*
*
0
*


X — Not affected.


N — Set if the most significant bit of the result is set; cleared otherwise.


Z — Set if the result is zero; cleared otherwise.


V - Always cleared.


C — Set according to the last bit rotated out of the operand; cleared when the rotate count is zero.


Instruction Execution Times:


rol
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


#1
8
*
12
12
14
16
18
16
20


#1-8
6+2n
*
*
*
*
*
*
*
*


Dn
6+2n
*
*
*
*
*
*
*
*


rol.l
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


#1-8
8+2n
*
*
*
*
*
*
*
*


Dn
8+2n
*
*
*
*
*
*
*
*


ROR

Operation:      Destination Rotated By Count → Destination


Assembler Syntax
ROd Dx,Dy
ROd # < data > ,Dy
ROd < ea >
where d is direction, L or R


Attributes: Size = (Byte, Word, Long)
Description: Rotates the bits of the operand in the direction specified (L or R). The extend bit is not included in the rotation. The rotate count for the rotation of a register is specified in either of two ways:

Immediate—The rotate count (1 – 8) is specified in the instruction.
Register—The rotate count is the value in the data register specified in the in- struction, modulo 64.

The size of the operation for register destinations is specified as byte, word, or long. The contents of memory, (ROd < ea > ), can be rotated one bit only, and operand size is restricted to a word.
The ROL instruction rotates the bits of the operand to the left; the rotate count deter- mines the number of bit positions rotated. Bits rotated out of the high-order bit go to the carry bit and also back into the low-order bit.
Condition Codes:


X
N
Z
V
C


*
*
*
0
*


X — Not affected.


N — Set if the most significant bit of the result is set; cleared otherwise.


Z — Set if the result is zero; cleared otherwise.


V - Always cleared.


C — Set according to the last bit rotated out of the operand; cleared when the rotate count is zero.


Instruction Execution Times:


ror
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


#1
8
*
12
12
14
16
18
16
20


#1-8
6+2n
*
*
*
*
*
*
*
*


Dn
6+2n
*
*
*
*
*
*
*
*


ror.l
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


#1-8
8+2n
*
*
*
*
*
*
*
*


Dn
8+2n
*
*
*
*
*
*
*
*


ROXL

Operation:      Destination Rotated With X By Count → Destination


Assembler Syntax
ROXd Dx,Dy
ROXd # < data > ,Dy
ROXd < ea >
where d is direction, L or R


Attributes: Size = (Byte, Word, Long)
Description: Rotates the bits of the operand in the direction specified (L or R). The extend bit is included in the rotation. The rotate count for the rotation of a register is specified in either of two ways:

Immediate—The rotate count (1 – 8) is specified in the instruction.
Register—The rotate count is the value in the data register specified in the in- struction, modulo 64.

The size of the operation for register destinations is specified as byte, word, or long. The contents of memory, < ea > , can be rotated one bit only, and operand size is restricted to a word. The ROXL instruction rotates the bits of the operand to the left; the rotate count determines the number of bit positions rotated. Bits rotated out of the high- order bit go to the carry bit and the extend bit; the previous value of the extend bit rotates into the low-order bit.
Condition Codes:


X
N
Z
V
C


*
*
*
0
*


X — Not affected.


N — Set if the most significant bit of the result is set; cleared otherwise.


Z — Set if the result is zero; cleared otherwise.


V - Always cleared.


C — Set according to the last bit rotated out of the operand; cleared when the rotate count is zero.


Instruction Execution Times:


roxl
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


#1
8
*
12
12
14
16
18
16
20


#1-8
6+2n
*
*
*
*
*
*
*
*


Dn
6+2n
*
*
*
*
*
*
*
*


roxl.l
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


#1-8
8+2n
*
*
*
*
*
*
*
*


Dn
8+2n
*
*
*
*
*
*
*
*


ROXR

Operation:      Destination Rotated With X By Count → Destination


Assembler Syntax
ROXd Dx,Dy
ROXd # < data > ,Dy
ROXd < ea >
where d is direction, L or R


Attributes: Size = (Byte, Word, Long)
Description: Rotates the bits of the operand in the direction specified (L or R). The extend bit is included in the rotation. The rotate count for the rotation of a register is specified in either of two ways:

Immediate—The rotate count (1 – 8) is specified in the instruction.
Register—The rotate count is the value in the data register specified in the in- struction, modulo 64.

The size of the operation for register destinations is specified as byte, word, or long. The contents of memory, < ea > , can be rotated one bit only, and operand size is restricted to a word. The ROXL instruction rotates the bits of the operand to the left; the rotate count determines the number of bit positions rotated. Bits rotated out of the high- order bit go to the carry bit and the extend bit; the previous value of the extend bit rotates into the low-order bit.
Condition Codes:


X
N
Z
V
C


*
*
*
0
*


X — Not affected.


N — Set if the most significant bit of the result is set; cleared otherwise.


Z — Set if the result is zero; cleared otherwise.


V - Always cleared.


C — Set according to the last bit rotated out of the operand; cleared when the rotate count is zero.


Instruction Execution Times:


roxr
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


#1
8
*
12
12
14
16
18
16
20


#1-8
6+2n
*
*
*
*
*
*
*
*


Dn
6+2n
*
*
*
*
*
*
*
*


roxr.l
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


#1-8
8+2n
*
*
*
*
*
*
*
*


Dn
8+2n
*
*
*
*
*
*
*
*


RTE

Operation:
If Supervisor State  
   Then (SP) → SR; SP + 2 → SP; (SP) → PC; SP + 4 → SP
Else TRAP


Assembler Syntax
rte


Attributes: Size = (Unsized)
Description: Loads the processor state information stored in the exception stack frame located at the top of the stack into the processor. The instruction examines the stack format field in the format/offset word to determine how much information must be restored.
Condition Codes:

Not affected.
Instruction Execution Times:


rte
20


rte.l
20


RTS

Operation:      (SP) → PC; SP + 4 → SP


Assembler Syntax
rts


Attributes: Size = (Unsized)
Description: Pulls the program counter value from the stack. The previous program counter value is lost.
Condition Codes:

Not affected.
Instruction Execution Times:


rts
16


rts.l
16


Scc

Operation:
If Condition True
Then 1s → Destination
Else 0s → Destination


Assembler Syntax
Scc < ea >


Attributes: Size = (Byte)
Description: Tests the specified condition code; if the condition is true, sets the byte specified by the effective address to TRUE (all ones). Otherwise, sets that byte to FALSE (all zeros).


Mnemonic
Condition
Mnemonic
Condition


CC (HI)
Carry Clear
LS
Low or Same


CS (LO)
Carry Set
LT
Less Than


EQ
Equal
MI
Minus


F
False
NE
Not Equal


GE
Greater or Equal
PL
PLus


GT
Greather Than
T
True


HI
High
VC
Overflow Clear


LE
Less or Equal
VS
Overflow Set


Condition Codes:

Not affected.
Instruction Execution Times:


scc
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


6
*
12
12
14
16
18
16
20


SUB

Operation:      Source - Destination → Destination


Assembler Syntax
sub < ea > ,Dn
sub Dn, < ea >


Attributes: Size = (Byte, Word, Long)
Description: Subtracts the source operand from the destination operand and stores the result in the destination. The size of the operation is specified as byte, word, or long. The mode of the instruction indicates which operand is the source, which is the destination, and which is the operand size. Notice that conditon flags are not affected when target is An
Condition Codes:


X
N
Z
V
C


*
*
*
*
*


X - Set the same as carry


N - Set if the result is negative; cleared otherwise.


Z — Set if the result is zero; cleared otherwise.


V — Set if an overflow is generated; cleared otherwise.


C — Set if a borrow is generated; cleared otherwise.


Instruction Execution Times:


sub
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


Dn
4
8
12
12
14
16
18
16
20


An
4
8
*
*
*
*
*
*
*


(An)
8
12
*
*
*
*
*
*
*


(An)+
8
12
*
*
*
*
*
*
*


-(An)
10
14
*
*
*
*
*
*
*


d(An)
12
16
*
*
*
*
*
*
*


d(An,Dn)
14
18
*
*
*
*
*
*
*


xxx.W
12
16
*
*
*
*
*
*
*


xxx.L
16
20
*
*
*
*
*
*
*


d(PC)
12
16
*
*
*
*
*
*
*


d(PC,Dn)
14
18
*
*
*
*
*
*
*


#xxx
10
14
16
16
18
20
22
20
24


sub.l
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


Dn
6
6
20
20
22
24
26
24
28


An
6
6
*
*
*
*
*
*
*


(An)
14
14
*
*
*
*
*
*
*


(An)+
14
14
*
*
*
*
*
*
*


-(An)
16
16
*
*
*
*
*
*
*


d(An)
18
18
*
*
*
*
*
*
*


d(An,Dn)
20
20
*
*
*
*
*
*
*


xxx.W
18
18
*
*
*
*
*
*
*


xxx.L
22
22
*
*
*
*
*
*
*


d(PC)
18
18
*
*
*
*
*
*
*


d(PC,Dn)
20
20
*
*
*
*
*
*
*


#xxx
16
16
28
28
30
32
34
32
36


SUBQ

Operation:      Immidate - Destination → Destination


Assembler Syntax
subq # < data > , < ea >


Attributes: Size = (Byte, Word, Long)
Description: Subtracts the immediate data (1 – 8) from the destination operand. The size of the operation is specified as byte, word, or long. Only word and long operations can be used with address registers, and the condition codes are not affected. When subtracting from address registers, the entire destination address register is used, despite the operation size.
Condition Codes:


X
N
Z
V
C


*
*
*
*
*


X — Set the same as carry


N — Set if the result is negative; cleared otherwise.


Z — Set if the result is zero; cleared otherwise.


V — Set if an overflow is generated; cleared otherwise.


C — Set if a carry is generated; cleared otherwise.


Instruction Execution Times:


subq
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


#xxx
4
8
12
12
14
16
18
16
20


subq.l
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


#xxx
8
8
20
20
22
24
26
24
28


SUBX

Operation:      Source - Destination + X → Destination


Assembler Syntax
subx Dy,Dx
subx -(Ay),-(Ax)


Attributes: Size = (Byte, Word, Long)
Description: Subtracts the source operand and the extend bit from the destination operand and stores the result in the destination location. The instruction has two modes:

Data register to data register—the data registers specified in the instruction con- tain the operands.
Memory to memory—the address registers specified in the instruction access the operands from memory using the predecrement addressing mode.

Condition Codes:


X
N
Z
V
C


*
*
*
*
*


X — Set the same as carry


N — Set if the result is negative; cleared otherwise.


Z — Cleared if the result is non-zero; unchanged otherwise.


V — Set if an overflow is generated; cleared otherwise.


C — Set if a carry is generated; cleared otherwise.


Instruction Execution Times:


subx
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


Dn
4
*
*
*
*
*
*
*
*


-(An)
*
*
*
*
18
*
*
*
*


subx.l
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


Dn
8
*
*
*
*
*
*
*
*


-(An)
*
*
*
*
30
*
*
*
*


SWAP

Operation:      Register 31 – 16 ←→ Register 15 – 0


Assembler Syntax
swap dn


Attributes: Size = (Word)
Description: Exchange the 16-bit words (halves) of a data register.
Condition Codes:


X
N
Z
V
C


-
*
*
0
0


X - Not affected


Set if the most significant bit of the 32-bit result is set; cleared otherwise.


Set if the 32-bit result is zero; cleared otherwise.


V — Always cleared.


C — Always cleared.


Instruction Execution Times:


swap
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


4
*
*
*
*
*
*
*
*


TRAP

Operation:
1 → S-Bit of SR
SSP – 4 → SSP 
PC → (SSP); 
SSP – 2 → SSP; 
SR → (SSP); Vector Address → P


Assembler Syntax
trap # < vector >


Attributes: Size = (Unsized)
Description: Causes a TRAP # < vector > exception. The instruction adds the immediate operand (vector) of the instruction to 32 to obtain the vector number. The range of vector values is 0 – 15, which provides 16 vectors.
Condition Codes:

Not affected.
Instruction Execution Times:


trap
# 


34


TRAPV

Operation:
If V 
    Then Trap


Assembler Syntax
trapv


Attributes: Size = (Unsized)
Description: If the overflow condition is set, causes a TRAPV exception with a vector number 7. If the overflow condition is not set, the processor performs no operation and execution continues with the next instruction.
Condition Codes:

Not affected.
Instruction Execution Times:


trapv
34


TST

Operation:      Destination Tested → Condition Codes; 1 → Bit 7 of Destination


Assembler Syntax
tst < ea >


Attributes: Size = (Byte, Word, Long)
Description: Compares the operand with zero and sets the condition codes according to the results of the test. The size of the operation is specified as byte, word, or long.
Condition Codes:


X
N
Z
V
C


-
*
*
0
0


X - Not affected


N — Set if the operand is negative; cleared otherwise.


Z — Set if the operand is zero; cleared otherwise.


V — Always cleared.


C — Always cleared.


Instruction Execution Times:


tst
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


4
*
8
8
10
12
14
12
16


tst.l
Dn
An
(An)
(An)+
-(An)
d(An)
d(An,Dn)
xxx.W
xxx.L


4
*
12
12
14
16
18
16
20
X	N	Z	V	C
*	U	0	U	*
X — Set the same as carry
N — Undefined
Z — Cleared if the result is nonzero; unchanged otherwise
V — Undefined
C — Set if a decimal carry was generated; cleared otherwise.
X	N	Z	V	C
*	*	*	*	*
X — Set the same as carry
N — Set if the result is negative; cleared otherwise.
Z — Set if the result is zero; cleared otherwise.
V — Set if an overflow is generated; cleared otherwise.
C — Set if a carry is generated; cleared otherwise.
add	Dn	An	(An)	(An)+	-(An)	d(An)	d(An,Dn)	xxx.W	xxx.L
Dn	4	8	12	12	14	16	18	16	20
An	4	8	*	*	*	*	*	*	*
(An)	8	12	*	*	*	*	*	*	*
(An)+	8	12	*	*	*	*	*	*	*
-(An)	10	14	*	*	*	*	*	*	*
d(An)	12	16	*	*	*	*	*	*	*
d(An,Dn)	14	18	*	*	*	*	*	*	*
xxx.W	12	16	*	*	*	*	*	*	*
xxx.L	16	20	*	*	*	*	*	*	*
d(PC)	12	16	*	*	*	*	*	*	*
d(PC,Dn)	14	18	*	*	*	*	*	*	*
#xxx	10	14	16	16	18	20	22	20	24
X	N	Z	V	C
*	*	*	*	*
X — Set the same as carry
N — Set if the result is negative; cleared otherwise.
Z — Cleared if the result is non-zero; unchanged otherwise.
V — Set if an overflow is generated; cleared otherwise.
C — Set if a carry is generated; cleared otherwise.
X	N	Z	V	C
-	*	*	0	0
X - Not Affected
N — Set if the most significant bit of the result is set; cleared otherwise.
Z — Set if the result is zero; cleared otherwise.
V — Always cleared.
C — Always cleared.
X	N	Z	V	C
*	*	*	*	*
X — Set according to the last bit shifted out of the operand; unaffected for a shift count of zero.
N — Set if the most significant bit of the result is set; cleared otherwise.
Z — Set if the result is zero; cleared otherwise.
V — Set if the most significant bit is changed at any time during the shift operation; cleared otherwise.
C — Set according to the last bit shifted out of the operand; cleared for a shift count of zero.
Mnemonic	Condition	Mnemonic	Condition
CC (HI)	Carry Clear	LS	Low or Same
CS (LO)	Carry Set	LT	Less Than
EQ	Equal	MI	Minus
F	False	NE	Not Equal
GE	Greater or Equal	PL	PLus
GT	Greather Than	T	True
HI	High	VC	Overflow Clear
LE	Less or Equal	VS	Overflow Set
X	N	Z	V	C
-	-	*	-	-
X — Not Affected.
N — Not Affected.
Z — Set if the bit tested is zero; cleared otherwise.
V — Not Affected.
C — Not Affected.
X	N	Z	V	C
-	0	*	0	0
X — Not Affected.
N — Always cleared.
Z — Always set.
V — Always cleared.
C — Always cleared.
Displacement	Branch Taken	Branch Not Taken
cc true	-	12
cc false, Count not Expired	10	-
cc false, Counter Expired	-	14