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Last active November 7, 2015 05:08
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load_slice_outline.md

Motivation

Instruction Slice Table

  • What is this used for?
  • Instructions in the IST get sent to another queue
  • Define address generating instructions
  • 128 entry 2-way set-associative least-recently-used replacement policy

Iterative Backward Dependency Analysis

  • Explain the register dependency table
  • Step by step example for Figure 2 (multiple loop iterations)
  • Only address-generating instructions, not data generating! e.g. a store will have a data register and an address register
  • At the end, figure on cumulative distribution of the number of address generating instructions found by subsequent IBDA iterations

10,0000 meter overview of design

  • Two instruction queues (A for general-purpose, B for address generating)
  • Additional blocks for IST, RDT
  • Based on a two-wide in order superscalar design
  • Fun dummy slide (flash it for a second) of architecture parameters

Experimental Setup

  • Sniper multi-core simulator... "cycle-level"
  • Giant figure on relative performance

Area and Power Overhead Experiments

  • Computed using CACTI 6.5
  • Area-normalized and Power-normalized performance
  • IST-size experiments

"Real-World" Constraint Experiments

  • Power <= 45W
  • Area <= 350mm^2
  • "load-slice is better" figure

Related Work

Conclusion

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