I hereby claim:
- I am erincandescent on github.
- I am erincandescent (https://keybase.io/erincandescent) on keybase.
- I have a public key ASDv23fqVwaH5NvQBQp0Y6Itt4lUspg2jfTc257yO_QGWAo
To claim this, I am signing this object:
echo *** Preparing for remote debug ***\n | |
target remote localhost:3333 | |
set arm fallback-mode auto | |
define ifsr | |
monitor arm mrc 15 0 5 0 1 | |
end | |
define ifar | |
monitor arm mrc 15 0 6 0 2 | |
end |
#include <stdio.h> | |
#include <time.h> | |
#include <stdint.h> | |
__asm( | |
".align 16\n" | |
"_overhead:\n" | |
"mov 4(%esp), %eax\n" | |
"mov $25, %ecx\n" | |
"1: dec %ecx\n" |
#![feature(custom_derive, plugin)] | |
#![plugin(serde_macros)] | |
extern crate serde; | |
extern crate serde_json; | |
#[derive(Serialize, Deserialize)] | |
struct S1 { | |
a: Test, | |
b: Test | |
} |
>>> for x in socket.getaddrinfo("rei.local", None, socket.AF_INET6): | |
... print(x) | |
... | |
(10, 1, 6, '', ('fe80::152:821e:3b05:9293', 0, 0, 0)) | |
(10, 2, 17, '', ('fe80::152:821e:3b05:9293', 0, 0, 0)) | |
(10, 3, 0, '', ('fe80::152:821e:3b05:9293', 0, 0, 0)) | |
>>> for x in socket.getaddrinfo("rei.local", None, socket.AF_UNSPEC): | |
... print(x) | |
... | |
(10, 1, 6, '', ('fe80::152:821e:3b05:9293%eth0', 0, 0, 2)) |
I hereby claim:
To claim this, I am signing this object:
{1:F01AAAAGRA0AXXX0057000289}{2:O1030919010321BBBBGRA0AXXX00570001710103210920N}{3:{108:MT103 003 OF 045}{121:c8b66b47-2bd9-48fe-be90-93c2096f27d2}}{4: | |
:20:5387354 | |
:23B:CRED | |
:23E:PHOB/20.527.19.60 | |
:32A:000526USD1101,50 | |
:33B:USD1121,50 | |
:50K:FRANZ HOLZAPFEL GMBH | |
VIENNA | |
:52A:BKAUATWW | |
:59:723491524 |
mkdir modloop-rpi | |
unsquashfs -d modloop-rpi/lib ${alpinePiArmhf}/boot/modloop-rpi 'modules/*/modules.*' 'modules/*/kernel/net/packet/af_packet.ko' | |
(cd modloop-rpi && find . | cpio -H newc -ov | gzip) > initramfs-ext-rpi | |
cat ${alpinePiArmhf}/boot/initramfs-rpi initramfs-ext-rpi > $out/initramfs-rpi |
# dhcp server settings: | |
# dhcp-mac=set:rpi,b8:27:eb:*:*:* | |
# dhcp-boot=tag:rpi,boot,10.69.69.179 | |
{ lib, stdenv, config, pkgs, ... }: | |
let | |
alpineRelease = "3.11"; | |
alpineRevision = "2"; | |
alpineVersion = "${alpineRelease}.${alpineRevision}"; | |
library IEEE; | |
use IEEE.STD_LOGIC_1164.ALL; | |
use IEEE.NUMERIC_STD.ALL; | |
entity NibblerCPU is Port( | |
clk : in STD_LOGIC; | |
rst : in STD_LOGIC; | |
prog_addr : out std_logic_vector(11 downto 0); | |
prog_data : in std_logic_vector(7 downto 0); |
This document was originally written several years ago. At the time I was working as an execution core verification engineer at Arm. The following points are coloured heavily by working in and around the execution cores of various processors. Apply a pinch of salt; points contain varying degrees of opinion.
It is still my opinion that RISC-V could be much better designed; though I will also say that if I was building a 32 or 64-bit CPU today I'd likely implement the architecture to benefit from the existing tooling.
Mostly based upon the RISC-V ISA spec v2.0. Some updates have been made for v2.2
The RISC-V ISA has pursued minimalism to a fault. There is a large emphasis on minimizing instruction count, normalizing encoding, etc. This pursuit of minimalism has resulted in false orthogonalities (such as reusing the same instruction for branches, calls and returns) and a requirement for superfluous instructions which impacts code density both in terms of size and