Skip to content

Instantly share code, notes, and snippets.

@erwei-xilinx
Created February 27, 2024 02:12
Show Gist options
  • Save erwei-xilinx/f1482b2b1c796e92be313a5091ab42e6 to your computer and use it in GitHub Desktop.
Save erwei-xilinx/f1482b2b1c796e92be313a5091ab42e6 to your computer and use it in GitHub Desktop.
IREE-AMD-AIE K-dimension tiling, (2k, 2k, 2k) GEMM IR dump.
This file has been truncated, but you can view the full file.
// -----// IR Dump Before AssignTargetDevicesPass (iree-hal-assign-target-devices) //----- //
module {
func.func @matmul_large(%arg0: tensor<2048x2048xi32>, %arg1: tensor<2048x2048xi32>) -> tensor<2048x2048xi32> {
%0 = tensor.empty() : tensor<2048x2048xi32>
%c0_i32 = arith.constant 0 : i32
%1 = linalg.fill ins(%c0_i32 : i32) outs(%0 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%2 = linalg.matmul ins(%arg0, %arg1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%1 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
return %2 : tensor<2048x2048xi32>
}
}
// -----// IR Dump After AssignTargetDevicesPass (iree-hal-assign-target-devices) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
func.func @matmul_large(%arg0: tensor<2048x2048xi32>, %arg1: tensor<2048x2048xi32>) -> tensor<2048x2048xi32> {
%0 = tensor.empty() : tensor<2048x2048xi32>
%c0_i32 = arith.constant 0 : i32
%1 = linalg.fill ins(%c0_i32 : i32) outs(%0 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%2 = linalg.matmul ins(%arg0, %arg1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%1 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
return %2 : tensor<2048x2048xi32>
}
}
// -----// IR Dump Before AutoInputConversionPipeline (iree-auto-input-conversion) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
func.func @matmul_large(%arg0: tensor<2048x2048xi32>, %arg1: tensor<2048x2048xi32>) -> tensor<2048x2048xi32> {
%0 = tensor.empty() : tensor<2048x2048xi32>
%c0_i32 = arith.constant 0 : i32
%1 = linalg.fill ins(%c0_i32 : i32) outs(%0 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%2 = linalg.matmul ins(%arg0, %arg1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%1 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
return %2 : tensor<2048x2048xi32>
}
}
// -----// IR Dump After AutoInputConversionPipeline (iree-auto-input-conversion) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
func.func @matmul_large(%arg0: tensor<2048x2048xi32>, %arg1: tensor<2048x2048xi32>) -> tensor<2048x2048xi32> {
%0 = tensor.empty() : tensor<2048x2048xi32>
%c0_i32 = arith.constant 0 : i32
%1 = linalg.fill ins(%c0_i32 : i32) outs(%0 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%2 = linalg.matmul ins(%arg0, %arg1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%1 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
return %2 : tensor<2048x2048xi32>
}
}
// -----// IR Dump Before IREEImportPublic (iree-import-public) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
func.func @matmul_large(%arg0: tensor<2048x2048xi32>, %arg1: tensor<2048x2048xi32>) -> tensor<2048x2048xi32> {
%0 = tensor.empty() : tensor<2048x2048xi32>
%c0_i32 = arith.constant 0 : i32
%1 = linalg.fill ins(%c0_i32 : i32) outs(%0 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%2 = linalg.matmul ins(%arg0, %arg1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%1 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
return %2 : tensor<2048x2048xi32>
}
}
// -----// IR Dump After IREEImportPublic (iree-import-public) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
func.func @matmul_large(%arg0: tensor<2048x2048xi32>, %arg1: tensor<2048x2048xi32>) -> tensor<2048x2048xi32> {
%0 = tensor.empty() : tensor<2048x2048xi32>
%c0_i32 = arith.constant 0 : i32
%1 = linalg.fill ins(%c0_i32 : i32) outs(%0 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%2 = linalg.matmul ins(%arg0, %arg1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%1 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
return %2 : tensor<2048x2048xi32>
}
}
// -----// IR Dump Before ImportMLProgram (iree-import-ml-program) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
func.func @matmul_large(%arg0: tensor<2048x2048xi32>, %arg1: tensor<2048x2048xi32>) -> tensor<2048x2048xi32> {
%0 = tensor.empty() : tensor<2048x2048xi32>
%c0_i32 = arith.constant 0 : i32
%1 = linalg.fill ins(%c0_i32 : i32) outs(%0 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%2 = linalg.matmul ins(%arg0, %arg1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%1 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
return %2 : tensor<2048x2048xi32>
}
}
// -----// IR Dump After ImportMLProgram (iree-import-ml-program) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
func.func @matmul_large(%arg0: tensor<2048x2048xi32>, %arg1: tensor<2048x2048xi32>) -> tensor<2048x2048xi32> {
%0 = tensor.empty() : tensor<2048x2048xi32>
%c0_i32 = arith.constant 0 : i32
%1 = linalg.fill ins(%c0_i32 : i32) outs(%0 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%2 = linalg.matmul ins(%arg0, %arg1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%1 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
return %2 : tensor<2048x2048xi32>
}
}
// -----// IR Dump Before SanitizeModuleNames (iree-sanitize-module-names) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
func.func @matmul_large(%arg0: tensor<2048x2048xi32>, %arg1: tensor<2048x2048xi32>) -> tensor<2048x2048xi32> {
%0 = tensor.empty() : tensor<2048x2048xi32>
%c0_i32 = arith.constant 0 : i32
%1 = linalg.fill ins(%c0_i32 : i32) outs(%0 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%2 = linalg.matmul ins(%arg0, %arg1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%1 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
return %2 : tensor<2048x2048xi32>
}
}
// -----// IR Dump After SanitizeModuleNames (iree-sanitize-module-names) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
func.func @matmul_large(%arg0: tensor<2048x2048xi32>, %arg1: tensor<2048x2048xi32>) -> tensor<2048x2048xi32> {
%0 = tensor.empty() : tensor<2048x2048xi32>
%c0_i32 = arith.constant 0 : i32
%1 = linalg.fill ins(%c0_i32 : i32) outs(%0 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%2 = linalg.matmul ins(%arg0, %arg1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%1 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
return %2 : tensor<2048x2048xi32>
}
}
// -----// IR Dump Before ConvertMeshToFlow (iree-convert-mesh-to-flow) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
func.func @matmul_large(%arg0: tensor<2048x2048xi32>, %arg1: tensor<2048x2048xi32>) -> tensor<2048x2048xi32> {
%0 = tensor.empty() : tensor<2048x2048xi32>
%c0_i32 = arith.constant 0 : i32
%1 = linalg.fill ins(%c0_i32 : i32) outs(%0 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%2 = linalg.matmul ins(%arg0, %arg1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%1 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
return %2 : tensor<2048x2048xi32>
}
}
// -----// IR Dump After ConvertMeshToFlow (iree-convert-mesh-to-flow) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
func.func @matmul_large(%arg0: tensor<2048x2048xi32>, %arg1: tensor<2048x2048xi32>) -> tensor<2048x2048xi32> {
%c0_i32 = arith.constant 0 : i32
%0 = tensor.empty() : tensor<2048x2048xi32>
%1 = linalg.fill ins(%c0_i32 : i32) outs(%0 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%2 = linalg.matmul ins(%arg0, %arg1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%1 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
return %2 : tensor<2048x2048xi32>
}
}
// -----// IR Dump Before mlir::iree_compiler::IREE::ABI::ConvertStreamableOpsPass (iree-abi-convert-streamable-ops) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
func.func @matmul_large(%arg0: tensor<2048x2048xi32>, %arg1: tensor<2048x2048xi32>) -> tensor<2048x2048xi32> {
%c0_i32 = arith.constant 0 : i32
%0 = tensor.empty() : tensor<2048x2048xi32>
%1 = linalg.fill ins(%c0_i32 : i32) outs(%0 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%2 = linalg.matmul ins(%arg0, %arg1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%1 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
return %2 : tensor<2048x2048xi32>
}
}
// -----// IR Dump After mlir::iree_compiler::IREE::ABI::ConvertStreamableOpsPass (iree-abi-convert-streamable-ops) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
func.func @matmul_large(%arg0: tensor<2048x2048xi32>, %arg1: tensor<2048x2048xi32>) -> tensor<2048x2048xi32> {
%c0_i32 = arith.constant 0 : i32
%0 = tensor.empty() : tensor<2048x2048xi32>
%1 = linalg.fill ins(%c0_i32 : i32) outs(%0 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%2 = linalg.matmul ins(%arg0, %arg1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%1 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
return %2 : tensor<2048x2048xi32>
}
}
// -----// IR Dump Before mlir::iree_compiler::IREE::ABI::WrapEntryPointsPass (iree-abi-wrap-entry-points) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
func.func @matmul_large(%arg0: tensor<2048x2048xi32>, %arg1: tensor<2048x2048xi32>) -> tensor<2048x2048xi32> {
%c0_i32 = arith.constant 0 : i32
%0 = tensor.empty() : tensor<2048x2048xi32>
%1 = linalg.fill ins(%c0_i32 : i32) outs(%0 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%2 = linalg.matmul ins(%arg0, %arg1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%1 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
return %2 : tensor<2048x2048xi32>
}
}
// -----// IR Dump After mlir::iree_compiler::IREE::ABI::WrapEntryPointsPass (iree-abi-wrap-entry-points) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = call @_matmul_large(%0, %1) : (tensor<2048x2048xi32>, tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%3 = hal.tensor.export %2 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %3 : !hal.buffer_view
}
func.func private @_matmul_large(%arg0: tensor<2048x2048xi32>, %arg1: tensor<2048x2048xi32>) -> tensor<2048x2048xi32> {
%c0_i32 = arith.constant 0 : i32
%0 = tensor.empty() : tensor<2048x2048xi32>
%1 = linalg.fill ins(%c0_i32 : i32) outs(%0 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%2 = linalg.matmul ins(%arg0, %arg1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%1 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
return %2 : tensor<2048x2048xi32>
}
}
// -----// IR Dump Before Inliner (inline) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = call @_matmul_large(%0, %1) : (tensor<2048x2048xi32>, tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%3 = hal.tensor.export %2 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %3 : !hal.buffer_view
}
func.func private @_matmul_large(%arg0: tensor<2048x2048xi32>, %arg1: tensor<2048x2048xi32>) -> tensor<2048x2048xi32> {
%c0_i32 = arith.constant 0 : i32
%0 = tensor.empty() : tensor<2048x2048xi32>
%1 = linalg.fill ins(%c0_i32 : i32) outs(%0 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%2 = linalg.matmul ins(%arg0, %arg1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%1 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
return %2 : tensor<2048x2048xi32>
}
}
// -----// IR Dump Before Canonicalizer (canonicalize) //----- //
func.func private @_matmul_large(%arg0: tensor<2048x2048xi32>, %arg1: tensor<2048x2048xi32>) -> tensor<2048x2048xi32> {
%c0_i32 = arith.constant 0 : i32
%0 = tensor.empty() : tensor<2048x2048xi32>
%1 = linalg.fill ins(%c0_i32 : i32) outs(%0 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%2 = linalg.matmul ins(%arg0, %arg1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%1 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
return %2 : tensor<2048x2048xi32>
}
// -----// IR Dump After Canonicalizer (canonicalize) //----- //
func.func private @_matmul_large(%arg0: tensor<2048x2048xi32>, %arg1: tensor<2048x2048xi32>) -> tensor<2048x2048xi32> {
%c0_i32 = arith.constant 0 : i32
%0 = tensor.empty() : tensor<2048x2048xi32>
%1 = linalg.fill ins(%c0_i32 : i32) outs(%0 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%2 = linalg.matmul ins(%arg0, %arg1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%1 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
return %2 : tensor<2048x2048xi32>
}
// -----// IR Dump Before Canonicalizer (canonicalize) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = call @_matmul_large(%0, %1) : (tensor<2048x2048xi32>, tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%3 = hal.tensor.export %2 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %3 : !hal.buffer_view
}
// -----// IR Dump After Canonicalizer (canonicalize) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = call @_matmul_large(%0, %1) : (tensor<2048x2048xi32>, tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%3 = hal.tensor.export %2 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %3 : !hal.buffer_view
}
// -----// IR Dump Before Canonicalizer (canonicalize) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%c0_i32 = arith.constant 0 : i32
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
// -----// IR Dump After Canonicalizer (canonicalize) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
// -----// IR Dump After Inliner (inline) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
}
// -----// IR Dump Before Canonicalizer (canonicalize) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
// -----// IR Dump After Canonicalizer (canonicalize) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
// -----// IR Dump Before CSE (cse) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
// -----// IR Dump After CSE (cse) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
// -----// IR Dump Before SymbolDCE (symbol-dce) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
}
// -----// IR Dump After SymbolDCE (symbol-dce) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
}
// -----// IR Dump Before DemoteF64ToF32 (iree-util-demote-f64-to-f32) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
}
// -----// IR Dump After DemoteF64ToF32 (iree-util-demote-f64-to-f32) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
}
// -----// IR Dump Before RemoveZeroExtentTensors (iree-global-opt-remove-zero-extent-tensors) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
// -----// IR Dump After RemoveZeroExtentTensors (iree-global-opt-remove-zero-extent-tensors) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
// -----// IR Dump Before DetachElementwiseFromNamedOps (iree-global-opt-detach-elementwise-from-named-ops) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
// -----// IR Dump After DetachElementwiseFromNamedOps (iree-global-opt-detach-elementwise-from-named-ops) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
// -----// IR Dump Before LinalgNamedOpConversion (linalg-named-op-conversion) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
// -----// IR Dump After LinalgNamedOpConversion (linalg-named-op-conversion) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
// -----// IR Dump Before Convert1X1FilterConv2DToMatmul (iree-global-opt-convert-1x1-filter-conv2d-to-matmul) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
// -----// IR Dump After Convert1X1FilterConv2DToMatmul (iree-global-opt-convert-1x1-filter-conv2d-to-matmul) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
// -----// IR Dump Before EraseUnusedLinalgOperands (iree-global-opt-erase-unused-linalg-operands) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
}
// -----// IR Dump After EraseUnusedLinalgOperands (iree-global-opt-erase-unused-linalg-operands) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
}
// -----// IR Dump Before ExpandTensorShapes (iree-global-opt-expand-tensor-shapes) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
}
// -----// IR Dump After ExpandTensorShapes (iree-global-opt-expand-tensor-shapes) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
}
// -----// IR Dump Before ConvertElementwiseToLinalg (convert-elementwise-to-linalg) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
// -----// IR Dump After ConvertElementwiseToLinalg (convert-elementwise-to-linalg) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
// -----// IR Dump Before RaiseSpecialOps (iree-global-opt-raise-special-ops) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
// -----// IR Dump After RaiseSpecialOps (iree-global-opt-raise-special-ops) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
// -----// IR Dump Before DecomposeConcat (iree-global-opt-decompose-concat) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
// -----// IR Dump After DecomposeConcat (iree-global-opt-decompose-concat) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
// -----// IR Dump Before GeneralizeLinalgNamedOps (iree-global-opt-generalize-linalg-named-ops) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
// -----// IR Dump After GeneralizeLinalgNamedOps (iree-global-opt-generalize-linalg-named-ops) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
// -----// IR Dump Before FoldUnitExtentDims (iree-flow-fold-unit-extent-dims) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
// -----// IR Dump After FoldUnitExtentDims (iree-flow-fold-unit-extent-dims) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
// -----// IR Dump Before FuseDequantizationMatmul (iree-global-opt-fuse-dequantization-matmul) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
// -----// IR Dump After FuseDequantizationMatmul (iree-global-opt-fuse-dequantization-matmul) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
// -----// IR Dump Before Canonicalizer (canonicalize) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
// -----// IR Dump After Canonicalizer (canonicalize) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
// -----// IR Dump Before CSE (cse) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
// -----// IR Dump After CSE (cse) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
// -----// IR Dump Before Canonicalizer (canonicalize) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
// -----// IR Dump After Canonicalizer (canonicalize) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
// -----// IR Dump Before CSE (cse) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
// -----// IR Dump After CSE (cse) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
// -----// IR Dump Before SetEncoding (iree-global-opt-set-encoding) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
}
// -----// IR Dump After SetEncoding (iree-global-opt-set-encoding) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#map = affine_map<(d0, d1, d2) -> (d0, d2)>
#map1 = affine_map<(d0, d1, d2) -> (d2, d1)>
#map2 = affine_map<(d0, d1, d2) -> (d0, d1)>
#map3 = affine_map<()[s0, s1] -> (-s1 + (s1 ceildiv s0) * s0)>
#map4 = affine_map<()[s0] -> ((2048 ceildiv s0) * s0)>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c2048 = arith.constant 2048 : index
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2:2 = iree_linalg_ext.upper_bound_tile_size tensor<2048x2048xi32, #iree_linalg_ext.encoding<role = LHS, element_types = [i32, i32, i32], user_indexing_maps = [#map, #map1, #map2]>> -> index, index
%3 = affine.apply #map3()[%2#0, %c2048]
%4 = affine.apply #map3()[%2#1, %c2048]
%padded = tensor.pad %0 low[0, 0] high[%3, %4] {
^bb0(%arg2: index, %arg3: index):
tensor.yield %c0_i32 : i32
} : tensor<2048x2048xi32> to tensor<?x?xi32>
%5 = iree_linalg_ext.set_encoding %padded : tensor<?x?xi32> -> tensor<?x?xi32, #iree_linalg_ext.encoding<role = LHS, element_types = [i32, i32, i32], original_type = tensor<2048x2048xi32>, user_indexing_maps = [#map, #map1, #map2]>>
%6:2 = iree_linalg_ext.upper_bound_tile_size tensor<2048x2048xi32, #iree_linalg_ext.encoding<role = RHS, element_types = [i32, i32, i32], user_indexing_maps = [#map, #map1, #map2]>> -> index, index
%7 = affine.apply #map3()[%6#0, %c2048]
%8 = affine.apply #map3()[%6#1, %c2048]
%padded_0 = tensor.pad %1 low[0, 0] high[%7, %8] {
^bb0(%arg2: index, %arg3: index):
tensor.yield %c0_i32 : i32
} : tensor<2048x2048xi32> to tensor<?x?xi32>
%9 = iree_linalg_ext.set_encoding %padded_0 : tensor<?x?xi32> -> tensor<?x?xi32, #iree_linalg_ext.encoding<role = RHS, element_types = [i32, i32, i32], original_type = tensor<2048x2048xi32>, user_indexing_maps = [#map, #map1, #map2]>>
%10:2 = iree_linalg_ext.upper_bound_tile_size tensor<2048x2048xi32, #iree_linalg_ext.encoding<role = RESULT, element_types = [i32, i32, i32], user_indexing_maps = [#map, #map1, #map2]>> -> index, index
%11 = affine.apply #map4()[%10#0]
%12 = affine.apply #map4()[%10#1]
%13 = tensor.empty(%11, %12) : tensor<?x?xi32, #iree_linalg_ext.encoding<role = RESULT, element_types = [i32, i32, i32], original_type = tensor<2048x2048xi32>, user_indexing_maps = [#map, #map1, #map2]>>
%14 = linalg.fill ins(%c0_i32 : i32) outs(%13 : tensor<?x?xi32, #iree_linalg_ext.encoding<role = RESULT, element_types = [i32, i32, i32], original_type = tensor<2048x2048xi32>, user_indexing_maps = [#map, #map1, #map2]>>) -> tensor<?x?xi32, #iree_linalg_ext.encoding<role = RESULT, element_types = [i32, i32, i32], original_type = tensor<2048x2048xi32>, user_indexing_maps = [#map, #map1, #map2]>>
%15 = linalg.matmul ins(%5, %9 : tensor<?x?xi32, #iree_linalg_ext.encoding<role = LHS, element_types = [i32, i32, i32], original_type = tensor<2048x2048xi32>, user_indexing_maps = [#map, #map1, #map2]>>, tensor<?x?xi32, #iree_linalg_ext.encoding<role = RHS, element_types = [i32, i32, i32], original_type = tensor<2048x2048xi32>, user_indexing_maps = [#map, #map1, #map2]>>) outs(%14 : tensor<?x?xi32, #iree_linalg_ext.encoding<role = RESULT, element_types = [i32, i32, i32], original_type = tensor<2048x2048xi32>, user_indexing_maps = [#map, #map1, #map2]>>) -> tensor<?x?xi32, #iree_linalg_ext.encoding<role = RESULT, element_types = [i32, i32, i32], original_type = tensor<2048x2048xi32>, user_indexing_maps = [#map, #map1, #map2]>>
%16 = iree_linalg_ext.unset_encoding %15 : tensor<?x?xi32, #iree_linalg_ext.encoding<role = RESULT, element_types = [i32, i32, i32], original_type = tensor<2048x2048xi32>, user_indexing_maps = [#map, #map1, #map2]>> -> tensor<?x?xi32>
%extracted_slice = tensor.extract_slice %16[0, 0] [2048, 2048] [1, 1] : tensor<?x?xi32> to tensor<2048x2048xi32>
%17 = hal.tensor.export %extracted_slice "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %17 : !hal.buffer_view
}
}
// -----// IR Dump Before MaterializeHomogeneousEncodings (iree-global-opt-materialize-homogeneous-encodings) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#map = affine_map<(d0, d1, d2) -> (d0, d2)>
#map1 = affine_map<(d0, d1, d2) -> (d2, d1)>
#map2 = affine_map<(d0, d1, d2) -> (d0, d1)>
#map3 = affine_map<()[s0, s1] -> (-s1 + (s1 ceildiv s0) * s0)>
#map4 = affine_map<()[s0] -> ((2048 ceildiv s0) * s0)>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c2048 = arith.constant 2048 : index
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2:2 = iree_linalg_ext.upper_bound_tile_size tensor<2048x2048xi32, #iree_linalg_ext.encoding<role = LHS, element_types = [i32, i32, i32], user_indexing_maps = [#map, #map1, #map2]>> -> index, index
%3 = affine.apply #map3()[%2#0, %c2048]
%4 = affine.apply #map3()[%2#1, %c2048]
%padded = tensor.pad %0 low[0, 0] high[%3, %4] {
^bb0(%arg2: index, %arg3: index):
tensor.yield %c0_i32 : i32
} : tensor<2048x2048xi32> to tensor<?x?xi32>
%5 = iree_linalg_ext.set_encoding %padded : tensor<?x?xi32> -> tensor<?x?xi32, #iree_linalg_ext.encoding<role = LHS, element_types = [i32, i32, i32], original_type = tensor<2048x2048xi32>, user_indexing_maps = [#map, #map1, #map2]>>
%6:2 = iree_linalg_ext.upper_bound_tile_size tensor<2048x2048xi32, #iree_linalg_ext.encoding<role = RHS, element_types = [i32, i32, i32], user_indexing_maps = [#map, #map1, #map2]>> -> index, index
%7 = affine.apply #map3()[%6#0, %c2048]
%8 = affine.apply #map3()[%6#1, %c2048]
%padded_0 = tensor.pad %1 low[0, 0] high[%7, %8] {
^bb0(%arg2: index, %arg3: index):
tensor.yield %c0_i32 : i32
} : tensor<2048x2048xi32> to tensor<?x?xi32>
%9 = iree_linalg_ext.set_encoding %padded_0 : tensor<?x?xi32> -> tensor<?x?xi32, #iree_linalg_ext.encoding<role = RHS, element_types = [i32, i32, i32], original_type = tensor<2048x2048xi32>, user_indexing_maps = [#map, #map1, #map2]>>
%10:2 = iree_linalg_ext.upper_bound_tile_size tensor<2048x2048xi32, #iree_linalg_ext.encoding<role = RESULT, element_types = [i32, i32, i32], user_indexing_maps = [#map, #map1, #map2]>> -> index, index
%11 = affine.apply #map4()[%10#0]
%12 = affine.apply #map4()[%10#1]
%13 = tensor.empty(%11, %12) : tensor<?x?xi32, #iree_linalg_ext.encoding<role = RESULT, element_types = [i32, i32, i32], original_type = tensor<2048x2048xi32>, user_indexing_maps = [#map, #map1, #map2]>>
%14 = linalg.fill ins(%c0_i32 : i32) outs(%13 : tensor<?x?xi32, #iree_linalg_ext.encoding<role = RESULT, element_types = [i32, i32, i32], original_type = tensor<2048x2048xi32>, user_indexing_maps = [#map, #map1, #map2]>>) -> tensor<?x?xi32, #iree_linalg_ext.encoding<role = RESULT, element_types = [i32, i32, i32], original_type = tensor<2048x2048xi32>, user_indexing_maps = [#map, #map1, #map2]>>
%15 = linalg.matmul ins(%5, %9 : tensor<?x?xi32, #iree_linalg_ext.encoding<role = LHS, element_types = [i32, i32, i32], original_type = tensor<2048x2048xi32>, user_indexing_maps = [#map, #map1, #map2]>>, tensor<?x?xi32, #iree_linalg_ext.encoding<role = RHS, element_types = [i32, i32, i32], original_type = tensor<2048x2048xi32>, user_indexing_maps = [#map, #map1, #map2]>>) outs(%14 : tensor<?x?xi32, #iree_linalg_ext.encoding<role = RESULT, element_types = [i32, i32, i32], original_type = tensor<2048x2048xi32>, user_indexing_maps = [#map, #map1, #map2]>>) -> tensor<?x?xi32, #iree_linalg_ext.encoding<role = RESULT, element_types = [i32, i32, i32], original_type = tensor<2048x2048xi32>, user_indexing_maps = [#map, #map1, #map2]>>
%16 = iree_linalg_ext.unset_encoding %15 : tensor<?x?xi32, #iree_linalg_ext.encoding<role = RESULT, element_types = [i32, i32, i32], original_type = tensor<2048x2048xi32>, user_indexing_maps = [#map, #map1, #map2]>> -> tensor<?x?xi32>
%extracted_slice = tensor.extract_slice %16[0, 0] [2048, 2048] [1, 1] : tensor<?x?xi32> to tensor<2048x2048xi32>
%17 = hal.tensor.export %extracted_slice "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %17 : !hal.buffer_view
}
}
// -----// IR Dump Before MaterializeEncodingIntoNop (iree-codegen-materialize-encoding-into-nop) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c2048 = arith.constant 2048 : index
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2:2 = iree_linalg_ext.upper_bound_tile_size tensor<2048x2048xi32, #iree_linalg_ext.encoding<role = LHS, element_types = [i32, i32, i32], user_indexing_maps = [affine_map<(d0, d1, d2) -> (d0, d2)>, affine_map<(d0, d1, d2) -> (d2, d1)>, affine_map<(d0, d1, d2) -> (d0, d1)>]>> -> index, index
%3 = affine.apply affine_map<()[s0, s1] -> (-s1 + (s1 ceildiv s0) * s0)>()[%2#0, %c2048]
%4 = affine.apply affine_map<()[s0, s1] -> (-s1 + (s1 ceildiv s0) * s0)>()[%2#1, %c2048]
%padded = tensor.pad %0 low[0, 0] high[%3, %4] {
^bb0(%arg2: index, %arg3: index):
tensor.yield %c0_i32 : i32
} : tensor<2048x2048xi32> to tensor<?x?xi32>
%5 = iree_linalg_ext.set_encoding %padded : tensor<?x?xi32> -> tensor<?x?xi32, #iree_linalg_ext.encoding<role = LHS, element_types = [i32, i32, i32], original_type = tensor<2048x2048xi32>, user_indexing_maps = [affine_map<(d0, d1, d2) -> (d0, d2)>, affine_map<(d0, d1, d2) -> (d2, d1)>, affine_map<(d0, d1, d2) -> (d0, d1)>]>>
%6:2 = iree_linalg_ext.upper_bound_tile_size tensor<2048x2048xi32, #iree_linalg_ext.encoding<role = RHS, element_types = [i32, i32, i32], user_indexing_maps = [affine_map<(d0, d1, d2) -> (d0, d2)>, affine_map<(d0, d1, d2) -> (d2, d1)>, affine_map<(d0, d1, d2) -> (d0, d1)>]>> -> index, index
%7 = affine.apply affine_map<()[s0, s1] -> (-s1 + (s1 ceildiv s0) * s0)>()[%6#0, %c2048]
%8 = affine.apply affine_map<()[s0, s1] -> (-s1 + (s1 ceildiv s0) * s0)>()[%6#1, %c2048]
%padded_0 = tensor.pad %1 low[0, 0] high[%7, %8] {
^bb0(%arg2: index, %arg3: index):
tensor.yield %c0_i32 : i32
} : tensor<2048x2048xi32> to tensor<?x?xi32>
%9 = iree_linalg_ext.set_encoding %padded_0 : tensor<?x?xi32> -> tensor<?x?xi32, #iree_linalg_ext.encoding<role = RHS, element_types = [i32, i32, i32], original_type = tensor<2048x2048xi32>, user_indexing_maps = [affine_map<(d0, d1, d2) -> (d0, d2)>, affine_map<(d0, d1, d2) -> (d2, d1)>, affine_map<(d0, d1, d2) -> (d0, d1)>]>>
%10:2 = iree_linalg_ext.upper_bound_tile_size tensor<2048x2048xi32, #iree_linalg_ext.encoding<role = RESULT, element_types = [i32, i32, i32], user_indexing_maps = [affine_map<(d0, d1, d2) -> (d0, d2)>, affine_map<(d0, d1, d2) -> (d2, d1)>, affine_map<(d0, d1, d2) -> (d0, d1)>]>> -> index, index
%11 = affine.apply affine_map<()[s0] -> ((2048 ceildiv s0) * s0)>()[%10#0]
%12 = affine.apply affine_map<()[s0] -> ((2048 ceildiv s0) * s0)>()[%10#1]
%13 = tensor.empty(%11, %12) : tensor<?x?xi32, #iree_linalg_ext.encoding<role = RESULT, element_types = [i32, i32, i32], original_type = tensor<2048x2048xi32>, user_indexing_maps = [affine_map<(d0, d1, d2) -> (d0, d2)>, affine_map<(d0, d1, d2) -> (d2, d1)>, affine_map<(d0, d1, d2) -> (d0, d1)>]>>
%14 = linalg.fill ins(%c0_i32 : i32) outs(%13 : tensor<?x?xi32, #iree_linalg_ext.encoding<role = RESULT, element_types = [i32, i32, i32], original_type = tensor<2048x2048xi32>, user_indexing_maps = [affine_map<(d0, d1, d2) -> (d0, d2)>, affine_map<(d0, d1, d2) -> (d2, d1)>, affine_map<(d0, d1, d2) -> (d0, d1)>]>>) -> tensor<?x?xi32, #iree_linalg_ext.encoding<role = RESULT, element_types = [i32, i32, i32], original_type = tensor<2048x2048xi32>, user_indexing_maps = [affine_map<(d0, d1, d2) -> (d0, d2)>, affine_map<(d0, d1, d2) -> (d2, d1)>, affine_map<(d0, d1, d2) -> (d0, d1)>]>>
%15 = linalg.matmul ins(%5, %9 : tensor<?x?xi32, #iree_linalg_ext.encoding<role = LHS, element_types = [i32, i32, i32], original_type = tensor<2048x2048xi32>, user_indexing_maps = [affine_map<(d0, d1, d2) -> (d0, d2)>, affine_map<(d0, d1, d2) -> (d2, d1)>, affine_map<(d0, d1, d2) -> (d0, d1)>]>>, tensor<?x?xi32, #iree_linalg_ext.encoding<role = RHS, element_types = [i32, i32, i32], original_type = tensor<2048x2048xi32>, user_indexing_maps = [affine_map<(d0, d1, d2) -> (d0, d2)>, affine_map<(d0, d1, d2) -> (d2, d1)>, affine_map<(d0, d1, d2) -> (d0, d1)>]>>) outs(%14 : tensor<?x?xi32, #iree_linalg_ext.encoding<role = RESULT, element_types = [i32, i32, i32], original_type = tensor<2048x2048xi32>, user_indexing_maps = [affine_map<(d0, d1, d2) -> (d0, d2)>, affine_map<(d0, d1, d2) -> (d2, d1)>, affine_map<(d0, d1, d2) -> (d0, d1)>]>>) -> tensor<?x?xi32, #iree_linalg_ext.encoding<role = RESULT, element_types = [i32, i32, i32], original_type = tensor<2048x2048xi32>, user_indexing_maps = [affine_map<(d0, d1, d2) -> (d0, d2)>, affine_map<(d0, d1, d2) -> (d2, d1)>, affine_map<(d0, d1, d2) -> (d0, d1)>]>>
%16 = iree_linalg_ext.unset_encoding %15 : tensor<?x?xi32, #iree_linalg_ext.encoding<role = RESULT, element_types = [i32, i32, i32], original_type = tensor<2048x2048xi32>, user_indexing_maps = [affine_map<(d0, d1, d2) -> (d0, d2)>, affine_map<(d0, d1, d2) -> (d2, d1)>, affine_map<(d0, d1, d2) -> (d0, d1)>]>> -> tensor<?x?xi32>
%extracted_slice = tensor.extract_slice %16[0, 0] [2048, 2048] [1, 1] : tensor<?x?xi32> to tensor<2048x2048xi32>
%17 = hal.tensor.export %extracted_slice "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %17 : !hal.buffer_view
}
// -----// IR Dump After MaterializeEncodingIntoNop (iree-codegen-materialize-encoding-into-nop) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c2048 = arith.constant 2048 : index
%c0 = arith.constant 0 : index
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%padded = tensor.pad %0 low[0, 0] high[%c0, %c0] {
^bb0(%arg2: index, %arg3: index):
tensor.yield %c0_i32 : i32
} : tensor<2048x2048xi32> to tensor<?x?xi32>
%padded_0 = tensor.pad %1 low[0, 0] high[%c0, %c0] {
^bb0(%arg2: index, %arg3: index):
tensor.yield %c0_i32 : i32
} : tensor<2048x2048xi32> to tensor<?x?xi32>
%2 = tensor.empty(%c2048, %c2048) : tensor<?x?xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<?x?xi32>) -> tensor<?x?xi32>
%4 = linalg.matmul ins(%padded, %padded_0 : tensor<?x?xi32>, tensor<?x?xi32>) outs(%3 : tensor<?x?xi32>) -> tensor<?x?xi32>
%extracted_slice = tensor.extract_slice %4[0, 0] [2048, 2048] [1, 1] : tensor<?x?xi32> to tensor<2048x2048xi32>
%5 = hal.tensor.export %extracted_slice "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
// -----// IR Dump Before Canonicalizer (canonicalize) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c2048 = arith.constant 2048 : index
%c0 = arith.constant 0 : index
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%padded = tensor.pad %0 low[0, 0] high[%c0, %c0] {
^bb0(%arg2: index, %arg3: index):
tensor.yield %c0_i32 : i32
} : tensor<2048x2048xi32> to tensor<?x?xi32>
%padded_0 = tensor.pad %1 low[0, 0] high[%c0, %c0] {
^bb0(%arg2: index, %arg3: index):
tensor.yield %c0_i32 : i32
} : tensor<2048x2048xi32> to tensor<?x?xi32>
%2 = tensor.empty(%c2048, %c2048) : tensor<?x?xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<?x?xi32>) -> tensor<?x?xi32>
%4 = linalg.matmul ins(%padded, %padded_0 : tensor<?x?xi32>, tensor<?x?xi32>) outs(%3 : tensor<?x?xi32>) -> tensor<?x?xi32>
%extracted_slice = tensor.extract_slice %4[0, 0] [2048, 2048] [1, 1] : tensor<?x?xi32> to tensor<2048x2048xi32>
%5 = hal.tensor.export %extracted_slice "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
// -----// IR Dump After Canonicalizer (canonicalize) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
// -----// IR Dump After MaterializeHomogeneousEncodings (iree-global-opt-materialize-homogeneous-encodings) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
}
// -----// IR Dump Before Canonicalizer (canonicalize) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
}
// -----// IR Dump After Canonicalizer (canonicalize) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
}
// -----// IR Dump Before CSE (cse) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
}
// -----// IR Dump After CSE (cse) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
}
// -----// IR Dump Before SimplifyPackUnpack (iree-global-opt-simplify-pack-unpack) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
}
// -----// IR Dump After SimplifyPackUnpack (iree-global-opt-simplify-pack-unpack) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
}
// -----// IR Dump Before GeneralizeLinalgNamedOps (iree-global-opt-generalize-linalg-named-ops) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
// -----// IR Dump After GeneralizeLinalgNamedOps (iree-global-opt-generalize-linalg-named-ops) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
// -----// IR Dump Before FixedPointIterator (iree-util-fixed-point-iterator) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
}
// -----// IR Dump Before SimplifyGlobalAccesses (iree-util-simplify-global-accesses) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
// -----// IR Dump After SimplifyGlobalAccesses (iree-util-simplify-global-accesses) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
// -----// IR Dump Before ApplyPatterns (iree-util-apply-patterns) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie], iree.fixedpoint.iteration = 0 : index} {
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
}
// -----// IR Dump After ApplyPatterns (iree-util-apply-patterns) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie], iree.fixedpoint.iteration = 0 : index} {
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
}
// -----// IR Dump Before FoldGlobals (iree-util-fold-globals) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie], iree.fixedpoint.iteration = 0 : index} {
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
}
// -----// IR Dump After FoldGlobals (iree-util-fold-globals) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie], iree.fixedpoint.iteration = 0 : index} {
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
}
// -----// IR Dump Before IPO (iree-util-ipo) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie], iree.fixedpoint.iteration = 0 : index} {
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
}
// -----// IR Dump After IPO (iree-util-ipo) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie], iree.fixedpoint.iteration = 0 : index} {
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
}
// -----// IR Dump Before Canonicalizer (canonicalize) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie], iree.fixedpoint.iteration = 0 : index} {
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
}
// -----// IR Dump After Canonicalizer (canonicalize) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie], iree.fixedpoint.iteration = 0 : index} {
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
}
// -----// IR Dump Before CSE (cse) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie], iree.fixedpoint.iteration = 0 : index} {
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
}
// -----// IR Dump After CSE (cse) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie], iree.fixedpoint.iteration = 0 : index} {
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
}
// -----// IR Dump Before HoistIntoGlobals (iree-util-hoist-into-globals) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie], iree.fixedpoint.iteration = 0 : index} {
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
}
// -----// IR Dump After HoistIntoGlobals (iree-util-hoist-into-globals) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie], iree.fixedpoint.iteration = 0 : index} {
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
}
// -----// IR Dump Before JitGlobals (iree-consteval-jit-globals) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie], iree.fixedpoint.iteration = 0 : index} {
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
}
// -----// IR Dump After JitGlobals (iree-consteval-jit-globals) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie], iree.fixedpoint.iteration = 0 : index} {
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
}
// -----// IR Dump Before Canonicalizer (canonicalize) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
// -----// IR Dump After Canonicalizer (canonicalize) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
// -----// IR Dump Before CSE (cse) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
// -----// IR Dump After CSE (cse) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
// -----// IR Dump After FixedPointIterator (iree-util-fixed-point-iterator) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
}
// -----// IR Dump Before RaiseSpecialOps (iree-global-opt-raise-special-ops) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
// -----// IR Dump After RaiseSpecialOps (iree-global-opt-raise-special-ops) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
// -----// IR Dump Before VerifyInputLegality (iree-verify-input-legality) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
}
// -----// IR Dump After VerifyInputLegality (iree-verify-input-legality) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
}
// -----// IR Dump Before TensorPadToTensorInsertSlice (iree-flow-tensor-pad-to-tensor-insert-slice) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
}
// -----// IR Dump After TensorPadToTensorInsertSlice (iree-flow-tensor-pad-to-tensor-insert-slice) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
}
// -----// IR Dump Before InterchangeGenericOps (iree-flow-interchange-generic-ops) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
// -----// IR Dump After InterchangeGenericOps (iree-flow-interchange-generic-ops) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
// -----// IR Dump Before ResolveShapedTypeResultDims (resolve-shaped-type-result-dims) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
// -----// IR Dump After ResolveShapedTypeResultDims (resolve-shaped-type-result-dims) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
// -----// IR Dump Before Canonicalizer (canonicalize) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
// -----// IR Dump After Canonicalizer (canonicalize) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
// -----// IR Dump Before CSE (cse) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
// -----// IR Dump After CSE (cse) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
// -----// IR Dump Before FusionOfTensorOps (iree-flow-fusion-of-tensor-ops) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
// -----// IR Dump After FusionOfTensorOps (iree-flow-fusion-of-tensor-ops) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
// -----// IR Dump Before Canonicalizer (canonicalize) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
// -----// IR Dump After Canonicalizer (canonicalize) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
// -----// IR Dump Before CSE (cse) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
// -----// IR Dump After CSE (cse) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
// -----// IR Dump Before SplitReduction (iree-flow-split-reduction-ops) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
// -----// IR Dump After SplitReduction (iree-flow-split-reduction-ops) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
// -----// IR Dump Before InterchangeGenericOps (iree-flow-interchange-generic-ops) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
// -----// IR Dump After InterchangeGenericOps (iree-flow-interchange-generic-ops) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
// -----// IR Dump Before FormScalarDispatches (iree-flow-form-scalar-dispatches) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
// -----// IR Dump After FormScalarDispatches (iree-flow-form-scalar-dispatches) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
// -----// IR Dump Before FormDispatchRegions (iree-flow-form-dispatch-regions) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
// -----// IR Dump After FormDispatchRegions (iree-flow-form-dispatch-regions) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = flow.dispatch.region -> (tensor<2048x2048xi32>) {
%6 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.return %6 : tensor<2048x2048xi32>
}
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
// -----// IR Dump Before CloneProducersIntoDispatchRegions (iree-flow-clone-producers-into-dispatch-regions) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = flow.dispatch.region -> (tensor<2048x2048xi32>) {
%6 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.return %6 : tensor<2048x2048xi32>
}
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
// -----// IR Dump After CloneProducersIntoDispatchRegions (iree-flow-clone-producers-into-dispatch-regions) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = flow.dispatch.region -> (tensor<2048x2048xi32>) {
%6 = tensor.empty() : tensor<2048x2048xi32>
%c0_i32_0 = arith.constant 0 : i32
%7 = linalg.fill ins(%c0_i32_0 : i32) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%8 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%7 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.return %8 : tensor<2048x2048xi32>
}
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
// -----// IR Dump Before CollapseDimensions (iree-flow-collapse-dimensions) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = flow.dispatch.region -> (tensor<2048x2048xi32>) {
%6 = tensor.empty() : tensor<2048x2048xi32>
%c0_i32_0 = arith.constant 0 : i32
%7 = linalg.fill ins(%c0_i32_0 : i32) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%8 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%7 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.return %8 : tensor<2048x2048xi32>
}
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
// -----// IR Dump After CollapseDimensions (iree-flow-collapse-dimensions) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = flow.dispatch.region -> (tensor<2048x2048xi32>) {
%6 = tensor.empty() : tensor<2048x2048xi32>
%c0_i32_0 = arith.constant 0 : i32
%7 = linalg.fill ins(%c0_i32_0 : i32) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%8 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%7 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.return %8 : tensor<2048x2048xi32>
}
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
// -----// IR Dump Before FormDispatchWorkgroups (iree-flow-form-dispatch-workgroups) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = flow.dispatch.region -> (tensor<2048x2048xi32>) {
%6 = tensor.empty() : tensor<2048x2048xi32>
%c0_i32_0 = arith.constant 0 : i32
%7 = linalg.fill ins(%c0_i32_0 : i32) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%8 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%7 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.return %8 : tensor<2048x2048xi32>
}
%5 = hal.tensor.export %4 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %5 : !hal.buffer_view
}
// -----// IR Dump After FormDispatchWorkgroups (iree-flow-form-dispatch-workgroups) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = flow.dispatch.workgroups(%0, %1) : (tensor<2048x2048xi32>, tensor<2048x2048xi32>) -> tensor<2048x2048xi32> =
(%arg2: !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>, %arg3: !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>, %arg4: !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>) {
%c0_i32 = arith.constant 0 : i32
%4 = flow.dispatch.tensor.load %arg2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = flow.dispatch.tensor.load %arg3, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%6 = tensor.empty() : tensor<2048x2048xi32>
%7 = linalg.fill ins(%c0_i32 : i32) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%8 = linalg.matmul ins(%4, %5 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%7 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %8, %arg4, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
flow.return
} count() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
flow.return %x, %y, %z : index, index, index
}
%3 = hal.tensor.export %2 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %3 : !hal.buffer_view
}
// -----// IR Dump Before CaptureDispatchDynamicDims (iree-flow-capture-dispatch-dynamic-dims) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = flow.dispatch.workgroups(%0, %1) : (tensor<2048x2048xi32>, tensor<2048x2048xi32>) -> tensor<2048x2048xi32> =
(%arg2: !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>, %arg3: !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>, %arg4: !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>) {
%c0_i32 = arith.constant 0 : i32
%4 = flow.dispatch.tensor.load %arg2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = flow.dispatch.tensor.load %arg3, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%6 = tensor.empty() : tensor<2048x2048xi32>
%7 = linalg.fill ins(%c0_i32 : i32) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%8 = linalg.matmul ins(%4, %5 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%7 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %8, %arg4, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
flow.return
} count() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
flow.return %x, %y, %z : index, index, index
}
%3 = hal.tensor.export %2 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %3 : !hal.buffer_view
}
// -----// IR Dump After CaptureDispatchDynamicDims (iree-flow-capture-dispatch-dynamic-dims) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = flow.dispatch.workgroups(%0, %1) : (tensor<2048x2048xi32>, tensor<2048x2048xi32>) -> tensor<2048x2048xi32> =
(%arg2: !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>, %arg3: !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>, %arg4: !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>) {
%c0_i32 = arith.constant 0 : i32
%4 = flow.dispatch.tensor.load %arg2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = flow.dispatch.tensor.load %arg3, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%6 = tensor.empty() : tensor<2048x2048xi32>
%7 = linalg.fill ins(%c0_i32 : i32) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%8 = linalg.matmul ins(%4, %5 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%7 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %8, %arg4, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
flow.return
} count() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
flow.return %x, %y, %z : index, index, index
}
%3 = hal.tensor.export %2 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %3 : !hal.buffer_view
}
// -----// IR Dump Before Canonicalizer (canonicalize) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = flow.dispatch.workgroups(%0, %1) : (tensor<2048x2048xi32>, tensor<2048x2048xi32>) -> tensor<2048x2048xi32> =
(%arg2: !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>, %arg3: !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>, %arg4: !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>) {
%c0_i32 = arith.constant 0 : i32
%4 = flow.dispatch.tensor.load %arg2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = flow.dispatch.tensor.load %arg3, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%6 = tensor.empty() : tensor<2048x2048xi32>
%7 = linalg.fill ins(%c0_i32 : i32) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%8 = linalg.matmul ins(%4, %5 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%7 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %8, %arg4, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
flow.return
} count() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
flow.return %x, %y, %z : index, index, index
}
%3 = hal.tensor.export %2 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %3 : !hal.buffer_view
}
// -----// IR Dump After Canonicalizer (canonicalize) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = flow.dispatch.workgroups(%0, %1) : (tensor<2048x2048xi32>, tensor<2048x2048xi32>) -> tensor<2048x2048xi32> =
(%arg2: !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>, %arg3: !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>, %arg4: !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>) {
%c0_i32 = arith.constant 0 : i32
%4 = flow.dispatch.tensor.load %arg2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = flow.dispatch.tensor.load %arg3, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%6 = tensor.empty() : tensor<2048x2048xi32>
%7 = linalg.fill ins(%c0_i32 : i32) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%8 = linalg.matmul ins(%4, %5 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%7 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %8, %arg4, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
flow.return
} count() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
flow.return %x, %y, %z : index, index, index
}
%3 = hal.tensor.export %2 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %3 : !hal.buffer_view
}
// -----// IR Dump Before CSE (cse) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = flow.dispatch.workgroups(%0, %1) : (tensor<2048x2048xi32>, tensor<2048x2048xi32>) -> tensor<2048x2048xi32> =
(%arg2: !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>, %arg3: !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>, %arg4: !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>) {
%c0_i32 = arith.constant 0 : i32
%4 = flow.dispatch.tensor.load %arg2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = flow.dispatch.tensor.load %arg3, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%6 = tensor.empty() : tensor<2048x2048xi32>
%7 = linalg.fill ins(%c0_i32 : i32) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%8 = linalg.matmul ins(%4, %5 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%7 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %8, %arg4, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
flow.return
} count() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
flow.return %x, %y, %z : index, index, index
}
%3 = hal.tensor.export %2 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %3 : !hal.buffer_view
}
// -----// IR Dump After CSE (cse) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = flow.dispatch.workgroups(%0, %1) : (tensor<2048x2048xi32>, tensor<2048x2048xi32>) -> tensor<2048x2048xi32> =
(%arg2: !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>, %arg3: !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>, %arg4: !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>) {
%c0_i32 = arith.constant 0 : i32
%4 = flow.dispatch.tensor.load %arg2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = flow.dispatch.tensor.load %arg3, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%6 = tensor.empty() : tensor<2048x2048xi32>
%7 = linalg.fill ins(%c0_i32 : i32) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%8 = linalg.matmul ins(%4, %5 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%7 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %8, %arg4, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
flow.return
} count() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
flow.return %x, %y, %z : index, index, index
}
%3 = hal.tensor.export %2 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %3 : !hal.buffer_view
}
// -----// IR Dump Before InitializeEmptyTensors (iree-flow-initialize-empty-tensors) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = flow.dispatch.workgroups(%0, %1) : (tensor<2048x2048xi32>, tensor<2048x2048xi32>) -> tensor<2048x2048xi32> =
(%arg2: !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>, %arg3: !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>, %arg4: !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>) {
%c0_i32 = arith.constant 0 : i32
%4 = flow.dispatch.tensor.load %arg2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = flow.dispatch.tensor.load %arg3, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%6 = tensor.empty() : tensor<2048x2048xi32>
%7 = linalg.fill ins(%c0_i32 : i32) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%8 = linalg.matmul ins(%4, %5 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%7 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %8, %arg4, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
flow.return
} count() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
flow.return %x, %y, %z : index, index, index
}
%3 = hal.tensor.export %2 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %3 : !hal.buffer_view
}
// -----// IR Dump After InitializeEmptyTensors (iree-flow-initialize-empty-tensors) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = flow.dispatch.workgroups(%0, %1) : (tensor<2048x2048xi32>, tensor<2048x2048xi32>) -> tensor<2048x2048xi32> =
(%arg2: !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>, %arg3: !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>, %arg4: !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>) {
%c0_i32 = arith.constant 0 : i32
%4 = flow.dispatch.tensor.load %arg2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = flow.dispatch.tensor.load %arg3, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%6 = tensor.empty() : tensor<2048x2048xi32>
%7 = linalg.fill ins(%c0_i32 : i32) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%8 = linalg.matmul ins(%4, %5 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%7 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %8, %arg4, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
flow.return
} count() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
flow.return %x, %y, %z : index, index, index
}
%3 = hal.tensor.export %2 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %3 : !hal.buffer_view
}
// -----// IR Dump Before OutlineDispatchExterns (iree-flow-outline-dispatch-externs) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = flow.dispatch.workgroups(%0, %1) : (tensor<2048x2048xi32>, tensor<2048x2048xi32>) -> tensor<2048x2048xi32> =
(%arg2: !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>, %arg3: !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>, %arg4: !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>) {
%c0_i32 = arith.constant 0 : i32
%4 = flow.dispatch.tensor.load %arg2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = flow.dispatch.tensor.load %arg3, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%6 = tensor.empty() : tensor<2048x2048xi32>
%7 = linalg.fill ins(%c0_i32 : i32) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%8 = linalg.matmul ins(%4, %5 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%7 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %8, %arg4, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
flow.return
} count() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
flow.return %x, %y, %z : index, index, index
}
%3 = hal.tensor.export %2 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %3 : !hal.buffer_view
}
}
// -----// IR Dump After OutlineDispatchExterns (iree-flow-outline-dispatch-externs) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = flow.dispatch.workgroups(%0, %1) : (tensor<2048x2048xi32>, tensor<2048x2048xi32>) -> tensor<2048x2048xi32> =
(%arg2: !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>, %arg3: !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>, %arg4: !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>) {
%c0_i32 = arith.constant 0 : i32
%4 = flow.dispatch.tensor.load %arg2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = flow.dispatch.tensor.load %arg3, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%6 = tensor.empty() : tensor<2048x2048xi32>
%7 = linalg.fill ins(%c0_i32 : i32) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%8 = linalg.matmul ins(%4, %5 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%7 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %8, %arg4, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
flow.return
} count() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
flow.return %x, %y, %z : index, index, index
}
%3 = hal.tensor.export %2 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %3 : !hal.buffer_view
}
}
// -----// IR Dump Before OutlineDispatchRegions (iree-flow-outline-dispatch-regions) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = flow.dispatch.workgroups(%0, %1) : (tensor<2048x2048xi32>, tensor<2048x2048xi32>) -> tensor<2048x2048xi32> =
(%arg2: !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>, %arg3: !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>, %arg4: !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>) {
%c0_i32 = arith.constant 0 : i32
%4 = flow.dispatch.tensor.load %arg2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = flow.dispatch.tensor.load %arg3, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%6 = tensor.empty() : tensor<2048x2048xi32>
%7 = linalg.fill ins(%c0_i32 : i32) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%8 = linalg.matmul ins(%4, %5 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%7 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %8, %arg4, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
flow.return
} count() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
flow.return %x, %y, %z : index, index, index
}
%3 = hal.tensor.export %2 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %3 : !hal.buffer_view
}
}
// -----// IR Dump After OutlineDispatchRegions (iree-flow-outline-dispatch-regions) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
flow.executable private @matmul_large_dispatch_0 {
flow.executable.export public @matmul_large_dispatch_0 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
flow.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0(%arg0: !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>, %arg1: !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>, %arg2: !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>) {
%c0_i32 = arith.constant 0 : i32
%0 = flow.dispatch.tensor.load %arg0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%1 = flow.dispatch.tensor.load %arg1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %4, %arg2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = flow.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0(%0, %1) : (tensor<2048x2048xi32>, tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%3 = hal.tensor.export %2 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %3 : !hal.buffer_view
}
}
// -----// IR Dump Before AnnotateDispatches (iree-flow-annotate-dispatches) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
flow.executable private @matmul_large_dispatch_0 {
flow.executable.export public @matmul_large_dispatch_0 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
flow.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0(%arg0: !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>, %arg1: !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>, %arg2: !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>) {
%c0_i32 = arith.constant 0 : i32
%0 = flow.dispatch.tensor.load %arg0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%1 = flow.dispatch.tensor.load %arg1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %4, %arg2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = flow.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0(%0, %1) : (tensor<2048x2048xi32>, tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%3 = hal.tensor.export %2 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %3 : !hal.buffer_view
}
}
// -----// IR Dump After AnnotateDispatches (iree-flow-annotate-dispatches) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
flow.executable private @matmul_large_dispatch_0 {
flow.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
flow.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>, %arg1: !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>, %arg2: !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>) {
%c0_i32 = arith.constant 0 : i32
%0 = flow.dispatch.tensor.load %arg0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%1 = flow.dispatch.tensor.load %arg1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %4, %arg2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = flow.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%0, %1) : (tensor<2048x2048xi32>, tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%3 = hal.tensor.export %2 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %3 : !hal.buffer_view
}
}
// -----// IR Dump Before StripDebugOps (iree-util-strip-debug-ops) //----- //
flow.executable private @matmul_large_dispatch_0 {
flow.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
flow.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>, %arg1: !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>, %arg2: !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>) {
%c0_i32 = arith.constant 0 : i32
%0 = flow.dispatch.tensor.load %arg0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%1 = flow.dispatch.tensor.load %arg1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %4, %arg2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
// -----// IR Dump After StripDebugOps (iree-util-strip-debug-ops) //----- //
flow.executable private @matmul_large_dispatch_0 {
flow.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
flow.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>, %arg1: !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>, %arg2: !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>) {
%c0_i32 = arith.constant 0 : i32
%0 = flow.dispatch.tensor.load %arg0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%1 = flow.dispatch.tensor.load %arg1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %4, %arg2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
// -----// IR Dump Before Canonicalizer (canonicalize) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = flow.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%0, %1) : (tensor<2048x2048xi32>, tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%3 = hal.tensor.export %2 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %3 : !hal.buffer_view
}
// -----// IR Dump After Canonicalizer (canonicalize) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = flow.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%0, %1) : (tensor<2048x2048xi32>, tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%3 = hal.tensor.export %2 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %3 : !hal.buffer_view
}
// -----// IR Dump Before DeduplicateExecutables (iree-flow-deduplicate-executables) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
flow.executable private @matmul_large_dispatch_0 {
flow.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
flow.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>, %arg1: !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>, %arg2: !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>) {
%c0_i32 = arith.constant 0 : i32
%0 = flow.dispatch.tensor.load %arg0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%1 = flow.dispatch.tensor.load %arg1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %4, %arg2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = flow.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%0, %1) : (tensor<2048x2048xi32>, tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%3 = hal.tensor.export %2 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %3 : !hal.buffer_view
}
}
// -----// IR Dump After DeduplicateExecutables (iree-flow-deduplicate-executables) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
flow.executable private @matmul_large_dispatch_0 {
flow.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
flow.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>, %arg1: !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>, %arg2: !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>) {
%c0_i32 = arith.constant 0 : i32
%0 = flow.dispatch.tensor.load %arg0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%1 = flow.dispatch.tensor.load %arg1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %4, %arg2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = flow.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%0, %1) : (tensor<2048x2048xi32>, tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%3 = hal.tensor.export %2 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %3 : !hal.buffer_view
}
}
// -----// IR Dump Before Canonicalizer (canonicalize) //----- //
flow.executable private @matmul_large_dispatch_0 {
flow.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
flow.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>, %arg1: !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>, %arg2: !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>) {
%c0_i32 = arith.constant 0 : i32
%0 = flow.dispatch.tensor.load %arg0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%1 = flow.dispatch.tensor.load %arg1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %4, %arg2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
// -----// IR Dump After Canonicalizer (canonicalize) //----- //
flow.executable private @matmul_large_dispatch_0 {
flow.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
flow.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>, %arg1: !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>, %arg2: !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>) {
%c0_i32 = arith.constant 0 : i32
%0 = flow.dispatch.tensor.load %arg0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%1 = flow.dispatch.tensor.load %arg1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %4, %arg2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
// -----// IR Dump Before CSE (cse) //----- //
flow.executable private @matmul_large_dispatch_0 {
flow.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
flow.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>, %arg1: !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>, %arg2: !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>) {
%c0_i32 = arith.constant 0 : i32
%0 = flow.dispatch.tensor.load %arg0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%1 = flow.dispatch.tensor.load %arg1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %4, %arg2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
// -----// IR Dump After CSE (cse) //----- //
flow.executable private @matmul_large_dispatch_0 {
flow.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
flow.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>, %arg1: !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>, %arg2: !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>) {
%c0_i32 = arith.constant 0 : i32
%0 = flow.dispatch.tensor.load %arg0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%1 = flow.dispatch.tensor.load %arg1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %4, %arg2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
// -----// IR Dump Before CleanupTensorShapes (iree-flow-cleanup-tensor-shapes) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = flow.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%0, %1) : (tensor<2048x2048xi32>, tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%3 = hal.tensor.export %2 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %3 : !hal.buffer_view
}
// -----// IR Dump After CleanupTensorShapes (iree-flow-cleanup-tensor-shapes) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = flow.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%0, %1) : (tensor<2048x2048xi32>, tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%3 = hal.tensor.export %2 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %3 : !hal.buffer_view
}
// -----// IR Dump Before Canonicalizer (canonicalize) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = flow.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%0, %1) : (tensor<2048x2048xi32>, tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%3 = hal.tensor.export %2 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %3 : !hal.buffer_view
}
// -----// IR Dump After Canonicalizer (canonicalize) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = flow.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%0, %1) : (tensor<2048x2048xi32>, tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%3 = hal.tensor.export %2 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %3 : !hal.buffer_view
}
// -----// IR Dump Before CSE (cse) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = flow.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%0, %1) : (tensor<2048x2048xi32>, tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%3 = hal.tensor.export %2 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %3 : !hal.buffer_view
}
// -----// IR Dump After CSE (cse) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = flow.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%0, %1) : (tensor<2048x2048xi32>, tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%3 = hal.tensor.export %2 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %3 : !hal.buffer_view
}
// -----// IR Dump Before SymbolDCE (symbol-dce) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
flow.executable private @matmul_large_dispatch_0 {
flow.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
flow.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>, %arg1: !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>, %arg2: !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>) {
%c0_i32 = arith.constant 0 : i32
%0 = flow.dispatch.tensor.load %arg0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%1 = flow.dispatch.tensor.load %arg1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %4, %arg2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = flow.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%0, %1) : (tensor<2048x2048xi32>, tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%3 = hal.tensor.export %2 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %3 : !hal.buffer_view
}
}
// -----// IR Dump After SymbolDCE (symbol-dce) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
flow.executable private @matmul_large_dispatch_0 {
flow.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
flow.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>, %arg1: !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>, %arg2: !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>) {
%c0_i32 = arith.constant 0 : i32
%0 = flow.dispatch.tensor.load %arg0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%1 = flow.dispatch.tensor.load %arg1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %4, %arg2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = flow.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%0, %1) : (tensor<2048x2048xi32>, tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%3 = hal.tensor.export %2 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %3 : !hal.buffer_view
}
}
// -----// IR Dump Before VerifyInputPass (iree-stream-verify-input) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
flow.executable private @matmul_large_dispatch_0 {
flow.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
flow.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>, %arg1: !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>, %arg2: !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>) {
%c0_i32 = arith.constant 0 : i32
%0 = flow.dispatch.tensor.load %arg0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%1 = flow.dispatch.tensor.load %arg1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %4, %arg2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = flow.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%0, %1) : (tensor<2048x2048xi32>, tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%3 = hal.tensor.export %2 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %3 : !hal.buffer_view
}
}
// -----// IR Dump After VerifyInputPass (iree-stream-verify-input) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
flow.executable private @matmul_large_dispatch_0 {
flow.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
flow.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>, %arg1: !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>, %arg2: !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>) {
%c0_i32 = arith.constant 0 : i32
%0 = flow.dispatch.tensor.load %arg0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%1 = flow.dispatch.tensor.load %arg1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %4, %arg2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = flow.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%0, %1) : (tensor<2048x2048xi32>, tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%3 = hal.tensor.export %2 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %3 : !hal.buffer_view
}
}
// -----// IR Dump Before Canonicalizer (canonicalize) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = flow.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%0, %1) : (tensor<2048x2048xi32>, tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%3 = hal.tensor.export %2 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %3 : !hal.buffer_view
}
// -----// IR Dump After Canonicalizer (canonicalize) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = flow.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%0, %1) : (tensor<2048x2048xi32>, tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%3 = hal.tensor.export %2 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %3 : !hal.buffer_view
}
// -----// IR Dump Before CSE (cse) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = flow.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%0, %1) : (tensor<2048x2048xi32>, tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%3 = hal.tensor.export %2 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %3 : !hal.buffer_view
}
// -----// IR Dump After CSE (cse) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = flow.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%0, %1) : (tensor<2048x2048xi32>, tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%3 = hal.tensor.export %2 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %3 : !hal.buffer_view
}
// -----// IR Dump Before SimplifyGlobalAccesses (iree-util-simplify-global-accesses) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = flow.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%0, %1) : (tensor<2048x2048xi32>, tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%3 = hal.tensor.export %2 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %3 : !hal.buffer_view
}
// -----// IR Dump After SimplifyGlobalAccesses (iree-util-simplify-global-accesses) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = flow.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%0, %1) : (tensor<2048x2048xi32>, tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%3 = hal.tensor.export %2 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %3 : !hal.buffer_view
}
// -----// IR Dump Before ApplyPatterns (iree-util-apply-patterns) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
flow.executable private @matmul_large_dispatch_0 {
flow.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
flow.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>, %arg1: !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>, %arg2: !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>) {
%c0_i32 = arith.constant 0 : i32
%0 = flow.dispatch.tensor.load %arg0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%1 = flow.dispatch.tensor.load %arg1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %4, %arg2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = flow.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%0, %1) : (tensor<2048x2048xi32>, tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%3 = hal.tensor.export %2 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %3 : !hal.buffer_view
}
}
// -----// IR Dump After ApplyPatterns (iree-util-apply-patterns) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
flow.executable private @matmul_large_dispatch_0 {
flow.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
flow.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>, %arg1: !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>, %arg2: !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>) {
%c0_i32 = arith.constant 0 : i32
%0 = flow.dispatch.tensor.load %arg0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%1 = flow.dispatch.tensor.load %arg1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %4, %arg2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = flow.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%0, %1) : (tensor<2048x2048xi32>, tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%3 = hal.tensor.export %2 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %3 : !hal.buffer_view
}
}
// -----// IR Dump Before FoldGlobals (iree-util-fold-globals) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
flow.executable private @matmul_large_dispatch_0 {
flow.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
flow.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>, %arg1: !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>, %arg2: !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>) {
%c0_i32 = arith.constant 0 : i32
%0 = flow.dispatch.tensor.load %arg0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%1 = flow.dispatch.tensor.load %arg1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %4, %arg2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = flow.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%0, %1) : (tensor<2048x2048xi32>, tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%3 = hal.tensor.export %2 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %3 : !hal.buffer_view
}
}
// -----// IR Dump After FoldGlobals (iree-util-fold-globals) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
flow.executable private @matmul_large_dispatch_0 {
flow.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
flow.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>, %arg1: !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>, %arg2: !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>) {
%c0_i32 = arith.constant 0 : i32
%0 = flow.dispatch.tensor.load %arg0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%1 = flow.dispatch.tensor.load %arg1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %4, %arg2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = flow.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%0, %1) : (tensor<2048x2048xi32>, tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%3 = hal.tensor.export %2 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %3 : !hal.buffer_view
}
}
// -----// IR Dump Before FuseGlobals (iree-util-fuse-globals) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
flow.executable private @matmul_large_dispatch_0 {
flow.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
flow.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>, %arg1: !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>, %arg2: !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>) {
%c0_i32 = arith.constant 0 : i32
%0 = flow.dispatch.tensor.load %arg0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%1 = flow.dispatch.tensor.load %arg1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %4, %arg2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = flow.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%0, %1) : (tensor<2048x2048xi32>, tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%3 = hal.tensor.export %2 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %3 : !hal.buffer_view
}
}
// -----// IR Dump After FuseGlobals (iree-util-fuse-globals) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
flow.executable private @matmul_large_dispatch_0 {
flow.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
flow.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>, %arg1: !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>, %arg2: !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>) {
%c0_i32 = arith.constant 0 : i32
%0 = flow.dispatch.tensor.load %arg0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%1 = flow.dispatch.tensor.load %arg1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %4, %arg2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = flow.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%0, %1) : (tensor<2048x2048xi32>, tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%3 = hal.tensor.export %2 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %3 : !hal.buffer_view
}
}
// -----// IR Dump Before IPO (iree-util-ipo) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
flow.executable private @matmul_large_dispatch_0 {
flow.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
flow.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>, %arg1: !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>, %arg2: !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>) {
%c0_i32 = arith.constant 0 : i32
%0 = flow.dispatch.tensor.load %arg0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%1 = flow.dispatch.tensor.load %arg1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %4, %arg2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = flow.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%0, %1) : (tensor<2048x2048xi32>, tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%3 = hal.tensor.export %2 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %3 : !hal.buffer_view
}
}
// -----// IR Dump After IPO (iree-util-ipo) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
flow.executable private @matmul_large_dispatch_0 {
flow.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
flow.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>, %arg1: !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>, %arg2: !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>) {
%c0_i32 = arith.constant 0 : i32
%0 = flow.dispatch.tensor.load %arg0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%1 = flow.dispatch.tensor.load %arg1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %4, %arg2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = flow.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%0, %1) : (tensor<2048x2048xi32>, tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%3 = hal.tensor.export %2 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %3 : !hal.buffer_view
}
}
// -----// IR Dump Before OutlineConstants (iree-util-outline-constants) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
flow.executable private @matmul_large_dispatch_0 {
flow.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
flow.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>, %arg1: !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>, %arg2: !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>) {
%c0_i32 = arith.constant 0 : i32
%0 = flow.dispatch.tensor.load %arg0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%1 = flow.dispatch.tensor.load %arg1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %4, %arg2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = flow.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%0, %1) : (tensor<2048x2048xi32>, tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%3 = hal.tensor.export %2 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %3 : !hal.buffer_view
}
}
// -----// IR Dump After OutlineConstants (iree-util-outline-constants) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
flow.executable private @matmul_large_dispatch_0 {
flow.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
flow.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>, %arg1: !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>, %arg2: !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>) {
%c0_i32 = arith.constant 0 : i32
%0 = flow.dispatch.tensor.load %arg0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%1 = flow.dispatch.tensor.load %arg1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %4, %arg2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = flow.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%0, %1) : (tensor<2048x2048xi32>, tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%3 = hal.tensor.export %2 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %3 : !hal.buffer_view
}
}
// -----// IR Dump Before Canonicalizer (canonicalize) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = flow.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%0, %1) : (tensor<2048x2048xi32>, tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%3 = hal.tensor.export %2 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %3 : !hal.buffer_view
}
// -----// IR Dump After Canonicalizer (canonicalize) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = flow.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%0, %1) : (tensor<2048x2048xi32>, tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%3 = hal.tensor.export %2 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %3 : !hal.buffer_view
}
// -----// IR Dump Before CSE (cse) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = flow.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%0, %1) : (tensor<2048x2048xi32>, tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%3 = hal.tensor.export %2 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %3 : !hal.buffer_view
}
// -----// IR Dump After CSE (cse) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = flow.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%0, %1) : (tensor<2048x2048xi32>, tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%3 = hal.tensor.export %2 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %3 : !hal.buffer_view
}
// -----// IR Dump Before SimplifyGlobalAccesses (iree-util-simplify-global-accesses) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = flow.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%0, %1) : (tensor<2048x2048xi32>, tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%3 = hal.tensor.export %2 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %3 : !hal.buffer_view
}
// -----// IR Dump After SimplifyGlobalAccesses (iree-util-simplify-global-accesses) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = flow.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%0, %1) : (tensor<2048x2048xi32>, tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%3 = hal.tensor.export %2 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %3 : !hal.buffer_view
}
// -----// IR Dump Before ApplyPatterns (iree-util-apply-patterns) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
flow.executable private @matmul_large_dispatch_0 {
flow.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
flow.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>, %arg1: !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>, %arg2: !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>) {
%c0_i32 = arith.constant 0 : i32
%0 = flow.dispatch.tensor.load %arg0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%1 = flow.dispatch.tensor.load %arg1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %4, %arg2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = flow.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%0, %1) : (tensor<2048x2048xi32>, tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%3 = hal.tensor.export %2 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %3 : !hal.buffer_view
}
}
// -----// IR Dump After ApplyPatterns (iree-util-apply-patterns) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
flow.executable private @matmul_large_dispatch_0 {
flow.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
flow.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>, %arg1: !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>, %arg2: !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>) {
%c0_i32 = arith.constant 0 : i32
%0 = flow.dispatch.tensor.load %arg0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%1 = flow.dispatch.tensor.load %arg1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %4, %arg2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = flow.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%0, %1) : (tensor<2048x2048xi32>, tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%3 = hal.tensor.export %2 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %3 : !hal.buffer_view
}
}
// -----// IR Dump Before FoldGlobals (iree-util-fold-globals) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
flow.executable private @matmul_large_dispatch_0 {
flow.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
flow.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>, %arg1: !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>, %arg2: !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>) {
%c0_i32 = arith.constant 0 : i32
%0 = flow.dispatch.tensor.load %arg0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%1 = flow.dispatch.tensor.load %arg1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %4, %arg2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = flow.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%0, %1) : (tensor<2048x2048xi32>, tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%3 = hal.tensor.export %2 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %3 : !hal.buffer_view
}
}
// -----// IR Dump After FoldGlobals (iree-util-fold-globals) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
flow.executable private @matmul_large_dispatch_0 {
flow.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
flow.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>, %arg1: !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>, %arg2: !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>) {
%c0_i32 = arith.constant 0 : i32
%0 = flow.dispatch.tensor.load %arg0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%1 = flow.dispatch.tensor.load %arg1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %4, %arg2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = flow.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%0, %1) : (tensor<2048x2048xi32>, tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%3 = hal.tensor.export %2 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %3 : !hal.buffer_view
}
}
// -----// IR Dump Before FuseGlobals (iree-util-fuse-globals) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
flow.executable private @matmul_large_dispatch_0 {
flow.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
flow.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>, %arg1: !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>, %arg2: !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>) {
%c0_i32 = arith.constant 0 : i32
%0 = flow.dispatch.tensor.load %arg0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%1 = flow.dispatch.tensor.load %arg1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %4, %arg2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = flow.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%0, %1) : (tensor<2048x2048xi32>, tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%3 = hal.tensor.export %2 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %3 : !hal.buffer_view
}
}
// -----// IR Dump After FuseGlobals (iree-util-fuse-globals) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
flow.executable private @matmul_large_dispatch_0 {
flow.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
flow.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>, %arg1: !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>, %arg2: !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>) {
%c0_i32 = arith.constant 0 : i32
%0 = flow.dispatch.tensor.load %arg0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%1 = flow.dispatch.tensor.load %arg1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %4, %arg2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = flow.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%0, %1) : (tensor<2048x2048xi32>, tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%3 = hal.tensor.export %2 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %3 : !hal.buffer_view
}
}
// -----// IR Dump Before IPO (iree-util-ipo) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
flow.executable private @matmul_large_dispatch_0 {
flow.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
flow.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>, %arg1: !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>, %arg2: !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>) {
%c0_i32 = arith.constant 0 : i32
%0 = flow.dispatch.tensor.load %arg0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%1 = flow.dispatch.tensor.load %arg1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %4, %arg2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = flow.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%0, %1) : (tensor<2048x2048xi32>, tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%3 = hal.tensor.export %2 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %3 : !hal.buffer_view
}
}
// -----// IR Dump After IPO (iree-util-ipo) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
flow.executable private @matmul_large_dispatch_0 {
flow.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
flow.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>, %arg1: !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>, %arg2: !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>) {
%c0_i32 = arith.constant 0 : i32
%0 = flow.dispatch.tensor.load %arg0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%1 = flow.dispatch.tensor.load %arg1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %4, %arg2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = flow.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%0, %1) : (tensor<2048x2048xi32>, tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%3 = hal.tensor.export %2 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %3 : !hal.buffer_view
}
}
// -----// IR Dump Before ConvertToStreamPass (iree-stream-conversion) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
flow.executable private @matmul_large_dispatch_0 {
flow.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
flow.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>, %arg1: !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>, %arg2: !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>) {
%c0_i32 = arith.constant 0 : i32
%0 = flow.dispatch.tensor.load %arg0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%1 = flow.dispatch.tensor.load %arg1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%2 = tensor.empty() : tensor<2048x2048xi32>
%3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%4 = linalg.matmul ins(%0, %1 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%3 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %4, %arg2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<2048x2048xi32>
%1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<2048x2048xi32>
%2 = flow.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%0, %1) : (tensor<2048x2048xi32>, tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%3 = hal.tensor.export %2 "output0" : tensor<2048x2048xi32> -> !hal.buffer_view
return %3 : !hal.buffer_view
}
}
// -----// IR Dump After ConvertToStreamPass (iree-stream-conversion) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%c0_i32 = arith.constant 0 : i32
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
%c2048 = arith.constant 2048 : index
%c2048_0 = arith.constant 2048 : index
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048_0]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.sizeof tensor<2048x2048xi32> : index
%1 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%0}
%2 = stream.async.transfer %1 : !stream.resource<external>{%0} -> !stream.resource<*>{%0}
%element_type_i32_1 = hal.element_type<i32> : i32
%dense_row_major_2 = hal.encoding_type<dense_row_major> : i32
%c2048_3 = arith.constant 2048 : index
%c2048_4 = arith.constant 2048 : index
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048_3, %c2048_4]) type(%element_type_i32_1) encoding(%dense_row_major_2)
%3 = stream.tensor.sizeof tensor<2048x2048xi32> : index
%4 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%3}
%5 = stream.async.transfer %4 : !stream.resource<external>{%3} -> !stream.resource<*>{%3}
%c0 = arith.constant 0 : index
%6 = stream.tensor.sizeof tensor<2048x2048xi32> : index
%7 = stream.async.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%2[%c0 to %0 for %0], %5[%c0 to %3 for %3]) : (!stream.resource<*>{%0}, !stream.resource<*>{%3}) -> !stream.resource<*>{%6}
%8 = stream.async.transfer %7 : !stream.resource<*>{%6} -> !stream.resource<external>{%6}
%9 = stream.tensor.export %8 : tensor<2048x2048xi32> in !stream.resource<external>{%6} -> !hal.buffer_view
return %9 : !hal.buffer_view
}
}
// -----// IR Dump Before VerifyLoweringToTensorsPass (iree-stream-verify-lowering-to-tensors) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%c0_i32 = arith.constant 0 : i32
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
%c2048 = arith.constant 2048 : index
%c2048_0 = arith.constant 2048 : index
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048_0]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.sizeof tensor<2048x2048xi32> : index
%1 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%0}
%2 = stream.async.transfer %1 : !stream.resource<external>{%0} -> !stream.resource<*>{%0}
%element_type_i32_1 = hal.element_type<i32> : i32
%dense_row_major_2 = hal.encoding_type<dense_row_major> : i32
%c2048_3 = arith.constant 2048 : index
%c2048_4 = arith.constant 2048 : index
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048_3, %c2048_4]) type(%element_type_i32_1) encoding(%dense_row_major_2)
%3 = stream.tensor.sizeof tensor<2048x2048xi32> : index
%4 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%3}
%5 = stream.async.transfer %4 : !stream.resource<external>{%3} -> !stream.resource<*>{%3}
%c0 = arith.constant 0 : index
%6 = stream.tensor.sizeof tensor<2048x2048xi32> : index
%7 = stream.async.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%2[%c0 to %0 for %0], %5[%c0 to %3 for %3]) : (!stream.resource<*>{%0}, !stream.resource<*>{%3}) -> !stream.resource<*>{%6}
%8 = stream.async.transfer %7 : !stream.resource<*>{%6} -> !stream.resource<external>{%6}
%9 = stream.tensor.export %8 : tensor<2048x2048xi32> in !stream.resource<external>{%6} -> !hal.buffer_view
return %9 : !hal.buffer_view
}
}
// -----// IR Dump After VerifyLoweringToTensorsPass (iree-stream-verify-lowering-to-tensors) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%c0_i32 = arith.constant 0 : i32
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
%c2048 = arith.constant 2048 : index
%c2048_0 = arith.constant 2048 : index
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048_0]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.sizeof tensor<2048x2048xi32> : index
%1 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%0}
%2 = stream.async.transfer %1 : !stream.resource<external>{%0} -> !stream.resource<*>{%0}
%element_type_i32_1 = hal.element_type<i32> : i32
%dense_row_major_2 = hal.encoding_type<dense_row_major> : i32
%c2048_3 = arith.constant 2048 : index
%c2048_4 = arith.constant 2048 : index
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048_3, %c2048_4]) type(%element_type_i32_1) encoding(%dense_row_major_2)
%3 = stream.tensor.sizeof tensor<2048x2048xi32> : index
%4 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%3}
%5 = stream.async.transfer %4 : !stream.resource<external>{%3} -> !stream.resource<*>{%3}
%c0 = arith.constant 0 : index
%6 = stream.tensor.sizeof tensor<2048x2048xi32> : index
%7 = stream.async.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%2[%c0 to %0 for %0], %5[%c0 to %3 for %3]) : (!stream.resource<*>{%0}, !stream.resource<*>{%3}) -> !stream.resource<*>{%6}
%8 = stream.async.transfer %7 : !stream.resource<*>{%6} -> !stream.resource<external>{%6}
%9 = stream.tensor.export %8 : tensor<2048x2048xi32> in !stream.resource<external>{%6} -> !hal.buffer_view
return %9 : !hal.buffer_view
}
}
// -----// IR Dump Before Canonicalizer (canonicalize) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
%c2048 = arith.constant 2048 : index
%c2048_0 = arith.constant 2048 : index
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048_0]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.sizeof tensor<2048x2048xi32> : index
%1 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%0}
%2 = stream.async.transfer %1 : !stream.resource<external>{%0} -> !stream.resource<*>{%0}
%element_type_i32_1 = hal.element_type<i32> : i32
%dense_row_major_2 = hal.encoding_type<dense_row_major> : i32
%c2048_3 = arith.constant 2048 : index
%c2048_4 = arith.constant 2048 : index
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048_3, %c2048_4]) type(%element_type_i32_1) encoding(%dense_row_major_2)
%3 = stream.tensor.sizeof tensor<2048x2048xi32> : index
%4 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%3}
%5 = stream.async.transfer %4 : !stream.resource<external>{%3} -> !stream.resource<*>{%3}
%c0 = arith.constant 0 : index
%6 = stream.tensor.sizeof tensor<2048x2048xi32> : index
%7 = stream.async.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%2[%c0 to %0 for %0], %5[%c0 to %3 for %3]) : (!stream.resource<*>{%0}, !stream.resource<*>{%3}) -> !stream.resource<*>{%6}
%8 = stream.async.transfer %7 : !stream.resource<*>{%6} -> !stream.resource<external>{%6}
%9 = stream.tensor.export %8 : tensor<2048x2048xi32> in !stream.resource<external>{%6} -> !hal.buffer_view
return %9 : !hal.buffer_view
}
// -----// IR Dump After Canonicalizer (canonicalize) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.sizeof tensor<2048x2048xi32> : index
%1 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%0}
%2 = stream.async.transfer %1 : !stream.resource<external>{%0} -> !stream.resource<*>{%0}
%element_type_i32_0 = hal.element_type<i32> : i32
%dense_row_major_1 = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32_0) encoding(%dense_row_major_1)
%3 = stream.tensor.sizeof tensor<2048x2048xi32> : index
%4 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%3}
%5 = stream.async.transfer %4 : !stream.resource<external>{%3} -> !stream.resource<*>{%3}
%6 = stream.tensor.sizeof tensor<2048x2048xi32> : index
%7 = stream.async.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%2[%c0 to %0 for %0], %5[%c0 to %3 for %3]) : (!stream.resource<*>{%0}, !stream.resource<*>{%3}) -> !stream.resource<*>{%6}
%8 = stream.async.transfer %7 : !stream.resource<*>{%6} -> !stream.resource<external>{%6}
%9 = stream.tensor.export %8 : tensor<2048x2048xi32> in !stream.resource<external>{%6} -> !hal.buffer_view
return %9 : !hal.buffer_view
}
// -----// IR Dump Before CSE (cse) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.sizeof tensor<2048x2048xi32> : index
%1 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%0}
%2 = stream.async.transfer %1 : !stream.resource<external>{%0} -> !stream.resource<*>{%0}
%element_type_i32_0 = hal.element_type<i32> : i32
%dense_row_major_1 = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32_0) encoding(%dense_row_major_1)
%3 = stream.tensor.sizeof tensor<2048x2048xi32> : index
%4 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%3}
%5 = stream.async.transfer %4 : !stream.resource<external>{%3} -> !stream.resource<*>{%3}
%6 = stream.tensor.sizeof tensor<2048x2048xi32> : index
%7 = stream.async.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%2[%c0 to %0 for %0], %5[%c0 to %3 for %3]) : (!stream.resource<*>{%0}, !stream.resource<*>{%3}) -> !stream.resource<*>{%6}
%8 = stream.async.transfer %7 : !stream.resource<*>{%6} -> !stream.resource<external>{%6}
%9 = stream.tensor.export %8 : tensor<2048x2048xi32> in !stream.resource<external>{%6} -> !hal.buffer_view
return %9 : !hal.buffer_view
}
// -----// IR Dump After CSE (cse) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.sizeof tensor<2048x2048xi32> : index
%1 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%0}
%2 = stream.async.transfer %1 : !stream.resource<external>{%0} -> !stream.resource<*>{%0}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%3 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%0}
%4 = stream.async.transfer %3 : !stream.resource<external>{%0} -> !stream.resource<*>{%0}
%5 = stream.async.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%2[%c0 to %0 for %0], %4[%c0 to %0 for %0]) : (!stream.resource<*>{%0}, !stream.resource<*>{%0}) -> !stream.resource<*>{%0}
%6 = stream.async.transfer %5 : !stream.resource<*>{%0} -> !stream.resource<external>{%0}
%7 = stream.tensor.export %6 : tensor<2048x2048xi32> in !stream.resource<external>{%0} -> !hal.buffer_view
return %7 : !hal.buffer_view
}
// -----// IR Dump Before SimplifyGlobalAccesses (iree-util-simplify-global-accesses) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.sizeof tensor<2048x2048xi32> : index
%1 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%0}
%2 = stream.async.transfer %1 : !stream.resource<external>{%0} -> !stream.resource<*>{%0}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%3 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%0}
%4 = stream.async.transfer %3 : !stream.resource<external>{%0} -> !stream.resource<*>{%0}
%5 = stream.async.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%2[%c0 to %0 for %0], %4[%c0 to %0 for %0]) : (!stream.resource<*>{%0}, !stream.resource<*>{%0}) -> !stream.resource<*>{%0}
%6 = stream.async.transfer %5 : !stream.resource<*>{%0} -> !stream.resource<external>{%0}
%7 = stream.tensor.export %6 : tensor<2048x2048xi32> in !stream.resource<external>{%0} -> !hal.buffer_view
return %7 : !hal.buffer_view
}
// -----// IR Dump After SimplifyGlobalAccesses (iree-util-simplify-global-accesses) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.sizeof tensor<2048x2048xi32> : index
%1 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%0}
%2 = stream.async.transfer %1 : !stream.resource<external>{%0} -> !stream.resource<*>{%0}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%3 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%0}
%4 = stream.async.transfer %3 : !stream.resource<external>{%0} -> !stream.resource<*>{%0}
%5 = stream.async.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%2[%c0 to %0 for %0], %4[%c0 to %0 for %0]) : (!stream.resource<*>{%0}, !stream.resource<*>{%0}) -> !stream.resource<*>{%0}
%6 = stream.async.transfer %5 : !stream.resource<*>{%0} -> !stream.resource<external>{%0}
%7 = stream.tensor.export %6 : tensor<2048x2048xi32> in !stream.resource<external>{%0} -> !hal.buffer_view
return %7 : !hal.buffer_view
}
// -----// IR Dump Before ApplyPatterns (iree-util-apply-patterns) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%c0_i32 = arith.constant 0 : i32
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.sizeof tensor<2048x2048xi32> : index
%1 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%0}
%2 = stream.async.transfer %1 : !stream.resource<external>{%0} -> !stream.resource<*>{%0}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%3 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%0}
%4 = stream.async.transfer %3 : !stream.resource<external>{%0} -> !stream.resource<*>{%0}
%5 = stream.async.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%2[%c0 to %0 for %0], %4[%c0 to %0 for %0]) : (!stream.resource<*>{%0}, !stream.resource<*>{%0}) -> !stream.resource<*>{%0}
%6 = stream.async.transfer %5 : !stream.resource<*>{%0} -> !stream.resource<external>{%0}
%7 = stream.tensor.export %6 : tensor<2048x2048xi32> in !stream.resource<external>{%0} -> !hal.buffer_view
return %7 : !hal.buffer_view
}
}
// -----// IR Dump After ApplyPatterns (iree-util-apply-patterns) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
%c0_i32 = arith.constant 0 : i32
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.sizeof tensor<2048x2048xi32> : index
%1 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%0}
%2 = stream.async.transfer %1 : !stream.resource<external>{%0} -> !stream.resource<*>{%0}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%3 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%0}
%4 = stream.async.transfer %3 : !stream.resource<external>{%0} -> !stream.resource<*>{%0}
%5 = stream.async.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%2[%c0 to %0 for %0], %4[%c0 to %0 for %0]) : (!stream.resource<*>{%0}, !stream.resource<*>{%0}) -> !stream.resource<*>{%0}
%6 = stream.async.transfer %5 : !stream.resource<*>{%0} -> !stream.resource<external>{%0}
%7 = stream.tensor.export %6 : tensor<2048x2048xi32> in !stream.resource<external>{%0} -> !hal.buffer_view
return %7 : !hal.buffer_view
}
}
// -----// IR Dump Before FoldGlobals (iree-util-fold-globals) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
%c0_i32 = arith.constant 0 : i32
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.sizeof tensor<2048x2048xi32> : index
%1 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%0}
%2 = stream.async.transfer %1 : !stream.resource<external>{%0} -> !stream.resource<*>{%0}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%3 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%0}
%4 = stream.async.transfer %3 : !stream.resource<external>{%0} -> !stream.resource<*>{%0}
%5 = stream.async.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%2[%c0 to %0 for %0], %4[%c0 to %0 for %0]) : (!stream.resource<*>{%0}, !stream.resource<*>{%0}) -> !stream.resource<*>{%0}
%6 = stream.async.transfer %5 : !stream.resource<*>{%0} -> !stream.resource<external>{%0}
%7 = stream.tensor.export %6 : tensor<2048x2048xi32> in !stream.resource<external>{%0} -> !hal.buffer_view
return %7 : !hal.buffer_view
}
}
// -----// IR Dump After FoldGlobals (iree-util-fold-globals) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
%c0_i32 = arith.constant 0 : i32
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.sizeof tensor<2048x2048xi32> : index
%1 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%0}
%2 = stream.async.transfer %1 : !stream.resource<external>{%0} -> !stream.resource<*>{%0}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%3 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%0}
%4 = stream.async.transfer %3 : !stream.resource<external>{%0} -> !stream.resource<*>{%0}
%5 = stream.async.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%2[%c0 to %0 for %0], %4[%c0 to %0 for %0]) : (!stream.resource<*>{%0}, !stream.resource<*>{%0}) -> !stream.resource<*>{%0}
%6 = stream.async.transfer %5 : !stream.resource<*>{%0} -> !stream.resource<external>{%0}
%7 = stream.tensor.export %6 : tensor<2048x2048xi32> in !stream.resource<external>{%0} -> !hal.buffer_view
return %7 : !hal.buffer_view
}
}
// -----// IR Dump Before FuseGlobals (iree-util-fuse-globals) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
%c0_i32 = arith.constant 0 : i32
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.sizeof tensor<2048x2048xi32> : index
%1 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%0}
%2 = stream.async.transfer %1 : !stream.resource<external>{%0} -> !stream.resource<*>{%0}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%3 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%0}
%4 = stream.async.transfer %3 : !stream.resource<external>{%0} -> !stream.resource<*>{%0}
%5 = stream.async.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%2[%c0 to %0 for %0], %4[%c0 to %0 for %0]) : (!stream.resource<*>{%0}, !stream.resource<*>{%0}) -> !stream.resource<*>{%0}
%6 = stream.async.transfer %5 : !stream.resource<*>{%0} -> !stream.resource<external>{%0}
%7 = stream.tensor.export %6 : tensor<2048x2048xi32> in !stream.resource<external>{%0} -> !hal.buffer_view
return %7 : !hal.buffer_view
}
}
// -----// IR Dump After FuseGlobals (iree-util-fuse-globals) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
%c0_i32 = arith.constant 0 : i32
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.sizeof tensor<2048x2048xi32> : index
%1 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%0}
%2 = stream.async.transfer %1 : !stream.resource<external>{%0} -> !stream.resource<*>{%0}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%3 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%0}
%4 = stream.async.transfer %3 : !stream.resource<external>{%0} -> !stream.resource<*>{%0}
%5 = stream.async.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%2[%c0 to %0 for %0], %4[%c0 to %0 for %0]) : (!stream.resource<*>{%0}, !stream.resource<*>{%0}) -> !stream.resource<*>{%0}
%6 = stream.async.transfer %5 : !stream.resource<*>{%0} -> !stream.resource<external>{%0}
%7 = stream.tensor.export %6 : tensor<2048x2048xi32> in !stream.resource<external>{%0} -> !hal.buffer_view
return %7 : !hal.buffer_view
}
}
// -----// IR Dump Before IPO (iree-util-ipo) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
%c0_i32 = arith.constant 0 : i32
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.sizeof tensor<2048x2048xi32> : index
%1 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%0}
%2 = stream.async.transfer %1 : !stream.resource<external>{%0} -> !stream.resource<*>{%0}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%3 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%0}
%4 = stream.async.transfer %3 : !stream.resource<external>{%0} -> !stream.resource<*>{%0}
%5 = stream.async.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%2[%c0 to %0 for %0], %4[%c0 to %0 for %0]) : (!stream.resource<*>{%0}, !stream.resource<*>{%0}) -> !stream.resource<*>{%0}
%6 = stream.async.transfer %5 : !stream.resource<*>{%0} -> !stream.resource<external>{%0}
%7 = stream.tensor.export %6 : tensor<2048x2048xi32> in !stream.resource<external>{%0} -> !hal.buffer_view
return %7 : !hal.buffer_view
}
}
// -----// IR Dump After IPO (iree-util-ipo) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
%c0_i32 = arith.constant 0 : i32
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.sizeof tensor<2048x2048xi32> : index
%1 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%0}
%2 = stream.async.transfer %1 : !stream.resource<external>{%0} -> !stream.resource<*>{%0}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%3 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%0}
%4 = stream.async.transfer %3 : !stream.resource<external>{%0} -> !stream.resource<*>{%0}
%5 = stream.async.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%2[%c0 to %0 for %0], %4[%c0 to %0 for %0]) : (!stream.resource<*>{%0}, !stream.resource<*>{%0}) -> !stream.resource<*>{%0}
%6 = stream.async.transfer %5 : !stream.resource<*>{%0} -> !stream.resource<external>{%0}
%7 = stream.tensor.export %6 : tensor<2048x2048xi32> in !stream.resource<external>{%0} -> !hal.buffer_view
return %7 : !hal.buffer_view
}
}
// -----// IR Dump Before CombineInitializers (iree-util-combine-initializers) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
%c0_i32 = arith.constant 0 : i32
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.sizeof tensor<2048x2048xi32> : index
%1 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%0}
%2 = stream.async.transfer %1 : !stream.resource<external>{%0} -> !stream.resource<*>{%0}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%3 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%0}
%4 = stream.async.transfer %3 : !stream.resource<external>{%0} -> !stream.resource<*>{%0}
%5 = stream.async.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%2[%c0 to %0 for %0], %4[%c0 to %0 for %0]) : (!stream.resource<*>{%0}, !stream.resource<*>{%0}) -> !stream.resource<*>{%0}
%6 = stream.async.transfer %5 : !stream.resource<*>{%0} -> !stream.resource<external>{%0}
%7 = stream.tensor.export %6 : tensor<2048x2048xi32> in !stream.resource<external>{%0} -> !hal.buffer_view
return %7 : !hal.buffer_view
}
}
// -----// IR Dump After CombineInitializers (iree-util-combine-initializers) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
%c0_i32 = arith.constant 0 : i32
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.sizeof tensor<2048x2048xi32> : index
%1 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%0}
%2 = stream.async.transfer %1 : !stream.resource<external>{%0} -> !stream.resource<*>{%0}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%3 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%0}
%4 = stream.async.transfer %3 : !stream.resource<external>{%0} -> !stream.resource<*>{%0}
%5 = stream.async.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%2[%c0 to %0 for %0], %4[%c0 to %0 for %0]) : (!stream.resource<*>{%0}, !stream.resource<*>{%0}) -> !stream.resource<*>{%0}
%6 = stream.async.transfer %5 : !stream.resource<*>{%0} -> !stream.resource<external>{%0}
%7 = stream.tensor.export %6 : tensor<2048x2048xi32> in !stream.resource<external>{%0} -> !hal.buffer_view
return %7 : !hal.buffer_view
}
}
// -----// IR Dump Before EncodeDeviceTensorsPass (iree-stream-encode-device-tensors) //----- //
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
%c0_i32 = arith.constant 0 : i32
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
// -----// IR Dump After EncodeDeviceTensorsPass (iree-stream-encode-device-tensors) //----- //
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
%c0_i32 = arith.constant 0 : i32
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
// -----// IR Dump Before EncodeHostTensorsPass (iree-stream-encode-host-tensors) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.sizeof tensor<2048x2048xi32> : index
%1 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%0}
%2 = stream.async.transfer %1 : !stream.resource<external>{%0} -> !stream.resource<*>{%0}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%3 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%0}
%4 = stream.async.transfer %3 : !stream.resource<external>{%0} -> !stream.resource<*>{%0}
%5 = stream.async.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%2[%c0 to %0 for %0], %4[%c0 to %0 for %0]) : (!stream.resource<*>{%0}, !stream.resource<*>{%0}) -> !stream.resource<*>{%0}
%6 = stream.async.transfer %5 : !stream.resource<*>{%0} -> !stream.resource<external>{%0}
%7 = stream.tensor.export %6 : tensor<2048x2048xi32> in !stream.resource<external>{%0} -> !hal.buffer_view
return %7 : !hal.buffer_view
}
// -----// IR Dump After EncodeHostTensorsPass (iree-stream-encode-host-tensors) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%1 = stream.async.transfer %0 : !stream.resource<external>{%c16777216} -> !stream.resource<*>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%2 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%3 = stream.async.transfer %2 : !stream.resource<external>{%c16777216} -> !stream.resource<*>{%c16777216}
%4 = stream.async.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%1[%c0 to %c16777216 for %c16777216], %3[%c0 to %c16777216 for %c16777216]) : (!stream.resource<*>{%c16777216}, !stream.resource<*>{%c16777216}) -> !stream.resource<*>{%c16777216}
%5 = stream.async.transfer %4 : !stream.resource<*>{%c16777216} -> !stream.resource<external>{%c16777216}
%6 = stream.tensor.export %5 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %6 : !hal.buffer_view
}
// -----// IR Dump Before Canonicalizer (canonicalize) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%1 = stream.async.transfer %0 : !stream.resource<external>{%c16777216} -> !stream.resource<*>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%2 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%3 = stream.async.transfer %2 : !stream.resource<external>{%c16777216} -> !stream.resource<*>{%c16777216}
%4 = stream.async.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%1[%c0 to %c16777216 for %c16777216], %3[%c0 to %c16777216 for %c16777216]) : (!stream.resource<*>{%c16777216}, !stream.resource<*>{%c16777216}) -> !stream.resource<*>{%c16777216}
%5 = stream.async.transfer %4 : !stream.resource<*>{%c16777216} -> !stream.resource<external>{%c16777216}
%6 = stream.tensor.export %5 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %6 : !hal.buffer_view
}
// -----// IR Dump After Canonicalizer (canonicalize) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%1 = stream.async.transfer %0 : !stream.resource<external>{%c16777216} -> !stream.resource<*>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%2 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%3 = stream.async.transfer %2 : !stream.resource<external>{%c16777216} -> !stream.resource<*>{%c16777216}
%4 = stream.async.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%1[%c0 to %c16777216 for %c16777216], %3[%c0 to %c16777216 for %c16777216]) : (!stream.resource<*>{%c16777216}, !stream.resource<*>{%c16777216}) -> !stream.resource<*>{%c16777216}
%5 = stream.async.transfer %4 : !stream.resource<*>{%c16777216} -> !stream.resource<external>{%c16777216}
%6 = stream.tensor.export %5 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %6 : !hal.buffer_view
}
// -----// IR Dump Before CSE (cse) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%1 = stream.async.transfer %0 : !stream.resource<external>{%c16777216} -> !stream.resource<*>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%2 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%3 = stream.async.transfer %2 : !stream.resource<external>{%c16777216} -> !stream.resource<*>{%c16777216}
%4 = stream.async.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%1[%c0 to %c16777216 for %c16777216], %3[%c0 to %c16777216 for %c16777216]) : (!stream.resource<*>{%c16777216}, !stream.resource<*>{%c16777216}) -> !stream.resource<*>{%c16777216}
%5 = stream.async.transfer %4 : !stream.resource<*>{%c16777216} -> !stream.resource<external>{%c16777216}
%6 = stream.tensor.export %5 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %6 : !hal.buffer_view
}
// -----// IR Dump After CSE (cse) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%1 = stream.async.transfer %0 : !stream.resource<external>{%c16777216} -> !stream.resource<*>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%2 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%3 = stream.async.transfer %2 : !stream.resource<external>{%c16777216} -> !stream.resource<*>{%c16777216}
%4 = stream.async.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%1[%c0 to %c16777216 for %c16777216], %3[%c0 to %c16777216 for %c16777216]) : (!stream.resource<*>{%c16777216}, !stream.resource<*>{%c16777216}) -> !stream.resource<*>{%c16777216}
%5 = stream.async.transfer %4 : !stream.resource<*>{%c16777216} -> !stream.resource<external>{%c16777216}
%6 = stream.tensor.export %5 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %6 : !hal.buffer_view
}
// -----// IR Dump Before SimplifyGlobalAccesses (iree-util-simplify-global-accesses) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%1 = stream.async.transfer %0 : !stream.resource<external>{%c16777216} -> !stream.resource<*>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%2 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%3 = stream.async.transfer %2 : !stream.resource<external>{%c16777216} -> !stream.resource<*>{%c16777216}
%4 = stream.async.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%1[%c0 to %c16777216 for %c16777216], %3[%c0 to %c16777216 for %c16777216]) : (!stream.resource<*>{%c16777216}, !stream.resource<*>{%c16777216}) -> !stream.resource<*>{%c16777216}
%5 = stream.async.transfer %4 : !stream.resource<*>{%c16777216} -> !stream.resource<external>{%c16777216}
%6 = stream.tensor.export %5 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %6 : !hal.buffer_view
}
// -----// IR Dump After SimplifyGlobalAccesses (iree-util-simplify-global-accesses) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%1 = stream.async.transfer %0 : !stream.resource<external>{%c16777216} -> !stream.resource<*>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%2 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%3 = stream.async.transfer %2 : !stream.resource<external>{%c16777216} -> !stream.resource<*>{%c16777216}
%4 = stream.async.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%1[%c0 to %c16777216 for %c16777216], %3[%c0 to %c16777216 for %c16777216]) : (!stream.resource<*>{%c16777216}, !stream.resource<*>{%c16777216}) -> !stream.resource<*>{%c16777216}
%5 = stream.async.transfer %4 : !stream.resource<*>{%c16777216} -> !stream.resource<external>{%c16777216}
%6 = stream.tensor.export %5 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %6 : !hal.buffer_view
}
// -----// IR Dump Before ApplyPatterns (iree-util-apply-patterns) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
%c0_i32 = arith.constant 0 : i32
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%1 = stream.async.transfer %0 : !stream.resource<external>{%c16777216} -> !stream.resource<*>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%2 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%3 = stream.async.transfer %2 : !stream.resource<external>{%c16777216} -> !stream.resource<*>{%c16777216}
%4 = stream.async.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%1[%c0 to %c16777216 for %c16777216], %3[%c0 to %c16777216 for %c16777216]) : (!stream.resource<*>{%c16777216}, !stream.resource<*>{%c16777216}) -> !stream.resource<*>{%c16777216}
%5 = stream.async.transfer %4 : !stream.resource<*>{%c16777216} -> !stream.resource<external>{%c16777216}
%6 = stream.tensor.export %5 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %6 : !hal.buffer_view
}
}
// -----// IR Dump After ApplyPatterns (iree-util-apply-patterns) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
%c0_i32 = arith.constant 0 : i32
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%1 = stream.async.transfer %0 : !stream.resource<external>{%c16777216} -> !stream.resource<*>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%2 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%3 = stream.async.transfer %2 : !stream.resource<external>{%c16777216} -> !stream.resource<*>{%c16777216}
%4 = stream.async.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%1[%c0 to %c16777216 for %c16777216], %3[%c0 to %c16777216 for %c16777216]) : (!stream.resource<*>{%c16777216}, !stream.resource<*>{%c16777216}) -> !stream.resource<*>{%c16777216}
%5 = stream.async.transfer %4 : !stream.resource<*>{%c16777216} -> !stream.resource<external>{%c16777216}
%6 = stream.tensor.export %5 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %6 : !hal.buffer_view
}
}
// -----// IR Dump Before FoldGlobals (iree-util-fold-globals) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
%c0_i32 = arith.constant 0 : i32
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%1 = stream.async.transfer %0 : !stream.resource<external>{%c16777216} -> !stream.resource<*>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%2 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%3 = stream.async.transfer %2 : !stream.resource<external>{%c16777216} -> !stream.resource<*>{%c16777216}
%4 = stream.async.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%1[%c0 to %c16777216 for %c16777216], %3[%c0 to %c16777216 for %c16777216]) : (!stream.resource<*>{%c16777216}, !stream.resource<*>{%c16777216}) -> !stream.resource<*>{%c16777216}
%5 = stream.async.transfer %4 : !stream.resource<*>{%c16777216} -> !stream.resource<external>{%c16777216}
%6 = stream.tensor.export %5 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %6 : !hal.buffer_view
}
}
// -----// IR Dump After FoldGlobals (iree-util-fold-globals) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
%c0_i32 = arith.constant 0 : i32
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%1 = stream.async.transfer %0 : !stream.resource<external>{%c16777216} -> !stream.resource<*>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%2 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%3 = stream.async.transfer %2 : !stream.resource<external>{%c16777216} -> !stream.resource<*>{%c16777216}
%4 = stream.async.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%1[%c0 to %c16777216 for %c16777216], %3[%c0 to %c16777216 for %c16777216]) : (!stream.resource<*>{%c16777216}, !stream.resource<*>{%c16777216}) -> !stream.resource<*>{%c16777216}
%5 = stream.async.transfer %4 : !stream.resource<*>{%c16777216} -> !stream.resource<external>{%c16777216}
%6 = stream.tensor.export %5 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %6 : !hal.buffer_view
}
}
// -----// IR Dump Before FuseGlobals (iree-util-fuse-globals) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
%c0_i32 = arith.constant 0 : i32
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%1 = stream.async.transfer %0 : !stream.resource<external>{%c16777216} -> !stream.resource<*>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%2 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%3 = stream.async.transfer %2 : !stream.resource<external>{%c16777216} -> !stream.resource<*>{%c16777216}
%4 = stream.async.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%1[%c0 to %c16777216 for %c16777216], %3[%c0 to %c16777216 for %c16777216]) : (!stream.resource<*>{%c16777216}, !stream.resource<*>{%c16777216}) -> !stream.resource<*>{%c16777216}
%5 = stream.async.transfer %4 : !stream.resource<*>{%c16777216} -> !stream.resource<external>{%c16777216}
%6 = stream.tensor.export %5 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %6 : !hal.buffer_view
}
}
// -----// IR Dump After FuseGlobals (iree-util-fuse-globals) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
%c0_i32 = arith.constant 0 : i32
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%1 = stream.async.transfer %0 : !stream.resource<external>{%c16777216} -> !stream.resource<*>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%2 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%3 = stream.async.transfer %2 : !stream.resource<external>{%c16777216} -> !stream.resource<*>{%c16777216}
%4 = stream.async.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%1[%c0 to %c16777216 for %c16777216], %3[%c0 to %c16777216 for %c16777216]) : (!stream.resource<*>{%c16777216}, !stream.resource<*>{%c16777216}) -> !stream.resource<*>{%c16777216}
%5 = stream.async.transfer %4 : !stream.resource<*>{%c16777216} -> !stream.resource<external>{%c16777216}
%6 = stream.tensor.export %5 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %6 : !hal.buffer_view
}
}
// -----// IR Dump Before IPO (iree-util-ipo) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
%c0_i32 = arith.constant 0 : i32
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%1 = stream.async.transfer %0 : !stream.resource<external>{%c16777216} -> !stream.resource<*>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%2 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%3 = stream.async.transfer %2 : !stream.resource<external>{%c16777216} -> !stream.resource<*>{%c16777216}
%4 = stream.async.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%1[%c0 to %c16777216 for %c16777216], %3[%c0 to %c16777216 for %c16777216]) : (!stream.resource<*>{%c16777216}, !stream.resource<*>{%c16777216}) -> !stream.resource<*>{%c16777216}
%5 = stream.async.transfer %4 : !stream.resource<*>{%c16777216} -> !stream.resource<external>{%c16777216}
%6 = stream.tensor.export %5 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %6 : !hal.buffer_view
}
}
// -----// IR Dump After IPO (iree-util-ipo) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
%c0_i32 = arith.constant 0 : i32
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%1 = stream.async.transfer %0 : !stream.resource<external>{%c16777216} -> !stream.resource<*>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%2 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%3 = stream.async.transfer %2 : !stream.resource<external>{%c16777216} -> !stream.resource<*>{%c16777216}
%4 = stream.async.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%1[%c0 to %c16777216 for %c16777216], %3[%c0 to %c16777216 for %c16777216]) : (!stream.resource<*>{%c16777216}, !stream.resource<*>{%c16777216}) -> !stream.resource<*>{%c16777216}
%5 = stream.async.transfer %4 : !stream.resource<*>{%c16777216} -> !stream.resource<external>{%c16777216}
%6 = stream.tensor.export %5 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %6 : !hal.buffer_view
}
}
// -----// IR Dump Before VerifyLoweringToAsyncResourcesPass (iree-stream-verify-lowering-to-async-resources) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
%c0_i32 = arith.constant 0 : i32
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%1 = stream.async.transfer %0 : !stream.resource<external>{%c16777216} -> !stream.resource<*>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%2 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%3 = stream.async.transfer %2 : !stream.resource<external>{%c16777216} -> !stream.resource<*>{%c16777216}
%4 = stream.async.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%1[%c0 to %c16777216 for %c16777216], %3[%c0 to %c16777216 for %c16777216]) : (!stream.resource<*>{%c16777216}, !stream.resource<*>{%c16777216}) -> !stream.resource<*>{%c16777216}
%5 = stream.async.transfer %4 : !stream.resource<*>{%c16777216} -> !stream.resource<external>{%c16777216}
%6 = stream.tensor.export %5 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %6 : !hal.buffer_view
}
}
// -----// IR Dump After VerifyLoweringToAsyncResourcesPass (iree-stream-verify-lowering-to-async-resources) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
%c0_i32 = arith.constant 0 : i32
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%1 = stream.async.transfer %0 : !stream.resource<external>{%c16777216} -> !stream.resource<*>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%2 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%3 = stream.async.transfer %2 : !stream.resource<external>{%c16777216} -> !stream.resource<*>{%c16777216}
%4 = stream.async.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%1[%c0 to %c16777216 for %c16777216], %3[%c0 to %c16777216 for %c16777216]) : (!stream.resource<*>{%c16777216}, !stream.resource<*>{%c16777216}) -> !stream.resource<*>{%c16777216}
%5 = stream.async.transfer %4 : !stream.resource<*>{%c16777216} -> !stream.resource<external>{%c16777216}
%6 = stream.tensor.export %5 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %6 : !hal.buffer_view
}
}
// -----// IR Dump Before MaterializeCopyOnWritePass (iree-stream-materialize-copy-on-write) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%1 = stream.async.transfer %0 : !stream.resource<external>{%c16777216} -> !stream.resource<*>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%2 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%3 = stream.async.transfer %2 : !stream.resource<external>{%c16777216} -> !stream.resource<*>{%c16777216}
%4 = stream.async.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%1[%c0 to %c16777216 for %c16777216], %3[%c0 to %c16777216 for %c16777216]) : (!stream.resource<*>{%c16777216}, !stream.resource<*>{%c16777216}) -> !stream.resource<*>{%c16777216}
%5 = stream.async.transfer %4 : !stream.resource<*>{%c16777216} -> !stream.resource<external>{%c16777216}
%6 = stream.tensor.export %5 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %6 : !hal.buffer_view
}
// -----// IR Dump After MaterializeCopyOnWritePass (iree-stream-materialize-copy-on-write) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%1 = stream.async.transfer %0 : !stream.resource<external>{%c16777216} -> !stream.resource<*>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%2 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%3 = stream.async.transfer %2 : !stream.resource<external>{%c16777216} -> !stream.resource<*>{%c16777216}
%4 = stream.async.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%1[%c0 to %c16777216 for %c16777216], %3[%c0 to %c16777216 for %c16777216]) : (!stream.resource<*>{%c16777216}, !stream.resource<*>{%c16777216}) -> !stream.resource<*>{%c16777216}
%5 = stream.async.transfer %4 : !stream.resource<*>{%c16777216} -> !stream.resource<external>{%c16777216}
%6 = stream.tensor.export %5 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %6 : !hal.buffer_view
}
// -----// IR Dump Before ElideAsyncCopiesPass (iree-stream-elide-async-copies) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
%c0_i32 = arith.constant 0 : i32
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%1 = stream.async.transfer %0 : !stream.resource<external>{%c16777216} -> !stream.resource<*>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%2 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%3 = stream.async.transfer %2 : !stream.resource<external>{%c16777216} -> !stream.resource<*>{%c16777216}
%4 = stream.async.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%1[%c0 to %c16777216 for %c16777216], %3[%c0 to %c16777216 for %c16777216]) : (!stream.resource<*>{%c16777216}, !stream.resource<*>{%c16777216}) -> !stream.resource<*>{%c16777216}
%5 = stream.async.transfer %4 : !stream.resource<*>{%c16777216} -> !stream.resource<external>{%c16777216}
%6 = stream.tensor.export %5 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %6 : !hal.buffer_view
}
}
// -----// IR Dump After ElideAsyncCopiesPass (iree-stream-elide-async-copies) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
%c0_i32 = arith.constant 0 : i32
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%1 = stream.async.transfer %0 : !stream.resource<external>{%c16777216} -> !stream.resource<*>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%2 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%3 = stream.async.transfer %2 : !stream.resource<external>{%c16777216} -> !stream.resource<*>{%c16777216}
%4 = stream.async.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%1[%c0 to %c16777216 for %c16777216], %3[%c0 to %c16777216 for %c16777216]) : (!stream.resource<*>{%c16777216}, !stream.resource<*>{%c16777216}) -> !stream.resource<*>{%c16777216}
%5 = stream.async.transfer %4 : !stream.resource<*>{%c16777216} -> !stream.resource<external>{%c16777216}
%6 = stream.tensor.export %5 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %6 : !hal.buffer_view
}
}
// -----// IR Dump Before Canonicalizer (canonicalize) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%1 = stream.async.transfer %0 : !stream.resource<external>{%c16777216} -> !stream.resource<*>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%2 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%3 = stream.async.transfer %2 : !stream.resource<external>{%c16777216} -> !stream.resource<*>{%c16777216}
%4 = stream.async.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%1[%c0 to %c16777216 for %c16777216], %3[%c0 to %c16777216 for %c16777216]) : (!stream.resource<*>{%c16777216}, !stream.resource<*>{%c16777216}) -> !stream.resource<*>{%c16777216}
%5 = stream.async.transfer %4 : !stream.resource<*>{%c16777216} -> !stream.resource<external>{%c16777216}
%6 = stream.tensor.export %5 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %6 : !hal.buffer_view
}
// -----// IR Dump After Canonicalizer (canonicalize) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%1 = stream.async.transfer %0 : !stream.resource<external>{%c16777216} -> !stream.resource<*>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%2 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%3 = stream.async.transfer %2 : !stream.resource<external>{%c16777216} -> !stream.resource<*>{%c16777216}
%4 = stream.async.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%1[%c0 to %c16777216 for %c16777216], %3[%c0 to %c16777216 for %c16777216]) : (!stream.resource<*>{%c16777216}, !stream.resource<*>{%c16777216}) -> !stream.resource<*>{%c16777216}
%5 = stream.async.transfer %4 : !stream.resource<*>{%c16777216} -> !stream.resource<external>{%c16777216}
%6 = stream.tensor.export %5 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %6 : !hal.buffer_view
}
// -----// IR Dump Before EmplaceAllocationsPass (iree-stream-emplace-allocations) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%1 = stream.async.transfer %0 : !stream.resource<external>{%c16777216} -> !stream.resource<*>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%2 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%3 = stream.async.transfer %2 : !stream.resource<external>{%c16777216} -> !stream.resource<*>{%c16777216}
%4 = stream.async.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%1[%c0 to %c16777216 for %c16777216], %3[%c0 to %c16777216 for %c16777216]) : (!stream.resource<*>{%c16777216}, !stream.resource<*>{%c16777216}) -> !stream.resource<*>{%c16777216}
%5 = stream.async.transfer %4 : !stream.resource<*>{%c16777216} -> !stream.resource<external>{%c16777216}
%6 = stream.tensor.export %5 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %6 : !hal.buffer_view
}
// -----// IR Dump After EmplaceAllocationsPass (iree-stream-emplace-allocations) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%1 = stream.async.transfer %0 : !stream.resource<external>{%c16777216} -> !stream.resource<*>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%2 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%3 = stream.async.transfer %2 : !stream.resource<external>{%c16777216} -> !stream.resource<*>{%c16777216}
%4 = stream.async.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%1[%c0 to %c16777216 for %c16777216], %3[%c0 to %c16777216 for %c16777216]) : (!stream.resource<*>{%c16777216}, !stream.resource<*>{%c16777216}) -> !stream.resource<*>{%c16777216}
%5 = stream.async.transfer %4 : !stream.resource<*>{%c16777216} -> !stream.resource<external>{%c16777216}
%6 = stream.tensor.export %5 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %6 : !hal.buffer_view
}
// -----// IR Dump Before RefineUsagePass (iree-stream-refine-usage) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
%c0_i32 = arith.constant 0 : i32
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%1 = stream.async.transfer %0 : !stream.resource<external>{%c16777216} -> !stream.resource<*>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%2 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%3 = stream.async.transfer %2 : !stream.resource<external>{%c16777216} -> !stream.resource<*>{%c16777216}
%4 = stream.async.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%1[%c0 to %c16777216 for %c16777216], %3[%c0 to %c16777216 for %c16777216]) : (!stream.resource<*>{%c16777216}, !stream.resource<*>{%c16777216}) -> !stream.resource<*>{%c16777216}
%5 = stream.async.transfer %4 : !stream.resource<*>{%c16777216} -> !stream.resource<external>{%c16777216}
%6 = stream.tensor.export %5 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %6 : !hal.buffer_view
}
}
// -----// IR Dump After RefineUsagePass (iree-stream-refine-usage) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
%c0_i32 = arith.constant 0 : i32
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%2 = stream.async.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%0[%c0 to %c16777216 for %c16777216], %1[%c0 to %c16777216 for %c16777216]) : (!stream.resource<external>{%c16777216}, !stream.resource<external>{%c16777216}) -> !stream.resource<external>{%c16777216}
%3 = stream.tensor.export %2 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %3 : !hal.buffer_view
}
}
// -----// IR Dump Before Canonicalizer (canonicalize) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%2 = stream.async.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%0[%c0 to %c16777216 for %c16777216], %1[%c0 to %c16777216 for %c16777216]) : (!stream.resource<external>{%c16777216}, !stream.resource<external>{%c16777216}) -> !stream.resource<external>{%c16777216}
%3 = stream.tensor.export %2 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %3 : !hal.buffer_view
}
// -----// IR Dump After Canonicalizer (canonicalize) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%2 = stream.async.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%0[%c0 to %c16777216 for %c16777216], %1[%c0 to %c16777216 for %c16777216]) : (!stream.resource<external>{%c16777216}, !stream.resource<external>{%c16777216}) -> !stream.resource<external>{%c16777216}
%3 = stream.tensor.export %2 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %3 : !hal.buffer_view
}
// -----// IR Dump Before CSE (cse) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%2 = stream.async.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%0[%c0 to %c16777216 for %c16777216], %1[%c0 to %c16777216 for %c16777216]) : (!stream.resource<external>{%c16777216}, !stream.resource<external>{%c16777216}) -> !stream.resource<external>{%c16777216}
%3 = stream.tensor.export %2 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %3 : !hal.buffer_view
}
// -----// IR Dump After CSE (cse) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%2 = stream.async.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%0[%c0 to %c16777216 for %c16777216], %1[%c0 to %c16777216 for %c16777216]) : (!stream.resource<external>{%c16777216}, !stream.resource<external>{%c16777216}) -> !stream.resource<external>{%c16777216}
%3 = stream.tensor.export %2 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %3 : !hal.buffer_view
}
// -----// IR Dump Before SimplifyGlobalAccesses (iree-util-simplify-global-accesses) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%2 = stream.async.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%0[%c0 to %c16777216 for %c16777216], %1[%c0 to %c16777216 for %c16777216]) : (!stream.resource<external>{%c16777216}, !stream.resource<external>{%c16777216}) -> !stream.resource<external>{%c16777216}
%3 = stream.tensor.export %2 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %3 : !hal.buffer_view
}
// -----// IR Dump After SimplifyGlobalAccesses (iree-util-simplify-global-accesses) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%2 = stream.async.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%0[%c0 to %c16777216 for %c16777216], %1[%c0 to %c16777216 for %c16777216]) : (!stream.resource<external>{%c16777216}, !stream.resource<external>{%c16777216}) -> !stream.resource<external>{%c16777216}
%3 = stream.tensor.export %2 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %3 : !hal.buffer_view
}
// -----// IR Dump Before ApplyPatterns (iree-util-apply-patterns) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
%c0_i32 = arith.constant 0 : i32
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%2 = stream.async.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%0[%c0 to %c16777216 for %c16777216], %1[%c0 to %c16777216 for %c16777216]) : (!stream.resource<external>{%c16777216}, !stream.resource<external>{%c16777216}) -> !stream.resource<external>{%c16777216}
%3 = stream.tensor.export %2 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %3 : !hal.buffer_view
}
}
// -----// IR Dump After ApplyPatterns (iree-util-apply-patterns) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
%c0_i32 = arith.constant 0 : i32
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%2 = stream.async.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%0[%c0 to %c16777216 for %c16777216], %1[%c0 to %c16777216 for %c16777216]) : (!stream.resource<external>{%c16777216}, !stream.resource<external>{%c16777216}) -> !stream.resource<external>{%c16777216}
%3 = stream.tensor.export %2 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %3 : !hal.buffer_view
}
}
// -----// IR Dump Before FoldGlobals (iree-util-fold-globals) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
%c0_i32 = arith.constant 0 : i32
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%2 = stream.async.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%0[%c0 to %c16777216 for %c16777216], %1[%c0 to %c16777216 for %c16777216]) : (!stream.resource<external>{%c16777216}, !stream.resource<external>{%c16777216}) -> !stream.resource<external>{%c16777216}
%3 = stream.tensor.export %2 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %3 : !hal.buffer_view
}
}
// -----// IR Dump After FoldGlobals (iree-util-fold-globals) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
%c0_i32 = arith.constant 0 : i32
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%2 = stream.async.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%0[%c0 to %c16777216 for %c16777216], %1[%c0 to %c16777216 for %c16777216]) : (!stream.resource<external>{%c16777216}, !stream.resource<external>{%c16777216}) -> !stream.resource<external>{%c16777216}
%3 = stream.tensor.export %2 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %3 : !hal.buffer_view
}
}
// -----// IR Dump Before FuseGlobals (iree-util-fuse-globals) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
%c0_i32 = arith.constant 0 : i32
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%2 = stream.async.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%0[%c0 to %c16777216 for %c16777216], %1[%c0 to %c16777216 for %c16777216]) : (!stream.resource<external>{%c16777216}, !stream.resource<external>{%c16777216}) -> !stream.resource<external>{%c16777216}
%3 = stream.tensor.export %2 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %3 : !hal.buffer_view
}
}
// -----// IR Dump After FuseGlobals (iree-util-fuse-globals) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
%c0_i32 = arith.constant 0 : i32
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%2 = stream.async.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%0[%c0 to %c16777216 for %c16777216], %1[%c0 to %c16777216 for %c16777216]) : (!stream.resource<external>{%c16777216}, !stream.resource<external>{%c16777216}) -> !stream.resource<external>{%c16777216}
%3 = stream.tensor.export %2 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %3 : !hal.buffer_view
}
}
// -----// IR Dump Before IPO (iree-util-ipo) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
%c0_i32 = arith.constant 0 : i32
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%2 = stream.async.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%0[%c0 to %c16777216 for %c16777216], %1[%c0 to %c16777216 for %c16777216]) : (!stream.resource<external>{%c16777216}, !stream.resource<external>{%c16777216}) -> !stream.resource<external>{%c16777216}
%3 = stream.tensor.export %2 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %3 : !hal.buffer_view
}
}
// -----// IR Dump After IPO (iree-util-ipo) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
%c0_i32 = arith.constant 0 : i32
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%2 = stream.async.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%0[%c0 to %c16777216 for %c16777216], %1[%c0 to %c16777216 for %c16777216]) : (!stream.resource<external>{%c16777216}, !stream.resource<external>{%c16777216}) -> !stream.resource<external>{%c16777216}
%3 = stream.tensor.export %2 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %3 : !hal.buffer_view
}
}
// -----// IR Dump Before VerifyAsyncAccessRangesPass (iree-stream-verify-async-access-ranges) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
%c0_i32 = arith.constant 0 : i32
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%2 = stream.async.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%0[%c0 to %c16777216 for %c16777216], %1[%c0 to %c16777216 for %c16777216]) : (!stream.resource<external>{%c16777216}, !stream.resource<external>{%c16777216}) -> !stream.resource<external>{%c16777216}
%3 = stream.tensor.export %2 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %3 : !hal.buffer_view
}
}
// -----// IR Dump After VerifyAsyncAccessRangesPass (iree-stream-verify-async-access-ranges) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
%c0_i32 = arith.constant 0 : i32
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%2 = stream.async.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%0[%c0 to %c16777216 for %c16777216], %1[%c0 to %c16777216 for %c16777216]) : (!stream.resource<external>{%c16777216}, !stream.resource<external>{%c16777216}) -> !stream.resource<external>{%c16777216}
%3 = stream.tensor.export %2 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %3 : !hal.buffer_view
}
}
// -----// IR Dump Before ScheduleExecutionPass (iree-stream-schedule-execution) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%2 = stream.async.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%0[%c0 to %c16777216 for %c16777216], %1[%c0 to %c16777216 for %c16777216]) : (!stream.resource<external>{%c16777216}, !stream.resource<external>{%c16777216}) -> !stream.resource<external>{%c16777216}
%3 = stream.tensor.export %2 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %3 : !hal.buffer_view
}
// -----// IR Dump After ScheduleExecutionPass (iree-stream-schedule-execution) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%results, %result_timepoint = stream.async.execute with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}) -> !stream.resource<external>{%c16777216} {
%4 = stream.async.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg2[%c0 to %c16777216 for %c16777216], %arg3[%c0 to %c16777216 for %c16777216]) : (!stream.resource<external>{%c16777216}, !stream.resource<external>{%c16777216}) -> !stream.resource<external>{%c16777216}
stream.yield %4 : !stream.resource<external>{%c16777216}
} => !stream.timepoint
%2 = stream.timepoint.await %result_timepoint => %results : !stream.resource<external>{%c16777216}
%3 = stream.tensor.export %2 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %3 : !hal.buffer_view
}
// -----// IR Dump Before ScheduleConcurrencyPass (iree-stream-schedule-concurrency) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%results, %result_timepoint = stream.async.execute with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}) -> !stream.resource<external>{%c16777216} {
%4 = stream.async.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg2[%c0 to %c16777216 for %c16777216], %arg3[%c0 to %c16777216 for %c16777216]) : (!stream.resource<external>{%c16777216}, !stream.resource<external>{%c16777216}) -> !stream.resource<external>{%c16777216}
stream.yield %4 : !stream.resource<external>{%c16777216}
} => !stream.timepoint
%2 = stream.timepoint.await %result_timepoint => %results : !stream.resource<external>{%c16777216}
%3 = stream.tensor.export %2 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %3 : !hal.buffer_view
}
// -----// IR Dump After ScheduleConcurrencyPass (iree-stream-schedule-concurrency) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%results, %result_timepoint = stream.async.execute with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}) -> !stream.resource<external>{%c16777216} {
%4 = stream.async.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg2[%c0 to %c16777216 for %c16777216], %arg3[%c0 to %c16777216 for %c16777216]) : (!stream.resource<external>{%c16777216}, !stream.resource<external>{%c16777216}) -> !stream.resource<external>{%c16777216}
stream.yield %4 : !stream.resource<external>{%c16777216}
} => !stream.timepoint
%2 = stream.timepoint.await %result_timepoint => %results : !stream.resource<external>{%c16777216}
%3 = stream.tensor.export %2 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %3 : !hal.buffer_view
}
// -----// IR Dump Before PropagateTimepointsPass (iree-stream-propagate-timepoints) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
%c0_i32 = arith.constant 0 : i32
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%results, %result_timepoint = stream.async.execute with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}) -> !stream.resource<external>{%c16777216} {
%4 = stream.async.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg2[%c0 to %c16777216 for %c16777216], %arg3[%c0 to %c16777216 for %c16777216]) : (!stream.resource<external>{%c16777216}, !stream.resource<external>{%c16777216}) -> !stream.resource<external>{%c16777216}
stream.yield %4 : !stream.resource<external>{%c16777216}
} => !stream.timepoint
%2 = stream.timepoint.await %result_timepoint => %results : !stream.resource<external>{%c16777216}
%3 = stream.tensor.export %2 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %3 : !hal.buffer_view
}
}
// -----// IR Dump After PropagateTimepointsPass (iree-stream-propagate-timepoints) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
%c0_i32 = arith.constant 0 : i32
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%2 = stream.timepoint.immediate => !stream.timepoint
%3 = stream.timepoint.immediate => !stream.timepoint
%4 = stream.timepoint.join max(%2, %3) => !stream.timepoint
%results, %result_timepoint = stream.async.execute await(%4) => with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}) -> !stream.resource<external>{%c16777216} {
%7 = stream.async.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg2[%c0 to %c16777216 for %c16777216], %arg3[%c0 to %c16777216 for %c16777216]) : (!stream.resource<external>{%c16777216}, !stream.resource<external>{%c16777216}) -> !stream.resource<external>{%c16777216}
stream.yield %7 : !stream.resource<external>{%c16777216}
} => !stream.timepoint
%5 = stream.timepoint.await %result_timepoint => %results : !stream.resource<external>{%c16777216}
%6 = stream.tensor.export %5 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %6 : !hal.buffer_view
}
}
// -----// IR Dump Before MaterializeBuiltinsPass (iree-stream-materialize-builtins) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
%c0_i32 = arith.constant 0 : i32
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%2 = stream.timepoint.immediate => !stream.timepoint
%3 = stream.timepoint.immediate => !stream.timepoint
%4 = stream.timepoint.join max(%2, %3) => !stream.timepoint
%results, %result_timepoint = stream.async.execute await(%4) => with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}) -> !stream.resource<external>{%c16777216} {
%7 = stream.async.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg2[%c0 to %c16777216 for %c16777216], %arg3[%c0 to %c16777216 for %c16777216]) : (!stream.resource<external>{%c16777216}, !stream.resource<external>{%c16777216}) -> !stream.resource<external>{%c16777216}
stream.yield %7 : !stream.resource<external>{%c16777216}
} => !stream.timepoint
%5 = stream.timepoint.await %result_timepoint => %results : !stream.resource<external>{%c16777216}
%6 = stream.tensor.export %5 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %6 : !hal.buffer_view
}
}
// -----// IR Dump After MaterializeBuiltinsPass (iree-stream-materialize-builtins) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
%c0_i32 = arith.constant 0 : i32
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%2 = stream.timepoint.immediate => !stream.timepoint
%3 = stream.timepoint.immediate => !stream.timepoint
%4 = stream.timepoint.join max(%2, %3) => !stream.timepoint
%results, %result_timepoint = stream.async.execute await(%4) => with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}) -> !stream.resource<external>{%c16777216} {
%7 = stream.async.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg2[%c0 to %c16777216 for %c16777216], %arg3[%c0 to %c16777216 for %c16777216]) : (!stream.resource<external>{%c16777216}, !stream.resource<external>{%c16777216}) -> !stream.resource<external>{%c16777216}
stream.yield %7 : !stream.resource<external>{%c16777216}
} => !stream.timepoint
%5 = stream.timepoint.await %result_timepoint => %results : !stream.resource<external>{%c16777216}
%6 = stream.tensor.export %5 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %6 : !hal.buffer_view
}
}
// -----// IR Dump Before Canonicalizer (canonicalize) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%2 = stream.timepoint.immediate => !stream.timepoint
%3 = stream.timepoint.immediate => !stream.timepoint
%4 = stream.timepoint.join max(%2, %3) => !stream.timepoint
%results, %result_timepoint = stream.async.execute await(%4) => with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}) -> !stream.resource<external>{%c16777216} {
%7 = stream.async.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg2[%c0 to %c16777216 for %c16777216], %arg3[%c0 to %c16777216 for %c16777216]) : (!stream.resource<external>{%c16777216}, !stream.resource<external>{%c16777216}) -> !stream.resource<external>{%c16777216}
stream.yield %7 : !stream.resource<external>{%c16777216}
} => !stream.timepoint
%5 = stream.timepoint.await %result_timepoint => %results : !stream.resource<external>{%c16777216}
%6 = stream.tensor.export %5 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %6 : !hal.buffer_view
}
// -----// IR Dump After Canonicalizer (canonicalize) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%results, %result_timepoint = stream.async.execute with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}) -> !stream.resource<external>{%c16777216} {
%4 = stream.async.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg2[%c0 to %c16777216 for %c16777216], %arg3[%c0 to %c16777216 for %c16777216]) : (!stream.resource<external>{%c16777216}, !stream.resource<external>{%c16777216}) -> !stream.resource<external>{%c16777216}
stream.yield %4 : !stream.resource<external>{%c16777216}
} => !stream.timepoint
%2 = stream.timepoint.await %result_timepoint => %results : !stream.resource<external>{%c16777216}
%3 = stream.tensor.export %2 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %3 : !hal.buffer_view
}
// -----// IR Dump Before CSE (cse) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%results, %result_timepoint = stream.async.execute with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}) -> !stream.resource<external>{%c16777216} {
%4 = stream.async.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg2[%c0 to %c16777216 for %c16777216], %arg3[%c0 to %c16777216 for %c16777216]) : (!stream.resource<external>{%c16777216}, !stream.resource<external>{%c16777216}) -> !stream.resource<external>{%c16777216}
stream.yield %4 : !stream.resource<external>{%c16777216}
} => !stream.timepoint
%2 = stream.timepoint.await %result_timepoint => %results : !stream.resource<external>{%c16777216}
%3 = stream.tensor.export %2 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %3 : !hal.buffer_view
}
// -----// IR Dump After CSE (cse) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%results, %result_timepoint = stream.async.execute with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}) -> !stream.resource<external>{%c16777216} {
%4 = stream.async.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg2[%c0 to %c16777216 for %c16777216], %arg3[%c0 to %c16777216 for %c16777216]) : (!stream.resource<external>{%c16777216}, !stream.resource<external>{%c16777216}) -> !stream.resource<external>{%c16777216}
stream.yield %4 : !stream.resource<external>{%c16777216}
} => !stream.timepoint
%2 = stream.timepoint.await %result_timepoint => %results : !stream.resource<external>{%c16777216}
%3 = stream.tensor.export %2 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %3 : !hal.buffer_view
}
// -----// IR Dump Before SimplifyGlobalAccesses (iree-util-simplify-global-accesses) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%results, %result_timepoint = stream.async.execute with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}) -> !stream.resource<external>{%c16777216} {
%4 = stream.async.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg2[%c0 to %c16777216 for %c16777216], %arg3[%c0 to %c16777216 for %c16777216]) : (!stream.resource<external>{%c16777216}, !stream.resource<external>{%c16777216}) -> !stream.resource<external>{%c16777216}
stream.yield %4 : !stream.resource<external>{%c16777216}
} => !stream.timepoint
%2 = stream.timepoint.await %result_timepoint => %results : !stream.resource<external>{%c16777216}
%3 = stream.tensor.export %2 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %3 : !hal.buffer_view
}
// -----// IR Dump After SimplifyGlobalAccesses (iree-util-simplify-global-accesses) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%results, %result_timepoint = stream.async.execute with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}) -> !stream.resource<external>{%c16777216} {
%4 = stream.async.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg2[%c0 to %c16777216 for %c16777216], %arg3[%c0 to %c16777216 for %c16777216]) : (!stream.resource<external>{%c16777216}, !stream.resource<external>{%c16777216}) -> !stream.resource<external>{%c16777216}
stream.yield %4 : !stream.resource<external>{%c16777216}
} => !stream.timepoint
%2 = stream.timepoint.await %result_timepoint => %results : !stream.resource<external>{%c16777216}
%3 = stream.tensor.export %2 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %3 : !hal.buffer_view
}
// -----// IR Dump Before ApplyPatterns (iree-util-apply-patterns) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
%c0_i32 = arith.constant 0 : i32
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%results, %result_timepoint = stream.async.execute with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}) -> !stream.resource<external>{%c16777216} {
%4 = stream.async.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg2[%c0 to %c16777216 for %c16777216], %arg3[%c0 to %c16777216 for %c16777216]) : (!stream.resource<external>{%c16777216}, !stream.resource<external>{%c16777216}) -> !stream.resource<external>{%c16777216}
stream.yield %4 : !stream.resource<external>{%c16777216}
} => !stream.timepoint
%2 = stream.timepoint.await %result_timepoint => %results : !stream.resource<external>{%c16777216}
%3 = stream.tensor.export %2 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %3 : !hal.buffer_view
}
}
// -----// IR Dump After ApplyPatterns (iree-util-apply-patterns) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
%c0_i32 = arith.constant 0 : i32
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%results, %result_timepoint = stream.async.execute with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}) -> !stream.resource<external>{%c16777216} {
%4 = stream.async.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg2[%c0 to %c16777216 for %c16777216], %arg3[%c0 to %c16777216 for %c16777216]) : (!stream.resource<external>{%c16777216}, !stream.resource<external>{%c16777216}) -> !stream.resource<external>{%c16777216}
stream.yield %4 : !stream.resource<external>{%c16777216}
} => !stream.timepoint
%2 = stream.timepoint.await %result_timepoint => %results : !stream.resource<external>{%c16777216}
%3 = stream.tensor.export %2 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %3 : !hal.buffer_view
}
}
// -----// IR Dump Before FoldGlobals (iree-util-fold-globals) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
%c0_i32 = arith.constant 0 : i32
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%results, %result_timepoint = stream.async.execute with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}) -> !stream.resource<external>{%c16777216} {
%4 = stream.async.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg2[%c0 to %c16777216 for %c16777216], %arg3[%c0 to %c16777216 for %c16777216]) : (!stream.resource<external>{%c16777216}, !stream.resource<external>{%c16777216}) -> !stream.resource<external>{%c16777216}
stream.yield %4 : !stream.resource<external>{%c16777216}
} => !stream.timepoint
%2 = stream.timepoint.await %result_timepoint => %results : !stream.resource<external>{%c16777216}
%3 = stream.tensor.export %2 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %3 : !hal.buffer_view
}
}
// -----// IR Dump After FoldGlobals (iree-util-fold-globals) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
%c0_i32 = arith.constant 0 : i32
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%results, %result_timepoint = stream.async.execute with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}) -> !stream.resource<external>{%c16777216} {
%4 = stream.async.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg2[%c0 to %c16777216 for %c16777216], %arg3[%c0 to %c16777216 for %c16777216]) : (!stream.resource<external>{%c16777216}, !stream.resource<external>{%c16777216}) -> !stream.resource<external>{%c16777216}
stream.yield %4 : !stream.resource<external>{%c16777216}
} => !stream.timepoint
%2 = stream.timepoint.await %result_timepoint => %results : !stream.resource<external>{%c16777216}
%3 = stream.tensor.export %2 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %3 : !hal.buffer_view
}
}
// -----// IR Dump Before FuseGlobals (iree-util-fuse-globals) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
%c0_i32 = arith.constant 0 : i32
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%results, %result_timepoint = stream.async.execute with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}) -> !stream.resource<external>{%c16777216} {
%4 = stream.async.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg2[%c0 to %c16777216 for %c16777216], %arg3[%c0 to %c16777216 for %c16777216]) : (!stream.resource<external>{%c16777216}, !stream.resource<external>{%c16777216}) -> !stream.resource<external>{%c16777216}
stream.yield %4 : !stream.resource<external>{%c16777216}
} => !stream.timepoint
%2 = stream.timepoint.await %result_timepoint => %results : !stream.resource<external>{%c16777216}
%3 = stream.tensor.export %2 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %3 : !hal.buffer_view
}
}
// -----// IR Dump After FuseGlobals (iree-util-fuse-globals) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
%c0_i32 = arith.constant 0 : i32
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%results, %result_timepoint = stream.async.execute with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}) -> !stream.resource<external>{%c16777216} {
%4 = stream.async.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg2[%c0 to %c16777216 for %c16777216], %arg3[%c0 to %c16777216 for %c16777216]) : (!stream.resource<external>{%c16777216}, !stream.resource<external>{%c16777216}) -> !stream.resource<external>{%c16777216}
stream.yield %4 : !stream.resource<external>{%c16777216}
} => !stream.timepoint
%2 = stream.timepoint.await %result_timepoint => %results : !stream.resource<external>{%c16777216}
%3 = stream.tensor.export %2 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %3 : !hal.buffer_view
}
}
// -----// IR Dump Before IPO (iree-util-ipo) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
%c0_i32 = arith.constant 0 : i32
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%results, %result_timepoint = stream.async.execute with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}) -> !stream.resource<external>{%c16777216} {
%4 = stream.async.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg2[%c0 to %c16777216 for %c16777216], %arg3[%c0 to %c16777216 for %c16777216]) : (!stream.resource<external>{%c16777216}, !stream.resource<external>{%c16777216}) -> !stream.resource<external>{%c16777216}
stream.yield %4 : !stream.resource<external>{%c16777216}
} => !stream.timepoint
%2 = stream.timepoint.await %result_timepoint => %results : !stream.resource<external>{%c16777216}
%3 = stream.tensor.export %2 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %3 : !hal.buffer_view
}
}
// -----// IR Dump After IPO (iree-util-ipo) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
%c0_i32 = arith.constant 0 : i32
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%results, %result_timepoint = stream.async.execute with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}) -> !stream.resource<external>{%c16777216} {
%4 = stream.async.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg2[%c0 to %c16777216 for %c16777216], %arg3[%c0 to %c16777216 for %c16777216]) : (!stream.resource<external>{%c16777216}, !stream.resource<external>{%c16777216}) -> !stream.resource<external>{%c16777216}
stream.yield %4 : !stream.resource<external>{%c16777216}
} => !stream.timepoint
%2 = stream.timepoint.await %result_timepoint => %results : !stream.resource<external>{%c16777216}
%3 = stream.tensor.export %2 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %3 : !hal.buffer_view
}
}
// -----// IR Dump Before VerifyLoweringToAsyncPass (iree-stream-verify-lowering-to-async) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
%c0_i32 = arith.constant 0 : i32
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%results, %result_timepoint = stream.async.execute with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}) -> !stream.resource<external>{%c16777216} {
%4 = stream.async.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg2[%c0 to %c16777216 for %c16777216], %arg3[%c0 to %c16777216 for %c16777216]) : (!stream.resource<external>{%c16777216}, !stream.resource<external>{%c16777216}) -> !stream.resource<external>{%c16777216}
stream.yield %4 : !stream.resource<external>{%c16777216}
} => !stream.timepoint
%2 = stream.timepoint.await %result_timepoint => %results : !stream.resource<external>{%c16777216}
%3 = stream.tensor.export %2 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %3 : !hal.buffer_view
}
}
// -----// IR Dump After VerifyLoweringToAsyncPass (iree-stream-verify-lowering-to-async) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
%c0_i32 = arith.constant 0 : i32
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%results, %result_timepoint = stream.async.execute with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}) -> !stream.resource<external>{%c16777216} {
%4 = stream.async.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg2[%c0 to %c16777216 for %c16777216], %arg3[%c0 to %c16777216 for %c16777216]) : (!stream.resource<external>{%c16777216}, !stream.resource<external>{%c16777216}) -> !stream.resource<external>{%c16777216}
stream.yield %4 : !stream.resource<external>{%c16777216}
} => !stream.timepoint
%2 = stream.timepoint.await %result_timepoint => %results : !stream.resource<external>{%c16777216}
%3 = stream.tensor.export %2 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %3 : !hal.buffer_view
}
}
// -----// IR Dump Before ScheduleAllocationPass (iree-stream-schedule-allocation) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
%c0_i32 = arith.constant 0 : i32
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%results, %result_timepoint = stream.async.execute with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}) -> !stream.resource<external>{%c16777216} {
%4 = stream.async.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg2[%c0 to %c16777216 for %c16777216], %arg3[%c0 to %c16777216 for %c16777216]) : (!stream.resource<external>{%c16777216}, !stream.resource<external>{%c16777216}) -> !stream.resource<external>{%c16777216}
stream.yield %4 : !stream.resource<external>{%c16777216}
} => !stream.timepoint
%2 = stream.timepoint.await %result_timepoint => %results : !stream.resource<external>{%c16777216}
%3 = stream.tensor.export %2 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %3 : !hal.buffer_view
}
}
// -----// IR Dump After ScheduleAllocationPass (iree-stream-schedule-allocation) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
%c0_i32 = arith.constant 0 : i32
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%c0_0 = arith.constant 0 : index
%result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c16777216} => !stream.timepoint
%2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}, %result as %arg4: !stream.resource<external>{%c16777216}) {
stream.cmd.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32 {
ro %arg2[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
ro %arg3[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
wo %arg4[%c0_0 for %c16777216] : !stream.resource<external>{%c16777216}
}
} => !stream.timepoint
%3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c16777216}
%4 = stream.tensor.export %3 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %4 : !hal.buffer_view
}
}
// -----// IR Dump Before PackConstantsPass (iree-stream-pack-constants) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%c0_0 = arith.constant 0 : index
%result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c16777216} => !stream.timepoint
%2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}, %result as %arg4: !stream.resource<external>{%c16777216}) {
stream.cmd.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32 {
ro %arg2[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
ro %arg3[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
wo %arg4[%c0_0 for %c16777216] : !stream.resource<external>{%c16777216}
}
} => !stream.timepoint
%3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c16777216}
%4 = stream.tensor.export %3 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %4 : !hal.buffer_view
}
// -----// IR Dump After PackConstantsPass (iree-stream-pack-constants) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%c0_0 = arith.constant 0 : index
%result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c16777216} => !stream.timepoint
%2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}, %result as %arg4: !stream.resource<external>{%c16777216}) {
stream.cmd.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32 {
ro %arg2[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
ro %arg3[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
wo %arg4[%c0_0 for %c16777216] : !stream.resource<external>{%c16777216}
}
} => !stream.timepoint
%3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c16777216}
%4 = stream.tensor.export %3 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %4 : !hal.buffer_view
}
// -----// IR Dump Before LayoutSlicesPass (iree-stream-layout-slices) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%c0_0 = arith.constant 0 : index
%result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c16777216} => !stream.timepoint
%2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}, %result as %arg4: !stream.resource<external>{%c16777216}) {
stream.cmd.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32 {
ro %arg2[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
ro %arg3[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
wo %arg4[%c0_0 for %c16777216] : !stream.resource<external>{%c16777216}
}
} => !stream.timepoint
%3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c16777216}
%4 = stream.tensor.export %3 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %4 : !hal.buffer_view
}
// -----// IR Dump After LayoutSlicesPass (iree-stream-layout-slices) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%c0_0 = arith.constant 0 : index
%result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c16777216} => !stream.timepoint
%2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}, %result as %arg4: !stream.resource<external>{%c16777216}) {
stream.cmd.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32 {
ro %arg2[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
ro %arg3[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
wo %arg4[%c0_0 for %c16777216] : !stream.resource<external>{%c16777216}
}
} => !stream.timepoint
%3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c16777216}
%4 = stream.tensor.export %3 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %4 : !hal.buffer_view
}
// -----// IR Dump Before PropagateSubranges (iree-util-propagate-subranges) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
%c0_i32 = arith.constant 0 : i32
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%c0_0 = arith.constant 0 : index
%result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c16777216} => !stream.timepoint
%2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}, %result as %arg4: !stream.resource<external>{%c16777216}) {
stream.cmd.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32 {
ro %arg2[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
ro %arg3[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
wo %arg4[%c0_0 for %c16777216] : !stream.resource<external>{%c16777216}
}
} => !stream.timepoint
%3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c16777216}
%4 = stream.tensor.export %3 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %4 : !hal.buffer_view
}
}
// -----// IR Dump After PropagateSubranges (iree-util-propagate-subranges) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
%c0_i32 = arith.constant 0 : i32
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%c0_0 = arith.constant 0 : index
%result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c16777216} => !stream.timepoint
%2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}, %result as %arg4: !stream.resource<external>{%c16777216}) {
stream.cmd.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32 {
ro %arg2[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
ro %arg3[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
wo %arg4[%c0_0 for %c16777216] : !stream.resource<external>{%c16777216}
}
} => !stream.timepoint
%3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c16777216}
%4 = stream.tensor.export %3 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %4 : !hal.buffer_view
}
}
// -----// IR Dump Before Canonicalizer (canonicalize) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%c0_0 = arith.constant 0 : index
%result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c16777216} => !stream.timepoint
%2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}, %result as %arg4: !stream.resource<external>{%c16777216}) {
stream.cmd.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32 {
ro %arg2[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
ro %arg3[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
wo %arg4[%c0_0 for %c16777216] : !stream.resource<external>{%c16777216}
}
} => !stream.timepoint
%3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c16777216}
%4 = stream.tensor.export %3 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %4 : !hal.buffer_view
}
// -----// IR Dump After Canonicalizer (canonicalize) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c16777216} => !stream.timepoint
%2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}, %result as %arg4: !stream.resource<external>{%c16777216}) {
stream.cmd.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32 {
ro %arg2[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
ro %arg3[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
wo %arg4[%c0 for %c16777216] : !stream.resource<external>{%c16777216}
}
} => !stream.timepoint
%3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c16777216}
%4 = stream.tensor.export %3 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %4 : !hal.buffer_view
}
// -----// IR Dump Before CSE (cse) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c16777216} => !stream.timepoint
%2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}, %result as %arg4: !stream.resource<external>{%c16777216}) {
stream.cmd.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32 {
ro %arg2[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
ro %arg3[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
wo %arg4[%c0 for %c16777216] : !stream.resource<external>{%c16777216}
}
} => !stream.timepoint
%3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c16777216}
%4 = stream.tensor.export %3 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %4 : !hal.buffer_view
}
// -----// IR Dump After CSE (cse) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c16777216} => !stream.timepoint
%2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}, %result as %arg4: !stream.resource<external>{%c16777216}) {
stream.cmd.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32 {
ro %arg2[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
ro %arg3[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
wo %arg4[%c0 for %c16777216] : !stream.resource<external>{%c16777216}
}
} => !stream.timepoint
%3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c16777216}
%4 = stream.tensor.export %3 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %4 : !hal.buffer_view
}
// -----// IR Dump Before SimplifyGlobalAccesses (iree-util-simplify-global-accesses) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c16777216} => !stream.timepoint
%2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}, %result as %arg4: !stream.resource<external>{%c16777216}) {
stream.cmd.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32 {
ro %arg2[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
ro %arg3[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
wo %arg4[%c0 for %c16777216] : !stream.resource<external>{%c16777216}
}
} => !stream.timepoint
%3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c16777216}
%4 = stream.tensor.export %3 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %4 : !hal.buffer_view
}
// -----// IR Dump After SimplifyGlobalAccesses (iree-util-simplify-global-accesses) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c16777216} => !stream.timepoint
%2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}, %result as %arg4: !stream.resource<external>{%c16777216}) {
stream.cmd.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32 {
ro %arg2[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
ro %arg3[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
wo %arg4[%c0 for %c16777216] : !stream.resource<external>{%c16777216}
}
} => !stream.timepoint
%3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c16777216}
%4 = stream.tensor.export %3 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %4 : !hal.buffer_view
}
// -----// IR Dump Before ApplyPatterns (iree-util-apply-patterns) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
%c0_i32 = arith.constant 0 : i32
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c16777216} => !stream.timepoint
%2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}, %result as %arg4: !stream.resource<external>{%c16777216}) {
stream.cmd.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32 {
ro %arg2[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
ro %arg3[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
wo %arg4[%c0 for %c16777216] : !stream.resource<external>{%c16777216}
}
} => !stream.timepoint
%3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c16777216}
%4 = stream.tensor.export %3 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %4 : !hal.buffer_view
}
}
// -----// IR Dump After ApplyPatterns (iree-util-apply-patterns) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
%c0_i32 = arith.constant 0 : i32
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c16777216} => !stream.timepoint
%2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}, %result as %arg4: !stream.resource<external>{%c16777216}) {
stream.cmd.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32 {
ro %arg2[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
ro %arg3[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
wo %arg4[%c0 for %c16777216] : !stream.resource<external>{%c16777216}
}
} => !stream.timepoint
%3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c16777216}
%4 = stream.tensor.export %3 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %4 : !hal.buffer_view
}
}
// -----// IR Dump Before FoldGlobals (iree-util-fold-globals) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
%c0_i32 = arith.constant 0 : i32
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c16777216} => !stream.timepoint
%2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}, %result as %arg4: !stream.resource<external>{%c16777216}) {
stream.cmd.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32 {
ro %arg2[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
ro %arg3[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
wo %arg4[%c0 for %c16777216] : !stream.resource<external>{%c16777216}
}
} => !stream.timepoint
%3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c16777216}
%4 = stream.tensor.export %3 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %4 : !hal.buffer_view
}
}
// -----// IR Dump After FoldGlobals (iree-util-fold-globals) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
%c0_i32 = arith.constant 0 : i32
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c16777216} => !stream.timepoint
%2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}, %result as %arg4: !stream.resource<external>{%c16777216}) {
stream.cmd.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32 {
ro %arg2[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
ro %arg3[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
wo %arg4[%c0 for %c16777216] : !stream.resource<external>{%c16777216}
}
} => !stream.timepoint
%3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c16777216}
%4 = stream.tensor.export %3 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %4 : !hal.buffer_view
}
}
// -----// IR Dump Before FuseGlobals (iree-util-fuse-globals) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
%c0_i32 = arith.constant 0 : i32
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c16777216} => !stream.timepoint
%2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}, %result as %arg4: !stream.resource<external>{%c16777216}) {
stream.cmd.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32 {
ro %arg2[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
ro %arg3[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
wo %arg4[%c0 for %c16777216] : !stream.resource<external>{%c16777216}
}
} => !stream.timepoint
%3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c16777216}
%4 = stream.tensor.export %3 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %4 : !hal.buffer_view
}
}
// -----// IR Dump After FuseGlobals (iree-util-fuse-globals) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
%c0_i32 = arith.constant 0 : i32
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c16777216} => !stream.timepoint
%2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}, %result as %arg4: !stream.resource<external>{%c16777216}) {
stream.cmd.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32 {
ro %arg2[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
ro %arg3[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
wo %arg4[%c0 for %c16777216] : !stream.resource<external>{%c16777216}
}
} => !stream.timepoint
%3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c16777216}
%4 = stream.tensor.export %3 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %4 : !hal.buffer_view
}
}
// -----// IR Dump Before IPO (iree-util-ipo) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
%c0_i32 = arith.constant 0 : i32
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c16777216} => !stream.timepoint
%2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}, %result as %arg4: !stream.resource<external>{%c16777216}) {
stream.cmd.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32 {
ro %arg2[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
ro %arg3[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
wo %arg4[%c0 for %c16777216] : !stream.resource<external>{%c16777216}
}
} => !stream.timepoint
%3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c16777216}
%4 = stream.tensor.export %3 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %4 : !hal.buffer_view
}
}
// -----// IR Dump After IPO (iree-util-ipo) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
%c0_i32 = arith.constant 0 : i32
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c16777216} => !stream.timepoint
%2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}, %result as %arg4: !stream.resource<external>{%c16777216}) {
stream.cmd.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32 {
ro %arg2[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
ro %arg3[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
wo %arg4[%c0 for %c16777216] : !stream.resource<external>{%c16777216}
}
} => !stream.timepoint
%3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c16777216}
%4 = stream.tensor.export %3 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %4 : !hal.buffer_view
}
}
// -----// IR Dump Before VerifyLoweringToCmdPass (iree-stream-verify-lowering-to-cmd) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
%c0_i32 = arith.constant 0 : i32
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c16777216} => !stream.timepoint
%2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}, %result as %arg4: !stream.resource<external>{%c16777216}) {
stream.cmd.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32 {
ro %arg2[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
ro %arg3[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
wo %arg4[%c0 for %c16777216] : !stream.resource<external>{%c16777216}
}
} => !stream.timepoint
%3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c16777216}
%4 = stream.tensor.export %3 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %4 : !hal.buffer_view
}
}
// -----// IR Dump After VerifyLoweringToCmdPass (iree-stream-verify-lowering-to-cmd) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
%c0_i32 = arith.constant 0 : i32
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c16777216} => !stream.timepoint
%2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}, %result as %arg4: !stream.resource<external>{%c16777216}) {
stream.cmd.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32 {
ro %arg2[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
ro %arg3[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
wo %arg4[%c0 for %c16777216] : !stream.resource<external>{%c16777216}
}
} => !stream.timepoint
%3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c16777216}
%4 = stream.tensor.export %3 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %4 : !hal.buffer_view
}
}
// -----// IR Dump Before Canonicalizer (canonicalize) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c16777216} => !stream.timepoint
%2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}, %result as %arg4: !stream.resource<external>{%c16777216}) {
stream.cmd.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32 {
ro %arg2[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
ro %arg3[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
wo %arg4[%c0 for %c16777216] : !stream.resource<external>{%c16777216}
}
} => !stream.timepoint
%3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c16777216}
%4 = stream.tensor.export %3 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %4 : !hal.buffer_view
}
// -----// IR Dump After Canonicalizer (canonicalize) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c16777216} => !stream.timepoint
%2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}, %result as %arg4: !stream.resource<external>{%c16777216}) {
stream.cmd.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32 {
ro %arg2[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
ro %arg3[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
wo %arg4[%c0 for %c16777216] : !stream.resource<external>{%c16777216}
}
} => !stream.timepoint
%3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c16777216}
%4 = stream.tensor.export %3 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %4 : !hal.buffer_view
}
// -----// IR Dump Before CSE (cse) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c16777216} => !stream.timepoint
%2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}, %result as %arg4: !stream.resource<external>{%c16777216}) {
stream.cmd.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32 {
ro %arg2[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
ro %arg3[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
wo %arg4[%c0 for %c16777216] : !stream.resource<external>{%c16777216}
}
} => !stream.timepoint
%3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c16777216}
%4 = stream.tensor.export %3 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %4 : !hal.buffer_view
}
// -----// IR Dump After CSE (cse) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c16777216} => !stream.timepoint
%2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}, %result as %arg4: !stream.resource<external>{%c16777216}) {
stream.cmd.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32 {
ro %arg2[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
ro %arg3[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
wo %arg4[%c0 for %c16777216] : !stream.resource<external>{%c16777216}
}
} => !stream.timepoint
%3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c16777216}
%4 = stream.tensor.export %3 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %4 : !hal.buffer_view
}
// -----// IR Dump Before SimplifyGlobalAccesses (iree-util-simplify-global-accesses) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c16777216} => !stream.timepoint
%2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}, %result as %arg4: !stream.resource<external>{%c16777216}) {
stream.cmd.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32 {
ro %arg2[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
ro %arg3[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
wo %arg4[%c0 for %c16777216] : !stream.resource<external>{%c16777216}
}
} => !stream.timepoint
%3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c16777216}
%4 = stream.tensor.export %3 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %4 : !hal.buffer_view
}
// -----// IR Dump After SimplifyGlobalAccesses (iree-util-simplify-global-accesses) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c16777216} => !stream.timepoint
%2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}, %result as %arg4: !stream.resource<external>{%c16777216}) {
stream.cmd.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32 {
ro %arg2[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
ro %arg3[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
wo %arg4[%c0 for %c16777216] : !stream.resource<external>{%c16777216}
}
} => !stream.timepoint
%3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c16777216}
%4 = stream.tensor.export %3 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %4 : !hal.buffer_view
}
// -----// IR Dump Before ApplyPatterns (iree-util-apply-patterns) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
%c0_i32 = arith.constant 0 : i32
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c16777216} => !stream.timepoint
%2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}, %result as %arg4: !stream.resource<external>{%c16777216}) {
stream.cmd.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32 {
ro %arg2[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
ro %arg3[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
wo %arg4[%c0 for %c16777216] : !stream.resource<external>{%c16777216}
}
} => !stream.timepoint
%3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c16777216}
%4 = stream.tensor.export %3 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %4 : !hal.buffer_view
}
}
// -----// IR Dump After ApplyPatterns (iree-util-apply-patterns) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
%c0_i32 = arith.constant 0 : i32
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c16777216} => !stream.timepoint
%2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}, %result as %arg4: !stream.resource<external>{%c16777216}) {
stream.cmd.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32 {
ro %arg2[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
ro %arg3[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
wo %arg4[%c0 for %c16777216] : !stream.resource<external>{%c16777216}
}
} => !stream.timepoint
%3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c16777216}
%4 = stream.tensor.export %3 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %4 : !hal.buffer_view
}
}
// -----// IR Dump Before FoldGlobals (iree-util-fold-globals) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
%c0_i32 = arith.constant 0 : i32
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c16777216} => !stream.timepoint
%2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}, %result as %arg4: !stream.resource<external>{%c16777216}) {
stream.cmd.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32 {
ro %arg2[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
ro %arg3[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
wo %arg4[%c0 for %c16777216] : !stream.resource<external>{%c16777216}
}
} => !stream.timepoint
%3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c16777216}
%4 = stream.tensor.export %3 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %4 : !hal.buffer_view
}
}
// -----// IR Dump After FoldGlobals (iree-util-fold-globals) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
%c0_i32 = arith.constant 0 : i32
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c16777216} => !stream.timepoint
%2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}, %result as %arg4: !stream.resource<external>{%c16777216}) {
stream.cmd.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32 {
ro %arg2[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
ro %arg3[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
wo %arg4[%c0 for %c16777216] : !stream.resource<external>{%c16777216}
}
} => !stream.timepoint
%3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c16777216}
%4 = stream.tensor.export %3 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %4 : !hal.buffer_view
}
}
// -----// IR Dump Before FuseGlobals (iree-util-fuse-globals) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
%c0_i32 = arith.constant 0 : i32
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c16777216} => !stream.timepoint
%2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}, %result as %arg4: !stream.resource<external>{%c16777216}) {
stream.cmd.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32 {
ro %arg2[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
ro %arg3[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
wo %arg4[%c0 for %c16777216] : !stream.resource<external>{%c16777216}
}
} => !stream.timepoint
%3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c16777216}
%4 = stream.tensor.export %3 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %4 : !hal.buffer_view
}
}
// -----// IR Dump After FuseGlobals (iree-util-fuse-globals) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
%c0_i32 = arith.constant 0 : i32
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c16777216} => !stream.timepoint
%2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}, %result as %arg4: !stream.resource<external>{%c16777216}) {
stream.cmd.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32 {
ro %arg2[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
ro %arg3[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
wo %arg4[%c0 for %c16777216] : !stream.resource<external>{%c16777216}
}
} => !stream.timepoint
%3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c16777216}
%4 = stream.tensor.export %3 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %4 : !hal.buffer_view
}
}
// -----// IR Dump Before IPO (iree-util-ipo) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
%c0_i32 = arith.constant 0 : i32
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c16777216} => !stream.timepoint
%2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}, %result as %arg4: !stream.resource<external>{%c16777216}) {
stream.cmd.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32 {
ro %arg2[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
ro %arg3[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
wo %arg4[%c0 for %c16777216] : !stream.resource<external>{%c16777216}
}
} => !stream.timepoint
%3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c16777216}
%4 = stream.tensor.export %3 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %4 : !hal.buffer_view
}
}
// -----// IR Dump After IPO (iree-util-ipo) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
%c0_i32 = arith.constant 0 : i32
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c16777216} => !stream.timepoint
%2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}, %result as %arg4: !stream.resource<external>{%c16777216}) {
stream.cmd.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32 {
ro %arg2[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
ro %arg3[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
wo %arg4[%c0 for %c16777216] : !stream.resource<external>{%c16777216}
}
} => !stream.timepoint
%3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c16777216}
%4 = stream.tensor.export %3 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %4 : !hal.buffer_view
}
}
// -----// IR Dump Before SCFToControlFlow (convert-scf-to-cf) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c16777216} => !stream.timepoint
%2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}, %result as %arg4: !stream.resource<external>{%c16777216}) {
stream.cmd.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32 {
ro %arg2[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
ro %arg3[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
wo %arg4[%c0 for %c16777216] : !stream.resource<external>{%c16777216}
}
} => !stream.timepoint
%3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c16777216}
%4 = stream.tensor.export %3 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %4 : !hal.buffer_view
}
// -----// IR Dump After SCFToControlFlow (convert-scf-to-cf) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c16777216} => !stream.timepoint
%2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}, %result as %arg4: !stream.resource<external>{%c16777216}) {
stream.cmd.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32 {
ro %arg2[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
ro %arg3[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
wo %arg4[%c0 for %c16777216] : !stream.resource<external>{%c16777216}
}
} => !stream.timepoint
%3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c16777216}
%4 = stream.tensor.export %3 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %4 : !hal.buffer_view
}
// -----// IR Dump Before FixedPointIterator (iree-util-fixed-point-iterator) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
%c0_i32 = arith.constant 0 : i32
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c16777216} => !stream.timepoint
%2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}, %result as %arg4: !stream.resource<external>{%c16777216}) {
stream.cmd.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32 {
ro %arg2[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
ro %arg3[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
wo %arg4[%c0 for %c16777216] : !stream.resource<external>{%c16777216}
}
} => !stream.timepoint
%3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c16777216}
%4 = stream.tensor.export %3 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %4 : !hal.buffer_view
}
}
// -----// IR Dump Before Canonicalizer (canonicalize) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c16777216} => !stream.timepoint
%2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}, %result as %arg4: !stream.resource<external>{%c16777216}) {
stream.cmd.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32 {
ro %arg2[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
ro %arg3[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
wo %arg4[%c0 for %c16777216] : !stream.resource<external>{%c16777216}
}
} => !stream.timepoint
%3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c16777216}
%4 = stream.tensor.export %3 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %4 : !hal.buffer_view
}
// -----// IR Dump After Canonicalizer (canonicalize) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c16777216} => !stream.timepoint
%2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}, %result as %arg4: !stream.resource<external>{%c16777216}) {
stream.cmd.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32 {
ro %arg2[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
ro %arg3[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
wo %arg4[%c0 for %c16777216] : !stream.resource<external>{%c16777216}
}
} => !stream.timepoint
%3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c16777216}
%4 = stream.tensor.export %3 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %4 : !hal.buffer_view
}
// -----// IR Dump Before CSE (cse) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c16777216} => !stream.timepoint
%2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}, %result as %arg4: !stream.resource<external>{%c16777216}) {
stream.cmd.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32 {
ro %arg2[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
ro %arg3[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
wo %arg4[%c0 for %c16777216] : !stream.resource<external>{%c16777216}
}
} => !stream.timepoint
%3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c16777216}
%4 = stream.tensor.export %3 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %4 : !hal.buffer_view
}
// -----// IR Dump After CSE (cse) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c16777216} => !stream.timepoint
%2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}, %result as %arg4: !stream.resource<external>{%c16777216}) {
stream.cmd.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32 {
ro %arg2[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
ro %arg3[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
wo %arg4[%c0 for %c16777216] : !stream.resource<external>{%c16777216}
}
} => !stream.timepoint
%3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c16777216}
%4 = stream.tensor.export %3 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %4 : !hal.buffer_view
}
// -----// IR Dump Before SimplifyGlobalAccesses (iree-util-simplify-global-accesses) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c16777216} => !stream.timepoint
%2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}, %result as %arg4: !stream.resource<external>{%c16777216}) {
stream.cmd.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32 {
ro %arg2[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
ro %arg3[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
wo %arg4[%c0 for %c16777216] : !stream.resource<external>{%c16777216}
}
} => !stream.timepoint
%3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c16777216}
%4 = stream.tensor.export %3 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %4 : !hal.buffer_view
}
// -----// IR Dump After SimplifyGlobalAccesses (iree-util-simplify-global-accesses) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c16777216} => !stream.timepoint
%2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}, %result as %arg4: !stream.resource<external>{%c16777216}) {
stream.cmd.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32 {
ro %arg2[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
ro %arg3[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
wo %arg4[%c0 for %c16777216] : !stream.resource<external>{%c16777216}
}
} => !stream.timepoint
%3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c16777216}
%4 = stream.tensor.export %3 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %4 : !hal.buffer_view
}
// -----// IR Dump Before ApplyPatterns (iree-util-apply-patterns) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie], iree.fixedpoint.iteration = 0 : index} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
%c0_i32 = arith.constant 0 : i32
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c16777216} => !stream.timepoint
%2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}, %result as %arg4: !stream.resource<external>{%c16777216}) {
stream.cmd.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32 {
ro %arg2[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
ro %arg3[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
wo %arg4[%c0 for %c16777216] : !stream.resource<external>{%c16777216}
}
} => !stream.timepoint
%3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c16777216}
%4 = stream.tensor.export %3 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %4 : !hal.buffer_view
}
}
// -----// IR Dump After ApplyPatterns (iree-util-apply-patterns) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie], iree.fixedpoint.iteration = 0 : index} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
%c0_i32 = arith.constant 0 : i32
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c16777216} => !stream.timepoint
%2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}, %result as %arg4: !stream.resource<external>{%c16777216}) {
stream.cmd.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32 {
ro %arg2[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
ro %arg3[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
wo %arg4[%c0 for %c16777216] : !stream.resource<external>{%c16777216}
}
} => !stream.timepoint
%3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c16777216}
%4 = stream.tensor.export %3 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %4 : !hal.buffer_view
}
}
// -----// IR Dump Before FoldGlobals (iree-util-fold-globals) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie], iree.fixedpoint.iteration = 0 : index} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
%c0_i32 = arith.constant 0 : i32
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c16777216} => !stream.timepoint
%2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}, %result as %arg4: !stream.resource<external>{%c16777216}) {
stream.cmd.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32 {
ro %arg2[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
ro %arg3[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
wo %arg4[%c0 for %c16777216] : !stream.resource<external>{%c16777216}
}
} => !stream.timepoint
%3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c16777216}
%4 = stream.tensor.export %3 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %4 : !hal.buffer_view
}
}
// -----// IR Dump After FoldGlobals (iree-util-fold-globals) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie], iree.fixedpoint.iteration = 0 : index} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
%c0_i32 = arith.constant 0 : i32
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c16777216} => !stream.timepoint
%2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}, %result as %arg4: !stream.resource<external>{%c16777216}) {
stream.cmd.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32 {
ro %arg2[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
ro %arg3[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
wo %arg4[%c0 for %c16777216] : !stream.resource<external>{%c16777216}
}
} => !stream.timepoint
%3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c16777216}
%4 = stream.tensor.export %3 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %4 : !hal.buffer_view
}
}
// -----// IR Dump Before FuseGlobals (iree-util-fuse-globals) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie], iree.fixedpoint.iteration = 0 : index} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
%c0_i32 = arith.constant 0 : i32
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c16777216} => !stream.timepoint
%2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}, %result as %arg4: !stream.resource<external>{%c16777216}) {
stream.cmd.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32 {
ro %arg2[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
ro %arg3[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
wo %arg4[%c0 for %c16777216] : !stream.resource<external>{%c16777216}
}
} => !stream.timepoint
%3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c16777216}
%4 = stream.tensor.export %3 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %4 : !hal.buffer_view
}
}
// -----// IR Dump After FuseGlobals (iree-util-fuse-globals) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie], iree.fixedpoint.iteration = 0 : index} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
%c0_i32 = arith.constant 0 : i32
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c16777216} => !stream.timepoint
%2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}, %result as %arg4: !stream.resource<external>{%c16777216}) {
stream.cmd.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32 {
ro %arg2[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
ro %arg3[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
wo %arg4[%c0 for %c16777216] : !stream.resource<external>{%c16777216}
}
} => !stream.timepoint
%3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c16777216}
%4 = stream.tensor.export %3 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %4 : !hal.buffer_view
}
}
// -----// IR Dump Before IPO (iree-util-ipo) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie], iree.fixedpoint.iteration = 0 : index} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
%c0_i32 = arith.constant 0 : i32
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c16777216} => !stream.timepoint
%2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}, %result as %arg4: !stream.resource<external>{%c16777216}) {
stream.cmd.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32 {
ro %arg2[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
ro %arg3[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
wo %arg4[%c0 for %c16777216] : !stream.resource<external>{%c16777216}
}
} => !stream.timepoint
%3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c16777216}
%4 = stream.tensor.export %3 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %4 : !hal.buffer_view
}
}
// -----// IR Dump After IPO (iree-util-ipo) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie], iree.fixedpoint.iteration = 0 : index} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
%c0_i32 = arith.constant 0 : i32
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c16777216} => !stream.timepoint
%2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}, %result as %arg4: !stream.resource<external>{%c16777216}) {
stream.cmd.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32 {
ro %arg2[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
ro %arg3[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
wo %arg4[%c0 for %c16777216] : !stream.resource<external>{%c16777216}
}
} => !stream.timepoint
%3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c16777216}
%4 = stream.tensor.export %3 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %4 : !hal.buffer_view
}
}
// -----// IR Dump Before ElideTimepointsPass (iree-stream-elide-timepoints) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie], iree.fixedpoint.iteration = 0 : index} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
%c0_i32 = arith.constant 0 : i32
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c16777216} => !stream.timepoint
%2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}, %result as %arg4: !stream.resource<external>{%c16777216}) {
stream.cmd.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32 {
ro %arg2[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
ro %arg3[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
wo %arg4[%c0 for %c16777216] : !stream.resource<external>{%c16777216}
}
} => !stream.timepoint
%3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c16777216}
%4 = stream.tensor.export %3 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %4 : !hal.buffer_view
}
}
// -----// IR Dump After ElideTimepointsPass (iree-stream-elide-timepoints) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie], iree.fixedpoint.iteration = 0 : index} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
%c0_i32 = arith.constant 0 : i32
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c16777216} => !stream.timepoint
%2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}, %result as %arg4: !stream.resource<external>{%c16777216}) {
stream.cmd.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32 {
ro %arg2[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
ro %arg3[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
wo %arg4[%c0 for %c16777216] : !stream.resource<external>{%c16777216}
}
} => !stream.timepoint
%3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c16777216}
%4 = stream.tensor.export %3 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %4 : !hal.buffer_view
}
}
// -----// IR Dump After FixedPointIterator (iree-util-fixed-point-iterator) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
%c0_i32 = arith.constant 0 : i32
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c16777216} => !stream.timepoint
%2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}, %result as %arg4: !stream.resource<external>{%c16777216}) {
stream.cmd.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32 {
ro %arg2[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
ro %arg3[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
wo %arg4[%c0 for %c16777216] : !stream.resource<external>{%c16777216}
}
} => !stream.timepoint
%3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c16777216}
%4 = stream.tensor.export %3 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %4 : !hal.buffer_view
}
}
// -----// IR Dump Before FuseDispatchBindingsPass (iree-stream-fuse-dispatch-bindings) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
%c0_i32 = arith.constant 0 : i32
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c16777216} => !stream.timepoint
%2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}, %result as %arg4: !stream.resource<external>{%c16777216}) {
stream.cmd.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32 {
ro %arg2[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
ro %arg3[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
wo %arg4[%c0 for %c16777216] : !stream.resource<external>{%c16777216}
}
} => !stream.timepoint
%3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c16777216}
%4 = stream.tensor.export %3 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %4 : !hal.buffer_view
}
}
// -----// IR Dump After FuseDispatchBindingsPass (iree-stream-fuse-dispatch-bindings) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding, %arg3: index, %arg4: index, %arg5: index) {
%c0_i32 = arith.constant 0 : i32
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%arg3] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%arg4] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%arg5] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c16777216} => !stream.timepoint
%c0_0 = arith.constant 0 : index
%2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}, %result as %arg4: !stream.resource<external>{%c16777216}) {
stream.cmd.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%c0, %c0, %c0 : index, index, index) {
ro %arg2[%c0_0 for %c16777216] : !stream.resource<external>{%c16777216},
ro %arg3[%c0_0 for %c16777216] : !stream.resource<external>{%c16777216},
wo %arg4[%c0_0 for %c16777216] : !stream.resource<external>{%c16777216}
}
} => !stream.timepoint
%3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c16777216}
%4 = stream.tensor.export %3 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %4 : !hal.buffer_view
}
}
// -----// IR Dump Before AnnotateDispatchArgumentsPass (iree-stream-annotate-dispatch-arguments) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding, %arg3: index, %arg4: index, %arg5: index) {
%c0_i32 = arith.constant 0 : i32
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%arg3] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%arg4] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%arg5] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c16777216} => !stream.timepoint
%c0_0 = arith.constant 0 : index
%2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}, %result as %arg4: !stream.resource<external>{%c16777216}) {
stream.cmd.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%c0, %c0, %c0 : index, index, index) {
ro %arg2[%c0_0 for %c16777216] : !stream.resource<external>{%c16777216},
ro %arg3[%c0_0 for %c16777216] : !stream.resource<external>{%c16777216},
wo %arg4[%c0_0 for %c16777216] : !stream.resource<external>{%c16777216}
}
} => !stream.timepoint
%3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c16777216}
%4 = stream.tensor.export %3 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %4 : !hal.buffer_view
}
}
// -----// IR Dump After AnnotateDispatchArgumentsPass (iree-stream-annotate-dispatch-arguments) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding {stream.alignment = 64 : index}, %arg1: !stream.binding {stream.alignment = 64 : index}, %arg2: !stream.binding {stream.alignment = 64 : index}, %arg3: index {stream.values = [0 : index]}, %arg4: index {stream.values = [0 : index]}, %arg5: index {stream.values = [0 : index]}) {
%c0_i32 = arith.constant 0 : i32
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%arg3] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%arg4] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%arg5] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c16777216} => !stream.timepoint
%c0_0 = arith.constant 0 : index
%2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}, %result as %arg4: !stream.resource<external>{%c16777216}) {
stream.cmd.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%c0, %c0, %c0 : index, index, index) {
ro %arg2[%c0_0 for %c16777216] : !stream.resource<external>{%c16777216},
ro %arg3[%c0_0 for %c16777216] : !stream.resource<external>{%c16777216},
wo %arg4[%c0_0 for %c16777216] : !stream.resource<external>{%c16777216}
}
} => !stream.timepoint
%3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c16777216}
%4 = stream.tensor.export %3 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %4 : !hal.buffer_view
}
}
// -----// IR Dump Before PackDispatchOperandsPass (iree-stream-pack-dispatch-operands) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding {stream.alignment = 64 : index}, %arg1: !stream.binding {stream.alignment = 64 : index}, %arg2: !stream.binding {stream.alignment = 64 : index}, %arg3: index {stream.values = [0 : index]}, %arg4: index {stream.values = [0 : index]}, %arg5: index {stream.values = [0 : index]}) {
%c0_i32 = arith.constant 0 : i32
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%arg3] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%arg4] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%arg5] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c16777216} => !stream.timepoint
%c0_0 = arith.constant 0 : index
%2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}, %result as %arg4: !stream.resource<external>{%c16777216}) {
stream.cmd.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%c0, %c0, %c0 : index, index, index) {
ro %arg2[%c0_0 for %c16777216] : !stream.resource<external>{%c16777216},
ro %arg3[%c0_0 for %c16777216] : !stream.resource<external>{%c16777216},
wo %arg4[%c0_0 for %c16777216] : !stream.resource<external>{%c16777216}
}
} => !stream.timepoint
%3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c16777216}
%4 = stream.tensor.export %3 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %4 : !hal.buffer_view
}
}
// -----// IR Dump After PackDispatchOperandsPass (iree-stream-pack-dispatch-operands) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding {stream.alignment = 64 : index}, %arg1: !stream.binding {stream.alignment = 64 : index}, %arg2: !stream.binding {stream.alignment = 64 : index}, %arg3: i32, %arg4: i32, %arg5: i32, %arg6: i32, %arg7: i32, %arg8: i32) {
%0 = arith.extui %arg3 : i32 to i64
%1 = arith.extui %arg4 : i32 to i64
%c32_i64 = arith.constant 32 : i64
%2 = arith.shli %1, %c32_i64 : i64
%3 = arith.ori %0, %2 : i64
%4 = arith.index_castui %3 {stream.values = [0 : index]} : i64 to index
%5 = arith.extui %arg5 : i32 to i64
%6 = arith.extui %arg6 : i32 to i64
%c32_i64_0 = arith.constant 32 : i64
%7 = arith.shli %6, %c32_i64_0 : i64
%8 = arith.ori %5, %7 : i64
%9 = arith.index_castui %8 {stream.values = [0 : index]} : i64 to index
%10 = arith.extui %arg7 : i32 to i64
%11 = arith.extui %arg8 : i32 to i64
%c32_i64_1 = arith.constant 32 : i64
%12 = arith.shli %11, %c32_i64_1 : i64
%13 = arith.ori %10, %12 : i64
%14 = arith.index_castui %13 {stream.values = [0 : index]} : i64 to index
%c0_i32 = arith.constant 0 : i32
%c0 = arith.constant 0 : index
%15 = stream.binding.subspan %arg0[%4] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%16 = stream.binding.subspan %arg1[%9] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%17 = stream.binding.subspan %arg2[%14] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%18 = flow.dispatch.tensor.load %15, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%19 = flow.dispatch.tensor.load %16, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%20 = tensor.empty() : tensor<2048x2048xi32>
%21 = linalg.fill ins(%c0_i32 : i32) outs(%20 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%22 = linalg.matmul ins(%18, %19 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%21 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %22, %17, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c16777216} => !stream.timepoint
%c0_0 = arith.constant 0 : index
%c0_i64 = arith.constant 0 : i64
%c0_i32 = arith.constant 0 : i32
%c32_i64 = arith.constant 32 : i64
%c0_i64_1 = arith.constant 0 : i64
%c0_i32_2 = arith.constant 0 : i32
%c0_i64_3 = arith.constant 0 : i64
%c0_i32_4 = arith.constant 0 : i32
%c32_i64_5 = arith.constant 32 : i64
%c0_i64_6 = arith.constant 0 : i64
%c0_i32_7 = arith.constant 0 : i32
%c0_i64_8 = arith.constant 0 : i64
%c0_i32_9 = arith.constant 0 : i32
%c32_i64_10 = arith.constant 32 : i64
%c0_i64_11 = arith.constant 0 : i64
%c0_i32_12 = arith.constant 0 : i32
%2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}, %result as %arg4: !stream.resource<external>{%c16777216}) {
stream.cmd.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%c0_i32, %c0_i32_2, %c0_i32_4, %c0_i32_7, %c0_i32_9, %c0_i32_12 : i32, i32, i32, i32, i32, i32) {
ro %arg2[%c0_0 for %c16777216] : !stream.resource<external>{%c16777216},
ro %arg3[%c0_0 for %c16777216] : !stream.resource<external>{%c16777216},
wo %arg4[%c0_0 for %c16777216] : !stream.resource<external>{%c16777216}
}
} => !stream.timepoint
%3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c16777216}
%4 = stream.tensor.export %3 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %4 : !hal.buffer_view
}
}
// -----// IR Dump Before Canonicalizer (canonicalize) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c16777216} => !stream.timepoint
%c0_0 = arith.constant 0 : index
%c0_i64 = arith.constant 0 : i64
%c0_i32 = arith.constant 0 : i32
%c32_i64 = arith.constant 32 : i64
%c0_i64_1 = arith.constant 0 : i64
%c0_i32_2 = arith.constant 0 : i32
%c0_i64_3 = arith.constant 0 : i64
%c0_i32_4 = arith.constant 0 : i32
%c32_i64_5 = arith.constant 32 : i64
%c0_i64_6 = arith.constant 0 : i64
%c0_i32_7 = arith.constant 0 : i32
%c0_i64_8 = arith.constant 0 : i64
%c0_i32_9 = arith.constant 0 : i32
%c32_i64_10 = arith.constant 32 : i64
%c0_i64_11 = arith.constant 0 : i64
%c0_i32_12 = arith.constant 0 : i32
%2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}, %result as %arg4: !stream.resource<external>{%c16777216}) {
stream.cmd.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%c0_i32, %c0_i32_2, %c0_i32_4, %c0_i32_7, %c0_i32_9, %c0_i32_12 : i32, i32, i32, i32, i32, i32) {
ro %arg2[%c0_0 for %c16777216] : !stream.resource<external>{%c16777216},
ro %arg3[%c0_0 for %c16777216] : !stream.resource<external>{%c16777216},
wo %arg4[%c0_0 for %c16777216] : !stream.resource<external>{%c16777216}
}
} => !stream.timepoint
%3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c16777216}
%4 = stream.tensor.export %3 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %4 : !hal.buffer_view
}
// -----// IR Dump After Canonicalizer (canonicalize) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c16777216} => !stream.timepoint
%2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}, %result as %arg4: !stream.resource<external>{%c16777216}) {
stream.cmd.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%c0_i32, %c0_i32, %c0_i32, %c0_i32, %c0_i32, %c0_i32 : i32, i32, i32, i32, i32, i32) {
ro %arg2[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
ro %arg3[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
wo %arg4[%c0 for %c16777216] : !stream.resource<external>{%c16777216}
}
} => !stream.timepoint
%3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c16777216}
%4 = stream.tensor.export %3 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %4 : !hal.buffer_view
}
// -----// IR Dump Before CSE (cse) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c16777216} => !stream.timepoint
%2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}, %result as %arg4: !stream.resource<external>{%c16777216}) {
stream.cmd.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%c0_i32, %c0_i32, %c0_i32, %c0_i32, %c0_i32, %c0_i32 : i32, i32, i32, i32, i32, i32) {
ro %arg2[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
ro %arg3[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
wo %arg4[%c0 for %c16777216] : !stream.resource<external>{%c16777216}
}
} => !stream.timepoint
%3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c16777216}
%4 = stream.tensor.export %3 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %4 : !hal.buffer_view
}
// -----// IR Dump After CSE (cse) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c16777216} => !stream.timepoint
%2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}, %result as %arg4: !stream.resource<external>{%c16777216}) {
stream.cmd.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%c0_i32, %c0_i32, %c0_i32, %c0_i32, %c0_i32, %c0_i32 : i32, i32, i32, i32, i32, i32) {
ro %arg2[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
ro %arg3[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
wo %arg4[%c0 for %c16777216] : !stream.resource<external>{%c16777216}
}
} => !stream.timepoint
%3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c16777216}
%4 = stream.tensor.export %3 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %4 : !hal.buffer_view
}
// -----// IR Dump Before SimplifyGlobalAccesses (iree-util-simplify-global-accesses) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c16777216} => !stream.timepoint
%2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}, %result as %arg4: !stream.resource<external>{%c16777216}) {
stream.cmd.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%c0_i32, %c0_i32, %c0_i32, %c0_i32, %c0_i32, %c0_i32 : i32, i32, i32, i32, i32, i32) {
ro %arg2[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
ro %arg3[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
wo %arg4[%c0 for %c16777216] : !stream.resource<external>{%c16777216}
}
} => !stream.timepoint
%3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c16777216}
%4 = stream.tensor.export %3 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %4 : !hal.buffer_view
}
// -----// IR Dump After SimplifyGlobalAccesses (iree-util-simplify-global-accesses) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c16777216} => !stream.timepoint
%2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}, %result as %arg4: !stream.resource<external>{%c16777216}) {
stream.cmd.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%c0_i32, %c0_i32, %c0_i32, %c0_i32, %c0_i32, %c0_i32 : i32, i32, i32, i32, i32, i32) {
ro %arg2[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
ro %arg3[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
wo %arg4[%c0 for %c16777216] : !stream.resource<external>{%c16777216}
}
} => !stream.timepoint
%3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c16777216}
%4 = stream.tensor.export %3 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %4 : !hal.buffer_view
}
// -----// IR Dump Before ApplyPatterns (iree-util-apply-patterns) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding {stream.alignment = 64 : index}, %arg1: !stream.binding {stream.alignment = 64 : index}, %arg2: !stream.binding {stream.alignment = 64 : index}, %arg3: i32, %arg4: i32, %arg5: i32, %arg6: i32, %arg7: i32, %arg8: i32) {
%0 = arith.extui %arg3 : i32 to i64
%1 = arith.extui %arg4 : i32 to i64
%c32_i64 = arith.constant 32 : i64
%2 = arith.shli %1, %c32_i64 : i64
%3 = arith.ori %0, %2 : i64
%4 = arith.index_castui %3 {stream.values = [0 : index]} : i64 to index
%5 = arith.extui %arg5 : i32 to i64
%6 = arith.extui %arg6 : i32 to i64
%c32_i64_0 = arith.constant 32 : i64
%7 = arith.shli %6, %c32_i64_0 : i64
%8 = arith.ori %5, %7 : i64
%9 = arith.index_castui %8 {stream.values = [0 : index]} : i64 to index
%10 = arith.extui %arg7 : i32 to i64
%11 = arith.extui %arg8 : i32 to i64
%c32_i64_1 = arith.constant 32 : i64
%12 = arith.shli %11, %c32_i64_1 : i64
%13 = arith.ori %10, %12 : i64
%14 = arith.index_castui %13 {stream.values = [0 : index]} : i64 to index
%c0_i32 = arith.constant 0 : i32
%c0 = arith.constant 0 : index
%15 = stream.binding.subspan %arg0[%4] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%16 = stream.binding.subspan %arg1[%9] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%17 = stream.binding.subspan %arg2[%14] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%18 = flow.dispatch.tensor.load %15, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%19 = flow.dispatch.tensor.load %16, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%20 = tensor.empty() : tensor<2048x2048xi32>
%21 = linalg.fill ins(%c0_i32 : i32) outs(%20 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%22 = linalg.matmul ins(%18, %19 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%21 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %22, %17, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c16777216} => !stream.timepoint
%2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}, %result as %arg4: !stream.resource<external>{%c16777216}) {
stream.cmd.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%c0_i32, %c0_i32, %c0_i32, %c0_i32, %c0_i32, %c0_i32 : i32, i32, i32, i32, i32, i32) {
ro %arg2[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
ro %arg3[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
wo %arg4[%c0 for %c16777216] : !stream.resource<external>{%c16777216}
}
} => !stream.timepoint
%3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c16777216}
%4 = stream.tensor.export %3 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %4 : !hal.buffer_view
}
}
// -----// IR Dump After ApplyPatterns (iree-util-apply-patterns) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding {stream.alignment = 64 : index}, %arg1: !stream.binding {stream.alignment = 64 : index}, %arg2: !stream.binding {stream.alignment = 64 : index}, %arg3: i32, %arg4: i32, %arg5: i32, %arg6: i32, %arg7: i32, %arg8: i32) {
%c0_i32 = arith.constant 0 : i32
%c32_i64 = arith.constant 32 : i64
%0 = arith.extui %arg3 : i32 to i64
%1 = arith.extui %arg4 : i32 to i64
%2 = arith.shli %1, %c32_i64 : i64
%3 = arith.ori %0, %2 : i64
%4 = arith.index_castui %3 {stream.values = [0 : index]} : i64 to index
%5 = arith.extui %arg5 : i32 to i64
%6 = arith.extui %arg6 : i32 to i64
%7 = arith.shli %6, %c32_i64 : i64
%8 = arith.ori %5, %7 : i64
%9 = arith.index_castui %8 {stream.values = [0 : index]} : i64 to index
%10 = arith.extui %arg7 : i32 to i64
%11 = arith.extui %arg8 : i32 to i64
%12 = arith.shli %11, %c32_i64 : i64
%13 = arith.ori %10, %12 : i64
%14 = arith.index_castui %13 {stream.values = [0 : index]} : i64 to index
%15 = stream.binding.subspan %arg0[%4] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%16 = stream.binding.subspan %arg1[%9] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%17 = stream.binding.subspan %arg2[%14] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%18 = flow.dispatch.tensor.load %15, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%19 = flow.dispatch.tensor.load %16, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%20 = tensor.empty() : tensor<2048x2048xi32>
%21 = linalg.fill ins(%c0_i32 : i32) outs(%20 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%22 = linalg.matmul ins(%18, %19 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%21 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %22, %17, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c16777216} => !stream.timepoint
%2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}, %result as %arg4: !stream.resource<external>{%c16777216}) {
stream.cmd.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%c0_i32, %c0_i32, %c0_i32, %c0_i32, %c0_i32, %c0_i32 : i32, i32, i32, i32, i32, i32) {
ro %arg2[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
ro %arg3[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
wo %arg4[%c0 for %c16777216] : !stream.resource<external>{%c16777216}
}
} => !stream.timepoint
%3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c16777216}
%4 = stream.tensor.export %3 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %4 : !hal.buffer_view
}
}
// -----// IR Dump Before FoldGlobals (iree-util-fold-globals) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding {stream.alignment = 64 : index}, %arg1: !stream.binding {stream.alignment = 64 : index}, %arg2: !stream.binding {stream.alignment = 64 : index}, %arg3: i32, %arg4: i32, %arg5: i32, %arg6: i32, %arg7: i32, %arg8: i32) {
%c0_i32 = arith.constant 0 : i32
%c32_i64 = arith.constant 32 : i64
%0 = arith.extui %arg3 : i32 to i64
%1 = arith.extui %arg4 : i32 to i64
%2 = arith.shli %1, %c32_i64 : i64
%3 = arith.ori %0, %2 : i64
%4 = arith.index_castui %3 {stream.values = [0 : index]} : i64 to index
%5 = arith.extui %arg5 : i32 to i64
%6 = arith.extui %arg6 : i32 to i64
%7 = arith.shli %6, %c32_i64 : i64
%8 = arith.ori %5, %7 : i64
%9 = arith.index_castui %8 {stream.values = [0 : index]} : i64 to index
%10 = arith.extui %arg7 : i32 to i64
%11 = arith.extui %arg8 : i32 to i64
%12 = arith.shli %11, %c32_i64 : i64
%13 = arith.ori %10, %12 : i64
%14 = arith.index_castui %13 {stream.values = [0 : index]} : i64 to index
%15 = stream.binding.subspan %arg0[%4] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%16 = stream.binding.subspan %arg1[%9] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%17 = stream.binding.subspan %arg2[%14] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%18 = flow.dispatch.tensor.load %15, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%19 = flow.dispatch.tensor.load %16, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%20 = tensor.empty() : tensor<2048x2048xi32>
%21 = linalg.fill ins(%c0_i32 : i32) outs(%20 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%22 = linalg.matmul ins(%18, %19 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%21 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %22, %17, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c16777216} => !stream.timepoint
%2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}, %result as %arg4: !stream.resource<external>{%c16777216}) {
stream.cmd.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%c0_i32, %c0_i32, %c0_i32, %c0_i32, %c0_i32, %c0_i32 : i32, i32, i32, i32, i32, i32) {
ro %arg2[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
ro %arg3[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
wo %arg4[%c0 for %c16777216] : !stream.resource<external>{%c16777216}
}
} => !stream.timepoint
%3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c16777216}
%4 = stream.tensor.export %3 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %4 : !hal.buffer_view
}
}
// -----// IR Dump After FoldGlobals (iree-util-fold-globals) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding {stream.alignment = 64 : index}, %arg1: !stream.binding {stream.alignment = 64 : index}, %arg2: !stream.binding {stream.alignment = 64 : index}, %arg3: i32, %arg4: i32, %arg5: i32, %arg6: i32, %arg7: i32, %arg8: i32) {
%c0_i32 = arith.constant 0 : i32
%c32_i64 = arith.constant 32 : i64
%0 = arith.extui %arg3 : i32 to i64
%1 = arith.extui %arg4 : i32 to i64
%2 = arith.shli %1, %c32_i64 : i64
%3 = arith.ori %0, %2 : i64
%4 = arith.index_castui %3 {stream.values = [0 : index]} : i64 to index
%5 = arith.extui %arg5 : i32 to i64
%6 = arith.extui %arg6 : i32 to i64
%7 = arith.shli %6, %c32_i64 : i64
%8 = arith.ori %5, %7 : i64
%9 = arith.index_castui %8 {stream.values = [0 : index]} : i64 to index
%10 = arith.extui %arg7 : i32 to i64
%11 = arith.extui %arg8 : i32 to i64
%12 = arith.shli %11, %c32_i64 : i64
%13 = arith.ori %10, %12 : i64
%14 = arith.index_castui %13 {stream.values = [0 : index]} : i64 to index
%15 = stream.binding.subspan %arg0[%4] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%16 = stream.binding.subspan %arg1[%9] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%17 = stream.binding.subspan %arg2[%14] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%18 = flow.dispatch.tensor.load %15, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%19 = flow.dispatch.tensor.load %16, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%20 = tensor.empty() : tensor<2048x2048xi32>
%21 = linalg.fill ins(%c0_i32 : i32) outs(%20 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%22 = linalg.matmul ins(%18, %19 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%21 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %22, %17, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c16777216} => !stream.timepoint
%2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}, %result as %arg4: !stream.resource<external>{%c16777216}) {
stream.cmd.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%c0_i32, %c0_i32, %c0_i32, %c0_i32, %c0_i32, %c0_i32 : i32, i32, i32, i32, i32, i32) {
ro %arg2[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
ro %arg3[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
wo %arg4[%c0 for %c16777216] : !stream.resource<external>{%c16777216}
}
} => !stream.timepoint
%3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c16777216}
%4 = stream.tensor.export %3 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %4 : !hal.buffer_view
}
}
// -----// IR Dump Before FuseGlobals (iree-util-fuse-globals) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding {stream.alignment = 64 : index}, %arg1: !stream.binding {stream.alignment = 64 : index}, %arg2: !stream.binding {stream.alignment = 64 : index}, %arg3: i32, %arg4: i32, %arg5: i32, %arg6: i32, %arg7: i32, %arg8: i32) {
%c0_i32 = arith.constant 0 : i32
%c32_i64 = arith.constant 32 : i64
%0 = arith.extui %arg3 : i32 to i64
%1 = arith.extui %arg4 : i32 to i64
%2 = arith.shli %1, %c32_i64 : i64
%3 = arith.ori %0, %2 : i64
%4 = arith.index_castui %3 {stream.values = [0 : index]} : i64 to index
%5 = arith.extui %arg5 : i32 to i64
%6 = arith.extui %arg6 : i32 to i64
%7 = arith.shli %6, %c32_i64 : i64
%8 = arith.ori %5, %7 : i64
%9 = arith.index_castui %8 {stream.values = [0 : index]} : i64 to index
%10 = arith.extui %arg7 : i32 to i64
%11 = arith.extui %arg8 : i32 to i64
%12 = arith.shli %11, %c32_i64 : i64
%13 = arith.ori %10, %12 : i64
%14 = arith.index_castui %13 {stream.values = [0 : index]} : i64 to index
%15 = stream.binding.subspan %arg0[%4] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%16 = stream.binding.subspan %arg1[%9] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%17 = stream.binding.subspan %arg2[%14] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%18 = flow.dispatch.tensor.load %15, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%19 = flow.dispatch.tensor.load %16, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%20 = tensor.empty() : tensor<2048x2048xi32>
%21 = linalg.fill ins(%c0_i32 : i32) outs(%20 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%22 = linalg.matmul ins(%18, %19 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%21 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %22, %17, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c16777216} => !stream.timepoint
%2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}, %result as %arg4: !stream.resource<external>{%c16777216}) {
stream.cmd.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%c0_i32, %c0_i32, %c0_i32, %c0_i32, %c0_i32, %c0_i32 : i32, i32, i32, i32, i32, i32) {
ro %arg2[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
ro %arg3[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
wo %arg4[%c0 for %c16777216] : !stream.resource<external>{%c16777216}
}
} => !stream.timepoint
%3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c16777216}
%4 = stream.tensor.export %3 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %4 : !hal.buffer_view
}
}
// -----// IR Dump After FuseGlobals (iree-util-fuse-globals) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding {stream.alignment = 64 : index}, %arg1: !stream.binding {stream.alignment = 64 : index}, %arg2: !stream.binding {stream.alignment = 64 : index}, %arg3: i32, %arg4: i32, %arg5: i32, %arg6: i32, %arg7: i32, %arg8: i32) {
%c0_i32 = arith.constant 0 : i32
%c32_i64 = arith.constant 32 : i64
%0 = arith.extui %arg3 : i32 to i64
%1 = arith.extui %arg4 : i32 to i64
%2 = arith.shli %1, %c32_i64 : i64
%3 = arith.ori %0, %2 : i64
%4 = arith.index_castui %3 {stream.values = [0 : index]} : i64 to index
%5 = arith.extui %arg5 : i32 to i64
%6 = arith.extui %arg6 : i32 to i64
%7 = arith.shli %6, %c32_i64 : i64
%8 = arith.ori %5, %7 : i64
%9 = arith.index_castui %8 {stream.values = [0 : index]} : i64 to index
%10 = arith.extui %arg7 : i32 to i64
%11 = arith.extui %arg8 : i32 to i64
%12 = arith.shli %11, %c32_i64 : i64
%13 = arith.ori %10, %12 : i64
%14 = arith.index_castui %13 {stream.values = [0 : index]} : i64 to index
%15 = stream.binding.subspan %arg0[%4] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%16 = stream.binding.subspan %arg1[%9] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%17 = stream.binding.subspan %arg2[%14] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%18 = flow.dispatch.tensor.load %15, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%19 = flow.dispatch.tensor.load %16, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%20 = tensor.empty() : tensor<2048x2048xi32>
%21 = linalg.fill ins(%c0_i32 : i32) outs(%20 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%22 = linalg.matmul ins(%18, %19 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%21 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %22, %17, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c16777216} => !stream.timepoint
%2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}, %result as %arg4: !stream.resource<external>{%c16777216}) {
stream.cmd.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%c0_i32, %c0_i32, %c0_i32, %c0_i32, %c0_i32, %c0_i32 : i32, i32, i32, i32, i32, i32) {
ro %arg2[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
ro %arg3[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
wo %arg4[%c0 for %c16777216] : !stream.resource<external>{%c16777216}
}
} => !stream.timepoint
%3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c16777216}
%4 = stream.tensor.export %3 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %4 : !hal.buffer_view
}
}
// -----// IR Dump Before IPO (iree-util-ipo) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding {stream.alignment = 64 : index}, %arg1: !stream.binding {stream.alignment = 64 : index}, %arg2: !stream.binding {stream.alignment = 64 : index}, %arg3: i32, %arg4: i32, %arg5: i32, %arg6: i32, %arg7: i32, %arg8: i32) {
%c0_i32 = arith.constant 0 : i32
%c32_i64 = arith.constant 32 : i64
%0 = arith.extui %arg3 : i32 to i64
%1 = arith.extui %arg4 : i32 to i64
%2 = arith.shli %1, %c32_i64 : i64
%3 = arith.ori %0, %2 : i64
%4 = arith.index_castui %3 {stream.values = [0 : index]} : i64 to index
%5 = arith.extui %arg5 : i32 to i64
%6 = arith.extui %arg6 : i32 to i64
%7 = arith.shli %6, %c32_i64 : i64
%8 = arith.ori %5, %7 : i64
%9 = arith.index_castui %8 {stream.values = [0 : index]} : i64 to index
%10 = arith.extui %arg7 : i32 to i64
%11 = arith.extui %arg8 : i32 to i64
%12 = arith.shli %11, %c32_i64 : i64
%13 = arith.ori %10, %12 : i64
%14 = arith.index_castui %13 {stream.values = [0 : index]} : i64 to index
%15 = stream.binding.subspan %arg0[%4] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%16 = stream.binding.subspan %arg1[%9] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%17 = stream.binding.subspan %arg2[%14] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%18 = flow.dispatch.tensor.load %15, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%19 = flow.dispatch.tensor.load %16, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%20 = tensor.empty() : tensor<2048x2048xi32>
%21 = linalg.fill ins(%c0_i32 : i32) outs(%20 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%22 = linalg.matmul ins(%18, %19 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%21 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %22, %17, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c16777216} => !stream.timepoint
%2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}, %result as %arg4: !stream.resource<external>{%c16777216}) {
stream.cmd.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%c0_i32, %c0_i32, %c0_i32, %c0_i32, %c0_i32, %c0_i32 : i32, i32, i32, i32, i32, i32) {
ro %arg2[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
ro %arg3[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
wo %arg4[%c0 for %c16777216] : !stream.resource<external>{%c16777216}
}
} => !stream.timepoint
%3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c16777216}
%4 = stream.tensor.export %3 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %4 : !hal.buffer_view
}
}
// -----// IR Dump After IPO (iree-util-ipo) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding {stream.alignment = 64 : index}, %arg1: !stream.binding {stream.alignment = 64 : index}, %arg2: !stream.binding {stream.alignment = 64 : index}, %arg3: i32, %arg4: i32, %arg5: i32, %arg6: i32, %arg7: i32, %arg8: i32) {
%c0_i32 = arith.constant 0 : i32
%c32_i64 = arith.constant 32 : i64
%0 = arith.extui %arg3 : i32 to i64
%1 = arith.extui %arg4 : i32 to i64
%2 = arith.shli %1, %c32_i64 : i64
%3 = arith.ori %0, %2 : i64
%4 = arith.index_castui %3 {stream.values = [0 : index]} : i64 to index
%5 = arith.extui %arg5 : i32 to i64
%6 = arith.extui %arg6 : i32 to i64
%7 = arith.shli %6, %c32_i64 : i64
%8 = arith.ori %5, %7 : i64
%9 = arith.index_castui %8 {stream.values = [0 : index]} : i64 to index
%10 = arith.extui %arg7 : i32 to i64
%11 = arith.extui %arg8 : i32 to i64
%12 = arith.shli %11, %c32_i64 : i64
%13 = arith.ori %10, %12 : i64
%14 = arith.index_castui %13 {stream.values = [0 : index]} : i64 to index
%15 = stream.binding.subspan %arg0[%4] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%16 = stream.binding.subspan %arg1[%9] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%17 = stream.binding.subspan %arg2[%14] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%18 = flow.dispatch.tensor.load %15, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%19 = flow.dispatch.tensor.load %16, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%20 = tensor.empty() : tensor<2048x2048xi32>
%21 = linalg.fill ins(%c0_i32 : i32) outs(%20 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%22 = linalg.matmul ins(%18, %19 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%21 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %22, %17, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c16777216} => !stream.timepoint
%2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}, %result as %arg4: !stream.resource<external>{%c16777216}) {
stream.cmd.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%c0_i32, %c0_i32, %c0_i32, %c0_i32, %c0_i32, %c0_i32 : i32, i32, i32, i32, i32, i32) {
ro %arg2[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
ro %arg3[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
wo %arg4[%c0 for %c16777216] : !stream.resource<external>{%c16777216}
}
} => !stream.timepoint
%3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c16777216}
%4 = stream.tensor.export %3 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %4 : !hal.buffer_view
}
}
// -----// IR Dump Before FoldUniformOperandsPass (iree-stream-fold-uniform-operands) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding {stream.alignment = 64 : index}, %arg1: !stream.binding {stream.alignment = 64 : index}, %arg2: !stream.binding {stream.alignment = 64 : index}, %arg3: i32, %arg4: i32, %arg5: i32, %arg6: i32, %arg7: i32, %arg8: i32) {
%c0_i32 = arith.constant 0 : i32
%c32_i64 = arith.constant 32 : i64
%0 = arith.extui %arg3 : i32 to i64
%1 = arith.extui %arg4 : i32 to i64
%2 = arith.shli %1, %c32_i64 : i64
%3 = arith.ori %0, %2 : i64
%4 = arith.index_castui %3 {stream.values = [0 : index]} : i64 to index
%5 = arith.extui %arg5 : i32 to i64
%6 = arith.extui %arg6 : i32 to i64
%7 = arith.shli %6, %c32_i64 : i64
%8 = arith.ori %5, %7 : i64
%9 = arith.index_castui %8 {stream.values = [0 : index]} : i64 to index
%10 = arith.extui %arg7 : i32 to i64
%11 = arith.extui %arg8 : i32 to i64
%12 = arith.shli %11, %c32_i64 : i64
%13 = arith.ori %10, %12 : i64
%14 = arith.index_castui %13 {stream.values = [0 : index]} : i64 to index
%15 = stream.binding.subspan %arg0[%4] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%16 = stream.binding.subspan %arg1[%9] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%17 = stream.binding.subspan %arg2[%14] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%18 = flow.dispatch.tensor.load %15, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%19 = flow.dispatch.tensor.load %16, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%20 = tensor.empty() : tensor<2048x2048xi32>
%21 = linalg.fill ins(%c0_i32 : i32) outs(%20 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%22 = linalg.matmul ins(%18, %19 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%21 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %22, %17, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c16777216} => !stream.timepoint
%2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}, %result as %arg4: !stream.resource<external>{%c16777216}) {
stream.cmd.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%c0_i32, %c0_i32, %c0_i32, %c0_i32, %c0_i32, %c0_i32 : i32, i32, i32, i32, i32, i32) {
ro %arg2[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
ro %arg3[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
wo %arg4[%c0 for %c16777216] : !stream.resource<external>{%c16777216}
}
} => !stream.timepoint
%3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c16777216}
%4 = stream.tensor.export %3 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %4 : !hal.buffer_view
}
}
// -----// IR Dump After FoldUniformOperandsPass (iree-stream-fold-uniform-operands) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding {stream.alignment = 64 : index}, %arg1: !stream.binding {stream.alignment = 64 : index}, %arg2: !stream.binding {stream.alignment = 64 : index}) {
%c0_i32 = arith.constant 0 : i32
%c0_i32_0 = arith.constant 0 : i32
%c32_i64 = arith.constant 32 : i64
%0 = arith.extui %c0_i32 : i32 to i64
%1 = arith.extui %c0_i32 : i32 to i64
%2 = arith.shli %1, %c32_i64 : i64
%3 = arith.ori %0, %2 : i64
%4 = arith.index_castui %3 {stream.values = [0 : index]} : i64 to index
%5 = arith.extui %c0_i32 : i32 to i64
%6 = arith.extui %c0_i32 : i32 to i64
%7 = arith.shli %6, %c32_i64 : i64
%8 = arith.ori %5, %7 : i64
%9 = arith.index_castui %8 {stream.values = [0 : index]} : i64 to index
%10 = arith.extui %c0_i32 : i32 to i64
%11 = arith.extui %c0_i32 : i32 to i64
%12 = arith.shli %11, %c32_i64 : i64
%13 = arith.ori %10, %12 : i64
%14 = arith.index_castui %13 {stream.values = [0 : index]} : i64 to index
%15 = stream.binding.subspan %arg0[%4] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%16 = stream.binding.subspan %arg1[%9] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%17 = stream.binding.subspan %arg2[%14] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%18 = flow.dispatch.tensor.load %15, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%19 = flow.dispatch.tensor.load %16, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%20 = tensor.empty() : tensor<2048x2048xi32>
%21 = linalg.fill ins(%c0_i32_0 : i32) outs(%20 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%22 = linalg.matmul ins(%18, %19 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%21 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %22, %17, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c16777216} => !stream.timepoint
%2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}, %result as %arg4: !stream.resource<external>{%c16777216}) {
stream.cmd.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32 {
ro %arg2[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
ro %arg3[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
wo %arg4[%c0 for %c16777216] : !stream.resource<external>{%c16777216}
}
} => !stream.timepoint
%3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c16777216}
%4 = stream.tensor.export %3 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %4 : !hal.buffer_view
}
}
// -----// IR Dump Before Canonicalizer (canonicalize) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c0_i32 = arith.constant 0 : i32
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c16777216} => !stream.timepoint
%2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}, %result as %arg4: !stream.resource<external>{%c16777216}) {
stream.cmd.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32 {
ro %arg2[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
ro %arg3[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
wo %arg4[%c0 for %c16777216] : !stream.resource<external>{%c16777216}
}
} => !stream.timepoint
%3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c16777216}
%4 = stream.tensor.export %3 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %4 : !hal.buffer_view
}
// -----// IR Dump After Canonicalizer (canonicalize) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c16777216} => !stream.timepoint
%2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}, %result as %arg4: !stream.resource<external>{%c16777216}) {
stream.cmd.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32 {
ro %arg2[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
ro %arg3[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
wo %arg4[%c0 for %c16777216] : !stream.resource<external>{%c16777216}
}
} => !stream.timepoint
%3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c16777216}
%4 = stream.tensor.export %3 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %4 : !hal.buffer_view
}
// -----// IR Dump Before CSE (cse) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c16777216} => !stream.timepoint
%2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}, %result as %arg4: !stream.resource<external>{%c16777216}) {
stream.cmd.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32 {
ro %arg2[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
ro %arg3[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
wo %arg4[%c0 for %c16777216] : !stream.resource<external>{%c16777216}
}
} => !stream.timepoint
%3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c16777216}
%4 = stream.tensor.export %3 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %4 : !hal.buffer_view
}
// -----// IR Dump After CSE (cse) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c16777216} => !stream.timepoint
%2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}, %result as %arg4: !stream.resource<external>{%c16777216}) {
stream.cmd.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32 {
ro %arg2[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
ro %arg3[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
wo %arg4[%c0 for %c16777216] : !stream.resource<external>{%c16777216}
}
} => !stream.timepoint
%3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c16777216}
%4 = stream.tensor.export %3 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %4 : !hal.buffer_view
}
// -----// IR Dump Before SimplifyGlobalAccesses (iree-util-simplify-global-accesses) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c16777216} => !stream.timepoint
%2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}, %result as %arg4: !stream.resource<external>{%c16777216}) {
stream.cmd.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32 {
ro %arg2[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
ro %arg3[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
wo %arg4[%c0 for %c16777216] : !stream.resource<external>{%c16777216}
}
} => !stream.timepoint
%3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c16777216}
%4 = stream.tensor.export %3 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %4 : !hal.buffer_view
}
// -----// IR Dump After SimplifyGlobalAccesses (iree-util-simplify-global-accesses) //----- //
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c16777216} => !stream.timepoint
%2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}, %result as %arg4: !stream.resource<external>{%c16777216}) {
stream.cmd.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32 {
ro %arg2[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
ro %arg3[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
wo %arg4[%c0 for %c16777216] : !stream.resource<external>{%c16777216}
}
} => !stream.timepoint
%3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c16777216}
%4 = stream.tensor.export %3 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %4 : !hal.buffer_view
}
// -----// IR Dump Before ApplyPatterns (iree-util-apply-patterns) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding {stream.alignment = 64 : index}, %arg1: !stream.binding {stream.alignment = 64 : index}, %arg2: !stream.binding {stream.alignment = 64 : index}) {
%c0_i32 = arith.constant 0 : i32
%c0_i32_0 = arith.constant 0 : i32
%c32_i64 = arith.constant 32 : i64
%0 = arith.extui %c0_i32 : i32 to i64
%1 = arith.extui %c0_i32 : i32 to i64
%2 = arith.shli %1, %c32_i64 : i64
%3 = arith.ori %0, %2 : i64
%4 = arith.index_castui %3 {stream.values = [0 : index]} : i64 to index
%5 = arith.extui %c0_i32 : i32 to i64
%6 = arith.extui %c0_i32 : i32 to i64
%7 = arith.shli %6, %c32_i64 : i64
%8 = arith.ori %5, %7 : i64
%9 = arith.index_castui %8 {stream.values = [0 : index]} : i64 to index
%10 = arith.extui %c0_i32 : i32 to i64
%11 = arith.extui %c0_i32 : i32 to i64
%12 = arith.shli %11, %c32_i64 : i64
%13 = arith.ori %10, %12 : i64
%14 = arith.index_castui %13 {stream.values = [0 : index]} : i64 to index
%15 = stream.binding.subspan %arg0[%4] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%16 = stream.binding.subspan %arg1[%9] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%17 = stream.binding.subspan %arg2[%14] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%18 = flow.dispatch.tensor.load %15, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%19 = flow.dispatch.tensor.load %16, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%20 = tensor.empty() : tensor<2048x2048xi32>
%21 = linalg.fill ins(%c0_i32_0 : i32) outs(%20 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%22 = linalg.matmul ins(%18, %19 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%21 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %22, %17, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c16777216} => !stream.timepoint
%2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}, %result as %arg4: !stream.resource<external>{%c16777216}) {
stream.cmd.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32 {
ro %arg2[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
ro %arg3[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
wo %arg4[%c0 for %c16777216] : !stream.resource<external>{%c16777216}
}
} => !stream.timepoint
%3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c16777216}
%4 = stream.tensor.export %3 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %4 : !hal.buffer_view
}
}
// -----// IR Dump After ApplyPatterns (iree-util-apply-patterns) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding {stream.alignment = 64 : index}, %arg1: !stream.binding {stream.alignment = 64 : index}, %arg2: !stream.binding {stream.alignment = 64 : index}) {
%c0_i32 = arith.constant 0 : i32
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c16777216} => !stream.timepoint
%2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}, %result as %arg4: !stream.resource<external>{%c16777216}) {
stream.cmd.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32 {
ro %arg2[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
ro %arg3[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
wo %arg4[%c0 for %c16777216] : !stream.resource<external>{%c16777216}
}
} => !stream.timepoint
%3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c16777216}
%4 = stream.tensor.export %3 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %4 : !hal.buffer_view
}
}
// -----// IR Dump Before FoldGlobals (iree-util-fold-globals) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding {stream.alignment = 64 : index}, %arg1: !stream.binding {stream.alignment = 64 : index}, %arg2: !stream.binding {stream.alignment = 64 : index}) {
%c0_i32 = arith.constant 0 : i32
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c16777216} => !stream.timepoint
%2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}, %result as %arg4: !stream.resource<external>{%c16777216}) {
stream.cmd.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32 {
ro %arg2[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
ro %arg3[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
wo %arg4[%c0 for %c16777216] : !stream.resource<external>{%c16777216}
}
} => !stream.timepoint
%3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c16777216}
%4 = stream.tensor.export %3 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %4 : !hal.buffer_view
}
}
// -----// IR Dump After FoldGlobals (iree-util-fold-globals) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding {stream.alignment = 64 : index}, %arg1: !stream.binding {stream.alignment = 64 : index}, %arg2: !stream.binding {stream.alignment = 64 : index}) {
%c0_i32 = arith.constant 0 : i32
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c16777216} => !stream.timepoint
%2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}, %result as %arg4: !stream.resource<external>{%c16777216}) {
stream.cmd.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32 {
ro %arg2[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
ro %arg3[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
wo %arg4[%c0 for %c16777216] : !stream.resource<external>{%c16777216}
}
} => !stream.timepoint
%3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c16777216}
%4 = stream.tensor.export %3 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %4 : !hal.buffer_view
}
}
// -----// IR Dump Before FuseGlobals (iree-util-fuse-globals) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding {stream.alignment = 64 : index}, %arg1: !stream.binding {stream.alignment = 64 : index}, %arg2: !stream.binding {stream.alignment = 64 : index}) {
%c0_i32 = arith.constant 0 : i32
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c16777216} => !stream.timepoint
%2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}, %result as %arg4: !stream.resource<external>{%c16777216}) {
stream.cmd.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32 {
ro %arg2[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
ro %arg3[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
wo %arg4[%c0 for %c16777216] : !stream.resource<external>{%c16777216}
}
} => !stream.timepoint
%3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c16777216}
%4 = stream.tensor.export %3 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %4 : !hal.buffer_view
}
}
// -----// IR Dump After FuseGlobals (iree-util-fuse-globals) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding {stream.alignment = 64 : index}, %arg1: !stream.binding {stream.alignment = 64 : index}, %arg2: !stream.binding {stream.alignment = 64 : index}) {
%c0_i32 = arith.constant 0 : i32
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c16777216} => !stream.timepoint
%2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}, %result as %arg4: !stream.resource<external>{%c16777216}) {
stream.cmd.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32 {
ro %arg2[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
ro %arg3[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
wo %arg4[%c0 for %c16777216] : !stream.resource<external>{%c16777216}
}
} => !stream.timepoint
%3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c16777216}
%4 = stream.tensor.export %3 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %4 : !hal.buffer_view
}
}
// -----// IR Dump Before IPO (iree-util-ipo) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding {stream.alignment = 64 : index}, %arg1: !stream.binding {stream.alignment = 64 : index}, %arg2: !stream.binding {stream.alignment = 64 : index}) {
%c0_i32 = arith.constant 0 : i32
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c16777216} => !stream.timepoint
%2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}, %result as %arg4: !stream.resource<external>{%c16777216}) {
stream.cmd.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32 {
ro %arg2[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
ro %arg3[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
wo %arg4[%c0 for %c16777216] : !stream.resource<external>{%c16777216}
}
} => !stream.timepoint
%3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c16777216}
%4 = stream.tensor.export %3 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %4 : !hal.buffer_view
}
}
// -----// IR Dump After IPO (iree-util-ipo) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding {stream.alignment = 64 : index}, %arg1: !stream.binding {stream.alignment = 64 : index}, %arg2: !stream.binding {stream.alignment = 64 : index}) {
%c0_i32 = arith.constant 0 : i32
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c16777216} => !stream.timepoint
%2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}, %result as %arg4: !stream.resource<external>{%c16777216}) {
stream.cmd.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32 {
ro %arg2[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
ro %arg3[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
wo %arg4[%c0 for %c16777216] : !stream.resource<external>{%c16777216}
}
} => !stream.timepoint
%3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c16777216}
%4 = stream.tensor.export %3 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %4 : !hal.buffer_view
}
}
// -----// IR Dump Before SymbolDCE (symbol-dce) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding {stream.alignment = 64 : index}, %arg1: !stream.binding {stream.alignment = 64 : index}, %arg2: !stream.binding {stream.alignment = 64 : index}) {
%c0_i32 = arith.constant 0 : i32
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c16777216} => !stream.timepoint
%2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}, %result as %arg4: !stream.resource<external>{%c16777216}) {
stream.cmd.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32 {
ro %arg2[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
ro %arg3[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
wo %arg4[%c0 for %c16777216] : !stream.resource<external>{%c16777216}
}
} => !stream.timepoint
%3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c16777216}
%4 = stream.tensor.export %3 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %4 : !hal.buffer_view
}
}
// -----// IR Dump After SymbolDCE (symbol-dce) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding {stream.alignment = 64 : index}, %arg1: !stream.binding {stream.alignment = 64 : index}, %arg2: !stream.binding {stream.alignment = 64 : index}) {
%c0_i32 = arith.constant 0 : i32
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c16777216} => !stream.timepoint
%2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}, %result as %arg4: !stream.resource<external>{%c16777216}) {
stream.cmd.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32 {
ro %arg2[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
ro %arg3[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
wo %arg4[%c0 for %c16777216] : !stream.resource<external>{%c16777216}
}
} => !stream.timepoint
%3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c16777216}
%4 = stream.tensor.export %3 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %4 : !hal.buffer_view
}
}
// -----// IR Dump Before CSE (cse) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding {stream.alignment = 64 : index}, %arg1: !stream.binding {stream.alignment = 64 : index}, %arg2: !stream.binding {stream.alignment = 64 : index}) {
%c0_i32 = arith.constant 0 : i32
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c16777216} => !stream.timepoint
%2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}, %result as %arg4: !stream.resource<external>{%c16777216}) {
stream.cmd.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32 {
ro %arg2[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
ro %arg3[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
wo %arg4[%c0 for %c16777216] : !stream.resource<external>{%c16777216}
}
} => !stream.timepoint
%3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c16777216}
%4 = stream.tensor.export %3 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %4 : !hal.buffer_view
}
}
// -----// IR Dump After CSE (cse) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding {stream.alignment = 64 : index}, %arg1: !stream.binding {stream.alignment = 64 : index}, %arg2: !stream.binding {stream.alignment = 64 : index}) {
%c0_i32 = arith.constant 0 : i32
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c16777216} => !stream.timepoint
%2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}, %result as %arg4: !stream.resource<external>{%c16777216}) {
stream.cmd.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32 {
ro %arg2[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
ro %arg3[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
wo %arg4[%c0 for %c16777216] : !stream.resource<external>{%c16777216}
}
} => !stream.timepoint
%3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c16777216}
%4 = stream.tensor.export %3 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %4 : !hal.buffer_view
}
}
// -----// IR Dump Before Canonicalizer (canonicalize) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding {stream.alignment = 64 : index}, %arg1: !stream.binding {stream.alignment = 64 : index}, %arg2: !stream.binding {stream.alignment = 64 : index}) {
%c0_i32 = arith.constant 0 : i32
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c16777216} => !stream.timepoint
%2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}, %result as %arg4: !stream.resource<external>{%c16777216}) {
stream.cmd.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32 {
ro %arg2[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
ro %arg3[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
wo %arg4[%c0 for %c16777216] : !stream.resource<external>{%c16777216}
}
} => !stream.timepoint
%3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c16777216}
%4 = stream.tensor.export %3 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %4 : !hal.buffer_view
}
}
// -----// IR Dump After Canonicalizer (canonicalize) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_dispatch_0 {
stream.executable.export public @matmul_large_dispatch_0_matmul_2048x2048x2048_i32 workgroups() -> (index, index, index) {
%x, %y, %z = flow.dispatch.workgroup_count_from_slice
stream.return %x, %y, %z : index, index, index
}
builtin.module {
func.func @matmul_large_dispatch_0_matmul_2048x2048x2048_i32(%arg0: !stream.binding {stream.alignment = 64 : index}, %arg1: !stream.binding {stream.alignment = 64 : index}, %arg2: !stream.binding {stream.alignment = 64 : index}) {
%c0_i32 = arith.constant 0 : i32
%c0 = arith.constant 0 : index
%0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>>
%2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
%3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<2048x2048xi32>> -> tensor<2048x2048xi32>
%5 = tensor.empty() : tensor<2048x2048xi32>
%6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
%7 = linalg.matmul ins(%3, %4 : tensor<2048x2048xi32>, tensor<2048x2048xi32>) outs(%6 : tensor<2048x2048xi32>) -> tensor<2048x2048xi32>
flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [2048, 2048], strides = [1, 1] : tensor<2048x2048xi32> -> !flow.dispatch.tensor<writeonly:tensor<2048x2048xi32>>
return
}
}
}
func.func @matmul_large(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_large(%input0: tensor<2048x2048xi32>, %input1: tensor<2048x2048xi32>) -> (%output0: tensor<2048x2048xi32>)"}} {
%c16777216 = arith.constant 16777216 : index
%c0 = arith.constant 0 : index
%c2048 = arith.constant 2048 : index
%element_type_i32 = hal.element_type<i32> : i32
%dense_row_major = hal.encoding_type<dense_row_major> : i32
hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c2048, %c2048]) type(%element_type_i32) encoding(%dense_row_major)
%1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<2048x2048xi32> in !stream.resource<external>{%c16777216}
%result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c16777216} => !stream.timepoint
%2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c16777216}, %1 as %arg3: !stream.resource<external>{%c16777216}, %result as %arg4: !stream.resource<external>{%c16777216}) {
stream.cmd.dispatch @matmul_large_dispatch_0::@matmul_large_dispatch_0_matmul_2048x2048x2048_i32 {
ro %arg2[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
ro %arg3[%c0 for %c16777216] : !stream.resource<external>{%c16777216},
wo %arg4[%c0 for %c16777216] : !stream.resource<external>{%c16777216}
}
} => !stream.timepoint
%3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c16777216}
%4 = stream.tensor.export %3 : tensor<2048x2048xi32> in !stream.resource<external>{%c16777216} -> !hal.buffer_view
return %4 : !hal.buffer_view
}
}
// -----// IR Dump Before CSE (cse) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
stream.executable private @matmul_large_disp
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment