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This is the generated verilog from @scanlime icebreaker-icestudio-ledmatrix design af3b1559
# Code generated by Icestudio 0.4.0-dev
# Thu, 25 Oct 2018 18:32:14 GMT
set_io v5beaf0[4] 28
set_io v5beaf0[3] 31
set_io v5beaf0[2] 34
set_io v5beaf0[1] 38
set_io v5beaf0[0] 43
set_io vb20513[5] 3
set_io vb20513[4] 48
set_io vb20513[3] 46
set_io vb20513[2] 4
set_io vb20513[1] 2
set_io vb20513[0] 47
set_io ve769fd 36
set_io ved4406 32
set_io v49b4e1 42
set_io v4b868e 20
set_io va7a15a 18
set_io v019261 19
set_io vclk 35
// Code generated by Icestudio 0.4.0-dev
// Thu, 25 Oct 2018 18:33:02 GMT
`default_nettype none
module main #(
parameter ve20419 = 21,
parameter v81a9d9 = 32,
parameter v37baad = 8,
parameter v449e78 = 16,
parameter ve8a52e = 64,
parameter v5038f9 = 2
) (
input v4b868e,
input va7a15a,
input v019261,
input vclk,
output [4:0] v5beaf0,
output [5:0] vb20513,
output ve769fd,
output ved4406,
output v49b4e1
);
localparam p1 = ve8a52e;
localparam p8 = ve8a52e;
localparam p13 = v449e78;
localparam p14 = v37baad;
localparam p15 = v81a9d9;
localparam p24 = v5038f9;
localparam p35 = ve8a52e;
localparam p36 = v5038f9;
localparam p43 = ve20419;
wire w0;
wire [0:17] w2;
wire [0:15] w3;
wire w4;
wire [0:17] w5;
wire [0:5] w6;
wire w7;
wire [0:4] w9;
wire [0:7] w10;
wire w11;
wire w12;
wire w16;
wire [0:7] w17;
wire [0:2] w18;
wire w19;
wire w20;
wire w21;
wire [0:15] w22;
wire [0:15] w23;
wire w25;
wire [0:15] w26;
wire [0:17] w27;
wire w28;
wire w29;
wire [0:12] w30;
wire [0:2] w31;
wire w32;
wire w33;
wire [0:23] w34;
wire [0:7] w37;
wire w38;
wire w39;
wire w40;
wire w41;
wire [0:7] w42;
wire w44;
wire w45;
wire w46;
wire w47;
wire w48;
wire w49;
wire w50;
wire w51;
wire w52;
wire w53;
wire w54;
wire w55;
wire w56;
wire w57;
assign ved4406 = w4;
assign vb20513 = w6;
assign v5beaf0 = w9;
assign ve769fd = w11;
assign v49b4e1 = w12;
assign w38 = v019261;
assign w44 = v4b868e;
assign w45 = va7a15a;
assign w57 = vclk;
assign w7 = w0;
assign w16 = w0;
assign w16 = w7;
assign w17 = w10;
assign w21 = w0;
assign w21 = w7;
assign w21 = w16;
assign w25 = w0;
assign w25 = w7;
assign w25 = w16;
assign w25 = w21;
assign w37 = w10;
assign w37 = w17;
assign w39 = w0;
assign w39 = w7;
assign w39 = w16;
assign w39 = w21;
assign w39 = w25;
assign w40 = w0;
assign w40 = w7;
assign w40 = w16;
assign w40 = w21;
assign w40 = w25;
assign w40 = w39;
assign w50 = w0;
assign w50 = w7;
assign w50 = w16;
assign w50 = w21;
assign w50 = w25;
assign w50 = w39;
assign w50 = w40;
assign w51 = w0;
assign w51 = w7;
assign w51 = w16;
assign w51 = w21;
assign w51 = w25;
assign w51 = w39;
assign w51 = w40;
assign w51 = w50;
assign w52 = w0;
assign w52 = w7;
assign w52 = w16;
assign w52 = w21;
assign w52 = w25;
assign w52 = w39;
assign w52 = w40;
assign w52 = w50;
assign w52 = w51;
assign w55 = w54;
assign w56 = w0;
assign w56 = w7;
assign w56 = w16;
assign w56 = w21;
assign w56 = w25;
assign w56 = w39;
assign w56 = w40;
assign w56 = w50;
assign w56 = w51;
assign w56 = w52;
v54f0a2 v21bd96 (
.vaf6a31(w0),
.v92aaa2(w57)
);
main_vcffc43 vcffc43 (
.i(w5),
.o(w6)
);
vf4d0c7 #(
.v5b95a2(p13),
.v6c40ff(p14),
.v8ec108(p15)
) v2f7934 (
.vce02ad(w10),
.vbfbaf3(w11),
.v51335c(w12),
.v3cbff5(w16),
.v0a0592(w18),
.v37d1cf(w19),
.v52ca42(w20),
.vc8113a(w32)
);
main_vecc840 vecc840 (
.o(w9),
.i(w10)
);
v711181 #(
.v50ce00(p8)
) v58d7d1 (
.v66dac2(w2),
.v6c5513(w3),
.v86c5ee(w4),
.v3f6289(w5),
.v3229ce(w7),
.v1f0052(w18),
.v5b3dad(w19),
.va4c5d1(w20)
);
v1ae7de #(
.v50ce00(p1),
.vda8e51(p24)
) v62cb18 (
.v3cbff5(w0),
.v1e6ce4(w2),
.vccd9be(w3),
.v491b7f(w17),
.v33b662(w26),
.vaa3627(w27),
.vc90278(w28)
);
v165218 v689eaa (
.v73ebd2(w22),
.vfa6578(w23),
.v21d6ed(w30),
.v5a724c(w31),
.vb0271f(w37)
);
v5021aa #(
.v0169f5(p35),
.v05bb19(p36)
) v1fdfd8 (
.v018f5d(w25),
.v4580d9(w26),
.v5d2321(w27),
.v96df49(w28),
.va97c98(w29),
.vdbb907(w30),
.v50ad40(w31),
.vebd715(w32),
.ve14339(w33),
.v2af97a(w34)
);
v6e4743 v9aacd4 (
.ve3da88(w38),
.v894a97(w39),
.v48fca4(w41)
);
v1908c7 v87b5fa (
.ve61c4f(w40),
.v0582aa(w41),
.vb39999(w42),
.v6fef9e(w47),
.v3fae6d(w49)
);
main_vad0fa5 vad0fa5 (
.clk(w21),
.x(w22),
.y(w23),
.begin_pixel(w29),
.pixel_done(w33),
.rgb(w34),
.counter(w42)
);
v6a5074 #(
.v100e1b(p43)
) vba3565 (
.v0daa9e(w50),
.v2efea4(w53)
);
vcfd9ba vae58af (
.v6a82dd(w44),
.vd4e5d7(w46),
.v444878(w51)
);
vcfd9ba ve69f63 (
.v6a82dd(w45),
.vd4e5d7(w48),
.v444878(w52)
);
v7ebc90 v965d8c (
.v3ca442(w46),
.vcbab45(w47),
.v0e28cb(w54)
);
v7ebc90 v2e8d24 (
.v3ca442(w48),
.vcbab45(w49),
.v0e28cb(w55)
);
vd34d32 va79f05 (
.v7b4b0b(w53),
.v3035d8(w54),
.v758b59(w56)
);
endmodule
module v54f0a2 (
input v92aaa2,
output vaf6a31
);
wire w0;
wire w1;
assign w0 = v92aaa2;
assign vaf6a31 = w1;
v54f0a2_v753474 v753474 (
.package_pin(w0),
.clock_out(w1)
);
endmodule
module v54f0a2_v753474 (
input package_pin,
output clock_out,
output locked
);
// Given input frequency: 12.000 MHz
// Requested output frequency: 30.000 MHz
// Achieved output frequency: 30.000 MHz
SB_PLL40_PAD #(
.FEEDBACK_PATH("SIMPLE"),
.DIVR(4'b0000), // DIVR = 0
.DIVF(7'b1001111), // DIVF = 79
.DIVQ(3'b101), // DIVQ = 5
.FILTER_RANGE(3'b001) // FILTER_RANGE = 1
) uut (
.PACKAGEPIN(package_pin),
.LOCK(locked),
.RESETB(1'b1),
.BYPASS(1'b0),
.PLLOUTCORE(clock_out)
);
endmodule
module vf4d0c7 #(
parameter v8ec108 = 32,
parameter v6c40ff = 8,
parameter v5b95a2 = 16
) (
input v3cbff5,
input v52ca42,
output [7:0] vce02ad,
output [2:0] v0a0592,
output vbfbaf3,
output v51335c,
output v37d1cf,
output vc8113a
);
localparam p0 = v8ec108;
localparam p1 = v6c40ff;
localparam p10 = v5b95a2;
wire [0:7] w2;
wire [0:2] w3;
wire w4;
wire w5;
wire w6;
wire w7;
wire w8;
wire w9;
assign vce02ad = w2;
assign v0a0592 = w3;
assign vbfbaf3 = w4;
assign v51335c = w5;
assign v37d1cf = w6;
assign vc8113a = w7;
assign w8 = v3cbff5;
assign w9 = v52ca42;
vf4d0c7_v076d09 #(
.num_scan_rows(p0),
.num_planes(p1),
.lsb_duration(p10)
) v076d09 (
.scan_row(w2),
.scan_plane(w3),
.latch(w4),
.blank(w5),
.scan_begin(w6),
.render_begin(w7),
.clk(w8),
.scan_done(w9)
);
endmodule
module vf4d0c7_v076d09 #(
parameter num_scan_rows = 0,
parameter num_planes = 0,
parameter lsb_duration = 0
) (
input clk,
input scan_done,
output [7:0] scan_row,
output [2:0] scan_plane,
output latch,
output blank,
output scan_begin,
output render_begin
);
// State machine to refresh each row on the LED matrix multiple times
// (for binary-weighted brightness control)
reg[7:0] scan_row = 0;
reg[2:0] scan_plane = 0;
reg blank = 1;
reg latch = 0;
reg scan_begin = 0;
reg render_begin = 0;
// One iteration of this state machine per bit-plane (several per line)
parameter S_DEFAULT = 0;
parameter S_WAIT = 1;
parameter S_LATCH_ASSERT = 2;
parameter S_LATCH_DEASSERT = 3;
reg [1:0] state = S_DEFAULT;
reg [12:0] unblank_timer = 0;
reg unblank_enable = 0;
always @(posedge clk) begin
case (state)
S_DEFAULT: begin
state <= S_WAIT;
scan_begin <= 1'b1;
if (!scan_plane) begin
// Concurrently with scanning out plane 0, start rendering
// every plane of the *next* line. It won't need to finish
// until this time one line in the future.
render_begin <= 1'b1;
end
if (unblank_enable) begin
// Only enable unblanking once we've rendered a complete
// line into the buffer, so we never display uninitialized
// memory. This is also where we initialize a binary-weighted
// timer to time each bit plane.
blank <= 0;
unblank_timer <= lsb_duration << scan_plane;
end
end
S_WAIT: begin
render_begin <= 0;
scan_begin <= 0;
if (unblank_timer)
unblank_timer <= unblank_timer - 1;
else
blank <= 1;
if (scan_done && blank)
state <= S_LATCH_ASSERT;
end
S_LATCH_ASSERT: begin
latch <= 1;
state <= S_LATCH_DEASSERT;
// Roll over counters during the latch assert clock cycle.
// This could happen at any time during blanking.
if (scan_plane == (num_planes - 1)) begin
// First plane of next row
scan_plane <= 0;
if (scan_row == (num_scan_rows - 1))
scan_row <= 0;
else
scan_row <= scan_row + 1;
// Allow unblanking for the first time only after there's
// been enough time for the first line to write to RAM
// (one full modulation cycle on one line)
unblank_enable <= 1'b1;
end
else begin
scan_plane <= scan_plane + 1;
end
end
S_LATCH_DEASSERT: begin
state <= S_DEFAULT;
latch <= 0;
end
endcase
end
endmodule
module v711181 #(
parameter v50ce00 = 64
) (
input v3229ce,
input v5b3dad,
input [2:0] v1f0052,
input [17:0] v66dac2,
output va4c5d1,
output [17:0] v3f6289,
output v86c5ee,
output [15:0] v6c5513
);
localparam p2 = v50ce00;
wire w0;
wire w1;
wire w3;
wire w4;
wire [0:2] w5;
wire [0:17] w6;
wire [0:17] w7;
wire w8;
wire w9;
wire [0:15] w10;
assign v86c5ee = w0;
assign w3 = v3229ce;
assign w4 = v5b3dad;
assign w5 = v1f0052;
assign w6 = v66dac2;
assign v3f6289 = w7;
assign va4c5d1 = w8;
assign w9 = v3229ce;
assign v6c5513 = w10;
assign w9 = w3;
v711181_v63128f #(
.pixels_per_scan_row(p2)
) v63128f (
.rgb_en(w1),
.clk(w3),
.begin_in(w4),
.scan_plane(w5),
.scan_data(w6),
.rgb(w7),
.done_out(w8),
.scan_addr(w10)
);
v711181_v961287 v961287 (
.sclk(w0),
.rgb_en(w1),
.clk(w9)
);
endmodule
module v711181_v63128f #(
parameter pixels_per_scan_row = 0
) (
input clk,
input begin_in,
input [2:0] scan_plane,
input [17:0] scan_data,
output done_out,
output [17:0] rgb,
output rgb_en,
output [15:0] scan_addr
);
// Render one line of pixels from RAM
// Scan-out state machine, reads individual
// bit planes from the line buffer and outputs both
// the bits and clock-enable signal for the bits.
reg[12:0] pixel_counter = 0;
reg[17:0] rgb = 0;
reg running = 0;
reg rgb_en = 0;
assign done_out = !running;
assign scan_addr = { pixel_counter, scan_plane };
always @(posedge clk) begin
if (begin_in) begin
pixel_counter <= 0;
rgb_en <= 0;
running <= 1;
end
else if (running) begin
rgb_en <= 1;
rgb <= scan_data;
if (pixel_counter == (pixels_per_scan_row - 1))
running <= 0;
else
pixel_counter <= pixel_counter + 1;
end
else
rgb_en <= 0;
end
endmodule
module v711181_v961287 (
input clk,
input rgb_en,
output sclk
);
// Gating for shift register output
// clock. rgb_en set to 1 at the same
// cycle as new data latched at 'rgb',
// and the rgb_en signal is latched
// on the following negative edge.
// Implememnted as a DDR output buffer
SB_IO #(
// DDR output, regular input
.PIN_TYPE(6'b010001)
) sclk_buf (
.PACKAGE_PIN(sclk),
.LATCH_INPUT_VALUE(1'b0),
.CLOCK_ENABLE(1'b1),
.INPUT_CLK(clk),
.OUTPUT_CLK(clk),
.OUTPUT_ENABLE(1'b1),
.D_OUT_0(1'b0),
.D_OUT_1(rgb_en)
);
endmodule
module v1ae7de #(
parameter v50ce00 = 64,
parameter vda8e51 = 2
) (
input v3cbff5,
input [7:0] v491b7f,
input [15:0] vccd9be,
input [15:0] v33b662,
input [17:0] vaa3627,
input vc90278,
output [17:0] v1e6ce4
);
localparam p0 = v50ce00;
localparam p7 = vda8e51;
wire w1;
wire [0:7] w2;
wire [0:15] w3;
wire [0:15] w4;
wire [0:17] w5;
wire [0:17] w6;
wire w8;
assign w1 = v3cbff5;
assign w2 = v491b7f;
assign w3 = vccd9be;
assign w4 = v33b662;
assign w5 = vaa3627;
assign v1e6ce4 = w6;
assign w8 = vc90278;
v1ae7de_v82786c #(
.pixels_per_scan_row(p0),
.num_lanes(p7)
) v82786c (
.clk(w1),
.scan_row(w2),
.scan_addr(w3),
.render_addr(w4),
.render_data(w5),
.scan_data(w6),
.render_we(w8)
);
endmodule
module v1ae7de_v82786c #(
parameter pixels_per_scan_row = 0,
parameter num_lanes = 0
) (
input clk,
input [7:0] scan_row,
input [15:0] scan_addr,
input [15:0] render_addr,
input [17:0] render_data,
input render_we,
output [17:0] scan_data
);
// Memory organized by pixel and by bit plane, enough to
// double-buffer one row of pixels, between rendering and
// brightness modulation where they must be output in
// a different order and repeatedly.
parameter num_buffers = 2;
parameter num_planes = 8;
parameter scan_data_width = num_lanes * 3;
reg [scan_data_width-1:0] ram [0:num_buffers*num_planes*(pixels_per_scan_row)-1];
wire buffer_toggle = scan_row[0];
reg [17:0] scan_data;
always @(posedge clk)
if (render_we)
ram[{ render_addr, buffer_toggle }] <= render_data[scan_data_width-1:0];
always @(posedge clk)
scan_data <= ram[{ scan_addr, !buffer_toggle }];
endmodule
module v165218 (
input [7:0] vb0271f,
input [12:0] v21d6ed,
input [2:0] v5a724c,
output [15:0] v73ebd2,
output [15:0] vfa6578
);
wire [0:7] w0;
wire [0:2] w1;
wire [0:15] w2;
wire [0:15] w3;
wire [0:12] w4;
assign w0 = vb0271f;
assign w1 = v5a724c;
assign v73ebd2 = w2;
assign vfa6578 = w3;
assign w4 = v21d6ed;
v165218_v08874e v08874e (
.scan_row(w0),
.lane_counter(w1),
.x(w2),
.y(w3),
.pixel_counter(w4)
);
endmodule
module v165218_v08874e (
input [7:0] scan_row,
input [12:0] pixel_counter,
input [2:0] lane_counter,
output [15:0] x,
output [15:0] y
);
// Addressing for a single 64x64 panel with 1:32 scan
// - Two halves (lanes 0 and 1)
// - 64 LEDs per scan row == 64 per physical row
// The row we're rendering is the one after the current scan
wire [4:0] render_row = scan_row[4:0] + 1;
assign x = { 10'b0, pixel_counter[5:0] };
assign y = { 10'b0, lane_counter[0], render_row };
endmodule
module v5021aa #(
parameter v0169f5 = 64,
parameter v05bb19 = 2
) (
input v018f5d,
input vebd715,
input [23:0] v2af97a,
input ve14339,
output [15:0] v4580d9,
output [17:0] v5d2321,
output v96df49,
output va97c98,
output [12:0] vdbb907,
output [2:0] v50ad40
);
localparam p3 = v05bb19;
localparam p8 = v0169f5;
wire w0;
wire w1;
wire [0:23] w2;
wire [0:15] w4;
wire [0:17] w5;
wire w6;
wire w7;
wire [0:2] w9;
wire [0:12] w10;
wire w11;
wire w12;
wire w13;
wire w14;
assign w0 = v018f5d;
assign w1 = vebd715;
assign w2 = v2af97a;
assign v4580d9 = w4;
assign v5d2321 = w5;
assign va97c98 = w6;
assign v96df49 = w7;
assign v50ad40 = w9;
assign vdbb907 = w10;
assign w11 = ve14339;
assign w14 = v018f5d;
assign w13 = w6;
assign w14 = w0;
v5021aa_v742430 #(
.num_lanes(p3),
.pixels_per_scan_row(p8)
) v742430 (
.clk(w0),
.begin_line(w1),
.rgb(w2),
.render_addr(w4),
.render_data(w5),
.begin_pixel(w6),
.render_we(w7),
.lane_counter(w9),
.pixel_counter(w10),
.pixel_done(w12)
);
v5021aa_v78bd19 v78bd19 (
.pixel_done(w11),
.latched_pixel_done(w12),
.begin_pixel(w13),
.clk(w14)
);
endmodule
module v5021aa_v742430 #(
parameter pixels_per_scan_row = 0,
parameter num_lanes = 0
) (
input clk,
input begin_line,
input [23:0] rgb,
input pixel_done,
output [15:0] render_addr,
output [17:0] render_data,
output render_we,
output begin_pixel,
output [12:0] pixel_counter,
output [2:0] lane_counter
);
// Double-buffer for one pixel from each lane.
reg [23:0] pixel_buffer [0:2*num_lanes-1];
// Outgoing: when triggered, send current pixel from all lanes
// via render_* signals to the line buffer. Iterates over bitplanes.
reg [15:0] render_addr = 0;
reg [17:0] render_data = 0;
reg render_we = 0;
reg [2:0] bitplane_counter = 0;
reg outgoing_active = 0;
parameter num_bitplanes = 8;
wire [23:0] lane0_rgb = pixel_buffer[{ 3'h0, !pixel_counter[0] }];
wire [23:0] lane1_rgb = pixel_buffer[{ 3'h1, !pixel_counter[0] }];
wire [23:0] lane2_rgb = pixel_buffer[{ 3'h2, !pixel_counter[0] }];
wire [23:0] lane3_rgb = pixel_buffer[{ 3'h3, !pixel_counter[0] }];
wire [23:0] lane4_rgb = pixel_buffer[{ 3'h4, !pixel_counter[0] }];
wire [23:0] lane5_rgb = pixel_buffer[{ 3'h5, !pixel_counter[0] }];
always @(posedge clk) begin
if (outgoing_trigger) begin
outgoing_active <= 1;
bitplane_counter <= 0;
render_we <= 0;
end
else if (outgoing_active) begin
// Address in line buffer: current pixel (pixel_counter was
// already incremented to work on the next one), plane index
render_addr <= { pixel_counter_previous, bitplane_counter };
// Data for line buffer: one bit from every lane, RGBRGBRGB...
render_data <= {
lane5_rgb[{2'h2, bitplane_counter}],
lane5_rgb[{2'h1, bitplane_counter}],
lane5_rgb[{2'h0, bitplane_counter}],
lane4_rgb[{2'h2, bitplane_counter}],
lane4_rgb[{2'h1, bitplane_counter}],
lane4_rgb[{2'h0, bitplane_counter}],
lane3_rgb[{2'h2, bitplane_counter}],
lane3_rgb[{2'h1, bitplane_counter}],
lane3_rgb[{2'h0, bitplane_counter}],
lane2_rgb[{2'h2, bitplane_counter}],
lane2_rgb[{2'h1, bitplane_counter}],
lane2_rgb[{2'h0, bitplane_counter}],
lane1_rgb[{2'h2, bitplane_counter}],
lane1_rgb[{2'h1, bitplane_counter}],
lane1_rgb[{2'h0, bitplane_counter}],
lane0_rgb[{2'h2, bitplane_counter}],
lane0_rgb[{2'h1, bitplane_counter}],
lane0_rgb[{2'h0, bitplane_counter}]
};
render_we <= 1;
if (bitplane_counter == (num_bitplanes - 1)) begin
outgoing_active <= 0;
end
else begin
bitplane_counter <= bitplane_counter + 1;
end
end
else begin
// Output is idle
render_we <= 0;
end
end
// Pixel iteration: When triggered by the refresh module,
// start outputting each pixel in a line, coordinating with the
// outgoing state machine above.
reg outgoing_trigger = 0;
reg begin_pixel = 0;
reg line_active = 0;
reg [12:0] pixel_counter = 0;
wire [12:0] pixel_counter_previous = pixel_counter - 13'h1;
reg [2:0] lane_counter = 0;
always @(posedge clk) begin
if (begin_line) begin
begin_pixel <= 1;
line_active <= 1;
outgoing_trigger <= 0;
pixel_counter <= 0;
lane_counter <= 0;
end
else if (line_active && pixel_done) begin
// Still looping, and we have a rendered pixel to store
pixel_buffer[{ lane_counter, pixel_counter[0] }] <= rgb;
if (lane_counter != (num_lanes - 1)) begin
// Render pixel for next lane next
lane_counter <= lane_counter + 1;
begin_pixel <= 1;
end
else begin
// Just finished all lanes for one pixel; output that
// pixel while we work on the next one (or while inactive,
// for the last pixel). Here we may need to wait for the
// outgoing state machine if it's still busy
if (outgoing_active) begin
// Still waiting on outgoing state machine
begin_pixel <= 0;
end
else begin
outgoing_trigger <= 1;
lane_counter <= 0;
pixel_counter <= pixel_counter + 1;
if (pixel_counter == (pixels_per_scan_row - 1)) begin
// Done with this line; wait for next.
// Keep outputting the last pixel, but stop rendering
line_active <= 0;
begin_pixel <= 0;
end
else begin
begin_pixel <= 1;
end
end
end
end
else begin
begin_pixel <= 0;
outgoing_trigger <= 0;
end
end
endmodule
module v5021aa_v78bd19 (
input clk,
input pixel_done,
input begin_pixel,
output latched_pixel_done
);
// Shaders only need to give us a one-cycle 'done' signal,
// internally though we'd like it to be asserted any time
// the shader isn't busy.
reg latched_pixel_done = 0;
always @(posedge clk) begin
if (pixel_done)
latched_pixel_done <= 1;
else if (begin_pixel)
latched_pixel_done <= 0;
end
endmodule
module v6e4743 (
input v894a97,
input ve3da88,
output v48fca4
);
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
assign w0 = ve3da88;
assign w1 = v894a97;
assign w2 = v894a97;
assign v48fca4 = w4;
assign w2 = w1;
vcfd9ba v506649 (
.v6a82dd(w0),
.v444878(w1),
.vd4e5d7(w3)
);
vd34d32 v467237 (
.v758b59(w2),
.v7b4b0b(w3),
.v3035d8(w4)
);
endmodule
module vcfd9ba (
input v444878,
input v6a82dd,
output vd4e5d7
);
wire w0;
wire w1;
wire w2;
assign vd4e5d7 = w0;
assign w1 = v444878;
assign w2 = v6a82dd;
vcfd9ba_va7041c va7041c (
.out(w0),
.clk(w1),
.in(w2)
);
endmodule
module vcfd9ba_va7041c (
input clk,
input in,
output out
);
//-- Debouncer Circuit
//-- It produces a stable output when the
//-- input signal is bouncing
reg btn_prev = 0;
reg btn_out_r = 0;
reg [16:0] counter = 0;
always @(posedge clk) begin
//-- If btn_prev and btn_in are differents
if (btn_prev ^ in == 1'b1) begin
//-- Reset the counter
counter <= 0;
//-- Capture the button status
btn_prev <= in;
end
//-- If no timeout, increase the counter
else if (counter[16] == 1'b0)
counter <= counter + 1;
else
//-- Set the output to the stable value
btn_out_r <= btn_prev;
end
assign out = btn_out_r;
endmodule
module vd34d32 (
input v758b59,
input v7b4b0b,
output v3035d8
);
wire w0;
wire w1;
wire w2;
assign w0 = v758b59;
assign v3035d8 = w1;
assign w2 = v7b4b0b;
vd34d32_vb3ff31 vb3ff31 (
.clk(w0),
.o(w1),
.i(w2)
);
endmodule
module vd34d32_vb3ff31 (
input clk,
input i,
output o
);
reg prev, o;
always @(posedge clk)
prev <= i;
always @(posedge clk)
o <= i && !prev;
endmodule
module v1908c7 (
input ve61c4f,
input v6fef9e,
input v3fae6d,
input v0582aa,
output [7:0] vb39999
);
wire [0:7] w0;
wire w1;
wire w2;
wire w3;
wire w4;
assign vb39999 = w0;
assign w1 = ve61c4f;
assign w2 = v6fef9e;
assign w3 = v3fae6d;
assign w4 = v0582aa;
v1908c7_vbac9f6 vbac9f6 (
.value(w0),
.clk(w1),
.up(w2),
.down(w3),
.reset(w4)
);
endmodule
module v1908c7_vbac9f6 (
input clk,
input up,
input down,
input reset,
output [7:0] value
);
reg[7:0] value = 0;
always @(posedge clk)
if (reset)
value <= 0;
else if (up && !down)
value <= value + 1;
else if (down && !up)
value <= value - 1;
endmodule
module v6a5074 #(
parameter v100e1b = 22
) (
input v0daa9e,
output v2efea4
);
localparam p2 = v100e1b;
wire w0;
wire w1;
assign v2efea4 = w0;
assign w1 = v0daa9e;
v6a5074_vac7386 #(
.N(p2)
) vac7386 (
.clk_out(w0),
.clk_in(w1)
);
endmodule
module v6a5074_vac7386 #(
parameter N = 0
) (
input clk_in,
output clk_out
);
//-- Number of bits of the prescaler
//parameter N = 22;
//-- divisor register
reg [N-1:0] divcounter;
//-- N bit counter
always @(posedge clk_in)
divcounter <= divcounter + 1;
//-- Use the most significant bit as output
assign clk_out = divcounter[N-1];
endmodule
module v7ebc90 (
input v0e28cb,
input v3ca442,
output vcbab45
);
wire w0;
wire w1;
wire w2;
assign w0 = v0e28cb;
assign w1 = v3ca442;
assign vcbab45 = w2;
v7ebc90_vf4938a vf4938a (
.a(w0),
.b(w1),
.c(w2)
);
endmodule
module v7ebc90_vf4938a (
input a,
input b,
output c
);
// AND logic gate
assign c = a & b;
endmodule
module main_vcffc43 (
input [17:0] i,
output [5:0] o
);
assign o = i[17:0];
endmodule
module main_vecc840 (
input [7:0] i,
output [4:0] o
);
assign o = i[4:0];
endmodule
module main_vad0fa5 (
input clk,
input [15:0] x,
input [15:0] y,
input begin_pixel,
input [7:0] counter,
output pixel_done,
output [23:0] rgb
);
reg[23:0] rgb;
reg pixel_done;
wire[7:0] x8 = { x[5:0], x[5:4] };
wire[7:0] y8 = { y[5:0], y[5:4] };
always @(posedge clk) begin
if (begin_pixel) begin
pixel_done <= 1;
rgb <= {
(x == counter) ? 8'hFF : 0,
(y == counter) ? 8'hFF : 0,
counter
};
end
else
pixel_done <= 0;
end
endmodule
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