Four 32-bit element ring buffer in Verilog

ring.v

// Four 32-bit element ring buffer
// https://www.snellman.net/blog/archive/2016-12-13-ring-buffers/
module ring
  ( input clk,
    input push, input pop,
    output full, output empty,
    input [31:0] in, output [31:0] out );

   reg [2:0] read;
   reg [2:0] write;
   reg [31:0] entries [3:0];

   assign empty = (read==write);
   assign full = (write-read)==3'd4;

   assign out = entries[read[1:0]];

   always @(posedge clk) begin
      if (push) begin entries[write[1:0]] <= in; write <= write+1; end
      if (pop) read <= read+1;
   end
endmodule