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Disassembler for Notch's 'DCPU-16'
/* See: http://0x10c.com/doc/dcpu-16.txt */
function hex(n) {
return '0x' + n.toString(16);
}
function disassemble (code) {
var PC = 0;
var operand = function (bits) {
var reg_names = ['A', 'B', 'C', 'X', 'Y', 'Z', 'I', 'J'];
if (bits <= 0x07) {
return reg_names[bits];
}
if (bits <= 0x0f) {
return '[' + reg_names[bits - 0x08] + ']';
}
if (bits <= 0x17) {
return '[' + hex(code[++PC]) + ' + ' + reg_names[bits - 0x10] + ']';
}
switch (bits) {
case 0x18:
return 'POP';
case 0x19:
return 'PEEK';
case 0x1a:
return 'PUSH';
case 0x1b:
return 'SP';
case 0x1c:
return 'PC';
case 0x1d:
return 'O';
case 0x1e:
return '[' + hex(code[++PC]) + ']';
case 0x1f:
/* literal */
return hex(code[++PC]);
}
/* literal */
return hex(bits - 0x20);
}
var basic_op = ['SET', 'ADD', 'SUB', 'MUL', 'DIV', 'MOD', 'SHL', 'SHR', 'AND', 'BOR',
'XOR', 'IFE', 'IFN', 'IFG', 'IFB'];
for (; PC < code.length; PC++) {
var inst = code[PC];
if ((inst & 0xf) == 0) {
/* non basic */
if (((inst >> 4) & 0x3f) == 0x01) {
console.log('JSR ' + operand(inst >> 10))
}
} else {
console.log(basic_op[inst & 0xf - 1] + ' ' + operand((inst >> 4) & 0x3f) + ', ' + operand(inst >> 10))
}
}
}
disassemble([0x7c01, 0x0030, 0x7de1, 0x1000, 0x0020, 0x7803, 0x1000, 0xc00d,
0x7dc1, 0x001a, 0xa861, 0x7c01, 0x2000, 0x2161, 0x2000, 0x8463,
0x806d, 0x7dc1, 0x000d, 0x9031, 0x7c10, 0x0018, 0x7dc1, 0x001a,
0x9037, 0x61c1, 0x7dc1, 0x001a, 0x0000, 0x0000, 0x0000, 0x0000]);
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