vhdl ex_amend example

ex_amend.eqy

[options]

[gold]
ghdl --std=08 gold.vhd -e top
prep -top top

[gate]
ghdl --std=08 gate.vhd -e top
prep -top top

[collect top]
join X
join Y

[partition top]
amend X

[strategy simple]
use sat
depth 10

gate.vhd

library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;

entity top is
   port (
      A: in std_logic;
      B: in std_logic;
      C: in std_logic;
      X: out std_logic_vector(1 downto 0);
      Y: out std_logic_vector(1 downto 0)
);
end top;

architecture rtl of top is
begin
   X <= (A xor B) & not (A xor B);
   Y <= "01" xor std_logic_vector(unsigned(std_logic_vector'("0") & (C xor X(1))) sll 1);
end architecture;

gold.vhd

library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;

entity top is
   port (
      A: in std_logic;
      B: in std_logic;
      C: in std_logic;
      X: out std_logic_vector(1 downto 0);
      Y: out std_logic_vector(1 downto 0)
);
end top;

architecture rtl of top is
begin
   X <= std_logic_vector(to_unsigned(1, 2) sll
        to_integer(unsigned(std_logic_vector'("0") & (A xor B))));
   Y <= X xor std_logic_vector(unsigned(std_logic_vector'("0") & C) sll 1);
end architecture;