keyboard.vhd

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;

entity keyboard is
    port(
        clk           :   in  std_ulogic;
        one           :   in  std_ulogic;
        rst           :   in  std_ulogic;
        one_pressed   :   in  std_ulogic
    );
end;
    
architecture behavioral of keyboard is
    signal one_latched  :   std_ulogic;
begin
    process(clk,rst)
        variable one_latched    :   std_ulogic;
    begin
        if rising_edge(clk) then
            if one='1' then
                one_latched := '1';
            elsif one = '0' and one_latched = '1' then
                one_latched := '0';
                one_pressed <= '1';
            end if;
        elsif rst = '1' then
            one_latched := '0';
            one_pressed <= '0';
        end if;
    end process;
end architecture;