convolutional.vhd

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-- Company: UGent - DMCS project 
-- Student: Francis Begyn 
-- 
-- Create Date: 1/11/2017
-- Design Name: Convolutional kernel
-- Module Name: entity - Behavioral
-- Project Name: FPGA Convolutional neural networks implentation
-- Target Devices: Xilinxs Zynq XC7Z020CLG484-1 FPGA.
-- Tool Versions: GHDL
-- Description:  
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;

entity conv is
    generic(
        N       : positive;
        bias    : positive;
        A       : integer range -2**15+1 to 2**15-1
    );
    port(
        clk     : in std_ulogic;
        filter  : in matrix3(0 to 2, 0 to 2, 0 to N);
        image   : in matrix3(0 to 2, 0 to 2, 0 to N);
        output  : out std_ulogic_vector(15 downto 0)
    );
-- Determine needed I/O for the convolutional kernel
end;

architecture Behavioral of conv is
    signal sums  : integer;
begin
    -- calculate the sum of products and store into internal signal sums
    -- so we can easily trigger the calculation
    sumProducts: process(clk)
        variable sum    : integer range -2**15+1 to 2**15-1 := 0;
    begin
        sum := 0;
        -- realise that all ths will happen in parallel on the FPGA
        for i in 0 to 2 loop
            for j in 0 to 2 loop
                for k in 0 to N loop
                    sum := sum + (image(i,j,k) * filter(i,j,k));
                end loop;
            end loop;
        end loop;
        -- if the SoP is below the bias level, mulitply with the slop A
        if sum - bias < 0 then
            sum := sum * A;
        end if;
        sums <= sum;
    end process;

    -- change the output if sums changes
    output <= std_ulogic_vector(to_signed(sums, 16));
end architecture Behavioral;