access_layer_send.vhd

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity access_layer_send is
	port(
		clk: in std_logic;
		clock_enable: in std_logic;
		rst: in std_logic;
		
		pn_start: out std_logic;

		sdo_posenc: in std_logic;
		sdo_spread: out std_logic
	);
end access_layer_send;

architecture behav of access_layer_send is

component pn_generator
port (
	clk: in std_logic;
	clock_enable: in std_logic;
	rst: in std_logic;

	input_mux: in std_logic_vector(1 downto 0); -- todo add mux

	pn_ml1: out std_logic;
	pn_ml2: out std_logic;
	pn_gold: out std_logic;
	pn_start: out std_logic
	);
end component;

signal pn_ml1_sig : std_logic;
signal pn_ml2_sig : std_logic;
signal pn_gold_sig : std_logic;
signal sdo_spread_sig : std_logic;

begin
	pn_gen : pn_generator PORT MAP(
		clk => clk,
		clock_enable => clock_enable,
		rst => rst,

		pn_ml1 => pn_ml1_sig,
		pn_ml2 => pn_ml2_sig,
		pn_gold => pn_gold_sig,
		pn_start => pn_start
	);

sdo_spread <= sdo_spread_sig;

comb_mux: process(input_mux)
begin
	case input_mux is
		when "00" => sdo_spread_sig <= sdo_posenc;
		when "01" => sdo_spread_sig <= sdo_posenc xor pn_ml1_sig;
		when "10" => sdo_spread_sig <= sdo_posenc xor pn_gold_sig;
		when "11" => sdo_spread_sig <= sdo_posenc xor pn_ml2_sig;
	end case;
end process comb_mux;



END behav;

errors

Model Technology ModelSim PE Student Edition vcom 10.4 Compiler 2014.12 Dec  3 2014
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package std_logic_arith
-- Loading package STD_LOGIC_UNSIGNED
-- Compiling entity access_layer_send
-- Compiling architecture behav of access_layer_send

** Error: Z:/Digitale Synthese/access_layer_send/access_layer_send.vhd(51): (vcom-1035) Formal port "input_mux" has OPEN or no actual associated with it.

** Error: Z:/Digitale Synthese/access_layer_send/access_layer_send.vhd(55): (vcom-1136) Unknown identifier "input_mux".

** Error: Z:/Digitale Synthese/access_layer_send/access_layer_send.vhd(55): Expression is not a signal.
** Error: Z:/Digitale Synthese/access_layer_send/access_layer_send.vhd(57): (vcom-1136) Unknown identifier "input_mux".

** Error: Z:/Digitale Synthese/access_layer_send/access_layer_send.vhd(67): VHDL Compiler exiting