Probleem

pn_generator.vhd

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity pn_generator is
	port(
		clk: in std_logic;
		clock_enable: in std_logic;
		rst: in std_logic;

		pn_ml1: out std_logic;
		pn_ml2: out std_logic;
		pn_gold: out std_logic;
		pn_start: out std_logic
	);
end pn_generator;

architecture behav of pn_generator is

signal present_shift_1 : std_logic_vector(5 downto 1) := "00000";
signal present_shift_2 : std_logic_vector(5 downto 1) := "00000";

signal next_shift_1, next_shift_2 : std_logic_vector(5 downto 1);

begin
-- TODO: vragen wat pn_start juist doet
pn_ml1 <= present_shift_1(1);
pn_ml2 <= present_shift_2(1);
pn_gold <= present_shift_1(1) xor present_shift_2(1);

com_update_next_1: process(present_shift_1)
begin
	next_shift_1 <= (present_shift_1(1) xor present_shift_1(4) ) & present_shift_1(4 downto 1);
end process com_update_next_1;

com_update_next_2: process(present_shift_2)
begin
	next_shift_2 <= (present_shift_2(1) xor present_shift_2(2) xor present_shift_2(4) xor present_shift_2(5)) & present_shift_2(4 downto 1);
end process com_update_next_2;

syn_clock: process(clk)
begin
	if rising_edge(clk) and clock_enable = '1' then
		
		if(rst = '1') then
			present_shift_1 <= "00010";
			present_shift_2 <= "00111";
		else
			present_shift_1 <= next_shift_1;
			present_shift_2 <= next_shift_2;
		end if;
	end if;
end process syn_clock;

-- com_reset: process(rst)
-- begin
--	if( rst = '1' ) then
--		next_shift_1 <= "00010";
--		next_shift_2 <= "00111";	
--	end if;
-- end process com_reset;


end behav;

pn_generator_tb.vhd

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity pn_generator_tb is
end pn_generator_tb;

architecture structural of pn_generator_tb is
-- Component debouncer
component pn_generator
port (
    
    		clk: in std_logic;
		clock_enable: in std_logic;
		rst: in std_logic;

		pn_ml1: out std_logic;
		pn_ml2: out std_logic;
		pn_gold: out std_logic;
		pn_start: out std_logic);
end component;

for uut : pn_generator use entity work.pn_generator(behav);

constant period: time := 100ns;

signal end_of_sim : boolean := false;

signal clk: std_logic;
signal clock_enable: std_logic;
signal rst: std_logic;

signal pn_ml1: std_logic;
signal pn_ml2: std_logic;
signal pn_gold: std_logic;
signal pn_start: std_logic;

BEGIN
	uut: pn_generator PORT MAP(
		clk => clk,
		clock_enable => clock_enable,
		pn_ml1 => pn_ml1,
		pn_ml2 => pn_ml2,
		pn_gold => pn_gold,
		pn_start => pn_start,
		rst => rst
	);

	clock : process
	begin
		clk <= '1';
		loop
			wait for period/2;
			clk <= '0';
			wait for period/2;
			clk <= '1';
			exit when end_of_sim;
		end loop;
		wait;
	end process clock;

test : process	
	BEGIN
		clock_enable <= '1';
		rst <= '1';
		wait for period * 2;
		rst <= '0';
		wait for period*100;
		rst <= '1';
		wait for period * 4;
		rst <= '0';
		wait for period * 120;
		end_of_sim <= true;
		WAIT;
END process test;
END;