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February 3, 2014 12:01
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<uboot>/include/configs/
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/* | |
* Copyright (C) 2012 Freescale Semiconductor, Inc. | |
* | |
* Configuration settings for the MX6Solo SABRE-AI Freescale board. | |
* | |
* This program is free software; you can redistribute it and/or | |
* modify it under the terms of the GNU General Public License as | |
* published by the Free Software Foundation; either version 2 of | |
* the License, or (at your option) any later version. | |
* | |
* This program is distributed in the hope that it will be useful, | |
* but WITHOUT ANY WARRANTY; without even the implied warranty of | |
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
* GNU General Public License for more details. | |
* | |
* You should have received a copy of the GNU General Public License | |
* along with this program; if not, write to the Free Software | |
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
* MA 02111-1307 USA | |
*/ | |
#ifndef WANDBOARD_H | |
#define WANDBOARD_H | |
#include <asm/arch/mx6.h> | |
/* High Level Configuration Options */ | |
#define CONFIG_ARMV7 /* This is armv7 Cortex-A9 CPU core */ | |
#define CONFIG_MXC | |
/*********Solo***************/ | |
#if 0 | |
#define CONFIG_MX6DL | |
#define CONFIG_MX6SOLO_DDR3 | |
#define CONFIG_DDR_32BIT | |
#endif | |
/*********DualLite***********/ | |
#if 0 | |
#define CONFIG_MX6DL | |
#define CONFIG_MX6DL_DDR3 | |
#define CONFIG_DDR_64BIT | |
#endif | |
/*********QUAD***************/ | |
#if 0 | |
#define CONFIG_MX6Q | |
/* #define CONFIG_CMD_SATA */ | |
#endif | |
/****************************/ | |
#define CONFIG_WANDBOARD | |
#define CONFIG_FLASH_HEADER | |
#define CONFIG_FLASH_HEADER_OFFSET 0x400 | |
#define CONFIG_MX6_CLK32 32768 | |
#define CONFIG_SKIP_RELOCATE_UBOOT | |
#define CONFIG_ARCH_CPU_INIT | |
#undef CONFIG_ARCH_MMU /* disable MMU first */ | |
#define CONFIG_L2_OFF /* disable L2 cache first*/ | |
#define CONFIG_MX6_HCLK_FREQ 24000000 | |
#define CONFIG_DISPLAY_CPUINFO | |
#define CONFIG_DISPLAY_BOARDINFO | |
#define CONFIG_SYS_64BIT_VSPRINTF | |
#define BOARD_LATE_INIT | |
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ | |
#define CONFIG_REVISION_TAG | |
#define CONFIG_SETUP_MEMORY_TAGS | |
/* | |
* Size of malloc() pool | |
*/ | |
#define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024) | |
/* size in bytes reserved for initial data */ | |
#define CONFIG_SYS_GBL_DATA_SIZE 128 | |
/* | |
* Hardware drivers | |
*/ | |
#define CONFIG_MXC_UART | |
#define CONFIG_MXC_GPIO | |
#define CONFIG_UART_BASE_ADDR UART1_BASE_ADDR | |
/* allow to overwrite serial and ethaddr */ | |
#define CONFIG_ENV_OVERWRITE | |
#define CONFIG_CONS_INDEX 1 | |
#define CONFIG_BAUDRATE 115200 | |
#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} | |
/*********************************************************** | |
* Command definition | |
***********************************************************/ | |
#include <config_cmd_default.h> | |
#define CONFIG_CMD_BDI /* bdinfo */ | |
#define CONFIG_CMD_CONSOLE /* coninfo */ | |
#define CONFIG_CMD_ECHO /* echo arguments */ | |
#define CONFIG_CMD_IMI /* iminfo */ | |
#define CONFIG_CMD_ITEST /* Integer (and string) test */ | |
#define CONFIG_CMD_LOADB /* loadb */ | |
#define CONFIG_CMD_LOADS /* loads */ | |
#define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop mtest */ | |
#define CONFIG_CMD_MISC /* Misc functions like sleep etc*/ | |
#define CONFIG_CMD_RUN /* run command in env variable */ | |
#define CONFIG_CMD_SAVEENV /* saveenv */ | |
#define CONFIG_CMD_SETGETDCR /* DCR support on 4xx */ | |
#define CONFIG_CMD_SOURCE /* "source" command support */ | |
#define CONFIG_CMD_XIMG /* Load part of Multi Image */ | |
#define CONFIG_MXC_FEC | |
#if defined(CONFIG_MXC_FEC) | |
#define CONFIG_CMD_PING | |
#define CONFIG_CMD_DHCP | |
#define CONFIG_CMD_MII | |
#define CONFIG_CMD_NET | |
#define CONFIG_NET_RETRY_COUNT 100 | |
#define CONFIG_NET_MULTI 1 | |
#define CONFIG_BOOTP_SUBNETMASK | |
#define CONFIG_BOOTP_GATEWAY | |
#define CONFIG_BOOTP_DNS | |
#define CONFIG_PRIME "FEC0" | |
#define CONFIG_FEC0_IOBASE ENET_BASE_ADDR | |
#define CONFIG_FEC0_PINMUX -1 | |
#define CONFIG_FEC0_MIIBASE -1 | |
#define CONFIG_FEC0_PHY_ADDR 1 | |
#define CONFIG_ETH_PRIME | |
#define CONFIG_RMII | |
#define CONFIG_IPADDR 192.168.1.103 | |
#define CONFIG_SERVERIP 192.168.1.101 | |
#define CONFIG_NETMASK 255.255.255.0 | |
#endif | |
#define CONFIG_CMD_IMXOTP | |
#define CONFIG_GET_FEC_MAC_ADDR_FROM_IIM | |
/* Enable below configure when supporting nand */ | |
#define CONFIG_CMD_MMC | |
#define CONFIG_CMD_ENV | |
#define CONFIG_CMD_REGUL | |
#define CONFIG_CMD_CLOCK | |
#define CONFIG_REF_CLK_FREQ CONFIG_MX6_HCLK_FREQ | |
#undef CONFIG_CMD_IMLS | |
#define CONFIG_CMD_IMX_DOWNLOAD_MODE | |
#define CONFIG_BOOTDELAY 2 | |
#define CONFIG_LOADADDR 0x10800000 /* loadaddr env var */ | |
#ifdef CONFIG_MX6Q | |
#define CONFIG_RD_LOADADDR (0x1300000) | |
#else | |
#define CONFIG_RD_LOADADDR (CONFIG_LOADADDR + 0x300000) | |
#endif | |
/* | |
#define CONFIG_EXTRA_ENV_SETTINGS \ | |
"bootargs=console=ttymxc0,115200 " \ | |
"root=/dev/mmcblk0p1 rootwait ro" \ | |
"video=mxcfb0:dev=hdmi,1920x1080M@60,if=RGB24" \ | |
"bootcmd=mmc dev 0; " \ | |
"mmc read ${loadaddr} 0x800 0x2200; bootm\0" | |
*/ | |
#define CONFIG_ARP_TIMEOUT 200UL | |
/* | |
* Miscellaneous configurable options | |
*/ | |
#define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
#ifdef CONFIG_DDR_32BIT | |
#define CONFIG_SYS_PROMPT "WANDBOARD SOLO U-Boot > " | |
#elif defined(CONFIG_DDR_64BIT) | |
#define CONFIG_SYS_PROMPT "WANDBOARD DualLite U-Boot > " | |
#else | |
#define CONFIG_SYS_PROMPT "WANDBOARD QUAD U-Boot > " | |
#endif | |
#define CONFIG_AUTO_COMPLETE | |
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ | |
/* Print Buffer Size */ | |
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) | |
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
#define CONFIG_SYS_MEMTEST_START 0x10000000 /* memtest works on */ | |
#define CONFIG_SYS_MEMTEST_END 0x10010000 | |
#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ | |
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR | |
#define CONFIG_SYS_HZ 1000 | |
#define CONFIG_CMDLINE_EDITING | |
/* | |
* OCOTP Configs | |
*/ | |
#ifdef CONFIG_CMD_IMXOTP | |
#define CONFIG_IMX_OTP | |
#define IMX_OTP_BASE OCOTP_BASE_ADDR | |
#define IMX_OTP_ADDR_MAX 0x7F | |
#define IMX_OTP_DATA_ERROR_VAL 0xBADABADA | |
#endif | |
/* | |
* I2C Configs | |
*/ | |
#ifdef CONFIG_CMD_I2C | |
#define CONFIG_HARD_I2C 1 | |
#define CONFIG_I2C_MXC 1 | |
#define CONFIG_SYS_I2C_PORT I2C3_BASE_ADDR | |
#define CONFIG_SYS_I2C_SPEED 100000 | |
#define CONFIG_SYS_I2C_SLAVE 0x30 | |
#endif | |
/* Regulator Configs */ | |
#ifdef CONFIG_CMD_REGUL | |
#define CONFIG_ANATOP_REGULATOR | |
#define CONFIG_CORE_REGULATOR_NAME "vdd1p1" | |
#define CONFIG_PERIPH_REGULATOR_NAME "vdd1p1" | |
#endif | |
/* | |
* SATA Configs | |
*/ | |
#ifdef CONFIG_CMD_SATA | |
#define CONFIG_DWC_AHSATA | |
#define CONFIG_SYS_SATA_MAX_DEVICE 1 | |
#define CONFIG_DWC_AHSATA_PORT_ID 0 | |
#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR | |
#define CONFIG_LBA48 | |
#define CONFIG_LIBATA | |
#define CONFIG_DOS_PARTITION 1 | |
#define CONFIG_CMD_FAT 1 | |
#define CONFIG_CMD_EXT2 1 | |
#endif | |
/* | |
* MMC Configs | |
*/ | |
#ifdef CONFIG_CMD_MMC | |
#define CONFIG_MMC | |
#define CONFIG_GENERIC_MMC | |
#define CONFIG_IMX_MMC | |
#define CONFIG_SYS_FSL_USDHC_NUM 3 | |
#define CONFIG_SYS_FSL_ESDHC_ADDR 0 | |
#define CONFIG_SYS_MMC_ENV_DEV 2 | |
#define CONFIG_DOS_PARTITION 1 | |
#define CONFIG_CMD_FAT 1 | |
#define CONFIG_CMD_EXT2 1 | |
/* detect whether SD1, 2, 3, or 4 is boot device */ | |
// #define CONFIG_DYNAMIC_MMC_DEVNO | |
/* SD3 and SD4 are 8 bit */ | |
#define CONFIG_MMC_8BIT_PORTS 0x0 | |
/* Setup target delay in DDR mode for each SD port */ | |
#define CONFIG_GET_DDR_TARGET_DELAY | |
#endif | |
/*----------------------------------------------------------------------- | |
* Stack sizes | |
* | |
* The stack sizes are set up in start.S using the settings below | |
*/ | |
#define CONFIG_STACKSIZE (256 * 1024) /* regular stack */ | |
/*----------------------------------------------------------------------- | |
* Physical Memory Map | |
*/ | |
#define CONFIG_NR_DRAM_BANKS 1 | |
#define PHYS_SDRAM_1 CSD0_DDR_BASE_ADDR | |
#ifdef CONFIG_DDR_32BIT | |
#define PHYS_SDRAM_1_SIZE (512u * 1024 * 1024) | |
#elif defined(CONFIG_DDR_64BIT) | |
#define PHYS_SDRAM_1_SIZE (1u * 1024 * 1024 * 1024) | |
#else | |
#define PHYS_SDRAM_1_SIZE (2u * 1024 * 1024 * 1024) | |
#endif | |
#define iomem_valid_addr(addr, size) \ | |
(addr >= PHYS_SDRAM_1 && addr <= (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)) | |
/*----------------------------------------------------------------------- | |
* FLASH and environment organization | |
*/ | |
#define CONFIG_SYS_NO_FLASH | |
/* Monitor at beginning of flash */ | |
#define CONFIG_FSL_ENV_IN_MMC | |
#define CONFIG_ENV_SECT_SIZE (8 * 1024) | |
#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE | |
#define CONFIG_ENV_IS_IN_MMC 1 | |
#define CONFIG_ENV_OFFSET (768 * 1024) | |
#ifdef CONFIG_SPLASH_SCREEN | |
/* | |
* Framebuffer and LCD | |
*/ | |
#define CONFIG_LCD | |
#define CONFIG_IPU_V3H | |
#define CONFIG_VIDEO_MX5 | |
#define CONFIG_IPU_CLKRATE 260000000 | |
#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE | |
#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE | |
#define CONFIG_SYS_CONSOLE_IS_IN_ENV | |
#define LCD_BPP LCD_COLOR16 | |
#define CONFIG_CMD_BMP | |
#define CONFIG_BMP_8BPP | |
#define CONFIG_FB_BASE (TEXT_BASE + 0x300000) | |
#define CONFIG_SPLASH_SCREEN_ALIGN | |
#define CONFIG_SYS_WHITE_ON_BLACK | |
#endif | |
#endif /* __CONFIG_H */ |
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/* | |
* Copyright (C) 2012 Freescale Semiconductor, Inc. | |
* | |
* Configuration settings for the MX6Q Sabre Lite2 Freescale board. | |
* | |
* This program is free software; you can redistribute it and/or | |
* modify it under the terms of the GNU General Public License as | |
* published by the Free Software Foundation; either version 2 of | |
* the License, or (at your option) any later version. | |
* | |
* This program is distributed in the hope that it will be useful, | |
* but WITHOUT ANY WARRANTY; without even the implied warranty of | |
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
* GNU General Public License for more details. | |
* | |
* You should have received a copy of the GNU General Public License | |
* along with this program; if not, write to the Free Software | |
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
* MA 02111-1307 USA | |
*/ | |
#ifndef WANDBOARD_ANDROID_H | |
#define WANDBOARD_ANDROID_H | |
#include "wandboard.h" | |
#define CONFIG_USB_DEVICE | |
#define CONFIG_IMX_UDC 1 | |
#define CONFIG_FASTBOOT 1 | |
#define CONFIG_FASTBOOT_STORAGE_EMMC_SATA | |
#define CONFIG_FASTBOOT_VENDOR_ID 0x18d1 | |
#define CONFIG_FASTBOOT_PRODUCT_ID 0x0d02 | |
#define CONFIG_FASTBOOT_BCD_DEVICE 0x311 | |
#define CONFIG_FASTBOOT_MANUFACTURER_STR "Freescale" | |
#define CONFIG_FASTBOOT_PRODUCT_NAME_STR "i.mx6q Sabre Smart Device" | |
#define CONFIG_FASTBOOT_INTERFACE_STR "Android fastboot" | |
#define CONFIG_FASTBOOT_CONFIGURATION_STR "Android fastboot" | |
#define CONFIG_FASTBOOT_SERIAL_NUM "12345" | |
#define CONFIG_FASTBOOT_SATA_NO 0 | |
/* For system.img growing up more than 256MB, more buffer needs | |
* to receive the system.img*/ | |
#define CONFIG_FASTBOOT_TRANSFER_BUF 0x2c000000 | |
#define CONFIG_FASTBOOT_TRANSFER_BUF_SIZE 0x14000000 /* 320M byte */ | |
#define CONFIG_CMD_BOOTI | |
#define CONFIG_ANDROID_RECOVERY | |
/* which mmc bus is your main storage ? */ | |
#define CONFIG_ANDROID_MAIN_MMC_BUS 2 | |
#define CONFIG_ANDROID_BOOT_PARTITION_MMC 1 | |
#define CONFIG_ANDROID_SYSTEM_PARTITION_MMC 5 | |
#define CONFIG_ANDROID_RECOVERY_PARTITION_MMC 2 | |
#define CONFIG_ANDROID_CACHE_PARTITION_MMC 6 | |
/* | |
#define CONFIG_ANDROID_MAIN_MMC_BUS 2 | |
#define CONFIG_ANDROID_BOOT_PARTITION_MMC 1 | |
#define CONFIG_ANDROID_SYSTEM_PARTITION_MMC 4 | |
#define CONFIG_ANDROID_RECOVERY_PARTITION_MMC 2 | |
#define CONFIG_ANDROID_CACHE_PARTITION_MMC 3 | |
*/ | |
#define CONFIG_ANDROID_RECOVERY_BOOTARGS_MMC NULL | |
#define CONFIG_ANDROID_RECOVERY_BOOTCMD_MMC \ | |
"booti mmc2 recovery" | |
#define CONFIG_ANDROID_RECOVERY_CMD_FILE "/recovery/command" | |
#define CONFIG_INITRD_TAG | |
#undef CONFIG_LOADADDR | |
#undef CONFIG_RD_LOADADDR | |
#undef CONFIG_EXTRA_ENV_SETTINGS | |
#define CONFIG_LOADADDR 0x10800000 /* loadaddr env var */ | |
#define CONFIG_RD_LOADADDR 0x11000000 | |
#define CONFIG_INITRD_TAG | |
#define CONFIG_BOOTCOMMAND "ext2load mmc 2:1 0x12000000 uImage;bootm 0x12000000;" | |
// From /media/BTRFS/android/device/fsl/wandboard/BoardConfig.mk | |
// console=ttymxc0,115200 init=/init video=mxcfb0:dev=hdmi,1280x720M@60,if=RGB24,bpp=32 video=mxcfb1:off video=mxcfb2:off fbmem=28M vmalloc=400M androidboot.console=ttymxc0 androidboot.hardware=freescale | |
#define CONFIG_EXTRA_ENV_SETTINGS \ | |
"netdev=eth0\0" \ | |
"ethprime=FEC0\0" \ | |
"fastboot_dev=mmc2\0" \ | |
"bootargs=console=ttymxc0,115200 init=/init " \ | |
"video=mxcfb0:dev=hdmi,1280x720M@60,if=RGB24,bpp=32 " \ | |
"video=mxcfb1:off video=mxcfb2:off " \ | |
"fbmem=28M vmalloc=400M " \ | |
"androidboot.console=ttymxc0 " \ | |
"androidboot.hardware=freescale " \ | |
"root=/dev/mmcblk0p2 rw " \ | |
"rootfstype=ext4 rootwait\0" \ | |
//"bootcmd=booti mmc2\0" \ | |
"bootcmd=ext2load mmc 2:1 0x12000000 uImage;" \ | |
"bootm 0x12000000;\0" \ | |
"splashimage=0x30000000\0" \ | |
"splashpos=m,m\0" \ | |
"lvds_num=1\0" | |
#endif |
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#ifndef WANDBOARD_ANDROID_QUAD_H | |
#define WANDBOARD_ANDROID_QUAD_H | |
/*********Solo***************/ | |
#if 0 | |
#define CONFIG_MX6DL | |
#define CONFIG_MX6SOLO_DDR3 | |
#define CONFIG_DDR_32BIT | |
#endif | |
/*********DualLite***********/ | |
#if 0 | |
#define CONFIG_MX6DL | |
#define CONFIG_MX6DL_DDR3 | |
#define CONFIG_DDR_64BIT | |
#endif | |
/*********QUAD***************/ | |
#if 1 | |
#define CONFIG_MX6Q | |
/* #define CONFIG_CMD_SATA */ | |
#endif | |
/****************************/ | |
#include "wandboard_android.h" | |
#endif |
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U-Boot 2009.08-00687-gb87aa36-dirty (feb 03 2014 - 12:45:38)
CPU: Freescale i.MX6 family TO1.2 at 792 MHz
Thermal sensor with ratio = 190
Temperature: 23 C, calibration data 0x5b252869
mx6q pll1: 792MHz
mx6q pll2: 528MHz
mx6q pll3: 480MHz
mx6q pll8: 50MHz
ipg clock : 66000000Hz
ipg per clock : 66000000Hz
uart clock : 80000000Hz
cspi clock : 60000000Hz
ahb clock : 132000000Hz
axi clock : 264000000Hz
emi_slow clock: 132000000Hz
ddr clock : 528000000Hz
usdhc1 clock : 198000000Hz
usdhc2 clock : 198000000Hz
usdhc3 clock : 198000000Hz
usdhc4 clock : 198000000Hz
nfc clock : 24000000Hz
Board: i.MX6Q-WandBoard: unknown-board Board: 0x63012 [POR ]
Boot Device: SD
DRAM: 2 GB
MMC: FSL_USDHC: 0,FSL_USDHC: 1,FSL_USDHC: 2
*** Warning - bad CRC or MMC, using default environment
In: serial
Out: serial
Err: serial
Gotr MAC = 00:1F:7B:B4:05:13
Net: got MAC address from IIM: 00:1f:7b:b4:05:13
FEC0 [PRIME]
WANDBOARD QUAD U-Boot > printenv
bootdelay=2
baudrate=115200
ipaddr=192.168.1.103
serverip=192.168.1.101
netmask=255.255.255.0
loadaddr=0x10800000
rd_loadaddr=0x11000000
netdev=eth0
ethprime=FEC0
fastboot_dev=mmc2
bootargs=console=ttymxc0,115200 init=/init video=mxcfb0:dev=hdmi,1280x720M@60,if=RGB24,bpp=32 video=mxcfb1:off video=mxcfb2:off fbmem=28M vmalloc=400M androidboot.console=ttymxc0 androidboot.hardware=freescale root=/dev/mmcblk0p2 rw rootfstype=ext4 rootwait
stdin=serial
stdout=serial
stderr=serial
ethact=FEC0
Environment size: 492/8188 bytes
WANDBOARD QUAD U-Boot > boot
WANDBOARD QUAD U-Boot > printenv bootcmd
Error: "bootcmd" not defined
WANDBOARD QUAD U-Boot >