up down counter prob

up_down_counter.vhd

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity up_down_counter is
	port(
		clk: in std_logic;
		clock_enable: in std_logic;
		rst: in std_logic;

		up_signal: in std_logic;
		down_signal: in std_logic;
		counter_value: out std_logic_vector(3 downto 0)
	);
end up_down_counter;

architecture behav of up_down_counter is

	signal next_counter_value: std_logic_vector(3 downto 0) := (others => '0');
	signal present_counter_value: std_logic_vector(3 downto 0) := (others => '0');

begin

counter_value <= present_counter_value;

com_update_counter_up: process(up_signal)
begin
	if(up_signal = '1') then
		if(present_counter_value = "1001") then
			next_counter_value <= (others => '0');
		else
			next_counter_value <= present_counter_value + '1';
		end if;
	end if;
end process com_update_counter_up;

com_update_counter_down: process(down_signal)
begin
	if(down_signal = '1') then
		if(present_counter_value = "0000") then
			next_counter_value <= "1001";
		else
			next_counter_value <= present_counter_value - '1';
		end if;
	end if;
end process com_update_counter_down;

syn_update_counter: process(clk)
begin
	if rising_edge(clk) and clock_enable = '1' then
		if( rst = '1') then
			present_counter_value <= (others => '0');
		else	
			present_counter_value <= next_counter_value;
		end if;
	end if;
end process syn_update_counter;

end behav;

up_down_counter_tb.vhd

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity up_down_counter_tb is
end up_down_counter_tb;

architecture structural of up_down_counter_tb is

component up_down_counter
port(
	clk: in std_logic;
	clock_enable: in std_logic;
	rst: in std_logic;

	up_signal: in std_logic;
	down_signal: in std_logic;
	counter_value: out std_logic_vector(3 downto 0)
);
end component;

for uut : up_down_counter use entity work.up_down_counter(behav);

constant period: time := 100ns;

signal end_of_sim : boolean := false;

signal clk: std_logic;
signal clock_enable: std_logic := '1';
signal rst: std_logic := '0';

signal up_signal: std_logic := '0';
signal down_signal: std_logic := '0';
signal counter_value: std_logic_vector(3 downto 0);

BEGIN
	uut: up_down_counter PORT MAP(
		clk => clk,
		clock_enable => clock_enable,
		rst => rst,
		
		up_signal => up_signal,
		down_signal => down_signal,
		counter_value => counter_value
	);

	clock : process
	begin
		clk <= '1';
		loop
			wait for period/2;
			clk <= '0';
			wait for period/2;
			clk <= '1';
			exit when end_of_sim;
		end loop;
		wait;
	end process clock;

test : process

	procedure pressbutton_up(presses : integer) is
	begin
		for I in 0 to 15 loop
			up_signal <= '1';
			wait for period;
			up_signal <= '0';
			wait for period;
		end loop;
	end pressbutton_up;

	procedure pressbutton_down(presses : integer) is
	begin
		for I in 0 to 15 loop
			down_signal <= '1';
			wait for period;
			down_signal <= '0';
			wait for period;
		end loop;
	end pressbutton_down;

BEGIN
	wait for period*2;
	pressbutton_up(9);
	pressbutton_down(9);
	rst <= '1';
	wait for period;
	rst <= '0';
	pressbutton_up(20);
	pressbutton_down(20);

	end_of_sim <= true;
	WAIT;

END process test;
end;