Register example in Verilog

Register.v

module Register(clock, r_enable, data_in, data_out);

input             clock;
input             r_enable;
input      [15:0] data_in;
output reg [15:0] data_out;

always @(posedge clock)
begin
    if(r_enable)
        data_out <= data_in;
end

endmodule

RegTestbench.v

`include "Register.v"
module RegisterTestbench;

reg         clock = 0;
reg         enable = 1;
reg  [15:0] value_in;
wire [15:0] value_out;

always #1 clock = !clock;

initial $dumpfile("registertestbench.vcd");
initial $dumpvars(0, RegisterTestbench);

Register r(clock, enable, value_in, value_out);

initial begin
    //These events must be in chronological order.
    # 5 value_in = 31;
    # 5 value_in = 127;
    # 5 enable = 0;
    # 5 value_in = 1023;
    # 5 $finish;
end
endmodule

To run this, use:
iverilog RegTestbench.v

An to display the result, just use gtkwave:
gtkwave registertestbench.vcd

Output at: http://en.zimagez.com/zimage/screenshot-05-11-2014-1613320.php

nice