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April 29, 2014 07:27
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insertps llc output
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| Args: ../llvm-cmake/bin/llc -O3 -mattr=sse4.1 -o - insertps.ll -debug | |
| Features:+64bit,+sse2,+sse4.1 | |
| CPU:generic | |
| Subtarget features: SSELevel 6, 3DNowLevel 0, 64bit 1 | |
| .section __TEXT,__text,regular,pure_instructions | |
| .macosx_version_min 13, 1 | |
| ********** Begin Constant Hoisting ********** | |
| ********** Function: move_1_to_2 | |
| ********** End Constant Hoisting ********** | |
| ********** Begin Constant Hoisting ********** | |
| ********** Function: dont_move_elems | |
| ********** End Constant Hoisting ********** | |
| ---- Branch Probability Info : move_1_to_2 ---- | |
| Computing probabilities for entry | |
| === move_1_to_2 | |
| Initial selection DAG: BB#0 'move_1_to_2:entry' | |
| SelectionDAG has 22 nodes: | |
| 0x7ff2bac071c0: ch = EntryToken | |
| 0x7ff2bac071c0: <multiple use> | |
| 0x7ff2bb802600: v4i32 = Register %vreg0 | |
| 0x7ff2bb802708: v4i32,ch = CopyFromReg 0x7ff2bac071c0, 0x7ff2bb802600 [ORD=1] | |
| 0x7ff2bac071c0: <multiple use> | |
| 0x7ff2bb802810: v4i32 = Register %vreg1 | |
| 0x7ff2bb802918: v4i32,ch = CopyFromReg 0x7ff2bac071c0, 0x7ff2bb802810 [ORD=1] | |
| 0x7ff2bb802a20: i32 = Constant<1> | |
| 0x7ff2bb802b28: i64 = Constant<1> | |
| 0x7ff2bb802d38: i32 = Constant<3> | |
| 0x7ff2bb802e40: i64 = Constant<3> | |
| 0x7ff2bb803158: i32 = Constant<2> | |
| 0x7ff2bb805118: v4i32 = Register %XMM0 | |
| 0x7ff2bac071c0: <multiple use> | |
| 0x7ff2bb805118: <multiple use> | |
| 0x7ff2bb803050: v4i32 = undef | |
| 0x7ff2bb802708: <multiple use> | |
| 0x7ff2bb802b28: <multiple use> | |
| 0x7ff2bb802c30: i32 = extract_vector_elt 0x7ff2bb802708, 0x7ff2bb802b28 [ORD=2] | |
| 0x7ff2bb803260: i64 = Constant<2> | |
| 0x7ff2bb803368: v4i32 = insert_vector_elt 0x7ff2bb803050, 0x7ff2bb802c30, 0x7ff2bb803260 [ORD=4] | |
| 0x7ff2bb803470: i32 = Constant<0> | |
| 0x7ff2bb802b28: <multiple use> | |
| 0x7ff2bb804e00: v4i32 = insert_vector_elt 0x7ff2bb803368, 0x7ff2bb803470, 0x7ff2bb802b28 [ORD=5] | |
| 0x7ff2bb802708: <multiple use> | |
| 0x7ff2bb802e40: <multiple use> | |
| 0x7ff2bb802f48: i32 = extract_vector_elt 0x7ff2bb802708, 0x7ff2bb802e40 [ORD=3] | |
| 0x7ff2bb802e40: <multiple use> | |
| 0x7ff2bb804f08: v4i32 = insert_vector_elt 0x7ff2bb804e00, 0x7ff2bb802f48, 0x7ff2bb802e40 [ORD=6] | |
| 0x7ff2bb805220: ch,glue = CopyToReg 0x7ff2bac071c0, 0x7ff2bb805118, 0x7ff2bb804f08 [ORD=7] | |
| 0x7ff2bb805220: <multiple use> | |
| 0x7ff2bb805010: i16 = TargetConstant<0> | |
| 0x7ff2bb805118: <multiple use> | |
| 0x7ff2bb805220: <multiple use> | |
| 0x7ff2bb805328: ch = X86ISD::RET_FLAG 0x7ff2bb805220, 0x7ff2bb805010, 0x7ff2bb805118, 0x7ff2bb805220:1 [ORD=7] | |
| Replacing.3 0x7ff2bb803368: v4i32 = insert_vector_elt 0x7ff2bb803050, 0x7ff2bb802c30, 0x7ff2bb803260 [ORD=4] | |
| With: 0x7ff2bb805538: v4i32 = BUILD_VECTOR 0x7ff2bb805430, 0x7ff2bb805430, 0x7ff2bb802c30, 0x7ff2bb805430 [ORD=4] | |
| Replacing.3 0x7ff2bb804e00: v4i32 = insert_vector_elt 0x7ff2bb805538, 0x7ff2bb803470, 0x7ff2bb802b28 [ORD=5] | |
| With: 0x7ff2bb803050: v4i32 = BUILD_VECTOR 0x7ff2bb805430, 0x7ff2bb803470, 0x7ff2bb802c30, 0x7ff2bb805430 [ORD=5] | |
| Replacing.3 0x7ff2bb804f08: v4i32 = insert_vector_elt 0x7ff2bb803050, 0x7ff2bb802f48, 0x7ff2bb802e40 [ORD=6] | |
| With: 0x7ff2bb805538: v4i32 = BUILD_VECTOR 0x7ff2bb805430, 0x7ff2bb803470, 0x7ff2bb802c30, 0x7ff2bb802f48 [ORD=6] | |
| Optimized lowered selection DAG: BB#0 'move_1_to_2:entry' | |
| SelectionDAG has 14 nodes: | |
| 0x7ff2bac071c0: ch = EntryToken | |
| 0x7ff2bac071c0: <multiple use> | |
| 0x7ff2bb802600: v4i32 = Register %vreg0 | |
| 0x7ff2bb802708: v4i32,ch = CopyFromReg 0x7ff2bac071c0, 0x7ff2bb802600 [ORD=1] | |
| 0x7ff2bb805118: v4i32 = Register %XMM0 | |
| 0x7ff2bac071c0: <multiple use> | |
| 0x7ff2bb805118: <multiple use> | |
| 0x7ff2bb805430: i32 = undef | |
| 0x7ff2bb803470: i32 = Constant<0> | |
| 0x7ff2bb802708: <multiple use> | |
| 0x7ff2bb802b28: i64 = Constant<1> | |
| 0x7ff2bb802c30: i32 = extract_vector_elt 0x7ff2bb802708, 0x7ff2bb802b28 [ORD=2] | |
| 0x7ff2bb802708: <multiple use> | |
| 0x7ff2bb802e40: i64 = Constant<3> | |
| 0x7ff2bb802f48: i32 = extract_vector_elt 0x7ff2bb802708, 0x7ff2bb802e40 [ORD=3] | |
| 0x7ff2bb805538: v4i32 = BUILD_VECTOR 0x7ff2bb805430, 0x7ff2bb803470, 0x7ff2bb802c30, 0x7ff2bb802f48 [ORD=6] | |
| 0x7ff2bb805220: ch,glue = CopyToReg 0x7ff2bac071c0, 0x7ff2bb805118, 0x7ff2bb805538 [ORD=7] | |
| 0x7ff2bb805220: <multiple use> | |
| 0x7ff2bb805010: i16 = TargetConstant<0> | |
| 0x7ff2bb805118: <multiple use> | |
| 0x7ff2bb805220: <multiple use> | |
| 0x7ff2bb805328: ch = X86ISD::RET_FLAG 0x7ff2bb805220, 0x7ff2bb805010, 0x7ff2bb805118, 0x7ff2bb805220:1 [ORD=7] | |
| Legally typed node: 0x7ff2bb805430: i32 = undef [ID=0] | |
| Legally typed node: 0x7ff2bb805118: v4i32 = Register %XMM0 [ID=0] | |
| Legally typed node: 0x7ff2bb805010: i16 = TargetConstant<0> [ID=0] | |
| Legally typed node: 0x7ff2bb803470: i32 = Constant<0> [ID=0] | |
| Legally typed node: 0x7ff2bb802e40: i64 = Constant<3> [ID=0] | |
| Legally typed node: 0x7ff2bb802b28: i64 = Constant<1> [ID=0] | |
| Legally typed node: 0x7ff2bb802600: v4i32 = Register %vreg0 [ID=0] | |
| Legally typed node: 0x7ff2bac071c0: ch = EntryToken [ID=0] | |
| Legally typed node: 0x7ff2bb802708: v4i32,ch = CopyFromReg 0x7ff2bac071c0, 0x7ff2bb802600 [ORD=1] [ID=0] | |
| Legally typed node: 0x7ff2bb802c30: i32 = extract_vector_elt 0x7ff2bb802708, 0x7ff2bb802b28 [ORD=2] [ID=0] | |
| Legally typed node: 0x7ff2bb802f48: i32 = extract_vector_elt 0x7ff2bb802708, 0x7ff2bb802e40 [ORD=3] [ID=0] | |
| Legally typed node: 0x7ff2bb805538: v4i32 = BUILD_VECTOR 0x7ff2bb805430, 0x7ff2bb803470, 0x7ff2bb802c30, 0x7ff2bb802f48 [ORD=6] [ID=0] | |
| Legally typed node: 0x7ff2bb805220: ch,glue = CopyToReg 0x7ff2bac071c0, 0x7ff2bb805118, 0x7ff2bb805538 [ORD=7] [ID=0] | |
| Legally typed node: 0x7ff2bb805328: ch = X86ISD::RET_FLAG 0x7ff2bb805220, 0x7ff2bb805010, 0x7ff2bb805118, 0x7ff2bb805220:1 [ORD=7] [ID=0] | |
| Legally typed node: 0x7fff5974ee40: ch = handlenode 0x7ff2bb805328 [ID=0] | |
| Type-legalized selection DAG: BB#0 'move_1_to_2:entry' | |
| SelectionDAG has 14 nodes: | |
| 0x7ff2bac071c0: ch = EntryToken [ID=-3] | |
| 0x7ff2bac071c0: <multiple use> | |
| 0x7ff2bb802600: v4i32 = Register %vreg0 [ID=-3] | |
| 0x7ff2bb802708: v4i32,ch = CopyFromReg 0x7ff2bac071c0, 0x7ff2bb802600 [ORD=1] [ID=-3] | |
| 0x7ff2bb805118: v4i32 = Register %XMM0 [ID=-3] | |
| 0x7ff2bac071c0: <multiple use> | |
| 0x7ff2bb805118: <multiple use> | |
| 0x7ff2bb805430: i32 = undef [ID=-3] | |
| 0x7ff2bb803470: i32 = Constant<0> [ID=-3] | |
| 0x7ff2bb802708: <multiple use> | |
| 0x7ff2bb802b28: i64 = Constant<1> [ID=-3] | |
| 0x7ff2bb802c30: i32 = extract_vector_elt 0x7ff2bb802708, 0x7ff2bb802b28 [ORD=2] [ID=-3] | |
| 0x7ff2bb802708: <multiple use> | |
| 0x7ff2bb802e40: i64 = Constant<3> [ID=-3] | |
| 0x7ff2bb802f48: i32 = extract_vector_elt 0x7ff2bb802708, 0x7ff2bb802e40 [ORD=3] [ID=-3] | |
| 0x7ff2bb805538: v4i32 = BUILD_VECTOR 0x7ff2bb805430, 0x7ff2bb803470, 0x7ff2bb802c30, 0x7ff2bb802f48 [ORD=6] [ID=-3] | |
| 0x7ff2bb805220: ch,glue = CopyToReg 0x7ff2bac071c0, 0x7ff2bb805118, 0x7ff2bb805538 [ORD=7] [ID=-3] | |
| 0x7ff2bb805220: <multiple use> | |
| 0x7ff2bb805010: i16 = TargetConstant<0> [ID=-3] | |
| 0x7ff2bb805118: <multiple use> | |
| 0x7ff2bb805220: <multiple use> | |
| 0x7ff2bb805328: ch = X86ISD::RET_FLAG 0x7ff2bb805220, 0x7ff2bb805010, 0x7ff2bb805118, 0x7ff2bb805220:1 [ORD=7] [ID=-3] | |
| Legalized selection DAG: BB#0 'move_1_to_2:entry' | |
| SelectionDAG has 9 nodes: | |
| 0x7ff2bac071c0: ch = EntryToken [ID=0] | |
| 0x7ff2bb805118: v4i32 = Register %XMM0 [ID=6] | |
| 0x7ff2bac071c0: <multiple use> | |
| 0x7ff2bb802600: v4i32 = Register %vreg0 [ID=1] | |
| 0x7ff2bb802708: v4i32,ch = CopyFromReg 0x7ff2bac071c0, 0x7ff2bb802600 [ORD=1] [ID=8] | |
| 0x7ff2bac071c0: <multiple use> | |
| 0x7ff2bb805118: <multiple use> | |
| 0x7ff2bb802708: <multiple use> | |
| 0x7ff2bb802708: <multiple use> | |
| 0x7ff2bb802810: i64 = Constant<99> | |
| 0x7ff2bb802918: v4i32 = X86ISD::INSERTPS 0x7ff2bb802708, 0x7ff2bb802708, 0x7ff2bb802810 [ORD=6] | |
| 0x7ff2bb805220: ch,glue = CopyToReg 0x7ff2bac071c0, 0x7ff2bb805118, 0x7ff2bb802918 [ORD=7] [ID=12] | |
| 0x7ff2bb805220: <multiple use> | |
| 0x7ff2bb805010: i16 = TargetConstant<0> [ID=5] | |
| 0x7ff2bb805118: <multiple use> | |
| 0x7ff2bb805220: <multiple use> | |
| 0x7ff2bb805328: ch = X86ISD::RET_FLAG 0x7ff2bb805220, 0x7ff2bb805010, 0x7ff2bb805118, 0x7ff2bb805220:1 [ORD=7] [ID=13] | |
| Optimized legalized selection DAG: BB#0 'move_1_to_2:entry' | |
| SelectionDAG has 9 nodes: | |
| 0x7ff2bac071c0: ch = EntryToken [ID=0] | |
| 0x7ff2bb805118: v4i32 = Register %XMM0 [ID=6] | |
| 0x7ff2bac071c0: <multiple use> | |
| 0x7ff2bb802600: v4i32 = Register %vreg0 [ID=1] | |
| 0x7ff2bb802708: v4i32,ch = CopyFromReg 0x7ff2bac071c0, 0x7ff2bb802600 [ORD=1] [ID=8] | |
| 0x7ff2bac071c0: <multiple use> | |
| 0x7ff2bb805118: <multiple use> | |
| 0x7ff2bb802708: <multiple use> | |
| 0x7ff2bb802708: <multiple use> | |
| 0x7ff2bb802810: i64 = Constant<99> | |
| 0x7ff2bb802918: v4i32 = X86ISD::INSERTPS 0x7ff2bb802708, 0x7ff2bb802708, 0x7ff2bb802810 [ORD=6] | |
| 0x7ff2bb805220: ch,glue = CopyToReg 0x7ff2bac071c0, 0x7ff2bb805118, 0x7ff2bb802918 [ORD=7] [ID=12] | |
| 0x7ff2bb805220: <multiple use> | |
| 0x7ff2bb805010: i16 = TargetConstant<0> [ID=5] | |
| 0x7ff2bb805118: <multiple use> | |
| 0x7ff2bb805220: <multiple use> | |
| 0x7ff2bb805328: ch = X86ISD::RET_FLAG 0x7ff2bb805220, 0x7ff2bb805010, 0x7ff2bb805118, 0x7ff2bb805220:1 [ORD=7] [ID=13] | |
| ===== Instruction selection begins: BB#0 'entry' | |
| Selecting: 0x7ff2bb805328: ch = X86ISD::RET_FLAG 0x7ff2bb805220, 0x7ff2bb805010, 0x7ff2bb805118, 0x7ff2bb805220:1 [ORD=7] [ID=8] | |
| ISEL: Starting pattern match on root node: 0x7ff2bb805328: ch = X86ISD::RET_FLAG 0x7ff2bb805220, 0x7ff2bb805010, 0x7ff2bb805118, 0x7ff2bb805220:1 [ORD=7] [ID=8] | |
| Skipped scope entry (due to false predicate) at index 96026, continuing at 96035 | |
| Morphed node: 0x7ff2bb805328: ch = RETQ 0x7ff2bb805118, 0x7ff2bb805220, 0x7ff2bb805220:1 [ORD=7] | |
| ISEL: Match complete! | |
| => 0x7ff2bb805328: ch = RETQ 0x7ff2bb805118, 0x7ff2bb805220, 0x7ff2bb805220:1 [ORD=7] | |
| Selecting: 0x7ff2bb805220: ch,glue = CopyToReg 0x7ff2bac071c0, 0x7ff2bb805118, 0x7ff2bb802918 [ORD=7] [ID=7] | |
| => 0x7ff2bb805220: ch,glue = CopyToReg 0x7ff2bac071c0, 0x7ff2bb805118, 0x7ff2bb802918 [ORD=7] | |
| Selecting: 0x7ff2bb802918: v4i32 = X86ISD::INSERTPS 0x7ff2bb802708, 0x7ff2bb802708, 0x7ff2bb802810 [ORD=6] [ID=6] | |
| ISEL: Starting pattern match on root node: 0x7ff2bb802918: v4i32 = X86ISD::INSERTPS 0x7ff2bb802708, 0x7ff2bb802708, 0x7ff2bb802810 [ORD=6] [ID=6] | |
| Initial Opcode index to 156408 | |
| Match failed at index 156414 | |
| Continuing at 156938 | |
| Skipped scope entry (due to false predicate) at index 156949, continuing at 156963 | |
| Morphed node: 0x7ff2bb802918: v4f32 = INSERTPSrr 0x7ff2bb802708, 0x7ff2bb802708, 0x7ff2bb805010 [ORD=6] | |
| ISEL: Match complete! | |
| => 0x7ff2bb802918: v4f32 = INSERTPSrr 0x7ff2bb802708, 0x7ff2bb802708, 0x7ff2bb805010 [ORD=6] | |
| Selecting: 0x7ff2bb802708: v4i32,ch = CopyFromReg 0x7ff2bac071c0, 0x7ff2bb802600 [ORD=1] [ID=5] | |
| => 0x7ff2bb802708: v4i32,ch = CopyFromReg 0x7ff2bac071c0, 0x7ff2bb802600 [ORD=1] | |
| Selecting: 0x7ff2bb805118: v4i32 = Register %XMM0 [ID=3] | |
| => 0x7ff2bb805118: v4i32 = Register %XMM0 | |
| Selecting: 0x7ff2bb802600: v4i32 = Register %vreg0 [ID=1] | |
| => 0x7ff2bb802600: v4i32 = Register %vreg0 | |
| Selecting: 0x7ff2bac071c0: ch = EntryToken [ID=0] | |
| => 0x7ff2bac071c0: ch = EntryToken | |
| ===== Instruction selection ends: | |
| Selected selection DAG: BB#0 'move_1_to_2:entry' | |
| SelectionDAG has 8 nodes: | |
| 0x7ff2bac071c0: ch = EntryToken | |
| 0x7ff2bb805118: v4i32 = Register %XMM0 | |
| 0x7ff2bac071c0: <multiple use> | |
| 0x7ff2bb802600: v4i32 = Register %vreg0 | |
| 0x7ff2bb802708: v4i32,ch = CopyFromReg 0x7ff2bac071c0, 0x7ff2bb802600 [ORD=1] | |
| 0x7ff2bac071c0: <multiple use> | |
| 0x7ff2bb805118: <multiple use> | |
| 0x7ff2bb802708: <multiple use> | |
| 0x7ff2bb802708: <multiple use> | |
| 0x7ff2bb805010: i64 = TargetConstant<99> | |
| 0x7ff2bb802918: v4f32 = INSERTPSrr 0x7ff2bb802708, 0x7ff2bb802708, 0x7ff2bb805010 [ORD=6] | |
| 0x7ff2bb805220: ch,glue = CopyToReg 0x7ff2bac071c0, 0x7ff2bb805118, 0x7ff2bb802918 [ORD=7] | |
| 0x7ff2bb805118: <multiple use> | |
| 0x7ff2bb805220: <multiple use> | |
| 0x7ff2bb805220: <multiple use> | |
| 0x7ff2bb805328: ch = RETQ 0x7ff2bb805118, 0x7ff2bb805220, 0x7ff2bb805220:1 [ORD=7] | |
| ********** List Scheduling BB#0 'entry' ********** | |
| SU(0): 0x7ff2bb805328: ch = RETQ 0x7ff2bb805118, 0x7ff2bb805220, 0x7ff2bb805220:1 [ORD=7] [ID=0] | |
| 0x7ff2bb805220: ch,glue = CopyToReg 0x7ff2bac071c0, 0x7ff2bb805118, 0x7ff2bb802918 [ORD=7] [ID=0] | |
| # preds left : 1 | |
| # succs left : 0 | |
| # rdefs left : 0 | |
| Latency : 1 | |
| Depth : 2 | |
| Height : 0 | |
| Predecessors: | |
| val SU(1): Latency=1 | |
| SU(1): 0x7ff2bb802918: v4f32 = INSERTPSrr 0x7ff2bb802708, 0x7ff2bb802708, 0x7ff2bb805010 [ORD=6] [ID=1] | |
| # preds left : 1 | |
| # succs left : 1 | |
| # rdefs left : 1 | |
| Latency : 1 | |
| Depth : 1 | |
| Height : 1 | |
| Predecessors: | |
| val SU(2): Latency=1 | |
| Successors: | |
| val SU(0): Latency=1 | |
| SU(2): 0x7ff2bb802708: v4i32,ch = CopyFromReg 0x7ff2bac071c0, 0x7ff2bb802600 [ORD=1] [ID=2] | |
| # preds left : 0 | |
| # succs left : 1 | |
| # rdefs left : 1 | |
| Latency : 1 | |
| Depth : 0 | |
| Height : 2 | |
| Successors: | |
| val SU(1): Latency=1 | |
| Examining Available: | |
| Height 0: SU(0): 0x7ff2bb805328: ch = RETQ 0x7ff2bb805118, 0x7ff2bb805220, 0x7ff2bb805220:1 [ORD=7] [ID=0] | |
| 0x7ff2bb805220: ch,glue = CopyToReg 0x7ff2bac071c0, 0x7ff2bb805118, 0x7ff2bb802918 [ORD=7] [ID=0] | |
| *** Scheduling [0]: SU(0): 0x7ff2bb805328: ch = RETQ 0x7ff2bb805118, 0x7ff2bb805220, 0x7ff2bb805220:1 [ORD=7] [ID=0] | |
| 0x7ff2bb805220: ch,glue = CopyToReg 0x7ff2bac071c0, 0x7ff2bb805118, 0x7ff2bb802918 [ORD=7] [ID=0] | |
| Examining Available: | |
| Height 1: SU(1): 0x7ff2bb802918: v4f32 = INSERTPSrr 0x7ff2bb802708, 0x7ff2bb802708, 0x7ff2bb805010 [ORD=6] [ID=1] | |
| *** Scheduling [1]: SU(1): 0x7ff2bb802918: v4f32 = INSERTPSrr 0x7ff2bb802708, 0x7ff2bb802708, 0x7ff2bb805010 [ORD=6] [ID=1] | |
| Examining Available: | |
| Height 2: SU(2): 0x7ff2bb802708: v4i32,ch = CopyFromReg 0x7ff2bac071c0, 0x7ff2bb802600 [ORD=1] [ID=2] | |
| *** Scheduling [2]: SU(2): 0x7ff2bb802708: v4i32,ch = CopyFromReg 0x7ff2bac071c0, 0x7ff2bb802600 [ORD=1] [ID=2] | |
| *** Final schedule *** | |
| SU(2): 0x7ff2bb802708: v4i32,ch = CopyFromReg 0x7ff2bac071c0, 0x7ff2bb802600 [ORD=1] [ID=2] | |
| SU(1): 0x7ff2bb802918: v4f32 = INSERTPSrr 0x7ff2bb802708, 0x7ff2bb802708, 0x7ff2bb805010 [ORD=6] [ID=1] | |
| SU(0): 0x7ff2bb805328: ch = RETQ 0x7ff2bb805118, 0x7ff2bb805220, 0x7ff2bb805220:1 [ORD=7] [ID=0] | |
| 0x7ff2bb805220: ch,glue = CopyToReg 0x7ff2bac071c0, 0x7ff2bb805118, 0x7ff2bb802918 [ORD=7] [ID=0] | |
| Total amount of phi nodes to update: 0 | |
| *** MachineFunction at end of ISel *** | |
| # Machine code for function move_1_to_2: SSA | |
| Function Live Ins: %XMM0 in %vreg0 | |
| BB#0: derived from LLVM BB %entry | |
| Live Ins: %XMM0 | |
| %vreg0<def> = COPY %XMM0; VR128:%vreg0 | |
| %vreg2<def,tied1> = INSERTPSrr %vreg0<tied0>, %vreg0, 99; VR128:%vreg2,%vreg0,%vreg0 | |
| %XMM0<def> = COPY %vreg2; VR128:%vreg2 | |
| RETQ %XMM0 | |
| # End machine code for function move_1_to_2. | |
| # Machine code for function move_1_to_2: SSA | |
| Function Live Ins: %XMM0 in %vreg0 | |
| 0B BB#0: derived from LLVM BB %entry | |
| Live Ins: %XMM0 | |
| 16B %vreg0<def> = COPY %XMM0; VR128:%vreg0 | |
| 32B %vreg2<def,tied1> = INSERTPSrr %vreg0<tied0>, %vreg0, 99; VR128:%vreg2,%vreg0,%vreg0 | |
| 48B %XMM0<def> = COPY %vreg2; VR128:%vreg2 | |
| 64B RETQ %XMM0 | |
| # End machine code for function move_1_to_2. | |
| ********** Stack Coloring ********** | |
| ********** Function: move_1_to_2 | |
| ******** Pre-regalloc Machine LICM: move_1_to_2 ******** | |
| Entering: entry | |
| Exiting: entry | |
| ******** Machine Sinking ******** | |
| ********** PEEPHOLE OPTIMIZER ********** | |
| ********** Function: move_1_to_2 | |
| ********** PROCESS IMPLICIT DEFS ********** | |
| ********** Function: move_1_to_2 | |
| ********** REWRITING TWO-ADDR INSTRS ********** | |
| ********** Function: move_1_to_2 | |
| %vreg2<def,tied1> = INSERTPSrr %vreg0<kill,tied0>, %vreg0, 99; VR128:%vreg2,%vreg0,%vreg0 | |
| prepend: %vreg2<def> = COPY %vreg0; VR128:%vreg2,%vreg0 | |
| rewrite to: %vreg2<def,tied1> = INSERTPSrr %vreg2<tied0>, %vreg2, 99; VR128:%vreg2 | |
| # Machine code for function move_1_to_2: Post SSA | |
| Function Live Ins: %XMM0 in %vreg0 | |
| 0B BB#0: derived from LLVM BB %entry | |
| Live Ins: %XMM0 | |
| 16B %vreg0<def> = COPY %XMM0<kill>; VR128:%vreg0 | |
| 32B %vreg2<def> = COPY %vreg0<kill>; VR128:%vreg2,%vreg0 | |
| 48B %vreg2<def,tied1> = INSERTPSrr %vreg2<tied0>, %vreg2, 99; VR128:%vreg2 | |
| 64B %XMM0<def> = COPY %vreg2<kill>; VR128:%vreg2 | |
| 80B RETQ %XMM0<kill> | |
| # End machine code for function move_1_to_2. | |
| Computing live-in reg-units in ABI blocks. | |
| 0B BB#0 XMM0#0 | |
| Created 1 new intervals. | |
| ********** INTERVALS ********** | |
| XMM0 [0B,16r:0)[64r,80r:1) 0@0B-phi 1@64r | |
| %vreg0 [16r,32r:0) 0@16r | |
| %vreg2 [32r,48r:0)[48r,64r:1) 0@32r 1@48r | |
| RegMasks: | |
| ********** MACHINEINSTRS ********** | |
| # Machine code for function move_1_to_2: Post SSA | |
| Function Live Ins: %XMM0 in %vreg0 | |
| 0B BB#0: derived from LLVM BB %entry | |
| Live Ins: %XMM0 | |
| 16B %vreg0<def> = COPY %XMM0; VR128:%vreg0 | |
| 32B %vreg2<def> = COPY %vreg0; VR128:%vreg2,%vreg0 | |
| 48B %vreg2<def,tied1> = INSERTPSrr %vreg2<tied0>, %vreg2, 99; VR128:%vreg2 | |
| 64B %XMM0<def> = COPY %vreg2; VR128:%vreg2 | |
| 80B RETQ %XMM0 | |
| # End machine code for function move_1_to_2. | |
| ********** SIMPLE REGISTER COALESCING ********** | |
| ********** Function: move_1_to_2 | |
| ********** JOINING INTERVALS *********** | |
| entry: | |
| 16B %vreg0<def> = COPY %XMM0; VR128:%vreg0 | |
| Considering merging %vreg0 with %XMM0 | |
| Can only merge into reserved registers. | |
| 64B %XMM0<def> = COPY %vreg2; VR128:%vreg2 | |
| Considering merging %vreg2 with %XMM0 | |
| Can only merge into reserved registers. | |
| 32B %vreg2<def> = COPY %vreg0; VR128:%vreg2,%vreg0 | |
| Considering merging to VR128 with %vreg0 in %vreg2 | |
| RHS = %vreg0 [16r,32r:0) 0@16r | |
| LHS = %vreg2 [32r,48r:0)[48r,64r:1) 0@32r 1@48r | |
| merge %vreg2:0@32r into %vreg0:0@16r --> @16r | |
| erased: 32r %vreg2<def> = COPY %vreg0; VR128:%vreg2,%vreg0 | |
| AllocationOrder(VR128) = [ %XMM0 %XMM1 %XMM2 %XMM3 %XMM4 %XMM5 %XMM6 %XMM7 %XMM8 %XMM9 %XMM10 %XMM11 %XMM12 %XMM13 %XMM14 %XMM15 ] | |
| updated: 16B %vreg2<def> = COPY %XMM0; VR128:%vreg2 | |
| Joined. Result = %vreg2 [16r,48r:0)[48r,64r:1) 0@16r 1@48r | |
| Trying to inflate 0 regs. | |
| ********** INTERVALS ********** | |
| XMM0 [0B,16r:0)[64r,80r:1) 0@0B-phi 1@64r | |
| %vreg2 [16r,48r:0)[48r,64r:1) 0@16r 1@48r | |
| RegMasks: | |
| ********** MACHINEINSTRS ********** | |
| # Machine code for function move_1_to_2: Post SSA | |
| Function Live Ins: %XMM0 in %vreg0 | |
| 0B BB#0: derived from LLVM BB %entry | |
| Live Ins: %XMM0 | |
| 16B %vreg2<def> = COPY %XMM0; VR128:%vreg2 | |
| 48B %vreg2<def,tied1> = INSERTPSrr %vreg2<tied0>, %vreg2, 99; VR128:%vreg2 | |
| 64B %XMM0<def> = COPY %vreg2; VR128:%vreg2 | |
| 80B RETQ %XMM0 | |
| # End machine code for function move_1_to_2. | |
| Before MISsched: | |
| # Machine code for function move_1_to_2: Post SSA | |
| Function Live Ins: %XMM0 in %vreg0 | |
| BB#0: derived from LLVM BB %entry | |
| Live Ins: %XMM0 | |
| %vreg2<def> = COPY %XMM0; VR128:%vreg2 | |
| %vreg2<def,tied1> = INSERTPSrr %vreg2<tied0>, %vreg2, 99; VR128:%vreg2 | |
| %XMM0<def> = COPY %vreg2; VR128:%vreg2 | |
| RETQ %XMM0 | |
| # End machine code for function move_1_to_2. | |
| AllocationOrder(GR32) = [ %EAX %ECX %EDX %ESI %EDI %R8D %R9D %R10D %R11D %EBX %EBP %R14D %R15D %R12D %R13D ] | |
| AllocationOrder(GR16) = [ %AX %CX %DX %SI %DI %R8W %R9W %R10W %R11W %BX %BP %R14W %R15W %R12W %R13W ] | |
| AllocationOrder(GR8) = [ %AL %CL %DL %SIL %DIL %R8B %R9B %R10B %R11B %BL %BPL %R14B %R15B %R12B %R13B ] | |
| ********** MI Scheduling ********** | |
| move_1_to_2:BB#0 entry | |
| From: %vreg2<def> = COPY %XMM0; VR128:%vreg2 | |
| To: RETQ %XMM0 | |
| RegionInstrs: 3 Remaining: 0 | |
| Disabled scoreboard hazard recognizer | |
| Disabled scoreboard hazard recognizer | |
| SU(0): %vreg2<def> = COPY %XMM0; VR128:%vreg2 | |
| # preds left : 0 | |
| # succs left : 3 | |
| # rdefs left : 0 | |
| Latency : 0 | |
| Depth : 0 | |
| Height : 1 | |
| Successors: | |
| val SU(1): Latency=0 Reg=%vreg2 | |
| out SU(1): Latency=0 | |
| antiSU(2): Latency=0 | |
| SU(1): %vreg2<def,tied1> = INSERTPSrr %vreg2<tied0>, %vreg2, 99; VR128:%vreg2 | |
| # preds left : 2 | |
| # succs left : 1 | |
| # rdefs left : 0 | |
| Latency : 1 | |
| Depth : 0 | |
| Height : 1 | |
| Predecessors: | |
| val SU(0): Latency=0 Reg=%vreg2 | |
| out SU(0): Latency=0 | |
| Successors: | |
| val SU(2): Latency=1 Reg=%vreg2 | |
| SU(2): %XMM0<def> = COPY %vreg2; VR128:%vreg2 | |
| # preds left : 2 | |
| # succs left : 1 | |
| # rdefs left : 0 | |
| Latency : 0 | |
| Depth : 1 | |
| Height : 0 | |
| Predecessors: | |
| val SU(1): Latency=1 Reg=%vreg2 | |
| antiSU(0): Latency=0 | |
| Successors: | |
| ch SU(4294967295) *: Latency=0 | |
| Critical Path: 1 | |
| Scheduling SU(2) %XMM0<def> = COPY %vreg2; VR128:%vreg2 | |
| Ready @0c | |
| BotQ.A TopLatency SU(2) 1c | |
| BotQ.A @0c | |
| Retired: 0 | |
| Executed: 0c | |
| Critical: 0c, 0 MOps | |
| ExpectedLatency: 0c | |
| - Latency limited. | |
| Scheduling SU(1) %vreg2<def,tied1> = INSERTPSrr %vreg2<tied0>, %vreg2, 99; VR128:%vreg2 | |
| Ready @1c | |
| BotQ.A BotLatency SU(1) 1c | |
| BotQ.A @0c | |
| Retired: 1 | |
| Executed: 0c | |
| Critical: 0c, 1 MOps | |
| ExpectedLatency: 1c | |
| - Latency limited. | |
| Scheduling SU(0) %vreg2<def> = COPY %XMM0; VR128:%vreg2 | |
| Ready @1c | |
| BotQ.A @0c | |
| Retired: 1 | |
| Executed: 0c | |
| Critical: 0c, 1 MOps | |
| ExpectedLatency: 1c | |
| - Latency limited. | |
| *** Final schedule for BB#0 *** | |
| SU(0): %vreg2<def> = COPY %XMM0; VR128:%vreg2 | |
| SU(1): %vreg2<def,tied1> = INSERTPSrr %vreg2<tied0>, %vreg2, 99; VR128:%vreg2 | |
| SU(2): %XMM0<def> = COPY %vreg2; VR128:%vreg2 | |
| ********** INTERVALS ********** | |
| XMM0 [0B,16r:0)[64r,80r:1) 0@0B-phi 1@64r | |
| %vreg2 [16r,48r:0)[48r,64r:1) 0@16r 1@48r | |
| RegMasks: | |
| ********** MACHINEINSTRS ********** | |
| # Machine code for function move_1_to_2: Post SSA | |
| Function Live Ins: %XMM0 in %vreg0 | |
| 0B BB#0: derived from LLVM BB %entry | |
| Live Ins: %XMM0 | |
| 16B %vreg2<def> = COPY %XMM0; VR128:%vreg2 | |
| 48B %vreg2<def,tied1> = INSERTPSrr %vreg2<tied0>, %vreg2, 99; VR128:%vreg2 | |
| 64B %XMM0<def> = COPY %vreg2; VR128:%vreg2 | |
| 80B RETQ %XMM0 | |
| # End machine code for function move_1_to_2. | |
| block-frequency: move_1_to_2 | |
| ============================ | |
| reverse-post-order-traversal | |
| - 0: BB0[entry] | |
| loop-detection | |
| compute-mass-in-function | |
| - node: BB0[entry] | |
| => mass: ffffffffffffffff | |
| float-to-int: min = 1.0, max = 1.0, factor = 8.0 | |
| - BB0[entry]: float = 1.0, scaled = 8.0, int = 8 | |
| block-frequency-info: move_1_to_2 | |
| - BB0[entry]: float = 1.0, int = 8 | |
| ********** COMPUTING LIVE DEBUG VARIABLES: move_1_to_2 ********** | |
| ********** DEBUG VARIABLES ********** | |
| ********** GREEDY REGISTER ALLOCATION ********** | |
| ********** Function: move_1_to_2 | |
| ********** Compute Spill Weights ********** | |
| ********** Function: move_1_to_2 | |
| ********** INTERVALS ********** | |
| XMM0 [0B,16r:0)[64r,80r:1) 0@0B-phi 1@64r | |
| %vreg2 [16r,48r:0)[48r,64r:1) 0@16r 1@48r | |
| RegMasks: | |
| ********** MACHINEINSTRS ********** | |
| # Machine code for function move_1_to_2: Post SSA | |
| Function Live Ins: %XMM0 in %vreg0 | |
| 0B BB#0: derived from LLVM BB %entry | |
| Live Ins: %XMM0 | |
| 16B %vreg2<def> = COPY %XMM0; VR128:%vreg2 | |
| 48B %vreg2<def,tied1> = INSERTPSrr %vreg2<tied0>, %vreg2, 99; VR128:%vreg2 | |
| 64B %XMM0<def> = COPY %vreg2; VR128:%vreg2 | |
| 80B RETQ %XMM0 | |
| # End machine code for function move_1_to_2. | |
| selectOrSplit VR128:%vreg2 [16r,48r:0)[48r,64r:1) 0@16r 1@48r w=inf | |
| AllocationOrder(VR128) = [ %XMM0 %XMM1 %XMM2 %XMM3 %XMM4 %XMM5 %XMM6 %XMM7 %XMM8 %XMM9 %XMM10 %XMM11 %XMM12 %XMM13 %XMM14 %XMM15 ] | |
| hints: %XMM0 | |
| assigning %vreg2 to %XMM0: XMM0 | |
| ********** REWRITE VIRTUAL REGISTERS ********** | |
| ********** Function: move_1_to_2 | |
| ********** REGISTER MAP ********** | |
| [%vreg2 -> %XMM0] VR128 | |
| 0B BB#0: derived from LLVM BB %entry | |
| Live Ins: %XMM0 | |
| 16B %vreg2<def> = COPY %XMM0; VR128:%vreg2 | |
| 48B %vreg2<def,tied1> = INSERTPSrr %vreg2<kill,tied0>, %vreg2, 99; VR128:%vreg2 | |
| 64B %XMM0<def> = COPY %vreg2<kill>; VR128:%vreg2 | |
| 80B RETQ %XMM0 | |
| > %XMM0<def> = COPY %XMM0 | |
| Deleting identity copy. | |
| > %XMM0<def,tied1> = INSERTPSrr %XMM0<kill,tied0>, %XMM0, 99 | |
| > %XMM0<def> = COPY %XMM0<kill> | |
| Deleting identity copy. | |
| > RETQ %XMM0 | |
| ********** EMITTING LIVE DEBUG VARIABLES ********** | |
| ********** Stack Slot Coloring ********** | |
| ********** Function: move_1_to_2 | |
| ******** Post-regalloc Machine LICM: move_1_to_2 ******** | |
| MCP: CopyPropagateBlock entry | |
| Machine Function | |
| ********** EXPANDING POST-RA PSEUDO INSTRS ********** | |
| ********** Function: move_1_to_2 | |
| block-frequency: move_1_to_2 | |
| ============================ | |
| reverse-post-order-traversal | |
| - 0: BB0[entry] | |
| loop-detection | |
| compute-mass-in-function | |
| - node: BB0[entry] | |
| => mass: ffffffffffffffff | |
| float-to-int: min = 1.0, max = 1.0, factor = 8.0 | |
| - BB0[entry]: float = 1.0, scaled = 8.0, int = 8 | |
| block-frequency-info: move_1_to_2 | |
| - BB0[entry]: float = 1.0, int = 8 | |
| ********** FIX EXECUTION DEPENDENCIES: VR128 ********** | |
| BB#0: entry | |
| XMM0: 0 %XMM0<def,tied1> = INSERTPSrr %XMM0<kill,tied0>, %XMM0, 99 | |
| .globl _move_1_to_2 | |
| .align 4, 0x90 | |
| _move_1_to_2: ## @move_1_to_2 | |
| .cfi_startproc | |
| ## BB#0: ## %entry | |
| insertps $99, %xmm0, %xmm0 ## xmm0 = zero,zero,xmm0[1,3] | |
| retq | |
| .cfi_endproc | |
| ---- Branch Probability Info : dont_move_elems ---- | |
| Computing probabilities for entry | |
| === dont_move_elems | |
| Initial selection DAG: BB#0 'dont_move_elems:entry' | |
| SelectionDAG has 22 nodes: | |
| 0x7ff2bac071c0: ch = EntryToken | |
| 0x7ff2bac071c0: <multiple use> | |
| 0x7ff2bb805010: v4i32 = Register %vreg0 | |
| 0x7ff2bb805328: v4i32,ch = CopyFromReg 0x7ff2bac071c0, 0x7ff2bb805010 [ORD=1] | |
| 0x7ff2bac071c0: <multiple use> | |
| 0x7ff2bb805220: v4i32 = Register %vreg1 | |
| 0x7ff2bb802918: v4i32,ch = CopyFromReg 0x7ff2bac071c0, 0x7ff2bb805220 [ORD=1] | |
| 0x7ff2bb802708: i32 = Constant<2> | |
| 0x7ff2bb805118: i64 = Constant<2> | |
| 0x7ff2bb802810: i32 = Constant<3> | |
| 0x7ff2bb805430: i64 = Constant<3> | |
| 0x7ff2bb802f48: i32 = Constant<1> | |
| 0x7ff2bb803050: v4i32 = Register %XMM0 | |
| 0x7ff2bac071c0: <multiple use> | |
| 0x7ff2bb803050: <multiple use> | |
| 0x7ff2bb802b28: v4i32 = undef | |
| 0x7ff2bb805328: <multiple use> | |
| 0x7ff2bb805118: <multiple use> | |
| 0x7ff2bb802600: i32 = extract_vector_elt 0x7ff2bb805328, 0x7ff2bb805118 [ORD=2] | |
| 0x7ff2bb805118: <multiple use> | |
| 0x7ff2bb802c30: v4i32 = insert_vector_elt 0x7ff2bb802b28, 0x7ff2bb802600, 0x7ff2bb805118 [ORD=4] | |
| 0x7ff2bb802e40: i32 = Constant<0> | |
| 0x7ff2bb805538: i64 = Constant<1> | |
| 0x7ff2bb802a20: v4i32 = insert_vector_elt 0x7ff2bb802c30, 0x7ff2bb802e40, 0x7ff2bb805538 [ORD=5] | |
| 0x7ff2bb805328: <multiple use> | |
| 0x7ff2bb805430: <multiple use> | |
| 0x7ff2bb803470: i32 = extract_vector_elt 0x7ff2bb805328, 0x7ff2bb805430 [ORD=3] | |
| 0x7ff2bb805430: <multiple use> | |
| 0x7ff2bb802d38: v4i32 = insert_vector_elt 0x7ff2bb802a20, 0x7ff2bb803470, 0x7ff2bb805430 [ORD=6] | |
| 0x7ff2bb804f08: ch,glue = CopyToReg 0x7ff2bac071c0, 0x7ff2bb803050, 0x7ff2bb802d38 [ORD=7] | |
| 0x7ff2bb804f08: <multiple use> | |
| 0x7ff2bb803158: i16 = TargetConstant<0> | |
| 0x7ff2bb803050: <multiple use> | |
| 0x7ff2bb804f08: <multiple use> | |
| 0x7ff2bb804e00: ch = X86ISD::RET_FLAG 0x7ff2bb804f08, 0x7ff2bb803158, 0x7ff2bb803050, 0x7ff2bb804f08:1 [ORD=7] | |
| Replacing.3 0x7ff2bb802c30: v4i32 = insert_vector_elt 0x7ff2bb802b28, 0x7ff2bb802600, 0x7ff2bb805118 [ORD=4] | |
| With: 0x7ff2bb803260: v4i32 = BUILD_VECTOR 0x7ff2bb802f48, 0x7ff2bb802f48, 0x7ff2bb802600, 0x7ff2bb802f48 [ORD=4] | |
| Replacing.3 0x7ff2bb802a20: v4i32 = insert_vector_elt 0x7ff2bb803260, 0x7ff2bb802e40, 0x7ff2bb805538 [ORD=5] | |
| With: 0x7ff2bb802b28: v4i32 = BUILD_VECTOR 0x7ff2bb802f48, 0x7ff2bb802e40, 0x7ff2bb802600, 0x7ff2bb802f48 [ORD=5] | |
| Replacing.3 0x7ff2bb802d38: v4i32 = insert_vector_elt 0x7ff2bb802b28, 0x7ff2bb803470, 0x7ff2bb805430 [ORD=6] | |
| With: 0x7ff2bb803260: v4i32 = BUILD_VECTOR 0x7ff2bb802f48, 0x7ff2bb802e40, 0x7ff2bb802600, 0x7ff2bb803470 [ORD=6] | |
| Optimized lowered selection DAG: BB#0 'dont_move_elems:entry' | |
| SelectionDAG has 14 nodes: | |
| 0x7ff2bac071c0: ch = EntryToken | |
| 0x7ff2bac071c0: <multiple use> | |
| 0x7ff2bb805010: v4i32 = Register %vreg0 | |
| 0x7ff2bb805328: v4i32,ch = CopyFromReg 0x7ff2bac071c0, 0x7ff2bb805010 [ORD=1] | |
| 0x7ff2bb803050: v4i32 = Register %XMM0 | |
| 0x7ff2bac071c0: <multiple use> | |
| 0x7ff2bb803050: <multiple use> | |
| 0x7ff2bb802f48: i32 = undef | |
| 0x7ff2bb802e40: i32 = Constant<0> | |
| 0x7ff2bb805328: <multiple use> | |
| 0x7ff2bb805118: i64 = Constant<2> | |
| 0x7ff2bb802600: i32 = extract_vector_elt 0x7ff2bb805328, 0x7ff2bb805118 [ORD=2] | |
| 0x7ff2bb805328: <multiple use> | |
| 0x7ff2bb805430: i64 = Constant<3> | |
| 0x7ff2bb803470: i32 = extract_vector_elt 0x7ff2bb805328, 0x7ff2bb805430 [ORD=3] | |
| 0x7ff2bb803260: v4i32 = BUILD_VECTOR 0x7ff2bb802f48, 0x7ff2bb802e40, 0x7ff2bb802600, 0x7ff2bb803470 [ORD=6] | |
| 0x7ff2bb804f08: ch,glue = CopyToReg 0x7ff2bac071c0, 0x7ff2bb803050, 0x7ff2bb803260 [ORD=7] | |
| 0x7ff2bb804f08: <multiple use> | |
| 0x7ff2bb803158: i16 = TargetConstant<0> | |
| 0x7ff2bb803050: <multiple use> | |
| 0x7ff2bb804f08: <multiple use> | |
| 0x7ff2bb804e00: ch = X86ISD::RET_FLAG 0x7ff2bb804f08, 0x7ff2bb803158, 0x7ff2bb803050, 0x7ff2bb804f08:1 [ORD=7] | |
| Legally typed node: 0x7ff2bb802f48: i32 = undef [ID=0] | |
| Legally typed node: 0x7ff2bb803050: v4i32 = Register %XMM0 [ID=0] | |
| Legally typed node: 0x7ff2bb803158: i16 = TargetConstant<0> [ID=0] | |
| Legally typed node: 0x7ff2bb802e40: i32 = Constant<0> [ID=0] | |
| Legally typed node: 0x7ff2bb805430: i64 = Constant<3> [ID=0] | |
| Legally typed node: 0x7ff2bb805118: i64 = Constant<2> [ID=0] | |
| Legally typed node: 0x7ff2bb805010: v4i32 = Register %vreg0 [ID=0] | |
| Legally typed node: 0x7ff2bac071c0: ch = EntryToken [ID=0] | |
| Legally typed node: 0x7ff2bb805328: v4i32,ch = CopyFromReg 0x7ff2bac071c0, 0x7ff2bb805010 [ORD=1] [ID=0] | |
| Legally typed node: 0x7ff2bb802600: i32 = extract_vector_elt 0x7ff2bb805328, 0x7ff2bb805118 [ORD=2] [ID=0] | |
| Legally typed node: 0x7ff2bb803470: i32 = extract_vector_elt 0x7ff2bb805328, 0x7ff2bb805430 [ORD=3] [ID=0] | |
| Legally typed node: 0x7ff2bb803260: v4i32 = BUILD_VECTOR 0x7ff2bb802f48, 0x7ff2bb802e40, 0x7ff2bb802600, 0x7ff2bb803470 [ORD=6] [ID=0] | |
| Legally typed node: 0x7ff2bb804f08: ch,glue = CopyToReg 0x7ff2bac071c0, 0x7ff2bb803050, 0x7ff2bb803260 [ORD=7] [ID=0] | |
| Legally typed node: 0x7ff2bb804e00: ch = X86ISD::RET_FLAG 0x7ff2bb804f08, 0x7ff2bb803158, 0x7ff2bb803050, 0x7ff2bb804f08:1 [ORD=7] [ID=0] | |
| Legally typed node: 0x7fff5974ee40: ch = handlenode 0x7ff2bb804e00 [ID=0] | |
| Type-legalized selection DAG: BB#0 'dont_move_elems:entry' | |
| SelectionDAG has 14 nodes: | |
| 0x7ff2bac071c0: ch = EntryToken [ID=-3] | |
| 0x7ff2bac071c0: <multiple use> | |
| 0x7ff2bb805010: v4i32 = Register %vreg0 [ID=-3] | |
| 0x7ff2bb805328: v4i32,ch = CopyFromReg 0x7ff2bac071c0, 0x7ff2bb805010 [ORD=1] [ID=-3] | |
| 0x7ff2bb803050: v4i32 = Register %XMM0 [ID=-3] | |
| 0x7ff2bac071c0: <multiple use> | |
| 0x7ff2bb803050: <multiple use> | |
| 0x7ff2bb802f48: i32 = undef [ID=-3] | |
| 0x7ff2bb802e40: i32 = Constant<0> [ID=-3] | |
| 0x7ff2bb805328: <multiple use> | |
| 0x7ff2bb805118: i64 = Constant<2> [ID=-3] | |
| 0x7ff2bb802600: i32 = extract_vector_elt 0x7ff2bb805328, 0x7ff2bb805118 [ORD=2] [ID=-3] | |
| 0x7ff2bb805328: <multiple use> | |
| 0x7ff2bb805430: i64 = Constant<3> [ID=-3] | |
| 0x7ff2bb803470: i32 = extract_vector_elt 0x7ff2bb805328, 0x7ff2bb805430 [ORD=3] [ID=-3] | |
| 0x7ff2bb803260: v4i32 = BUILD_VECTOR 0x7ff2bb802f48, 0x7ff2bb802e40, 0x7ff2bb802600, 0x7ff2bb803470 [ORD=6] [ID=-3] | |
| 0x7ff2bb804f08: ch,glue = CopyToReg 0x7ff2bac071c0, 0x7ff2bb803050, 0x7ff2bb803260 [ORD=7] [ID=-3] | |
| 0x7ff2bb804f08: <multiple use> | |
| 0x7ff2bb803158: i16 = TargetConstant<0> [ID=-3] | |
| 0x7ff2bb803050: <multiple use> | |
| 0x7ff2bb804f08: <multiple use> | |
| 0x7ff2bb804e00: ch = X86ISD::RET_FLAG 0x7ff2bb804f08, 0x7ff2bb803158, 0x7ff2bb803050, 0x7ff2bb804f08:1 [ORD=7] [ID=-3] | |
| Legalized selection DAG: BB#0 'dont_move_elems:entry' | |
| SelectionDAG has 9 nodes: | |
| 0x7ff2bac071c0: ch = EntryToken [ID=0] | |
| 0x7ff2bb803050: v4i32 = Register %XMM0 [ID=6] | |
| 0x7ff2bac071c0: <multiple use> | |
| 0x7ff2bb805010: v4i32 = Register %vreg0 [ID=1] | |
| 0x7ff2bb805328: v4i32,ch = CopyFromReg 0x7ff2bac071c0, 0x7ff2bb805010 [ORD=1] [ID=8] | |
| 0x7ff2bac071c0: <multiple use> | |
| 0x7ff2bb803050: <multiple use> | |
| 0x7ff2bb805328: <multiple use> | |
| 0x7ff2bb805328: <multiple use> | |
| 0x7ff2bb805220: i64 = Constant<163> | |
| 0x7ff2bb802918: v4i32 = X86ISD::INSERTPS 0x7ff2bb805328, 0x7ff2bb805328, 0x7ff2bb805220 [ORD=6] | |
| 0x7ff2bb804f08: ch,glue = CopyToReg 0x7ff2bac071c0, 0x7ff2bb803050, 0x7ff2bb802918 [ORD=7] [ID=12] | |
| 0x7ff2bb804f08: <multiple use> | |
| 0x7ff2bb803158: i16 = TargetConstant<0> [ID=5] | |
| 0x7ff2bb803050: <multiple use> | |
| 0x7ff2bb804f08: <multiple use> | |
| 0x7ff2bb804e00: ch = X86ISD::RET_FLAG 0x7ff2bb804f08, 0x7ff2bb803158, 0x7ff2bb803050, 0x7ff2bb804f08:1 [ORD=7] [ID=13] | |
| Optimized legalized selection DAG: BB#0 'dont_move_elems:entry' | |
| SelectionDAG has 9 nodes: | |
| 0x7ff2bac071c0: ch = EntryToken [ID=0] | |
| 0x7ff2bb803050: v4i32 = Register %XMM0 [ID=6] | |
| 0x7ff2bac071c0: <multiple use> | |
| 0x7ff2bb805010: v4i32 = Register %vreg0 [ID=1] | |
| 0x7ff2bb805328: v4i32,ch = CopyFromReg 0x7ff2bac071c0, 0x7ff2bb805010 [ORD=1] [ID=8] | |
| 0x7ff2bac071c0: <multiple use> | |
| 0x7ff2bb803050: <multiple use> | |
| 0x7ff2bb805328: <multiple use> | |
| 0x7ff2bb805328: <multiple use> | |
| 0x7ff2bb805220: i64 = Constant<163> | |
| 0x7ff2bb802918: v4i32 = X86ISD::INSERTPS 0x7ff2bb805328, 0x7ff2bb805328, 0x7ff2bb805220 [ORD=6] | |
| 0x7ff2bb804f08: ch,glue = CopyToReg 0x7ff2bac071c0, 0x7ff2bb803050, 0x7ff2bb802918 [ORD=7] [ID=12] | |
| 0x7ff2bb804f08: <multiple use> | |
| 0x7ff2bb803158: i16 = TargetConstant<0> [ID=5] | |
| 0x7ff2bb803050: <multiple use> | |
| 0x7ff2bb804f08: <multiple use> | |
| 0x7ff2bb804e00: ch = X86ISD::RET_FLAG 0x7ff2bb804f08, 0x7ff2bb803158, 0x7ff2bb803050, 0x7ff2bb804f08:1 [ORD=7] [ID=13] | |
| ===== Instruction selection begins: BB#0 'entry' | |
| Selecting: 0x7ff2bb804e00: ch = X86ISD::RET_FLAG 0x7ff2bb804f08, 0x7ff2bb803158, 0x7ff2bb803050, 0x7ff2bb804f08:1 [ORD=7] [ID=8] | |
| ISEL: Starting pattern match on root node: 0x7ff2bb804e00: ch = X86ISD::RET_FLAG 0x7ff2bb804f08, 0x7ff2bb803158, 0x7ff2bb803050, 0x7ff2bb804f08:1 [ORD=7] [ID=8] | |
| Initial Opcode index to 96018 | |
| Skipped scope entry (due to false predicate) at index 96026, continuing at 96035 | |
| Morphed node: 0x7ff2bb804e00: ch = RETQ 0x7ff2bb803050, 0x7ff2bb804f08, 0x7ff2bb804f08:1 [ORD=7] | |
| ISEL: Match complete! | |
| => 0x7ff2bb804e00: ch = RETQ 0x7ff2bb803050, 0x7ff2bb804f08, 0x7ff2bb804f08:1 [ORD=7] | |
| Selecting: 0x7ff2bb804f08: ch,glue = CopyToReg 0x7ff2bac071c0, 0x7ff2bb803050, 0x7ff2bb802918 [ORD=7] [ID=7] | |
| => 0x7ff2bb804f08: ch,glue = CopyToReg 0x7ff2bac071c0, 0x7ff2bb803050, 0x7ff2bb802918 [ORD=7] | |
| Selecting: 0x7ff2bb802918: v4i32 = X86ISD::INSERTPS 0x7ff2bb805328, 0x7ff2bb805328, 0x7ff2bb805220 [ORD=6] [ID=6] | |
| ISEL: Starting pattern match on root node: 0x7ff2bb802918: v4i32 = X86ISD::INSERTPS 0x7ff2bb805328, 0x7ff2bb805328, 0x7ff2bb805220 [ORD=6] [ID=6] | |
| Initial Opcode index to 156408 | |
| Match failed at index 156414 | |
| Continuing at 156938 | |
| Skipped scope entry (due to false predicate) at index 156949, continuing at 156963 | |
| Morphed node: 0x7ff2bb802918: v4f32 = INSERTPSrr 0x7ff2bb805328, 0x7ff2bb805328, 0x7ff2bb803158 [ORD=6] | |
| ISEL: Match complete! | |
| => 0x7ff2bb802918: v4f32 = INSERTPSrr 0x7ff2bb805328, 0x7ff2bb805328, 0x7ff2bb803158 [ORD=6] | |
| Selecting: 0x7ff2bb805328: v4i32,ch = CopyFromReg 0x7ff2bac071c0, 0x7ff2bb805010 [ORD=1] [ID=5] | |
| => 0x7ff2bb805328: v4i32,ch = CopyFromReg 0x7ff2bac071c0, 0x7ff2bb805010 [ORD=1] | |
| Selecting: 0x7ff2bb803050: v4i32 = Register %XMM0 [ID=3] | |
| => 0x7ff2bb803050: v4i32 = Register %XMM0 | |
| Selecting: 0x7ff2bb805010: v4i32 = Register %vreg0 [ID=1] | |
| => 0x7ff2bb805010: v4i32 = Register %vreg0 | |
| Selecting: 0x7ff2bac071c0: ch = EntryToken [ID=0] | |
| => 0x7ff2bac071c0: ch = EntryToken | |
| ===== Instruction selection ends: | |
| Selected selection DAG: BB#0 'dont_move_elems:entry' | |
| SelectionDAG has 8 nodes: | |
| 0x7ff2bac071c0: ch = EntryToken | |
| 0x7ff2bb803050: v4i32 = Register %XMM0 | |
| 0x7ff2bac071c0: <multiple use> | |
| 0x7ff2bb805010: v4i32 = Register %vreg0 | |
| 0x7ff2bb805328: v4i32,ch = CopyFromReg 0x7ff2bac071c0, 0x7ff2bb805010 [ORD=1] | |
| 0x7ff2bac071c0: <multiple use> | |
| 0x7ff2bb803050: <multiple use> | |
| 0x7ff2bb805328: <multiple use> | |
| 0x7ff2bb805328: <multiple use> | |
| 0x7ff2bb803158: i64 = TargetConstant<163> | |
| 0x7ff2bb802918: v4f32 = INSERTPSrr 0x7ff2bb805328, 0x7ff2bb805328, 0x7ff2bb803158 [ORD=6] | |
| 0x7ff2bb804f08: ch,glue = CopyToReg 0x7ff2bac071c0, 0x7ff2bb803050, 0x7ff2bb802918 [ORD=7] | |
| 0x7ff2bb803050: <multiple use> | |
| 0x7ff2bb804f08: <multiple use> | |
| 0x7ff2bb804f08: <multiple use> | |
| 0x7ff2bb804e00: ch = RETQ 0x7ff2bb803050, 0x7ff2bb804f08, 0x7ff2bb804f08:1 [ORD=7] | |
| ********** List Scheduling BB#0 'entry' ********** | |
| SU(0): 0x7ff2bb804e00: ch = RETQ 0x7ff2bb803050, 0x7ff2bb804f08, 0x7ff2bb804f08:1 [ORD=7] [ID=0] | |
| 0x7ff2bb804f08: ch,glue = CopyToReg 0x7ff2bac071c0, 0x7ff2bb803050, 0x7ff2bb802918 [ORD=7] [ID=0] | |
| # preds left : 1 | |
| # succs left : 0 | |
| # rdefs left : 0 | |
| Latency : 1 | |
| Depth : 2 | |
| Height : 0 | |
| Predecessors: | |
| val SU(1): Latency=1 | |
| SU(1): 0x7ff2bb802918: v4f32 = INSERTPSrr 0x7ff2bb805328, 0x7ff2bb805328, 0x7ff2bb803158 [ORD=6] [ID=1] | |
| # preds left : 1 | |
| # succs left : 1 | |
| # rdefs left : 1 | |
| Latency : 1 | |
| Depth : 1 | |
| Height : 1 | |
| Predecessors: | |
| val SU(2): Latency=1 | |
| Successors: | |
| val SU(0): Latency=1 | |
| SU(2): 0x7ff2bb805328: v4i32,ch = CopyFromReg 0x7ff2bac071c0, 0x7ff2bb805010 [ORD=1] [ID=2] | |
| # preds left : 0 | |
| # succs left : 1 | |
| # rdefs left : 1 | |
| Latency : 1 | |
| Depth : 0 | |
| Height : 2 | |
| Successors: | |
| val SU(1): Latency=1 | |
| Examining Available: | |
| Height 0: SU(0): 0x7ff2bb804e00: ch = RETQ 0x7ff2bb803050, 0x7ff2bb804f08, 0x7ff2bb804f08:1 [ORD=7] [ID=0] | |
| 0x7ff2bb804f08: ch,glue = CopyToReg 0x7ff2bac071c0, 0x7ff2bb803050, 0x7ff2bb802918 [ORD=7] [ID=0] | |
| *** Scheduling [0]: SU(0): 0x7ff2bb804e00: ch = RETQ 0x7ff2bb803050, 0x7ff2bb804f08, 0x7ff2bb804f08:1 [ORD=7] [ID=0] | |
| 0x7ff2bb804f08: ch,glue = CopyToReg 0x7ff2bac071c0, 0x7ff2bb803050, 0x7ff2bb802918 [ORD=7] [ID=0] | |
| Examining Available: | |
| Height 1: SU(1): 0x7ff2bb802918: v4f32 = INSERTPSrr 0x7ff2bb805328, 0x7ff2bb805328, 0x7ff2bb803158 [ORD=6] [ID=1] | |
| *** Scheduling [1]: SU(1): 0x7ff2bb802918: v4f32 = INSERTPSrr 0x7ff2bb805328, 0x7ff2bb805328, 0x7ff2bb803158 [ORD=6] [ID=1] | |
| Examining Available: | |
| Height 2: SU(2): 0x7ff2bb805328: v4i32,ch = CopyFromReg 0x7ff2bac071c0, 0x7ff2bb805010 [ORD=1] [ID=2] | |
| *** Scheduling [2]: SU(2): 0x7ff2bb805328: v4i32,ch = CopyFromReg 0x7ff2bac071c0, 0x7ff2bb805010 [ORD=1] [ID=2] | |
| *** Final schedule *** | |
| SU(2): 0x7ff2bb805328: v4i32,ch = CopyFromReg 0x7ff2bac071c0, 0x7ff2bb805010 [ORD=1] [ID=2] | |
| SU(1): 0x7ff2bb802918: v4f32 = INSERTPSrr 0x7ff2bb805328, 0x7ff2bb805328, 0x7ff2bb803158 [ORD=6] [ID=1] | |
| SU(0): 0x7ff2bb804e00: ch = RETQ 0x7ff2bb803050, 0x7ff2bb804f08, 0x7ff2bb804f08:1 [ORD=7] [ID=0] | |
| 0x7ff2bb804f08: ch,glue = CopyToReg 0x7ff2bac071c0, 0x7ff2bb803050, 0x7ff2bb802918 [ORD=7] [ID=0] | |
| Total amount of phi nodes to update: 0 | |
| *** MachineFunction at end of ISel *** | |
| # Machine code for function dont_move_elems: SSA | |
| Function Live Ins: %XMM0 in %vreg0 | |
| BB#0: derived from LLVM BB %entry | |
| Live Ins: %XMM0 | |
| %vreg0<def> = COPY %XMM0; VR128:%vreg0 | |
| %vreg2<def,tied1> = INSERTPSrr %vreg0<tied0>, %vreg0, 163; VR128:%vreg2,%vreg0,%vreg0 | |
| %XMM0<def> = COPY %vreg2; VR128:%vreg2 | |
| RETQ %XMM0 | |
| # End machine code for function dont_move_elems. | |
| # Machine code for function dont_move_elems: SSA | |
| Function Live Ins: %XMM0 in %vreg0 | |
| 0B BB#0: derived from LLVM BB %entry | |
| Live Ins: %XMM0 | |
| 16B %vreg0<def> = COPY %XMM0; VR128:%vreg0 | |
| 32B %vreg2<def,tied1> = INSERTPSrr %vreg0<tied0>, %vreg0, 163; VR128:%vreg2,%vreg0,%vreg0 | |
| 48B %XMM0<def> = COPY %vreg2; VR128:%vreg2 | |
| 64B RETQ %XMM0 | |
| # End machine code for function dont_move_elems. | |
| ********** Stack Coloring ********** | |
| ********** Function: dont_move_elems | |
| ******** Pre-regalloc Machine LICM: dont_move_elems ******** | |
| Entering: entry | |
| Exiting: entry | |
| ******** Machine Sinking ******** | |
| ********** PEEPHOLE OPTIMIZER ********** | |
| ********** Function: dont_move_elems | |
| ********** PROCESS IMPLICIT DEFS ********** | |
| ********** Function: dont_move_elems | |
| ********** REWRITING TWO-ADDR INSTRS ********** | |
| ********** Function: dont_move_elems | |
| %vreg2<def,tied1> = INSERTPSrr %vreg0<kill,tied0>, %vreg0, 163; VR128:%vreg2,%vreg0,%vreg0 | |
| prepend: %vreg2<def> = COPY %vreg0; VR128:%vreg2,%vreg0 | |
| rewrite to: %vreg2<def,tied1> = INSERTPSrr %vreg2<tied0>, %vreg2, 163; VR128:%vreg2 | |
| # Machine code for function dont_move_elems: Post SSA | |
| Function Live Ins: %XMM0 in %vreg0 | |
| 0B BB#0: derived from LLVM BB %entry | |
| Live Ins: %XMM0 | |
| 16B %vreg0<def> = COPY %XMM0<kill>; VR128:%vreg0 | |
| 32B %vreg2<def> = COPY %vreg0<kill>; VR128:%vreg2,%vreg0 | |
| 48B %vreg2<def,tied1> = INSERTPSrr %vreg2<tied0>, %vreg2, 163; VR128:%vreg2 | |
| 64B %XMM0<def> = COPY %vreg2<kill>; VR128:%vreg2 | |
| 80B RETQ %XMM0<kill> | |
| # End machine code for function dont_move_elems. | |
| Computing live-in reg-units in ABI blocks. | |
| 0B BB#0 XMM0#0 | |
| Created 1 new intervals. | |
| ********** INTERVALS ********** | |
| XMM0 [0B,16r:0)[64r,80r:1) 0@0B-phi 1@64r | |
| %vreg0 [16r,32r:0) 0@16r | |
| %vreg2 [32r,48r:0)[48r,64r:1) 0@32r 1@48r | |
| RegMasks: | |
| ********** MACHINEINSTRS ********** | |
| # Machine code for function dont_move_elems: Post SSA | |
| Function Live Ins: %XMM0 in %vreg0 | |
| 0B BB#0: derived from LLVM BB %entry | |
| Live Ins: %XMM0 | |
| 16B %vreg0<def> = COPY %XMM0; VR128:%vreg0 | |
| 32B %vreg2<def> = COPY %vreg0; VR128:%vreg2,%vreg0 | |
| 48B %vreg2<def,tied1> = INSERTPSrr %vreg2<tied0>, %vreg2, 163; VR128:%vreg2 | |
| 64B %XMM0<def> = COPY %vreg2; VR128:%vreg2 | |
| 80B RETQ %XMM0 | |
| # End machine code for function dont_move_elems. | |
| ********** SIMPLE REGISTER COALESCING ********** | |
| ********** Function: dont_move_elems | |
| ********** JOINING INTERVALS *********** | |
| entry: | |
| 16B %vreg0<def> = COPY %XMM0; VR128:%vreg0 | |
| Considering merging %vreg0 with %XMM0 | |
| Can only merge into reserved registers. | |
| 64B %XMM0<def> = COPY %vreg2; VR128:%vreg2 | |
| Considering merging %vreg2 with %XMM0 | |
| Can only merge into reserved registers. | |
| 32B %vreg2<def> = COPY %vreg0; VR128:%vreg2,%vreg0 | |
| Considering merging to VR128 with %vreg0 in %vreg2 | |
| RHS = %vreg0 [16r,32r:0) 0@16r | |
| LHS = %vreg2 [32r,48r:0)[48r,64r:1) 0@32r 1@48r | |
| merge %vreg2:0@32r into %vreg0:0@16r --> @16r | |
| erased: 32r %vreg2<def> = COPY %vreg0; VR128:%vreg2,%vreg0 | |
| updated: 16B %vreg2<def> = COPY %XMM0; VR128:%vreg2 | |
| Joined. Result = %vreg2 [16r,48r:0)[48r,64r:1) 0@16r 1@48r | |
| Trying to inflate 0 regs. | |
| ********** INTERVALS ********** | |
| XMM0 [0B,16r:0)[64r,80r:1) 0@0B-phi 1@64r | |
| %vreg2 [16r,48r:0)[48r,64r:1) 0@16r 1@48r | |
| RegMasks: | |
| ********** MACHINEINSTRS ********** | |
| # Machine code for function dont_move_elems: Post SSA | |
| Function Live Ins: %XMM0 in %vreg0 | |
| 0B BB#0: derived from LLVM BB %entry | |
| Live Ins: %XMM0 | |
| 16B %vreg2<def> = COPY %XMM0; VR128:%vreg2 | |
| 48B %vreg2<def,tied1> = INSERTPSrr %vreg2<tied0>, %vreg2, 163; VR128:%vreg2 | |
| 64B %XMM0<def> = COPY %vreg2; VR128:%vreg2 | |
| 80B RETQ %XMM0 | |
| # End machine code for function dont_move_elems. | |
| Before MISsched: | |
| # Machine code for function dont_move_elems: Post SSA | |
| Function Live Ins: %XMM0 in %vreg0 | |
| BB#0: derived from LLVM BB %entry | |
| Live Ins: %XMM0 | |
| %vreg2<def> = COPY %XMM0; VR128:%vreg2 | |
| %vreg2<def,tied1> = INSERTPSrr %vreg2<tied0>, %vreg2, 163; VR128:%vreg2 | |
| %XMM0<def> = COPY %vreg2; VR128:%vreg2 | |
| RETQ %XMM0 | |
| # End machine code for function dont_move_elems. | |
| ********** MI Scheduling ********** | |
| dont_move_elems:BB#0 entry | |
| From: %vreg2<def> = COPY %XMM0; VR128:%vreg2 | |
| To: RETQ %XMM0 | |
| RegionInstrs: 3 Remaining: 0 | |
| Disabled scoreboard hazard recognizer | |
| Disabled scoreboard hazard recognizer | |
| SU(0): %vreg2<def> = COPY %XMM0; VR128:%vreg2 | |
| # preds left : 0 | |
| # succs left : 3 | |
| # rdefs left : 0 | |
| Latency : 0 | |
| Depth : 0 | |
| Height : 1 | |
| Successors: | |
| val SU(1): Latency=0 Reg=%vreg2 | |
| out SU(1): Latency=0 | |
| antiSU(2): Latency=0 | |
| SU(1): %vreg2<def,tied1> = INSERTPSrr %vreg2<tied0>, %vreg2, 163; VR128:%vreg2 | |
| # preds left : 2 | |
| # succs left : 1 | |
| # rdefs left : 0 | |
| Latency : 1 | |
| Depth : 0 | |
| Height : 1 | |
| Predecessors: | |
| val SU(0): Latency=0 Reg=%vreg2 | |
| out SU(0): Latency=0 | |
| Successors: | |
| val SU(2): Latency=1 Reg=%vreg2 | |
| SU(2): %XMM0<def> = COPY %vreg2; VR128:%vreg2 | |
| # preds left : 2 | |
| # succs left : 1 | |
| # rdefs left : 0 | |
| Latency : 0 | |
| Depth : 1 | |
| Height : 0 | |
| Predecessors: | |
| val SU(1): Latency=1 Reg=%vreg2 | |
| antiSU(0): Latency=0 | |
| Successors: | |
| ch SU(4294967295) *: Latency=0 | |
| Critical Path: 1 | |
| Scheduling SU(2) %XMM0<def> = COPY %vreg2; VR128:%vreg2 | |
| Ready @0c | |
| BotQ.A TopLatency SU(2) 1c | |
| BotQ.A @0c | |
| Retired: 0 | |
| Executed: 0c | |
| Critical: 0c, 0 MOps | |
| ExpectedLatency: 0c | |
| - Latency limited. | |
| Scheduling SU(1) %vreg2<def,tied1> = INSERTPSrr %vreg2<tied0>, %vreg2, 163; VR128:%vreg2 | |
| Ready @1c | |
| BotQ.A BotLatency SU(1) 1c | |
| BotQ.A @0c | |
| Retired: 1 | |
| Executed: 0c | |
| Critical: 0c, 1 MOps | |
| ExpectedLatency: 1c | |
| - Latency limited. | |
| Scheduling SU(0) %vreg2<def> = COPY %XMM0; VR128:%vreg2 | |
| Ready @1c | |
| BotQ.A @0c | |
| Retired: 1 | |
| Executed: 0c | |
| Critical: 0c, 1 MOps | |
| ExpectedLatency: 1c | |
| - Latency limited. | |
| *** Final schedule for BB#0 *** | |
| SU(0): %vreg2<def> = COPY %XMM0; VR128:%vreg2 | |
| SU(1): %vreg2<def,tied1> = INSERTPSrr %vreg2<tied0>, %vreg2, 163; VR128:%vreg2 | |
| SU(2): %XMM0<def> = COPY %vreg2; VR128:%vreg2 | |
| ********** INTERVALS ********** | |
| XMM0 [0B,16r:0)[64r,80r:1) 0@0B-phi 1@64r | |
| %vreg2 [16r,48r:0)[48r,64r:1) 0@16r 1@48r | |
| RegMasks: | |
| ********** MACHINEINSTRS ********** | |
| # Machine code for function dont_move_elems: Post SSA | |
| Function Live Ins: %XMM0 in %vreg0 | |
| 0B BB#0: derived from LLVM BB %entry | |
| Live Ins: %XMM0 | |
| 16B %vreg2<def> = COPY %XMM0; VR128:%vreg2 | |
| 48B %vreg2<def,tied1> = INSERTPSrr %vreg2<tied0>, %vreg2, 163; VR128:%vreg2 | |
| 64B %XMM0<def> = COPY %vreg2; VR128:%vreg2 | |
| 80B RETQ %XMM0 | |
| # End machine code for function dont_move_elems. | |
| block-frequency: dont_move_elems | |
| ================================ | |
| reverse-post-order-traversal | |
| - 0: BB0[entry] | |
| loop-detection | |
| compute-mass-in-function | |
| - node: BB0[entry] | |
| => mass: ffffffffffffffff | |
| float-to-int: min = 1.0, max = 1.0, factor = 8.0 | |
| - BB0[entry]: float = 1.0, scaled = 8.0, int = 8 | |
| block-frequency-info: dont_move_elems | |
| - BB0[entry]: float = 1.0, int = 8 | |
| ********** COMPUTING LIVE DEBUG VARIABLES: dont_move_elems ********** | |
| ********** DEBUG VARIABLES ********** | |
| ********** GREEDY REGISTER ALLOCATION ********** | |
| ********** Function: dont_move_elems | |
| ********** Compute Spill Weights ********** | |
| ********** Function: dont_move_elems | |
| ********** INTERVALS ********** | |
| XMM0 [0B,16r:0)[64r,80r:1) 0@0B-phi 1@64r | |
| %vreg2 [16r,48r:0)[48r,64r:1) 0@16r 1@48r | |
| RegMasks: | |
| ********** MACHINEINSTRS ********** | |
| # Machine code for function dont_move_elems: Post SSA | |
| Function Live Ins: %XMM0 in %vreg0 | |
| 0B BB#0: derived from LLVM BB %entry | |
| Live Ins: %XMM0 | |
| 16B %vreg2<def> = COPY %XMM0; VR128:%vreg2 | |
| 48B %vreg2<def,tied1> = INSERTPSrr %vreg2<tied0>, %vreg2, 163; VR128:%vreg2 | |
| 64B %XMM0<def> = COPY %vreg2; VR128:%vreg2 | |
| 80B RETQ %XMM0 | |
| # End machine code for function dont_move_elems. | |
| selectOrSplit VR128:%vreg2 [16r,48r:0)[48r,64r:1) 0@16r 1@48r w=inf | |
| hints: %XMM0 | |
| assigning %vreg2 to %XMM0: XMM0 | |
| ********** REWRITE VIRTUAL REGISTERS ********** | |
| ********** Function: dont_move_elems | |
| ********** REGISTER MAP ********** | |
| [%vreg2 -> %XMM0] VR128 | |
| 0B BB#0: derived from LLVM BB %entry | |
| Live Ins: %XMM0 | |
| 16B %vreg2<def> = COPY %XMM0; VR128:%vreg2 | |
| 48B %vreg2<def,tied1> = INSERTPSrr %vreg2<kill,tied0>, %vreg2, 163; VR128:%vreg2 | |
| 64B %XMM0<def> = COPY %vreg2<kill>; VR128:%vreg2 | |
| 80B RETQ %XMM0 | |
| > %XMM0<def> = COPY %XMM0 | |
| Deleting identity copy. | |
| > %XMM0<def,tied1> = INSERTPSrr %XMM0<kill,tied0>, %XMM0, 163 | |
| > %XMM0<def> = COPY %XMM0<kill> | |
| Deleting identity copy. | |
| > RETQ %XMM0 | |
| ********** EMITTING LIVE DEBUG VARIABLES ********** | |
| ********** Stack Slot Coloring ********** | |
| ********** Function: dont_move_elems | |
| ******** Post-regalloc Machine LICM: dont_move_elems ******** | |
| MCP: CopyPropagateBlock entry | |
| Machine Function | |
| ********** EXPANDING POST-RA PSEUDO INSTRS ********** | |
| ********** Function: dont_move_elems | |
| block-frequency: dont_move_elems | |
| ================================ | |
| reverse-post-order-traversal | |
| - 0: BB0[entry] | |
| loop-detection | |
| compute-mass-in-function | |
| - node: BB0[entry] | |
| => mass: ffffffffffffffff | |
| float-to-int: min = 1.0, max = 1.0, factor = 8.0 | |
| - BB0[entry]: float = 1.0, scaled = 8.0, int = 8 | |
| block-frequency-info: dont_move_elems | |
| - BB0[entry]: float = 1.0, int = 8 | |
| ********** FIX EXECUTION DEPENDENCIES: VR128 ********** | |
| BB#0: entry | |
| XMM0: 0 %XMM0<def,tied1> = INSERTPSrr %XMM0<kill,tied0>, %XMM0, 163 | |
| .globl _dont_move_elems | |
| .align 4, 0x90 | |
| _dont_move_elems: ## @dont_move_elems | |
| .cfi_startproc | |
| ## BB#0: ## %entry | |
| insertps $163, %xmm0, %xmm0 ## xmm0 = zero,zero,xmm0[2,3] | |
| retq | |
| .cfi_endproc | |
| .subsections_via_symbols |
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