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fincs/armstub7.disasm.txt Secret

Created September 24, 2020 21:43
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armstub7.disasm.txt
armstub7.elf: file format elf32-littlearm
Disassembly of section .init:
00000000 <_start>:
0: ee106fb0 mrc 15, 0, r6, cr0, cr0, {5}
4: fa000004 blx 1c <_main>
00000008 <_secure_monitor>:
8: e300c1b1 movw ip, #433 ; 0x1b1
c: ee01cf11 mcr 15, 0, ip, cr1, cr1, {0}
10: e300c1fa movw ip, #506 ; 0x1fa
14: e16ff00c msr SPSR_fsxc, ip
18: e1b0f00e movs pc, lr
0000001c <_main>:
1c: 2000 movs r0, #0
1e: 07b6 lsls r6, r6, #30
20: f04f 4780 mov.w r7, #1073741824 ; 0x40000000
24: ee11 1f30 mrc 15, 0, r1, cr1, cr0, {1}
28: f041 0140 orr.w r1, r1, #64 ; 0x40
2c: ee01 1f30 mcr 15, 0, r1, cr1, cr0, {1}
30: ee11 1f10 mrc 15, 0, r1, cr1, cr0, {0}
34: f441 5180 orr.w r1, r1, #4096 ; 0x1000
38: ee01 1f10 mcr 15, 0, r1, cr1, cr0, {0}
3c: 490f ldr r1, [pc, #60] ; (7c <_main+0x60>)
3e: ee01 1f51 mcr 15, 0, r1, cr1, cr1, {2}
42: 490f ldr r1, [pc, #60] ; (80 <_main+0x64>)
44: ee0e 1f10 mcr 15, 0, r1, cr14, cr0, {0}
48: 2101 movs r1, #1
4a: ee0e 1f33 mcr 15, 0, r1, cr14, cr3, {1}
4e: ee0c 0f30 mcr 15, 0, r0, cr12, cr0, {1}
52: f3bf 8f6f isb sy
56: f7f0 8000 smc #0
5a: ee0c 0f10 mcr 15, 0, r0, cr12, cr0, {0}
5e: ec40 0f4e mcrr 15, 4, r0, r0, cr14
62: f640 4142 movw r1, #3138 ; 0xc42
66: e9df 2324 ldrd r2, r3, [pc, #144] ; f8 <atags> ; 0x90
6a: b136 cbz r6, 7a <_main+0x5e>
6c: 0eb6 lsrs r6, r6, #26
6e: 36cc adds r6, #204 ; 0xcc
70: bf20 wfe
72: 59bb ldr r3, [r7, r6]
74: 2b00 cmp r3, #0
76: d0fb beq.n 70 <_main+0x54>
78: 51bb str r3, [r7, r6]
7a: 4718 bx r3
7c: 00060c00 .word 0x00060c00
80: 0124f800 .word 0x0124f800
...
f0: 5afe570b .word 0x5afe570b
f4: 00000000 .word 0x00000000
000000f8 <atags>:
f8: 00000000 .word 0x00000000
000000fc <kernel>:
fc: 00000000 .word 0x00000000
Raw
armstub8-32-gic.disasm.txt
armstub8-32-gic.elf: file format elf32-littlearm
Disassembly of section .init:
00000000 <_start>:
0: ee106fb0 mrc 15, 0, r6, cr0, cr0, {5}
4: fa000005 blx 20 <_main>
00000008 <_secure_monitor>:
8: ee011f30 mcr 15, 0, r1, cr1, cr0, {1}
c: e300c1b1 movw ip, #433 ; 0x1b1
10: ee01cf11 mcr 15, 0, ip, cr1, cr1, {0}
14: e300c1fa movw ip, #506 ; 0x1fa
18: e16ff00c msr SPSR_fsxc, ip
1c: e1b0f00e movs pc, lr
00000020 <_main>:
20: 2000 movs r0, #0
22: 07b6 lsls r6, r6, #30
24: 4f25 ldr r7, [pc, #148] ; (bc <_main+0x9c>)
26: ec52 1f1f mrrc 15, 1, r1, r2, cr15
2a: f041 0140 orr.w r1, r1, #64 ; 0x40
2e: f022 0203 bic.w r2, r2, #3
32: ec42 1f1f mcrr 15, 1, r1, r2, cr15
36: ee11 1f10 mrc 15, 0, r1, cr1, cr0, {0}
3a: f441 5180 orr.w r1, r1, #4096 ; 0x1000
3e: ee01 1f10 mcr 15, 0, r1, cr1, cr0, {0}
42: f507 2582 add.w r5, r7, #266240 ; 0x41000
46: b90e cbnz r6, 4c <_main+0x2c>
48: 2103 movs r1, #3
4a: 6029 str r1, [r5, #0]
4c: f04f 31ff mov.w r1, #4294967295
50: 2208 movs r2, #8
52: f105 0580 add.w r5, r5, #128 ; 0x80
56: f845 1b04 str.w r1, [r5], #4
5a: 3a01 subs r2, #1
5c: d1fb bne.n 56 <_main+0x36>
5e: f507 2584 add.w r5, r7, #270336 ; 0x42000
62: f240 11e7 movw r1, #487 ; 0x1e7
66: 6029 str r1, [r5, #0]
68: 21ff movs r1, #255 ; 0xff
6a: 6069 str r1, [r5, #4]
6c: f44f 6140 mov.w r1, #3072 ; 0xc00
70: ee01 1f51 mcr 15, 0, r1, cr1, cr1, {2}
74: 4912 ldr r1, [pc, #72] ; (c0 <_main+0xa0>)
76: ee0e 1f10 mcr 15, 0, r1, cr14, cr0, {0}
7a: f04f 4100 mov.w r1, #2147483648 ; 0x80000000
7e: 60b9 str r1, [r7, #8]
80: 2101 movs r1, #1
82: ee0e 1f33 mcr 15, 0, r1, cr14, cr3, {1}
86: ee0c 0f30 mcr 15, 0, r0, cr12, cr0, {1}
8a: f3bf 8f6f isb sy
8e: 2173 movs r1, #115 ; 0x73
90: f7f0 8000 smc #0
94: ee0c 0f10 mcr 15, 0, r0, cr12, cr0, {0}
98: ec40 0f4e mcrr 15, 4, r0, r0, cr14
9c: 2122 movs r1, #34 ; 0x22
9e: ee29 1f50 mcr 15, 1, r1, cr9, cr0, {2}
a2: f640 4142 movw r1, #3138 ; 0xc42
a6: e9df 2314 ldrd r2, r3, [pc, #80] ; f8 <atags> ; 0x50
aa: b136 cbz r6, ba <_main+0x9a>
ac: 0eb6 lsrs r6, r6, #26
ae: 36cc adds r6, #204 ; 0xcc
b0: bf20 wfe
b2: 59bb ldr r3, [r7, r6]
b4: 2b00 cmp r3, #0
b6: d0fb beq.n b0 <_main+0x90>
b8: 51bb str r3, [r7, r6]
ba: 4718 bx r3
bc: ff800000 .word 0xff800000
c0: 0337f980 .word 0x0337f980
...
f0: 5afe570b .word 0x5afe570b
f4: 00000000 .word 0x00000000
000000f8 <atags>:
f8: 00000000 .word 0x00000000
000000fc <kernel>:
fc: 00000000 .word 0x00000000
Raw
armstub8-32.disasm.txt
armstub8-32.elf: file format elf32-littlearm
Disassembly of section .init:
00000000 <_start>:
0: ee106fb0 mrc 15, 0, r6, cr0, cr0, {5}
4: fa000005 blx 20 <_main>
00000008 <_secure_monitor>:
8: ee011f30 mcr 15, 0, r1, cr1, cr0, {1}
c: e300c1b1 movw ip, #433 ; 0x1b1
10: ee01cf11 mcr 15, 0, ip, cr1, cr1, {0}
14: e300c1fa movw ip, #506 ; 0x1fa
18: e16ff00c msr SPSR_fsxc, ip
1c: e1b0f00e movs pc, lr
00000020 <_main>:
20: 2000 movs r0, #0
22: 07b6 lsls r6, r6, #30
24: f04f 4780 mov.w r7, #1073741824 ; 0x40000000
28: ec52 1f1f mrrc 15, 1, r1, r2, cr15
2c: f041 0140 orr.w r1, r1, #64 ; 0x40
30: ec42 1f1f mcrr 15, 1, r1, r2, cr15
34: ee11 1f10 mrc 15, 0, r1, cr1, cr0, {0}
38: f441 5180 orr.w r1, r1, #4096 ; 0x1000
3c: ee01 1f10 mcr 15, 0, r1, cr1, cr0, {0}
40: f44f 6140 mov.w r1, #3072 ; 0xc00
44: ee01 1f51 mcr 15, 0, r1, cr1, cr1, {2}
48: 490e ldr r1, [pc, #56] ; (84 <_main+0x64>)
4a: ee0e 1f10 mcr 15, 0, r1, cr14, cr0, {0}
4e: 2101 movs r1, #1
50: ee0e 1f33 mcr 15, 0, r1, cr14, cr3, {1}
54: ee0c 0f30 mcr 15, 0, r0, cr12, cr0, {1}
58: f3bf 8f6f isb sy
5c: 2173 movs r1, #115 ; 0x73
5e: f7f0 8000 smc #0
62: ee0c 0f10 mcr 15, 0, r0, cr12, cr0, {0}
66: ec40 0f4e mcrr 15, 4, r0, r0, cr14
6a: f640 4142 movw r1, #3138 ; 0xc42
6e: e9df 2322 ldrd r2, r3, [pc, #136] ; f8 <atags> ; 0x88
72: b136 cbz r6, 82 <_main+0x62>
74: 0eb6 lsrs r6, r6, #26
76: 36cc adds r6, #204 ; 0xcc
78: bf20 wfe
7a: 59bb ldr r3, [r7, r6]
7c: 2b00 cmp r3, #0
7e: d0fb beq.n 78 <_main+0x58>
80: 51bb str r3, [r7, r6]
82: 4718 bx r3
84: 0124f800 .word 0x0124f800
...
f0: 5afe570b .word 0x5afe570b
f4: 00000000 .word 0x00000000
000000f8 <atags>:
f8: 00000000 .word 0x00000000
000000fc <kernel>:
fc: 00000000 .word 0x00000000
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