Operation Bit pattern A1 A2 A3
btst dn,dm %0000'nnn1'0000'0mmm BTSR1
btst dn,am %0000'nnn1'0000'1mmm MPIW1
btst dn,(am) %0000'nnn1'0001'0mmm ADRW1 BTSM1
btst dn,(am)+ %0000'nnn1'0001'1mmm PINW1 BTSM1
btst dn,-(am) %0000'nnn1'0010'0mmm PDCW1 BTSM1
btst dn,d16(am) %0000'nnn1'0010'1mmm ADSW1 BTSM1
btst dn,d8(am,Xl) %0000'nnn1'0011'0mmm AIXW0 BTSM1
btst dn,(w16).w %0000'nnn1'0011'1000 ABWW1 BTSM1
btst dn,(w32).l %0000'nnn1'0011'1001 ABLW1 BTSM1
btst dn,d16(pc) %0000'nnn1'0011'1010 ADSW1 BTSM1
btst dn,d8(pc,Xl) %0000'nnn1'0011'1011 AIXW1 BTSM1
btst dn,#w16 %0000'nnn1'0011'1100 E#W1 BTSI1
Here, dn corresponds to bitfield RX and the register used by (when applicable) is bitfield RY (see Fig. 6).
Routine Label FC NMA TYPE CBC ORIGIN ROW DESTINATIONS
MMRW3 i a1
E#W1 E#W1 i a2
BTSM1 BTSM1 i MMRW3 dbi
BTSR1 BTSR1 i BTSR2 dbi EXGE1
BTSI1 i BTSR2 dbi
BTSR2 i bc d4 BCSR4 BTSTR3
BTSR3 n a1 BCBC1
BCSR4 n a1 BCBC1
-------------------------------------------
| <> | trix | total read immediate or instruction
| au -> db -> aob,au,pc |----------|
| (dbin) -> ab -> rydl,ath | a2 | starting address A2
| edb -> dbin,irc |----------|
| +2 -> au | x | don't care
| |----------|
| | ukdt | unknown, data temporary register
|-----------------------------------------|
| 270 | e#w1 | e#w1 |
-------------------------------------------
-------------------------------------------
| < | irix | initiate read immediate or instruction
| au -> db -> aob,au,pc |----------|
| (dbin) -> abe -> alu | dbi | direct branch, (IRC) -> IR
| (dcr) -> dbe -> alu |----------|
| +2 -> au | 1i | AND, set Z flag, keep all other condition codes
| |----------|
| | dxuk | don't care, unknown
|-----------------------------------------|
| 32f | btsm1 | btsm1 |
-------------------------------------------
|
+-> mmrw3
-------------------------------------------
| < | irix | initiate read immediate or instruction
| au -> aob,pc |----------|
| (rx) -> ab -> at,dcr | dbi | direct branch, (IRC) -> IR
| (ry) -> db -> au |----------|
| 0 -> au | x | don't care
| |----------|
| | ukry | unknown, RY field in macroinstruction
|-----------------------------------------|
| 127 | btsr1 | exge1 |
-------------------------------------------
|
+-> btsr2
-------------------------------------------
| < | irix | initiate read immediate or instruction
| (ath) -> db -> ryh |----------|
| au -> aob,pc | dbi | direct branch, (IRC) -> IR
| (rx) -> ab -> dcr |----------|
| | x | don't care
| |----------|
| | rxdt | RX field of macroinstruction, data temporary register
|-----------------------------------------|
| 34b | btsi1 | btsi1 |
-------------------------------------------
|
+-> btsr2
-------------------------------------------
| > | frix | finish read immediate or instruction
| edb -> dbin,irc |----------|
| (pc) -> db -> au | bc | conditional branch
| (ryl) -> abe -> alu,alub |----------|
| -1 -> alu | 1n | AND, keep condition codes
| +2 -> au |----------|
| | |
|-----------------------------------------|
| 174 | btsr2 | btsr2 |
-------------------------------------------
|
+-> btsr3 if dcr[4]=1
+-> bcsr4 if dcr[4]=0
-------------------------------------------
| | np | no access, process only
| (dcr) -> dbe -> alu |----------|
| (ir) -> ird | a1 | starting address A1
| (ryh) -> ab -> alu |----------|
| | 1i | AND, modify Z flag, keep all other condition codes
| |----------|
| | |
|-----------------------------------------|
| 6a | btsr3 | btsr3 |
-------------------------------------------
-------------------------------------------
| | np | no access, process only
| alu -> ab -> ryl |----------|
| (alub) -> alu | a1 | starting address A1
| (dcr) -> db* -> alu |----------|
| (ir) -> ird | 1i | AND, set Z flag, keep all other condition codes
| |----------|
| | |
|-----------------------------------------|
| ea | bcsr4 | bcsr4 |
-------------------------------------------
-------------------------------------------
| > | frix | finish read immediate or instruction
| edb -> dbin,irc |----------|
| (ir) -> ird | a1 | starting address A1
| |----------|
| | x | don't care
| |----------|
| | |
|-----------------------------------------|
| 26 | mmrw3 | mmrw3 |
-------------------------------------------
-------------------------------------------
| | acc lbl |
| |----------|
| content | next mwa |
| |----------|
| | alu fun |
| |----------|
| | reg ptrs |
|-----------------------------------------|
| address | label | origin |
-------------------------------------------
data bus input buffer -> address bus -> low word of data register RY, high word of temporary address register
external data bus -> data bus input buffer, irc
au computes pc+2
Full read of immediate or instruction @ pc
branch to a2
high word of temporary address register -> data bus -> high word of data register RY
au result -> address output buffer, pc
register RX -> address bus -> bit manipulation decoder
Initiate read of immediate or instruction @ pc
branch to btsr2
external data bus -> data bus input buffer, irc
au computes pc+2
low word of register RY -> sign extend onto high section of address bus -> alu, alub
alu computes bitwise AND of -1 and low word of data register RY without setting flags
Finish read of immediate or instruction @ pc
if bit tested >= 16: branch to btsr3 else branch to bcsr4
bit manipulation decoder result -> sign extend onto high section of data bus -> alu
ir -> ird
high word of data register RY -> address bus -> alu
alu computes bitwise AND of bit manipulation decoder result and high word of data register RY
alu result -> address buffer -> low word of data register RY
alub -> alu
bit manipulation decoder result -> data bus (at least data section) -> alu
ir -> ird
alu computes bitwise AND of bit manipulation decoder result and low word of data register RY
E#W1 full buss cycle 4 cycles
BTSR1 init bus cycle 2 cycles
BTSI1 init bus cycle 2 cycles
BTSR2 finish bus cycle 2 cycles
BTSR3 empty bus cycle 2 cycles
BCSR4 empty bus cycle 2 cycles
btst dn,dm => BTSR1 BTSR2 BTSR3
=> BTSR1 BTSR2 BCSR4
---- 2(.5/0) 2(.5/0) 2(0/0) =6(1/0)
btst dn,#im => E#W1 BTSI1 BTSR2 BTSR3
=> E#W1 BTSI1 BTSR2 BCSR4
4(1/0) 2(.5/0) 2(.5/0) 2(0/0) =10(2/0)
btst dn,<ea> => <variable> BTSM1 MMRW3
<variable> 2(.5/0) 2(.5/0) =4(1/0)+<ea>
-------------------------------------------------------------------------------
| Exec Time | Data Bus Usage
BTST | INSTR EA | 1st Operand | 2nd OP (ea) | INSTR
------------------+-----------------+-------------+---------------+------------
Dn,<ea> : | | | |
.B : | | | |
(An) | 4(1/0) 4(1/0) | | nr | np
(An)+ | 4(1/0) 4(1/0) | | nr | np
-(An) | 4(1/0) 6(1/0) | | n nr | np
(d16,An) | 4(1/0) 8(2/0) | | np nr | np
(d8,An,Xn) | 4(1/0) 10(2/0) | | n np nr | np
(xxx).W | 4(1/0) 8(2/0) | | np nr | np
(xxx).L | 4(1/0) 12(3/0) | | np np nr | np
#<data> | 6(1/0) 4(1/0) | | np | np n
Dn,Dm : | | | |
.L : | 6(1/0) 0(0/0) | | | np n