folknology

#include <xs1.h>
#define BLD 1000000
#define TLD 200000000


out port biled = XS1_PORT_1F ;
in port button_0 = XS1_PORT_1K ;
in port button_1 = XS1_PORT_1L ;
enum cmds {STOP,START,ADVANCE,TOGGLE};

folknology

// XC
tl_controller(in port mode ,in port state, chanend cntrl, chanend sup){
  while(1)
    {
      select
	{
	case mode when pinseq (0) :> void :
	  {
	    cntrl <: TOGGLE;
	    break ;

folknology

#include "xs1bc.h"
#include <platform.h>
#define DELAY 50000000

// config and main stuff to run the BehaviouralC below
resource leds = XS1_PORT_4F;
resource stop = XS1_PORT_1L;

void bevec(resource leds,resource stop, resource timer);

folknology

// ------- Preamble -------- //
#include <avr/io.h>	
#include <avr/sleep.h>
#include <avr/interrupt.h>
#include <avr/pgmspace.h>
#include <util/delay.h> 
#include <math.h>

#define DELAY 128

folknology

// @TOP.PORTLIST
		// Top level SDRAM I/O ports
		o_ram_clk, o_ram_cke, o_ram_cs_n, o_ram_ras_n, o_ram_cas_n,
		o_ram_we_n, o_ram_bs, o_ram_addr, o_ram_udqm, o_ram_ldqm,
		io_ram_data
//@TOP.IODECL
	// SDRAM
	output	wire	o_ram_clk, o_ram_cke,
			o_ram_cs_n, o_ram_ras_n, o_ram_cas_n, o_ram_we_n;
	output	wire	[1:0]	o_ram_bs;

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localparam IDLE = 2'b00;
	localparam WBSTART = 2'b01;
	//localparam WBEND = 2'b10;

	reg [1:0] state;

	wire we;
	assign we = (mem_wstrb[0] | mem_wstrb[1] | mem_wstrb[2] | mem_wstrb[3]);

	always @(posedge wb_clk_i) begin

folknology

module master (
 input clk,
 input i_busy,
 output reg o_req
);
 localparam  N = 2;
 reg [N:0] cnt = 0;

 initial o_req = 0;

folknology

OpenSource FPGA Hardware and Tooling Past, Present and Future

Once upon a time we could only use proprietary tools and development boards supplied by FPGA vendors, This all changed in 2016 with the advent of the IceStorm opensource toolchain combined with open Hardware like the myStorm board. With the 2nd generation of tools and hardware sophisticated FPGA features are opening exciting avenues for 'Opensource all the way down', we hope to provide an update and crystal ball on where some of this could be leading to..

OpenSource FPGA Tooling past to present David Shah looks at where we have come from with the IceStorm toochain, and looks at how this has devloped recently and expanded Ice40 Lattice support to include new lower power, lower cost, reduced pincount FPGAs to inlcude their Ultra & Ultra Plus range.

OpenSource FPGA Hardware past to present Alan Wood talks about the journey through the early history of OpenSource FPGA open hardware from IcoBoard through myStorm too recent UltraPlus offer

folknology

###############################################################################
#                                                                             #
# Copyright 2017 myStorm Copyright and related                                #
# rights are licensed under the Solderpad Hardware License, Version 0.51      #
# (the “License”); you may not use this file except in compliance with        #
# the License. You may obtain a copy of the License at                        #
# http://solderpad.org/licenses/SHL-0.51. Unless required by applicable       #
# law or agreed to in writing, software, hardware and materials               #
# distributed under this License is distributed on an “AS IS” BASIS,          #
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or             #

folknology

reg[1:0] stps;
reg[2:0] seq = 0;
reg[3:0] phase;

assign {A,B,C,D} = phase;

always@(posedge clock)
    stps <= {stps[0:0],step};

always@(posedge clock) begin