folknology

target/riscv32imac-unknown-none-elf/release/firmware:     file format elf32-littleriscv


Disassembly of section .text:

00000000 <_start>:
   0:	000000b7          	lui	ra,0x0
   4:	00808067          	jr	8(ra) # 8 <_abs_start>

folknology

#![no_std]
#![no_main]

extern crate panic_halt;
extern crate riscv_rt;

use core::arch::asm;
use riscv_rt::entry;

// simple delay look using inline asm so it doesn't get optimized away

folknology

module top(
  input clk_25mhz,
  output [11:0] tile3
);

 reg [36:0] timer;

 wire [11:0] val = timer[36:25];
 wire [2:0] ca, _y, _dp, g, f, e, d, c, b, a;
 assign tile3[11:0] = {d, _y, c, _dp, b, e, a, f, g, ca};

folknology

import os
import subprocess
import serial
import serial.tools.list_ports as lp

from amaranth.build import *
from amaranth_boards.resources import *
from amaranth.vendor.lattice_ice40 import LatticeICE40Platform

__all__ = ["IceLogicBusPlatform"]

folknology

from amaranth import *
from mystorm.boards.icelogicbus import *


class Blink(Elaboratable):
    def elaborate(self, platform):
        led = platform.request("led")
        # led = platform.request("tx")
        timer = Signal(24)

folknology

from amaranth import *
from amaranth.build import *
from amaranth.hdl.ast import Rose

from mystorm_boards.icelogicbus import *

PMOD = 5

pmod = [
    Resource("pmod6", 0,

folknology

class QspiMem(Elaboratable):
    def __init__(self, addr_bits=32, data_bits=8):
        # parameters
        self.addr_bits = addr_bits  # Must be power of 2
        self.data_bits = data_bits  # currently must be 8
        self.addr_nibbles = 2*addr_bits
        self.data_nibbles =2*databits

        # inputs
        self.copi = Signal(4)

folknology

m amaranth import *
from amaranth.utils import bits_for

from mystorm_boards.icelogicbus import *
from HDL.Amaranth_Examples.Tiles.seven_seg_tile import SevenSegController, tile_resources

TILE = 1

class SpiMem(Elaboratable):
    def __init__(self, addr_bits=32, data_bits=8):

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    #[task(shared=[programmed], local=[qspi_driver])]
    fn dspi(cx: dspi::Context) {
        let driver = cx.local.qspi_driver;
        let mut programmed = cx.shared.programmed;

        programmed.lock(|programmed: &mut bool| {
            if *programmed {
                let count : u8 = 16;
                for _count  in 0..count {
                    let transaction = QspiTransaction {

folknology

class QSPIE2LedTest(Elaboratable):
    def elaborate(self, platform):
        leds12 = Cat([l for l in platform.request("leds12")])
        qspie = Cat([platform.request("qd0"),
                   platform.request("qd1"),
                   platform.request("qd2"),
                   platform.request("qd3"),
                   platform.request("qck"),
                   platform.request("qss"),
                   platform.request("qdr"),