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#[task(shared=[programmed], local=[qspi_driver])] | |
fn dspi(cx: dspi::Context) { | |
let driver = cx.local.qspi_driver; | |
let mut programmed = cx.shared.programmed; | |
programmed.lock(|programmed: &mut bool| { | |
if *programmed { | |
let count : u8 = 16; | |
for _count in 0..count { | |
let transaction = QspiTransaction { | |
iwidth: QspiWidth::NONE, | |
awidth: QspiWidth::NONE, | |
dwidth: QspiWidth::QUAD,//DUAL | |
instruction: 0, | |
address: None, | |
dummy: 0, | |
data_len: Some(1), | |
}; | |
//rprintln!("count:{}",_count as u8); | |
//let mut buf = [_count as u8]; | |
driver.write(&[_count], transaction).unwrap(); | |
//driver.poll_status(); | |
} | |
} | |
}); | |
} | |
// BTW below is the QSPI.write source from stm32f7_hal FYI | |
/// Polling indirect write. | |
pub fn write(&mut self, buf: &[u8], transaction: QspiTransaction) -> Result<(), Error> { | |
// Clear DMA bit since we are not using it | |
self.qspi.cr.modify(|_, w| w.dmaen().clear_bit()); | |
// Setup the transaction registers | |
self.setup_transaction(QspiMode::INDIRECT_WRITE, &transaction); | |
// If the transaction has data, write it word-by-word to the data register | |
if let Some(len) = transaction.data_len { | |
let mut idx: usize = 0; | |
while idx < len { | |
// Check if the FIFO is empty | |
let num_bytes = self.qspi.sr.read().flevel().bits(); | |
if num_bytes == 0 { | |
// Pack the word | |
let mut word: u32 = 0; | |
let num_pack = if (len - idx) >= 4 { 4 } else { len - idx }; | |
for i in 0..num_pack { | |
word |= (buf[idx] as u32) << (i * 8); | |
idx += 1; | |
} | |
// Write a word | |
unsafe { | |
self.qspi.dr.write(|w| w.data().bits(word)); | |
} | |
} | |
} | |
} | |
Ok(()) | |
} |
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