Created
May 29, 2022 10:05
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from amaranth import * | |
from amaranth.build import * | |
from amaranth.hdl.ast import Rose | |
from mystorm_boards.icelogicbus import * | |
PMOD = 5 | |
pmod = [ | |
Resource("pmod6", 0, | |
Subsignal("tps", | |
Pins("1 2 3 4 5 6 7 8 9 10 11 12", dir="o", conn=("pmod", PMOD)), | |
Attrs(IO_STANDARD="SB_LVCMOS") | |
) | |
) | |
] | |
class LogicPmodTest(Elaboratable): | |
def elaborate(self, platform): | |
tps = Cat([l for l in platform.request("pmod6")]) | |
qspi = platform.request("qspi") | |
m = Module() | |
m.d.sync += [ | |
tps[0:4].eq(qspi.data), | |
tps[7].eq(qspi.clk), | |
tps[8].eq(qspi.cs) | |
] | |
return m | |
def synth(): | |
platform = IceLogicBusPlatform() | |
platform.add_resources(pmod) | |
platform.build(LogicPmodTest(), do_program=True) | |
platform.bus_send(bytearray(b'\x03\x00\x00\x00\x00\x00\x00\x00\x01\x42')) | |
if __name__ == "__main__": | |
platform = IceLogicBusPlatform() | |
platform.add_resources(pmod) | |
platform.build(LogicPmodTest(), do_program=True) | |
platform.bus_send(bytearray(b'\x03\x00\x00\x00\x00\x00\x00\x00\x01\x42')) |
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