opensource fpga development

opensource-fpga.md

iverilog - only needed for simulating and analyzing

Prerequisites

sudo apt install iverilog gtkwave  

Here is a good starting point:
http://iverilog.wikia.com/wiki/Getting_Started
http://iverilog.wikia.com/wiki/GTKWAVE

• clone sram project as example:

git clone https://github.com/mattvenn/fpga-sram.git  

• Now compile the project and run it via the vvp runtime:

iverilog -o sram sram_tb.v sram.v
vvp sram

• Start gtkwave to analyze the behavior of all dumped vars:

gtkwave test.vcd &  

Icestorm tools - for synthesizing (some) Lattice ICEx FPGAs

Prerequisites

sudo apt-get install build-essential clang bison flex libreadline-dev \
                     gawk tcl-dev libffi-dev git mercurial graphviz   \
                     xdot pkg-config python python3 libftdi-dev \
                     qt5-default python3-dev libboost-dev \
                     libboost-filesystem-dev libboost-thread-dev \
                     libboost-program-options-dev libboost-python-dev  

Building the tools

• Icestorm (icepack, icebox, iceprog, icetime, chip databases)

git clone https://github.com/cliffordwolf/icestorm.git icestorm  
cd icestorm  
make -j4  
sudo make install  

• nextpnr (place&route tool, Arachne-PNR replacement)

git clone https://github.com/YosysHQ/nextpnr nextpnr  
mkdir build && cd build  
cmake -DARCH=ice40 -DCMAKE_INSTALL_PREFIX=/usr/local ..  
make -j4  
sudo make install  

• yosys (Verilog synthesis)

git clone https://github.com/cliffordwolf/yosys.git yosys  
cd yosys  
make -j$(nproc)  
sudo make install  

Building an example project for the Olimex ice40hx8k-evb board using the previous built tools

• Fetch blinky demo from:
  https://github.com/OLIMEX/iCE40HX8K-EVB/tree/master/demo/ice40hx8k-evb
• Prepare clock constraints for critical lines.
  -- First prepare a python file (e.g. clock_constraints.py) with the following constraints:
  Here an example for a clock constraint of 200MHz, which should fail during the pnr process
  (is just for show casing, that the constraint feature works)

ctx.addClock("clk_24KHz", 200)

• Now build it (with common clk frequency of 24MHz, and a clock constraint of 200MHz on the signal 'clk_24KHz')

yosys -p 'synth_ice40 -json example.json' example.v  
nextpnr-ice40 --hx8k --freq 24 --pre-pack clock_constraints.py --json example.json --pcf ice40hx8k-evb.pcf --asc example.asc 

You should now get an error, that the 200MHz can not be reached.
Now adapt the clock constraint of the clk_24KHz to 24Khz:

ctx.addClock("clk_24KHz", 0.024)

Now it should build just fine. You can now finish the process with:

icepack example.asc example.bin  

The binary file can then be flashed e.g. via 'iceprog'.

Links

http://www.clifford.at/icestorm/
https://tinyfpga.com/bx/guide.html
https://hackaday.com/2017/07/31/tinyfpga-is-a-tiny-fpga-board/
https://hackaday.com/2018/10/08/programming-a-risc-v-softcore-with-ada/