Created
November 25, 2015 01:49
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ls1021a_single.dts
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| /dts-v1/; | |
| // magic: 0xd00dfeed | |
| // totalsize: 0x5641 (22081) | |
| // off_dt_struct: 0x48 | |
| // off_dt_strings: 0x5050 | |
| // off_mem_rsvmap: 0x28 | |
| // version: 17 | |
| // last_comp_version: 16 | |
| // boot_cpuid_phys: 0xf00 | |
| // size_dt_strings: 0x5f1 | |
| // size_dt_struct: 0x5008 | |
| /memreserve/ 0x8ef1c000 0x6000; | |
| / { | |
| #address-cells = <0x00000002>; | |
| #size-cells = <0x00000002>; | |
| compatible = "fsl,ls1021a"; | |
| interrupt-parent = <0x00000001>; | |
| model = "LS1021A TWR Board"; | |
| chosen { | |
| bootargs = "root=/dev/mmcblk0p2 rw rootdelay=5 console=ttyS0,115200"; | |
| }; | |
| aliases { | |
| serial0 = "/soc/serial@2950000"; | |
| serial1 = "/soc/serial@2960000"; | |
| serial2 = "/soc/serial@2970000"; | |
| serial3 = "/soc/serial@2980000"; | |
| serial4 = "/soc/serial@2990000"; | |
| serial5 = "/soc/serial@29a0000"; | |
| gpio0 = "/soc/gpio@2300000"; | |
| gpio1 = "/soc/gpio@2310000"; | |
| gpio2 = "/soc/gpio@2320000"; | |
| gpio3 = "/soc/gpio@2330000"; | |
| ethernet0 = "/soc/ethernet@2d10000"; | |
| ethernet1 = "/soc/ethernet@2d50000"; | |
| ethernet2 = "/soc/ethernet@2d90000"; | |
| sysclk = "/soc/clocking@1ee1000/sysclk"; | |
| enet2_rgmii_phy = "/soc/mdio@2d24000/ethernet-phy@1"; | |
| enet0_sgmii_phy = "/soc/mdio@2d24000/ethernet-phy@2"; | |
| enet1_sgmii_phy = "/soc/mdio@2d24000/ethernet-phy@0"; | |
| }; | |
| memory { | |
| device_type = "memory"; | |
| reg = <0x00000000 0x80000000 0x00000000 0x20000000>; | |
| }; | |
| cpus { | |
| #address-cells = <0x00000001>; | |
| #size-cells = <0x00000000>; | |
| cpu@0 { | |
| clock-frequency = <0x00ca9a3b>; | |
| compatible = "arm,cortex-a7"; | |
| device_type = "cpu"; | |
| reg = <0x00000f00>; | |
| }; | |
| }; | |
| timer { | |
| compatible = "arm,armv7-timer"; | |
| interrupts = <0x00000001 0x0000000d 0x00000308 0x00000001 0x0000000e 0x00000308 0x00000001 0x0000000b 0x00000308 0x00000001 0x0000000a 0x00000308>; | |
| }; | |
| clocks { | |
| clock { | |
| compatible = "fixed-clock"; | |
| #clock-cells = <0x00000000>; | |
| clock-frequency = <0x01770000>; | |
| linux,phandle = <0x00000006>; | |
| phandle = <0x00000006>; | |
| }; | |
| }; | |
| pmu { | |
| compatible = "arm,cortex-a7-pmu"; | |
| interrupts = <0x00000000 0x0000008a 0x00000004 0x00000000 0x0000008b 0x00000004>; | |
| }; | |
| soc { | |
| #address-cells = <0x00000002>; | |
| #size-cells = <0x00000002>; | |
| compatible = "simple-bus"; | |
| interrupt-parent = <0x00000001>; | |
| ranges; | |
| smmu@1200000 { | |
| compatible = "arm,mmu-400"; | |
| reg = <0x00000000 0x01200000 0x00000000 0x00010000>; | |
| #global-interrupts = <0x00000002>; | |
| interrupts = <0x00000000 0x00000045 0x00000004 0x00000000 0x00000046 0x00000004>; | |
| }; | |
| smmu@1280000 { | |
| compatible = "arm,mmu-400"; | |
| reg = <0x00000000 0x01280000 0x00000000 0x00010000>; | |
| #global-interrupts = <0x00000002>; | |
| interrupts = <0x00000000 0x00000047 0x00000004 0x00000000 0x00000048 0x00000004>; | |
| }; | |
| smmu@1300000 { | |
| compatible = "arm,mmu-400"; | |
| reg = <0x00000000 0x01300000 0x00000000 0x00010000>; | |
| #global-interrupts = <0x00000001>; | |
| interrupts = <0x00000000 0x00000049 0x00000004>; | |
| }; | |
| smmu@1380000 { | |
| compatible = "arm,mmu-400"; | |
| reg = <0x00000000 0x01380000 0x00000000 0x00010000>; | |
| #global-interrupts = <0x00000001>; | |
| interrupts = <0x00000000 0x0000004a 0x00000004>; | |
| }; | |
| interrupt-controller@1400000 { | |
| compatible = "arm,cortex-a15-gic"; | |
| #interrupt-cells = <0x00000003>; | |
| interrupt-controller; | |
| reg = <0x00000000 0x01401000 0x00000000 0x00001000 0x00000000 0x01402000 0x00000000 0x00001000 0x00000000 0x01404000 0x00000000 0x00002000 0x00000000 0x01406000 0x00000000 0x00002000>; | |
| interrupts = <0x00000001 0x00000009 0x00000304>; | |
| linux,phandle = <0x00000001>; | |
| phandle = <0x00000001>; | |
| }; | |
| tzasc@1500000 { | |
| reg = <0x00000000 0x01500000 0x00000000 0x00010000>; | |
| interrupts = <0x00000000 0x0000007d 0x00000004>; | |
| status = "disabled"; | |
| }; | |
| dcfg@1ee0000 { | |
| compatible = "fsl,ls1021a-dcfg"; | |
| reg = <0x00000000 0x01ee0000 0x00000000 0x00010000>; | |
| }; | |
| quadspi@1550000 { | |
| #address-cells = <0x00000001>; | |
| #size-cells = <0x00000000>; | |
| compatible = "fsl,vf610-qspi"; | |
| reg = <0x00000000 0x01550000 0x00000000 0x00010000 0x00000000 0x40000000 0x00000000 0x10000000>; | |
| reg-names = "QuadSPI", "QuadSPI-memory"; | |
| interrupts = <0x00000000 0x00000083 0x00000004>; | |
| clock-names = "qspi_en", "qspi"; | |
| clocks = <0x00000002 0x00000001 0x00000002 0x00000001>; | |
| big-endian; | |
| status = "okay"; | |
| num-cs = <0x00000002>; | |
| bus-num = <0x00000000>; | |
| fsl,spi-num-chipselects = <0x00000002>; | |
| fsl,spi-flash-chipselects = <0x00000000>; | |
| s25fl128s@0 { | |
| #address-cells = <0x00000001>; | |
| #size-cells = <0x00000001>; | |
| compatible = "micron,n25q128a13"; | |
| spi-max-frequency = <0x01312d00>; | |
| reg = <0x00000000>; | |
| }; | |
| n25q128a13@1000000 { | |
| #address-cells = <0x00000001>; | |
| #size-cells = <0x00000001>; | |
| compatible = "micron,n25q128a13"; | |
| spi-max-frequency = <0x01312d00>; | |
| reg = <0x00000001>; | |
| }; | |
| }; | |
| esdhc@1560000 { | |
| compatible = "fsl,ls1021a-esdhc", "fsl,esdhc"; | |
| reg = <0x00000000 0x01560000 0x00000000 0x00010000>; | |
| interrupts = <0x00000000 0x0000005e 0x00000004>; | |
| clock-frequency = <0x11e1a300>; | |
| voltage-ranges = <0x00000708 0x00000708 0x00000ce4 0x00000ce4>; | |
| sdhci,auto-cmd12; | |
| big-endian; | |
| bus-width = <0x00000004>; | |
| status = "okay"; | |
| }; | |
| scfg@1570000 { | |
| compatible = "fsl,ls1021a-scfg"; | |
| reg = <0x00000000 0x01570000 0x00000000 0x00010000>; | |
| linux,phandle = <0x00000009>; | |
| phandle = <0x00000009>; | |
| }; | |
| crypto@1700000 { | |
| compatible = "fsl,sec-v5.3", "fsl,sec-v5.0", "fsl,sec-v4.0"; | |
| fsl,sec-era = <0x00000004>; | |
| #address-cells = <0x00000001>; | |
| #size-cells = <0x00000001>; | |
| reg = <0x00000000 0x01700000 0x00000000 0x00100000>; | |
| ranges = <0x00000000 0x00000000 0x01700000 0x00100000>; | |
| interrupts = <0x00000000 0x0000006b 0x00000004>; | |
| jr@10000 { | |
| compatible = "fsl,sec-v5.3-job-ring", "fsl,sec-v5.0-job-ring", "fsl,sec-v4.0-job-ring"; | |
| reg = <0x00010000 0x00010000>; | |
| interrupts = <0x00000000 0x00000067 0x00000004>; | |
| }; | |
| jr@20000 { | |
| compatible = "fsl,sec-v5.3-job-ring", "fsl,sec-v5.0-job-ring", "fsl,sec-v4.0-job-ring"; | |
| reg = <0x00020000 0x00010000>; | |
| interrupts = <0x00000000 0x00000068 0x00000004>; | |
| }; | |
| jr@30000 { | |
| compatible = "fsl,sec-v5.3-job-ring", "fsl,sec-v5.0-job-ring", "fsl,sec-v4.0-job-ring"; | |
| reg = <0x00030000 0x00010000>; | |
| interrupts = <0x00000000 0x00000069 0x00000004>; | |
| }; | |
| jr@40000 { | |
| compatible = "fsl,sec-v5.3-job-ring", "fsl,sec-v5.0-job-ring", "fsl,sec-v4.0-job-ring"; | |
| reg = <0x00040000 0x00010000>; | |
| interrupts = <0x00000000 0x0000006a 0x00000004>; | |
| }; | |
| }; | |
| sfp@1e80000 { | |
| reg = <0x00000000 0x01e80000 0x00000000 0x00010000>; | |
| status = "disabled"; | |
| }; | |
| snvs@1e90000 { | |
| reg = <0x00000000 0x01e90000 0x00000000 0x00010000>; | |
| status = "disabled"; | |
| }; | |
| serdes1@1ea0000 { | |
| reg = <0x00000000 0x01ea0000 0x00000000 0x00010000>; | |
| status = "disabled"; | |
| }; | |
| clocking@1ee1000 { | |
| compatible = "fsl,ls1021a-clockgen"; | |
| reg = <0x00000000 0x01ee1000 0x00000000 0x00010000>; | |
| #address-cells = <0x00000001>; | |
| #size-cells = <0x00000000>; | |
| sysclk { | |
| compatible = "fixed-clock"; | |
| #clock-cells = <0x00000000>; | |
| clock-frequency = <0x05f5e100>; | |
| clock-output-names = "sysclk"; | |
| linux,phandle = <0x00000003>; | |
| phandle = <0x00000003>; | |
| }; | |
| pll1@800 { | |
| compatible = "fsl,core-pll-clock"; | |
| #clock-cells = <0x00000001>; | |
| reg = <0x00000800>; | |
| clocks = <0x00000003>; | |
| clock-output-names = "cga-pll1", "cga-pll1-div2", "cga-pll1-div3", "cga-pll1-div4"; | |
| linux,phandle = <0x00000004>; | |
| phandle = <0x00000004>; | |
| }; | |
| pll2@820 { | |
| compatible = "fsl,core-pll-clock"; | |
| #clock-cells = <0x00000001>; | |
| reg = <0x00000820>; | |
| clocks = <0x00000003>; | |
| clock-output-names = "cga-pll2", "cga-pll2-div2", "cga-pll2-div3", "cga-pll2-div4"; | |
| }; | |
| pll@c00 { | |
| compatible = "fsl,core-pll-clock"; | |
| #clock-cells = <0x00000001>; | |
| reg = <0x00000c00>; | |
| clocks = <0x00000003>; | |
| clock-output-names = "platform-clk", "platform-clk-div2"; | |
| linux,phandle = <0x00000002>; | |
| phandle = <0x00000002>; | |
| }; | |
| clk0c0@0 { | |
| compatible = "fsl,core-mux-clock"; | |
| #clock-cells = <0x00000001>; | |
| reg = <0x00000000>; | |
| clock-names = "pll1cga", "pll1cga-div2"; | |
| clocks = <0x00000004 0x00000000 0x00000004 0x00000002>; | |
| clock-output-names = "cluster1-clk"; | |
| }; | |
| }; | |
| rcpm@1ee2000 { | |
| compatible = "fsl,ls1021a-rcpm", "fsl,qoriq-rcpm-2.1"; | |
| reg = <0x00000000 0x01ee2000 0x00000000 0x00010000>; | |
| }; | |
| dspi@2100000 { | |
| #address-cells = <0x00000001>; | |
| #size-cells = <0x00000000>; | |
| compatible = "fsl,vf610-dspi"; | |
| reg = <0x00000000 0x02100000 0x00000000 0x00010000>; | |
| interrupts = <0x00000000 0x00000060 0x00000004>; | |
| clock-names = "dspi"; | |
| clocks = <0x00000002 0x00000001>; | |
| spi-num-chipselects = <0x00000005>; | |
| big-endian; | |
| status = "disabled"; | |
| }; | |
| dspi@2110000 { | |
| #address-cells = <0x00000001>; | |
| #size-cells = <0x00000000>; | |
| compatible = "fsl,vf610-dspi"; | |
| reg = <0x00000000 0x02110000 0x00000000 0x00010000>; | |
| interrupts = <0x00000000 0x00000061 0x00000004>; | |
| clock-names = "dspi"; | |
| clocks = <0x00000002 0x00000001>; | |
| spi-num-chipselects = <0x00000005>; | |
| big-endian; | |
| status = "okay"; | |
| bus-num = <0x00000000>; | |
| s25fl064k@0 { | |
| #address-cells = <0x00000001>; | |
| #size-cells = <0x00000001>; | |
| compatible = "spansion,s25fl064k"; | |
| spi-max-frequency = <0x00f42400>; | |
| spi-cpol; | |
| spi-cpha; | |
| reg = <0x00000000>; | |
| }; | |
| }; | |
| i2c@2180000 { | |
| #address-cells = <0x00000001>; | |
| #size-cells = <0x00000000>; | |
| compatible = "fsl,vf610-i2c"; | |
| reg = <0x00000000 0x02180000 0x00000000 0x00010000>; | |
| interrupts = <0x00000000 0x00000058 0x00000004>; | |
| clock-names = "i2c"; | |
| clocks = <0x00000002 0x00000001>; | |
| status = "okay"; | |
| }; | |
| i2c@2190000 { | |
| #address-cells = <0x00000001>; | |
| #size-cells = <0x00000000>; | |
| compatible = "fsl,vf610-i2c"; | |
| reg = <0x00000000 0x02190000 0x00000000 0x00010000>; | |
| interrupts = <0x00000000 0x00000059 0x00000004>; | |
| clock-names = "i2c"; | |
| clocks = <0x00000002 0x00000001>; | |
| status = "okay"; | |
| sgtl5000@a { | |
| compatible = "fsl,sgtl5000"; | |
| reg = <0x0000000a>; | |
| VDDA-supply = <0x00000005>; | |
| VDDIO-supply = <0x00000005>; | |
| clocks = <0x00000006 0x00000001>; | |
| linux,phandle = <0x00000011>; | |
| phandle = <0x00000011>; | |
| }; | |
| sii9022a@39 { | |
| compatible = "fsl,sii902x"; | |
| reg = <0x00000039>; | |
| interrupts = <0x00000000 0x000000a7 0x00000001>; | |
| }; | |
| }; | |
| i2c@21a0000 { | |
| #address-cells = <0x00000001>; | |
| #size-cells = <0x00000000>; | |
| compatible = "fsl,vf610-i2c"; | |
| reg = <0x00000000 0x021a0000 0x00000000 0x00010000>; | |
| interrupts = <0x00000000 0x0000005a 0x00000004>; | |
| clock-names = "i2c"; | |
| clocks = <0x00000002 0x00000001>; | |
| status = "okay"; | |
| ltc2945@67 { | |
| compatible = "lltc,ltc2945"; | |
| reg = <0x00000067>; | |
| }; | |
| }; | |
| serial@21c0500 { | |
| compatible = "fsl,ns16550", "fsl,16550-FIFO64"; | |
| reg = <0x00000000 0x021c0500 0x00000000 0x00000100>; | |
| interrupts = <0x00000000 0x00000056 0x00000004>; | |
| clock-frequency = <0x08f0d180>; | |
| fifo-size = <0x0000003f>; | |
| status = "okay"; | |
| }; | |
| serial@21c0600 { | |
| compatible = "fsl,ns16550", "fsl,16550-FIFO64"; | |
| reg = <0x00000000 0x021c0600 0x00000000 0x00000100>; | |
| interrupts = <0x00000000 0x00000056 0x00000004>; | |
| clock-frequency = <0x08f0d180>; | |
| fifo-size = <0x0000003f>; | |
| status = "okay"; | |
| }; | |
| serial@21d0500 { | |
| compatible = "fsl,ns16550", "fsl,16550-FIFO64"; | |
| reg = <0x00000000 0x021d0500 0x00000000 0x00000100>; | |
| interrupts = <0x00000000 0x00000057 0x00000004>; | |
| clock-frequency = <0x08f0d180>; | |
| fifo-size = <0x0000003f>; | |
| status = "disabled"; | |
| }; | |
| serial@21d0600 { | |
| compatible = "fsl,ns16550", "fsl,16550-FIFO64"; | |
| reg = <0x00000000 0x021d0600 0x00000000 0x00000100>; | |
| interrupts = <0x00000000 0x00000057 0x00000004>; | |
| clock-frequency = <0x08f0d180>; | |
| fifo-size = <0x0000003f>; | |
| status = "disabled"; | |
| }; | |
| gpio@2300000 { | |
| compatible = "fsl,ls1021a-gpio"; | |
| reg = <0x00000000 0x02300000 0x00000000 0x00010000>; | |
| interrupts = <0x00000000 0x00000062 0x00000004>; | |
| gpio-controller; | |
| #gpio-cells = <0x00000002>; | |
| interrupt-controller; | |
| #interrupt-cells = <0x00000002>; | |
| }; | |
| gpio@2310000 { | |
| compatible = "fsl,ls1021a-gpio"; | |
| reg = <0x00000000 0x02310000 0x00000000 0x00010000>; | |
| interrupts = <0x00000000 0x00000063 0x00000004>; | |
| gpio-controller; | |
| #gpio-cells = <0x00000002>; | |
| interrupt-controller; | |
| #interrupt-cells = <0x00000002>; | |
| }; | |
| gpio@2320000 { | |
| compatible = "fsl,ls1021a-gpio"; | |
| reg = <0x00000000 0x02320000 0x00000000 0x00010000>; | |
| interrupts = <0x00000000 0x00000064 0x00000004>; | |
| gpio-controller; | |
| #gpio-cells = <0x00000002>; | |
| interrupt-controller; | |
| #interrupt-cells = <0x00000002>; | |
| }; | |
| gpio@2330000 { | |
| compatible = "fsl,ls1021a-gpio"; | |
| reg = <0x00000000 0x02330000 0x00000000 0x00010000>; | |
| interrupts = <0x00000000 0x000000a6 0x00000004>; | |
| gpio-controller; | |
| #gpio-cells = <0x00000002>; | |
| interrupt-controller; | |
| #interrupt-cells = <0x00000002>; | |
| }; | |
| uqe@2400000 { | |
| #address-cells = <0x00000001>; | |
| #size-cells = <0x00000001>; | |
| device_type = "qe"; | |
| compatible = "fsl,qe"; | |
| fsl,qe-num-riscs = <0x00000001>; | |
| fsl,qe-num-snums = <0x0000001c>; | |
| ranges = <0x00000000 0x00000000 0x02400000 0x00040000>; | |
| reg = <0x00000000 0x02400000 0x00000000 0x00000480>; | |
| brg-frequency = <0x05f5e100>; | |
| bus-frequency = <0x0bebc200>; | |
| qeic@80 { | |
| compatible = "fsl,qe-ic"; | |
| reg = <0x00000080 0x00000080>; | |
| #address-cells = <0x00000000>; | |
| interrupt-controller; | |
| #interrupt-cells = <0x00000001>; | |
| interrupts = <0x00000000 0x0000006d 0x00000004 0x00000000 0x0000006d 0x00000004>; | |
| linux,phandle = <0x00000007>; | |
| phandle = <0x00000007>; | |
| }; | |
| ucc@2000 { | |
| cell-index = <0x00000001>; | |
| reg = <0x00002000 0x00000200>; | |
| interrupts = <0x00000020>; | |
| interrupt-parent = <0x00000007>; | |
| device_type = "serial"; | |
| compatible = "ucc_uart"; | |
| port-number = <0x00000000>; | |
| rx-clock-name = "brg1"; | |
| tx-clock-name = "brg1"; | |
| }; | |
| ucc@2200 { | |
| cell-index = <0x00000003>; | |
| reg = <0x00002200 0x00000200>; | |
| interrupts = <0x00000022>; | |
| interrupt-parent = <0x00000007>; | |
| device_type = "serial"; | |
| compatible = "ucc_uart"; | |
| port-number = <0x00000001>; | |
| rx-clock-name = "brg2"; | |
| tx-clock-name = "brg2"; | |
| }; | |
| muram@10000 { | |
| #address-cells = <0x00000001>; | |
| #size-cells = <0x00000001>; | |
| compatible = "fsl,qe-muram", "fsl,cpm-muram"; | |
| ranges = <0x00000000 0x00010000 0x00006000>; | |
| data-only@0 { | |
| compatible = "fsl,qe-muram-data", "fsl,cpm-muram-data"; | |
| reg = <0x00000000 0x00006000>; | |
| }; | |
| }; | |
| si@700 { | |
| #address-cells = <0x00000001>; | |
| #size-cells = <0x00000000>; | |
| compatible = "fsl,qe-si"; | |
| reg = <0x00000700 0x00000080>; | |
| }; | |
| siram@1000 { | |
| #address-cells = <0x00000001>; | |
| #size-cells = <0x00000001>; | |
| compatible = "fsl,qe-siram"; | |
| reg = <0x00001000 0x00000800>; | |
| }; | |
| }; | |
| serial@2950000 { | |
| compatible = "fsl,vf610-lpuart"; | |
| reg = <0x00000000 0x02950000 0x00000000 0x00001000>; | |
| interrupts = <0x00000000 0x00000050 0x00000004>; | |
| clocks = <0x00000003>; | |
| clock-names = "ipg"; | |
| fsl,lpuart32; | |
| status = "okay"; | |
| }; | |
| serial@2960000 { | |
| compatible = "fsl,vf610-lpuart"; | |
| reg = <0x00000000 0x02960000 0x00000000 0x00001000>; | |
| interrupts = <0x00000000 0x00000051 0x00000004>; | |
| clocks = <0x00000002 0x00000001>; | |
| clock-names = "ipg"; | |
| fsl,lpuart32; | |
| status = "disabled"; | |
| }; | |
| serial@2970000 { | |
| compatible = "fsl,vf610-lpuart"; | |
| reg = <0x00000000 0x02970000 0x00000000 0x00001000>; | |
| interrupts = <0x00000000 0x00000052 0x00000004>; | |
| clocks = <0x00000002 0x00000001>; | |
| clock-names = "ipg"; | |
| fsl,lpuart32; | |
| status = "disabled"; | |
| }; | |
| serial@2980000 { | |
| compatible = "fsl,vf610-lpuart"; | |
| reg = <0x00000000 0x02980000 0x00000000 0x00001000>; | |
| interrupts = <0x00000000 0x00000053 0x00000004>; | |
| clocks = <0x00000002 0x00000001>; | |
| clock-names = "ipg"; | |
| fsl,lpuart32; | |
| status = "disabled"; | |
| }; | |
| serial@2990000 { | |
| compatible = "fsl,vf610-lpuart"; | |
| reg = <0x00000000 0x02990000 0x00000000 0x00001000>; | |
| interrupts = <0x00000000 0x00000054 0x00000004>; | |
| clocks = <0x00000002 0x00000001>; | |
| clock-names = "ipg"; | |
| fsl,lpuart32; | |
| status = "disabled"; | |
| }; | |
| serial@29a0000 { | |
| compatible = "fsl,vf610-lpuart"; | |
| reg = <0x00000000 0x029a0000 0x00000000 0x00001000>; | |
| interrupts = <0x00000000 0x00000055 0x00000004>; | |
| clocks = <0x00000002 0x00000001>; | |
| clock-names = "ipg"; | |
| fsl,lpuart32; | |
| status = "disabled"; | |
| }; | |
| ftm0_1@29d0000 { | |
| compatible = "fsl,ftm-timer", "fsl,ftm-alarm"; | |
| reg = <0x00000000 0x029d0000 0x00000000 0x00010000 0x00000000 0x029e0000 0x00000000 0x00010000>; | |
| interrupts = <0x00000000 0x00000076 0x00000004>; | |
| clock-names = "ftm-evt", "ftm-src", "ftm-evt-counter-en", "ftm-src-counter-en"; | |
| clocks = <0x00000002 0x00000001 0x00000002 0x00000001 0x00000002 0x00000001 0x00000002 0x00000001>; | |
| big-endian; | |
| status = "okay"; | |
| }; | |
| ftm@29f0000 { | |
| reg = <0x00000000 0x029f0000 0x00000000 0x00010000>; | |
| interrupts = <0x00000000 0x00000078 0x00000004>; | |
| status = "disabled"; | |
| }; | |
| ftm@2a00000 { | |
| compatible = "fsl,vf610-ftm-pwm"; | |
| #pwm-cells = <0x00000003>; | |
| reg = <0x00000000 0x02a00000 0x00000000 0x00010000>; | |
| interrupts = <0x00000000 0x00000079 0x00000004>; | |
| clock-names = "ftm_sys", "ftm_ext", "ftm_fix", "ftm_cnt_clk_en"; | |
| clocks = <0x00000002 0x00000001 0x00000002 0x00000001 0x00000002 0x00000001 0x00000002 0x00000001>; | |
| big-endian; | |
| status = "disabled"; | |
| }; | |
| ftm@2a10000 { | |
| reg = <0x00000000 0x02a10000 0x00000000 0x00010000>; | |
| interrupts = <0x00000000 0x00000020 0x00000004>; | |
| status = "disabled"; | |
| }; | |
| ftm@2a20000 { | |
| reg = <0x00000000 0x02a20000 0x00000000 0x00010000>; | |
| interrupts = <0x00000000 0x00000021 0x00000004>; | |
| status = "disabled"; | |
| }; | |
| ftm@2a30000 { | |
| compatible = "fsl,vf610-ftm-pwm"; | |
| #pwm-cells = <0x00000003>; | |
| reg = <0x00000000 0x02a30000 0x00000000 0x00010000>; | |
| interrupts = <0x00000000 0x0000007b 0x00000004>; | |
| clock-names = "ftm_sys", "ftm_ext", "ftm_fix", "ftm_cnt_clk_en"; | |
| clocks = <0x00000002 0x00000001 0x00000002 0x00000001 0x00000002 0x00000001 0x00000002 0x00000001>; | |
| big-endian; | |
| status = "okay"; | |
| }; | |
| ftm@2a40000 { | |
| compatible = "fsl,vf610-ftm-pwm"; | |
| #pwm-cells = <0x00000003>; | |
| reg = <0x00000000 0x02a40000 0x00000000 0x00010000>; | |
| interrupts = <0x00000000 0x0000007c 0x00000004>; | |
| clock-names = "ftm_sys", "ftm_ext", "ftm_fix", "ftm_cnt_clk_en"; | |
| clocks = <0x00000002 0x00000001 0x00000002 0x00000001 0x00000002 0x00000001 0x00000002 0x00000001>; | |
| big-endian; | |
| status = "okay"; | |
| }; | |
| wdog@2ad0000 { | |
| compatible = "fsl,ls1021a-wdt", "fsl,imx21-wdt"; | |
| reg = <0x00000000 0x02ad0000 0x00000000 0x00010000>; | |
| interrupts = <0x00000000 0x00000073 0x00000004>; | |
| clocks = <0x00000002 0x00000001>; | |
| clock-names = "wdog"; | |
| big-endian; | |
| }; | |
| sai@2b50000 { | |
| compatible = "fsl,vf610-sai"; | |
| reg = <0x00000000 0x02b50000 0x00000000 0x00010000>; | |
| interrupts = <0x00000000 0x00000084 0x00000004>; | |
| clocks = <0x00000002 0x00000001>; | |
| clock-names = "sai"; | |
| dma-names = "tx", "rx"; | |
| dmas = <0x00000008 0x00000001 0x0000002f 0x00000008 0x00000001 0x0000002e>; | |
| big-endian-regs; | |
| status = "okay"; | |
| linux,phandle = <0x00000010>; | |
| phandle = <0x00000010>; | |
| }; | |
| sai@2b60000 { | |
| compatible = "fsl,vf610-sai"; | |
| reg = <0x00000000 0x02b60000 0x00000000 0x00010000>; | |
| interrupts = <0x00000000 0x00000085 0x00000004>; | |
| clocks = <0x00000002 0x00000001>; | |
| clock-names = "sai"; | |
| dma-names = "tx", "rx"; | |
| dmas = <0x00000008 0x00000001 0x0000002d 0x00000008 0x00000001 0x0000002c>; | |
| big-endian-regs; | |
| status = "disabled"; | |
| }; | |
| edma@2c00000 { | |
| #dma-cells = <0x00000002>; | |
| compatible = "fsl,vf610-edma"; | |
| reg = <0x00000000 0x02c00000 0x00000000 0x00010000 0x00000000 0x02c10000 0x00000000 0x00010000 0x00000000 0x02c20000 0x00000000 0x00010000>; | |
| interrupts = <0x00000000 0x00000087 0x00000004 0x00000000 0x00000087 0x00000004>; | |
| interrupt-names = "edma-tx", "edma-err"; | |
| dma-channels = <0x00000020>; | |
| big-endian; | |
| clock-names = "dmamux0", "dmamux1"; | |
| clocks = <0x00000002 0x00000001 0x00000002 0x00000001>; | |
| linux,phandle = <0x00000008>; | |
| phandle = <0x00000008>; | |
| }; | |
| dcu@2ce0000 { | |
| compatible = "fsl,vf610-dcu"; | |
| reg = <0x00000000 0x02ce0000 0x00000000 0x00010000>; | |
| interrupts = <0x00000000 0x000000ac 0x00000004>; | |
| clocks = <0x00000002 0x00000000>; | |
| clock-names = "dcu"; | |
| scfg-controller = <0x00000009>; | |
| big-endian; | |
| status = "okay"; | |
| display = <0x0000000a>; | |
| display@0 { | |
| bits-per-pixel = <0x00000018>; | |
| linux,phandle = <0x0000000a>; | |
| phandle = <0x0000000a>; | |
| display-timings { | |
| native-mode = <0x0000000b>; | |
| nl4827hc19 { | |
| clock-frequency = <0x00a5dcf0>; | |
| hactive = <0x000001e0>; | |
| vactive = <0x00000110>; | |
| hback-porch = <0x00000002>; | |
| hfront-porch = <0x00000002>; | |
| vback-porch = <0x00000002>; | |
| vfront-porch = <0x00000002>; | |
| hsync-len = <0x00000029>; | |
| vsync-len = <0x00000004>; | |
| hsync-active = <0x00000001>; | |
| vsync-active = <0x00000001>; | |
| linux,phandle = <0x0000000b>; | |
| phandle = <0x0000000b>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| mdio@2d24000 { | |
| #address-cells = <0x00000001>; | |
| #size-cells = <0x00000000>; | |
| device_type = "mdio"; | |
| compatible = "gianfar"; | |
| reg = <0x00000000 0x02d24000 0x00000000 0x00004000>; | |
| ethernet-phy@0 { | |
| reg = <0x00000000>; | |
| linux,phandle = <0x0000000e>; | |
| phandle = <0x0000000e>; | |
| }; | |
| ethernet-phy@1 { | |
| reg = <0x00000001>; | |
| linux,phandle = <0x0000000f>; | |
| phandle = <0x0000000f>; | |
| }; | |
| ethernet-phy@2 { | |
| reg = <0x00000002>; | |
| linux,phandle = <0x0000000d>; | |
| phandle = <0x0000000d>; | |
| }; | |
| tbi-phy@1f { | |
| reg = <0x0000001f>; | |
| device_type = "tbi-phy"; | |
| linux,phandle = <0x0000000c>; | |
| phandle = <0x0000000c>; | |
| }; | |
| }; | |
| ptp_clock@2d10e00 { | |
| compatible = "fsl,etsec-ptp"; | |
| reg = <0x00000000 0x02d10e00 0x00000000 0x000000b0>; | |
| interrupts = <0x00000000 0x000000ad 0x00000004>; | |
| fsl,tclk-period = <0x05000000>; | |
| fsl,tmr-prsc = <0x02000000>; | |
| fsl,tmr-add = <0xabaaaaaa>; | |
| fsl,tmr-fiper1 = <0xf6c99a3b>; | |
| fsl,tmr-fiper2 = <0x96860100>; | |
| fsl,max-adj = <0xff64cd1d>; | |
| }; | |
| ethernet@2d10000 { | |
| #address-cells = <0x00000002>; | |
| #size-cells = <0x00000002>; | |
| interrupt-parent = <0x00000001>; | |
| device_type = "network"; | |
| model = "eTSEC"; | |
| compatible = "fsl,etsec2"; | |
| fsl,dma-endian-le; | |
| fsl,num_rx_queues = <0x00000001>; | |
| fsl,num_tx_queues = <0x00000001>; | |
| local-mac-address = [00 04 ffffffff ffffffff ffffffff ffffff9f 03 4b 00]; | |
| ranges; | |
| tbi-handle = <0x0000000c>; | |
| phy-handle = <0x0000000d>; | |
| phy-connection-type = "sgmii"; | |
| status = "okay"; | |
| queue-group@0 { | |
| #address-cells = <0x00000001>; | |
| #size-cells = <0x00000001>; | |
| reg = <0x00000000 0x02d10000 0x00000000 0x00008000>; | |
| fsl,rx-bit-map = <0x000000ff>; | |
| fsl,tx-bit-map = <0x000000ff>; | |
| interrupts = <0x00000000 0x00000090 0x00000004 0x00000000 0x00000091 0x00000004 0x00000000 0x00000092 0x00000004>; | |
| }; | |
| }; | |
| ethernet@2d50000 { | |
| #address-cells = <0x00000002>; | |
| #size-cells = <0x00000002>; | |
| interrupt-parent = <0x00000001>; | |
| device_type = "network"; | |
| model = "eTSEC"; | |
| compatible = "fsl,etsec2"; | |
| fsl,dma-endian-le; | |
| fsl,num_rx_queues = <0x00000001>; | |
| fsl,num_tx_queues = <0x00000001>; | |
| local-mac-address = <0x0004ffff 0xff9f034b 0xffffffc0>; | |
| ranges; | |
| tbi-handle = <0x0000000c>; | |
| phy-handle = <0x0000000e>; | |
| phy-connection-type = "sgmii"; | |
| status = "okay"; | |
| queue-group@0 { | |
| #address-cells = <0x00000001>; | |
| #size-cells = <0x00000001>; | |
| reg = <0x00000000 0x02d50000 0x00000000 0x00008000>; | |
| fsl,rx-bit-map = <0x000000ff>; | |
| fsl,tx-bit-map = <0x000000ff>; | |
| interrupts = <0x00000000 0x00000096 0x00000004 0x00000000 0x00000098 0x00000004 0x00000000 0x00000099 0x00000004>; | |
| }; | |
| }; | |
| ethernet@2d90000 { | |
| #address-cells = <0x00000002>; | |
| #size-cells = <0x00000002>; | |
| interrupt-parent = <0x00000001>; | |
| device_type = "network"; | |
| model = "eTSEC"; | |
| compatible = "fsl,etsec2"; | |
| fsl,dma-endian-le; | |
| fsl,num_rx_queues = <0x00000001>; | |
| fsl,num_tx_queues = <0x00000001>; | |
| local-mac-address = <0x0004ffff 0xff9f034b 0xffffffc1>; | |
| ranges; | |
| phy-handle = <0x0000000f>; | |
| phy-connection-type = <0x72676d69>; | |
| status = "okay"; | |
| queue-group@0 { | |
| #address-cells = <0x00000001>; | |
| #size-cells = <0x00000001>; | |
| reg = <0x00000000 0x02d90000 0x00000000 0x00008000>; | |
| fsl,rx-bit-map = <0x000000ff>; | |
| fsl,tx-bit-map = <0x000000ff>; | |
| interrupts = <0x00000000 0x0000009d 0x00000004 0x00000000 0x0000009e 0x00000004 0x00000000 0x0000009f 0x00000004>; | |
| }; | |
| }; | |
| usb@8600000 { | |
| compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr"; | |
| reg = <0x00000000 0x08600000 0x00000000 0x00001000>; | |
| #address-cells = <0x00000001>; | |
| #size-cells = <0x00000000>; | |
| interrupts = <0x00000000 0x000000ab 0x00000004>; | |
| dr_mode = "host"; | |
| phy_type = "ulpi"; | |
| }; | |
| usb3@3100000 { | |
| compatible = "snps,dwc3"; | |
| reg = <0x00000000 0x03100000 0x00000000 0x00010000>; | |
| interrupts = <0x00000000 0x0000005d 0x00000004>; | |
| dr_mode = "host"; | |
| }; | |
| can@2a70000 { | |
| compatible = "fsl,ls1021a-flexcan"; | |
| reg = <0x00000000 0x02a70000 0x00000000 0x00001000>; | |
| interrupts = <0x00000000 0x0000007e 0x00000004>; | |
| clocks = <0x00000002 0x00000001>; | |
| clock-names = "per"; | |
| status = "okay"; | |
| }; | |
| can@2a80000 { | |
| compatible = "fsl,ls1021a-flexcan"; | |
| reg = <0x00000000 0x02a80000 0x00000000 0x00001000>; | |
| interrupts = <0x00000000 0x0000007f 0x00000004>; | |
| clocks = <0x00000002 0x00000001>; | |
| clock-names = "per"; | |
| status = "okay"; | |
| }; | |
| can@2a90000 { | |
| compatible = "fsl,ls1021a-flexcan"; | |
| reg = <0x00000000 0x02a90000 0x00000000 0x00001000>; | |
| interrupts = <0x00000000 0x00000080 0x00000004>; | |
| clocks = <0x00000002 0x00000001>; | |
| clock-names = "per"; | |
| status = "disabled"; | |
| }; | |
| can@2aa0000 { | |
| compatible = "fsl,ls1021a-flexcan"; | |
| reg = <0x00000000 0x02aa0000 0x00000000 0x00001000>; | |
| interrupts = <0x00000000 0x00000081 0x00000004>; | |
| clocks = <0x00000002 0x00000001>; | |
| clock-names = "per"; | |
| status = "disabled"; | |
| }; | |
| pcie@3400000 { | |
| compatible = "fsl,pcie", "fsl,ls1021a-pcie"; | |
| reg = <0x00000000 0x03400000 0x00000000 0x00010000>; | |
| interrupts = <0x00000000 0x000000b1 0x00000004 0x00000000 0x000000b3 0x00000004 0x00000000 0x000000b5 0x00000004 0x00000000 0x000000b7 0x00000004 0x00000000 0x0000005b 0x00000004>; | |
| interrupt-names = "intr", "msi", "pme", "cfg-err", "inta"; | |
| #address-cells = <0x00000003>; | |
| #size-cells = <0x00000002>; | |
| device_type = "pci"; | |
| num-lanes = <0x00000004>; | |
| bus-range = <0x00000000 0x000000ff>; | |
| ranges = <0x00000800 0x00000000 0x00000000 0x00000040 0x00000000 0x00000000 0x00080000 0x81000000 0x00000000 0x00000000 0x00000040 0x10000000 0x00000000 0x00010000 0x82000000 0x00000000 0x00000000 0x00000041 0x00000000 0x00000001 0x00000000>; | |
| interrupt-map-mask = <0x00000000 0x00000000 0x00000000 0x00000007>; | |
| interrupt-map = <0x00000000 0x00000000 0x00000000 0x00000001 0x00000001 0x00000000 0x0000005b 0x00000004 0x00000000 0x00000000 0x00000000 0x00000002 0x00000001 0x00000000 0x000000bc 0x00000004 0x00000000 0x00000000 0x00000000 0x00000003 0x00000001 0x00000000 0x000000be 0x00000004 0x00000000 0x00000000 0x00000000 0x00000004 0x00000001 0x00000000 0x000000c0 0x00000004>; | |
| }; | |
| pcie@3500000 { | |
| compatible = "fsl,pcie", "fsl,ls1021a-pcie"; | |
| reg = <0x00000000 0x03500000 0x00000000 0x00010000>; | |
| interrupts = <0x00000000 0x000000b2 0x00000004 0x00000000 0x000000b4 0x00000004 0x00000000 0x000000b6 0x00000004 0x00000000 0x000000b8 0x00000004 0x00000000 0x0000005c 0x00000004>; | |
| interrupt-names = "intr", "msi", "pme", "cfg-err", "inta"; | |
| #address-cells = <0x00000003>; | |
| #size-cells = <0x00000002>; | |
| device_type = "pci"; | |
| num-lanes = <0x00000002>; | |
| bus-range = <0x00000000 0x000000ff>; | |
| ranges = <0x00000800 0x00000000 0x00000000 0x00000048 0x00000000 0x00000000 0x10000000 0x81000000 0x00000000 0x00000000 0x00000048 0x10000000 0x00000000 0x00010000 0x82000000 0x00000000 0x00000000 0x00000049 0x00000000 0x00000001 0x00000000>; | |
| interrupt-map-mask = <0x00000000 0x00000000 0x00000000 0x00000007>; | |
| interrupt-map = <0x00000000 0x00000000 0x00000000 0x00000001 0x00000001 0x00000000 0x0000005c 0x00000004 0x00000000 0x00000000 0x00000000 0x00000002 0x00000001 0x00000000 0x000000bd 0x00000004 0x00000000 0x00000000 0x00000000 0x00000003 0x00000001 0x00000000 0x000000bf 0x00000004 0x00000000 0x00000000 0x00000000 0x00000004 0x00000001 0x00000000 0x000000c1 0x00000004>; | |
| }; | |
| }; | |
| dcsr@20000000 { | |
| #address-cells = <0x00000001>; | |
| #size-cells = <0x00000001>; | |
| compatible = "fsl,ls1021a-dcsr", "simple-bus"; | |
| ranges = <0x00000000 0x00000000 0x20000000 0x01000000>; | |
| dcsr-epu@0 { | |
| compatible = "fsl,ls1021a-dcsr-epu"; | |
| reg = <0x00000000 0x00010000>; | |
| }; | |
| dcsr-gdi@100000 { | |
| compatible = "fsl,ls1021a-dcsr-gdi"; | |
| reg = <0x00100000 0x00010000>; | |
| }; | |
| dcsr-dddi@120000 { | |
| compatible = "fsl,ls1021a-dcsr-dddi"; | |
| reg = <0x00120000 0x00010000>; | |
| }; | |
| dcsr-dcfg@220000 { | |
| compatible = "fsl,ls1021a-dcsr-dcfg"; | |
| reg = <0x00220000 0x00001000>; | |
| }; | |
| dcsr-clock@221000 { | |
| compatible = "fsl,ls1021a-dcsr-clock"; | |
| reg = <0x00221000 0x00001000>; | |
| }; | |
| dcsr-rcpm@222000 { | |
| compatible = "fsl,ls1021a-dcsr-rcpm"; | |
| reg = <0x00222000 0x00001000 0x00223000 0x00001000>; | |
| }; | |
| dcsr-ccp@225000 { | |
| compatible = "fsl,ls1021a-dcsr-ccp"; | |
| reg = <0x00225000 0x00001000>; | |
| }; | |
| dcsr-fusectrl@226000 { | |
| compatible = "fsl,ls1021a-dcsr-fusectrl"; | |
| reg = <0x00226000 0x00001000>; | |
| }; | |
| dcsr-dap@300000 { | |
| compatible = "fsl,ls1021a-dcsr-dap"; | |
| reg = <0x00300000 0x00010000>; | |
| }; | |
| dcsr-cstf@350000 { | |
| compatible = "fsl,ls1021a-dcsr-cstf"; | |
| reg = <0x00350000 0x00001000 0x003a7000 0x00001000>; | |
| }; | |
| dcsr-a7rom@360000 { | |
| compatible = "fsl,ls1021a-dcsr-a7rom"; | |
| reg = <0x00360000 0x00010000>; | |
| }; | |
| dcsr-a7cpu@370000 { | |
| compatible = "fsl,ls1021a-dcsr-a7cpu"; | |
| reg = <0x00370000 0x00008000>; | |
| }; | |
| dcsr-a7cti@378000 { | |
| compatible = "fsl,ls1021a-dcsr-a7cti"; | |
| reg = <0x00378000 0x00004000>; | |
| }; | |
| dcsr-etm@37c000 { | |
| compatible = "fsl,ls1021a-dcsr-etm"; | |
| reg = <0x0037c000 0x00001000 0x0037d000 0x00003000>; | |
| }; | |
| dcsr-hugorom@3a0000 { | |
| compatible = "fsl,ls1021a-dcsr-hugorom"; | |
| reg = <0x003a0000 0x00001000>; | |
| }; | |
| dcsr-etf@3a1000 { | |
| compatible = "fsl,ls1021a-dcsr-etf"; | |
| reg = <0x003a1000 0x00001000 0x003a2000 0x00001000>; | |
| }; | |
| dcsr-etr@3a3000 { | |
| compatible = "fsl,ls1021a-dcsr-etr"; | |
| reg = <0x003a3000 0x00001000>; | |
| }; | |
| dcsr-cti@3a4000 { | |
| compatible = "fsl,ls1021a-dcsr-cti"; | |
| reg = <0x003a4000 0x00001000 0x003a5000 0x00001000 0x003a6000 0x00001000>; | |
| }; | |
| dcsr-atbrepl@3a8000 { | |
| compatible = "fsl,ls1021a-dcsr-atbrepl"; | |
| reg = <0x003a8000 0x00001000>; | |
| }; | |
| dcsr-tsgen-ctrl@3a9000 { | |
| compatible = "fsl,ls1021a-dcsr-tsgen-ctrl"; | |
| reg = <0x003a9000 0x00001000>; | |
| }; | |
| dcsr-tsgen-read@3aa000 { | |
| compatible = "fsl,ls1021a-dcsr-tsgen-read"; | |
| reg = <0x003aa000 0x00001000>; | |
| }; | |
| }; | |
| regulators { | |
| compatible = "simple-bus"; | |
| #address-cells = <0x00000001>; | |
| #size-cells = <0x00000000>; | |
| regulator@0 { | |
| compatible = "regulator-fixed"; | |
| reg = <0x00000000>; | |
| regulator-name = "3P3V"; | |
| regulator-min-microvolt = <0x00325aa0>; | |
| regulator-max-microvolt = <0x00325aa0>; | |
| regulator-always-on; | |
| linux,phandle = <0x00000005>; | |
| phandle = <0x00000005>; | |
| }; | |
| }; | |
| sound { | |
| compatible = "fsl,vf610-sgtl5000"; | |
| simple-audio-card,name = "FSL-VF610-TWR-BOARD"; | |
| simple-audio-card,routing = "MIC_IN", "Microphone Jack", "Microphone Jack", "Mic Bias", "LINE_IN", "Line In Jack", "Headphone Jack", "HP_OUT", "Speaker Ext", "LINE_OUT"; | |
| simple-audio-card,cpu = <0x00000010>; | |
| simple-audio-card,codec = <0x00000011>; | |
| }; | |
| }; |
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