Trivial block RAM module

gistfile1.txt

module top( input clk, 
            input [ 10:0 ]    waddr, 
            input [ 7:0 ]     wdata,
            input [ 10:0 ]    raddr,
            output reg[ 7:0 ] rdata ); // ***** change the size to 6:0 and yosys no longer infers block RAM *****
   
   reg [ 7:0 ]                ebr[ 2047:0 ];

   always @( posedge clk ) begin
      ebr[ waddr ] <= wdata;
      rdata <= ebr[ raddr ];
   end
endmodule